Light-emitting element

Abstract

To provide a light-emitting element in which the deviation in light emission distribution between a first active layer and a second active layer can be reduced.SOLUTION: A light-emitting element includes a semiconductor laminate, first and second electrodes, and an insulating layer. The semiconductor laminate includes a first p-type semiconductor layer, a first active layer, a first n-type semiconductor layer, an intermediate layer, a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer. The semiconductor laminate includes first and second openings. The first opening is disposed continuing to the first p-type semiconductor layer and the first active layer. The second opening is disposed at a position overlapping with the first opening in a plan view. The second opening is disposed continuing to the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, and the second active layer. The first electrode is disposed inside the first opening and electrically connected to the first n-type semiconductor layer. The second electrode is disposed inside the first opening and inside the second opening, and is electrically connected to the second n-type semiconductor layer. The insulating layer is disposed between the first electrode and the second electrode and is in contact with the first and second electrodes.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiment relates to a light emitting device. [Background technology]

[0002] Patent Document 1 discloses a configuration in which a first LED including a first active region that emits green light and a second LED including a second active region that emits blue light are stacked via a tunnel junction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2009 / 0001389 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a light emitting device that can reduce the bias in the light emission distribution between the first active layer and the second active layer. [Means for solving the problem]

[0005] A light-emitting element according to one embodiment of the present invention includes a semiconductor stack, a first electrode, a second electrode, and an insulating layer. The semiconductor stack includes a first p-type semiconductor layer, a first active layer, a first n-type semiconductor layer, an intermediate layer, a second p-type semiconductor layer, a second active layer, and a second n-type semiconductor layer. The first active layer is disposed on the first p-type semiconductor layer. The first n-type semiconductor layer is disposed on the first active layer. The intermediate layer is disposed on the first n-type semiconductor layer. The second p-type semiconductor layer is disposed on the intermediate layer. The second active layer is disposed on the second p-type semiconductor layer. The second n-type semiconductor layer is disposed on the second active layer. The semiconductor stack includes a first opening and a second opening. The first opening is disposed contiguous with the first p-type semiconductor layer and the first active layer. The second opening is disposed at a position overlapping the first opening in a plan view. The second opening is disposed continuously with the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, and the second active layer. The first electrode is disposed inside the first opening. The first electrode is electrically connected to the first n-type semiconductor layer. The second electrode is disposed inside the first opening and inside the second opening. The second electrode is electrically connected to the second n-type semiconductor layer. The insulating layer is disposed between the first electrode and the second electrode. The insulating layer contacts the first electrode and the second electrode. [Effects of the Invention]

[0006] According to one embodiment of the present invention, it is possible to provide a light emitting device that can reduce the bias in the light emission distribution between the first active layer and the second active layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a light-emitting element according to a first embodiment. [Figure 2] 1 is a cross-sectional view illustrating a light-emitting element according to a first embodiment. [Figure 3] 3 is a cross-sectional view illustrating a current path in a first light-emitting state of the light-emitting element according to the first embodiment. FIG. [Figure 4]4 is a cross-sectional view illustrating a current path in the light-emitting element according to the first embodiment in a second light-emitting state. FIG. [Figure 5] 4 is a cross-sectional view illustrating a current path in a third light-emitting state of the light-emitting element according to the first embodiment. FIG. [Figure 6] FIG. 4 is a plan view illustrating a light emitting element according to a modified example of the first embodiment. [Figure 7] FIG. 4 is a cross-sectional view illustrating a light-emitting element according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a plan view illustrating a light-emitting element according to a second embodiment. [Figure 9] FIG. 4 is a cross-sectional view illustrating a light-emitting element according to a second embodiment. [Figure 10] FIG. 10 is a plan view illustrating a light emitting element according to a modified example of the second embodiment. [Figure 11] FIG. 10 is a plan view illustrating a light-emitting element according to a third embodiment. [Figure 12] FIG. 11 is a plan view illustrating a light emitting element according to a modified example of the third embodiment. [Figure 13] 3A to 3C are cross-sectional views illustrating a part of a method for manufacturing the light-emitting element according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views illustrating a part of a method for manufacturing the light-emitting element according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views illustrating a part of a method for manufacturing the light-emitting element according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views illustrating a part of a method for manufacturing the light-emitting element according to the first embodiment. [Figure 17] 3A to 3C are cross-sectional views illustrating a part of a method for manufacturing the light-emitting element according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate.

[0009] For ease of explanation, the following describes the arrangement and configuration of each part using an XYZ Cartesian coordinate system. The X, Y, and Z axes are perpendicular to one another. The direction in which the X axis extends is referred to as the "X direction," the direction in which the Y axis extends is referred to as the "Y direction," and the direction in which the Z axis extends is referred to as the "Z direction." For ease of explanation, the direction of the arrow in the Z direction is referred to as upward and the opposite direction is referred to as downward, but these directions are unrelated to the direction of gravity. Viewing in a direction along the Z direction is referred to as "planar view."

[0010] (First embodiment) FIG. 1 is a plan view illustrating a light emitting device according to a first embodiment. FIG. 2 is a cross-sectional view illustrating the light emitting device according to the first embodiment. FIG. 2 shows a cross section taken along line II-II in FIG. 1 and 2, the light emitting element 100 according to the first embodiment includes a semiconductor laminate 10, a first pad electrode 21, a second pad electrode 22, a lower electrode 23, a first electrode 31, a second electrode 32, a connection electrode 35, and an insulating layer 45. As shown in Fig. 1, the light emitting element 100 has a rectangular shape in a planar view. When the light emitting element 100 has a rectangular shape in a planar view, the length of one side of the rectangle is, for example, not less than 50 µm and not more than 2000 µm.

[0011] The semiconductor laminate 10 includes a first p-type semiconductor layer 11a, a first active layer 11b, a first n-type semiconductor layer 11c, an intermediate layer 13, a second p-type semiconductor layer 12a, a second active layer 12b, and a second n-type semiconductor layer 12c. The first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, and the second active layer 12b are located between the first p-type semiconductor layer 11a and the second n-type semiconductor layer 12c.

[0012] The first p-type semiconductor layer 11a is disposed at the bottom of the semiconductor laminate 10. The first active layer 11b is disposed on the first p-type semiconductor layer 11a. The first n-type semiconductor layer 11c is disposed on the first active layer 11b. The intermediate layer 13 is disposed on the first n-type semiconductor layer 11c. The second p-type semiconductor layer 12a is disposed on the intermediate layer 13. The second active layer 12b is disposed on the second p-type semiconductor layer 12a. The second n-type semiconductor layer 12c is disposed on the second active layer 12b.

[0013] The first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, and the second n-type semiconductor layer 12c are each made of, for example, a nitride semiconductor. x Al y Ga 1-x-y The term "nitride semiconductor" includes all semiconductors with compositions in which the composition ratios x and y in the chemical formula N (0≦x≦1, 0≦y≦1, x+y≦1) are varied within their respective ranges. In addition, the term "nitride semiconductor" also includes semiconductors with the above chemical formula that further contain Group V elements other than N (nitrogen), and semiconductors that further contain various elements added to control various physical properties such as conductivity type.

[0014] The first n-type semiconductor layer 11c and the second n-type semiconductor layer 12c contain, for example, Si (silicon) as an n-type impurity. The first p-type semiconductor layer 11a and the second p-type semiconductor layer 12a contain, for example, Mg (magnesium) as a p-type impurity. The first active layer 11b and the second active layer 12b are light-emitting layers that emit light and have, for example, an MQW (multiple quantum well) structure including multiple barrier layers and multiple well layers. The peak wavelength of the light emitted from the first active layer 11b may be the same as or different from the peak wavelength of the light emitted from the second active layer 12b.

[0015] The intermediate layer 13 includes at least one of a p-type semiconductor layer having a p-type impurity concentration higher than that of the second p-type semiconductor layer 12a and an n-type semiconductor layer having an n-type impurity concentration higher than that of the first n-type semiconductor layer 11c. The intermediate layer 13 functions as, for example, a tunnel junction layer.

[0016] In the light emitting device 100, the area of ​​the second active layer 12b is larger than the area of ​​the first active layer 11b in a plan view.

[0017] The semiconductor stack 10 has a first opening 16 and a second opening 17. The first opening 16 is disposed continuously with the first p-type semiconductor layer 11a and the first active layer 11b. The first opening 16 is a hole that penetrates the first p-type semiconductor layer 11a and the first active layer 11b in the Z direction. In the light-emitting element 100, the first opening 16 is disposed continuously with the first p-type semiconductor layer 11a, the first active layer 11b, and the first n-type semiconductor layer 11c. In the light-emitting element 100, the first opening 16 is a hole that penetrates the first p-type semiconductor layer 11a and the first active layer 11b in the Z direction and reaches the first n-type semiconductor layer 11c. The first opening 16 does not penetrate the first n-type semiconductor layer 11c. In the light-emitting element 100, the semiconductor stack 10 has a plurality of first openings 16. The semiconductor stack 10 has at least one first opening 16.

[0018] The second opening 17 is arranged continuously in the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, and the second active layer 12b. The second opening 17 is a hole that penetrates the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, and the second active layer 12b in the Z direction. In the light-emitting element 100, the second opening 17 is arranged continuously in the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, and the second n-type semiconductor layer 12c. In the light-emitting device 100, the second opening 17 is a hole that penetrates the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, and the second active layer 12b in the Z direction and reaches the second n-type semiconductor layer 12c. The second opening 17 does not penetrate the second n-type semiconductor layer 12c. In the light-emitting device 100, the semiconductor stack 10 has multiple second openings 17. The semiconductor stack 10 has at least one second opening 17. The second opening 17 is arranged at a position that overlaps with the first opening 16 in a plan view.

[0019] In the light-emitting device 100, the shape of the first opening 16 and the shape of the second opening 17 are each perfect circles in a plan view. In a plan view, the shape of the first opening 16 and the shape of the second opening 17 may each be semicircular, elliptical, polygonal, or the like. When the shape of the first opening 16 and the shape of the second opening 17 are each perfect circles, the diameter of the first opening 16 is, for example, 15 μm or less, and preferably 10 μm or more and 15 μm or less, and the diameter of the second opening 17 is, for example, smaller than 12 μm, and preferably 5 μm or more and 10 μm or less.

[0020] In the light-emitting element 100, in a planar view, the second connection portion 32a where the second electrode 32 and the second n-type semiconductor layer 12c contact at the second opening 17 is surrounded by the first connection portion 31a where the first electrode 31 and the first n-type semiconductor layer 11c contact at the first opening 16.

[0021] At least a portion of the top surface of the semiconductor laminate 10 has, for example, a plurality of protrusions. As shown in FIG. 2, the plurality of protrusions are arranged so as to overlap the first active layer 11b and the second active layer 12b in the Z direction. By having the plurality of protrusions on the top surface of the semiconductor laminate 10, it is possible to improve the light extraction efficiency of light emitted upward from the semiconductor laminate 10. The top surface of the semiconductor laminate 10 is the top surface of the second n-type semiconductor layer 12c. Note that the plurality of protrusions may be arranged not only in the region overlapping the first active layer 11b and the second active layer 12b, but also in the region overlapping only with the second active layer 12b.

[0022] The first pad electrode 21 is electrically connected to the first p-type semiconductor layer 11a. For example, in a plan view, the first pad electrode 21 is located away from the semiconductor laminate 10. For example, the first pad electrode 21 does not overlap with the semiconductor laminate 10 in the Z direction. The first pad electrode 21 may overlap with the semiconductor laminate 10 in the Z direction.

[0023] The second pad electrode 22 is electrically connected to the first n-type semiconductor layer 11c. For example, the second pad electrode 22 is located away from the semiconductor laminate 10 in a plan view. For example, the second pad electrode 22 does not overlap with the semiconductor laminate 10 in the Z direction. The second pad electrode 22 may overlap with the semiconductor laminate 10 in the Z direction. For example, the second pad electrode 22 is located on the opposite side of the semiconductor laminate 10 from the first pad electrode 21 in a plan view.

[0024] The lower electrode 23 is electrically connected to the second n-type semiconductor layer 12c. The lower electrode 23 is arranged, for example, below the semiconductor stack 10. In the light-emitting element 100, the lower electrode 23 is arranged at the bottom of the light-emitting element 100. In the light-emitting element 100, the lower electrode 23 is arranged below the semiconductor stack 10, the first pad electrode 21, the second pad electrode 22, the first electrode 31, the second electrode 32, the connection electrode 35, and the insulating layer 45. When mounting the light-emitting element 100 on a substrate or the like, the lower electrode 23 and the substrate are joined using a joining member such as a solder material.

[0025] The first pad electrode 21 and the second pad electrode 22 are each made of, for example, a metal material. Examples of the metal material that can be used include at least one of metals such as Ti (titanium), Pt (platinum), Rh (rhodium), Au (gold), Ni (nickel), Ta (tantalum), and Zr (zirconium), and alloys containing these metals. The first pad electrode 21 and the second pad electrode 22 may each be a single layer, or may be a laminate in which multiple layers are stacked. The first pad electrode 21 and the second pad electrode 22 may each be a laminate in which a Ti layer, a Pt layer, and an Au layer are stacked in this order, for example.

[0026] The lower electrode 23 is made of, for example, at least one of a metal material and a semiconductor material. The metal material may be the same as the metal material of the first pad electrode 21 and the second pad electrode 22. The semiconductor material may be, for example, Si. The lower electrode 23 may be, for example, a laminate in which a layer made of a semiconductor material is laminated on a metal layer.

[0027] The first electrode 31 electrically connects the second pad electrode 22 and the first n-type semiconductor layer 11c. The first electrode 31 is disposed inside the first opening 16. The first electrode 31 is not disposed inside the second opening 17. In the light-emitting element 100, the first electrode 31 extends from below the second pad electrode 22 to below the first n-type semiconductor layer 11c. In the light-emitting element 100, the first electrode 31 and the first n-type semiconductor layer 11c are in contact with each other at the first connection portion 31a, thereby electrically connecting the first electrode 31 and the first n-type semiconductor layer 11c.

[0028] The second electrode 32 electrically connects the lower electrode 23 and the second n-type semiconductor layer 12c. The second electrode 32 is disposed inside the first opening 16 and the second opening 17. In the light-emitting element 100, the second electrode 32 is disposed below the second n-type semiconductor layer 12c. In the light-emitting element 100, the second electrode 32 and the second n-type semiconductor layer 12c are in contact with each other at the second connection portion 32a, thereby electrically connecting the lower electrode 23 and the second n-type semiconductor layer 12c.

[0029] The connection electrode 35 electrically connects the first pad electrode 21 and the first p-type semiconductor layer 11a. In the light-emitting element 100, the connection electrode 35 extends from below the first pad electrode 21 to below the first p-type semiconductor layer 11a. In the light-emitting element 100, the connection electrode 35 and the first p-type semiconductor layer 11a are electrically connected via an interlayer electrode 25 located between the connection electrode 35 and the first p-type semiconductor layer 11a.

[0030] The first electrode 31, the second electrode 32, and the connection electrode 35 are each made of, for example, a metal material. Examples of the metal material include gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), nickel (Ni), tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), copper (Cu), indium (In), and lead (Pb), as well as alloys containing these metals. The first electrode 31, the second electrode 32, and the connection electrode 35 may each be a single layer or a laminated body having multiple layers stacked on top of each other. The first electrode 31, the second electrode 32, and the connection electrode 35 may each be a laminated body having a Ti layer, an Al alloy layer, a Ti layer, a Pt layer, an Au layer, and a Ti layer stacked in this order.

[0031] The insulating layer 45 is disposed between the first electrode 31 and the second electrode 32. The insulating layer 45 electrically insulates the first electrode 31 and the second electrode 32 from each other.

[0032] The insulating layer 45 is made of, for example, an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0033] The light-emitting element 100 further includes an interlayer insulating film 50. The interlayer insulating film 50 is disposed between the semiconductor stack 10 and the first electrode 31, between the semiconductor stack 10 and the second electrode 32, and between the semiconductor stack 10 and the connection electrode 35. A portion of the interlayer insulating film 50 is disposed inside the first opening 16 between the semiconductor stack 10 and the second electrode 32. A portion of the interlayer insulating film 50 surrounds the first electrode 31 in a plan view. Another portion of the interlayer insulating film 50 is disposed between the first electrode 31 and the connection electrode 35, electrically insulating the first electrode 31 from the connection electrode 35. Another portion of the interlayer insulating film 50 is disposed between the second electrode 32 and the connection electrode 35, electrically insulating the second electrode 32 from the connection electrode 35.

[0034] The interlayer insulating film 50 is made of, for example, an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0035] The light-emitting element 100 further includes a protective film 55. The protective film 55 is disposed on the semiconductor stack 10. The protective film 55 protects the semiconductor stack 10. For example, it is preferable that the thickness of the protective film 55 at a position where multiple convex portions on the top surface of the semiconductor stack 10 overlap is thinner than the thickness of the protective film 55 disposed at other positions. This can improve the light extraction efficiency of light emitted upward from the semiconductor stack 10.

[0036] The protective film 55 is made of, for example, an insulating material. The insulating material may be, for example, an oxide or nitride containing at least one element selected from the group consisting of Si (silicon), Ti (titanium), Zr (zirconium), Nb (niobium), Ta (tantalum), Al (aluminum), and Hf (hafnium). The insulating material may be, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0037] 1 and 2, in the light-emitting element 100, in a plan view, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at the first opening 16 is larger than the area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at the second opening 17. The area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at the second opening 17 is preferably, for example, 10% or more and less than 100% of the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at the first opening 16. Furthermore, when the semiconductor stack 10 has a plurality of first openings 16 and a plurality of second openings 17, the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at the plurality of first openings 16 is preferably larger than the total area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at the plurality of second openings 17. When the semiconductor laminate 10 has a plurality of first openings 16 and a plurality of second openings 17, it is more preferable that, in a planar view, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in each of the plurality of first openings 16 is larger than the area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other in each of the plurality of second openings 17.

[0038] In the light emitting device 100, the areas of the multiple first openings 16 are the same in a plan view. In the light emitting device 100, the areas of the multiple second openings 17 are the same in a plan view. In a plan view, the areas of the multiple first openings 16 may be different from each other. In a plan view, the areas of the multiple second openings 17 may be different from each other.

[0039] FIG. 3 is a cross-sectional view showing a current path in the light-emitting element according to the first embodiment in the first light-emitting state. FIG. 4 is a cross-sectional view showing a current path in the light-emitting element according to the first embodiment in the second light-emitting state. FIG. 5 is a cross-sectional view showing a current path in the light-emitting element according to the first embodiment in the third light-emitting state. As shown in FIGS. 3 to 5, the light emitting device 100 can emit light in three light emitting states: a first light emitting state, a second light emitting state, and a third light emitting state.

[0040] The first light-emitting state is a state in which both the first active layer 11b and the second active layer 12b emit light. FIG. 3 shows a current path in the first light-emitting state. As shown in FIG. 3, in the first light-emitting state, the first pad electrode 21 functions as a positive electrode, and the lower electrode 23 functions as a negative electrode. Current flows from the first pad electrode 21 through the connection electrode 35, the interlayer electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, and the second electrode 32 to the lower electrode 23. This causes both the first active layer 11b and the second active layer 12b to emit light.

[0041] The second light-emitting state is a state in which the first active layer 11b emits light without causing the second active layer 12b to emit light. FIG. 4 shows a current path in the second light-emitting state. As shown in FIG. 4, in the second light-emitting state, the first pad electrode 21 functions as a positive electrode and the second pad electrode 22 functions as a negative electrode. Current flows from the first pad electrode 21 through the connection electrode 35, the interlayer electrode 25, the first p-type semiconductor layer 11a, the first active layer 11b, the first n-type semiconductor layer 11c, the first electrode 31, and the connection electrode 35 to the second pad electrode 22. As a result, the second active layer 12b does not emit light, but the first active layer 11b emits light.

[0042] The third light-emitting state is a state in which the first active layer 11b does not emit light, but the second active layer 12b emits light. FIG. 5 shows a current path in the third light-emitting state. As shown in FIG. 5, in the third light-emitting state, the second pad electrode 22 functions as a positive electrode, and the lower electrode 23 functions as a negative electrode. Current flows from the second pad electrode 22 through the connection electrode 35, the first electrode 31, the first n-type semiconductor layer 11c, the intermediate layer 13, the second p-type semiconductor layer 12a, the second active layer 12b, the second n-type semiconductor layer 12c, and the second electrode 32 to the lower electrode 23. As a result, the first active layer 11b does not emit light, but the second active layer 12b emits light.

[0043] When negative electrodes are disposed corresponding to the first active layer 11b and the second active layer 12b, if the distance between the negative electrodes is large, the current density differs between the first active layer 11b and the second active layer 12b, which tends to cause a bias in the light emission distribution. In contrast, in the light-emitting device 100, the second opening 17 is disposed at a position overlapping the first opening 16 in a planar view, the first electrode 31 is disposed inside the first opening 16, and the second electrode 32 is disposed inside the first opening 16 and the second opening 17. This reduces the distance between the first electrode 31, which functions as a negative electrode when the first active layer 11b emits light, and the second electrode 32, which functions as a negative electrode when the second active layer 12b emits light, thereby reducing the bias in the current density between the first active layer 11b and the second active layer 12b. This reduces the bias in the light emission distribution between the first active layer 11b and the second active layer 12b.

[0044] Furthermore, when the second active layer 12b is caused to emit light, as in the third light-emitting state, the forward voltage VF is likely to be high due to the presence of the intermediate layer 13 in the current path. Furthermore, in the case of a light-emitting device 100 using a semiconductor stack 10 in which the second n-type semiconductor layer 12c, the second active layer 12b, the second p-type semiconductor layer 12a, the first n-type semiconductor layer 11c, the first active layer 11b, and the first p-type semiconductor layer 11a are formed in this order on a growth substrate, the first active layer 11b tends to have poorer crystallinity than the second active layer 12b. Therefore, when the first active layer 11b is caused to emit light, as in the second light-emitting state, the forward voltage VF is likely to be higher than when the second active layer 12b is caused to emit light, as in the third light-emitting state. Therefore, in the light-emitting element 100, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact at the first opening 16 is made larger than the area where the second electrode 32 and the second n-type semiconductor layer 12c contact at the second opening 17, thereby reducing the forward voltage VF at the first electrode 31 and improving the light emission intensity in the second light-emitting state and the third light-emitting state.

[0045] Furthermore, in the light-emitting element 100, the second connector 32a is surrounded by the first connector 31a. This allows the first opening 16 and the second opening 17 to be positioned so as not to overlap in plan view, and allows the in-plane light emission distribution characteristics of the first active layer 11b and the second active layer 12b to be closer to each other than when the first opening 16 and the second opening 17 are positioned so as not to overlap each other and the first connector 31a and the second connector 32a are respectively positioned therein.

[0046] Furthermore, in the light-emitting device 100, for example, the light emission of the first active layer 11b and the light emission of the second active layer 12b can be controlled separately. Therefore, for example, when the peak wavelength of the light emitted by the first active layer 11b is different from the peak wavelength of the light emitted by the second active layer 12b, the light-emitting device can switch the peak wavelength by switching the active layer to emit light. Furthermore, for example, when the peak wavelength of the light emitted by the first active layer 11b is the same as the peak wavelength of the light emitted by the second active layer 12b, the first active layer 11b and the second active layer 12b can be alternately used by switching the active layer to emit light. This reduces the influence of heat generation in the first active layer 11b and the second active layer 12b compared to when a single active layer is used to emit light, and reduces the shift in peak wavelength due to heat generation in the semiconductor stack 10. For example, when the first active layer 11b and the second active layer 12b emit ultraviolet light, the first active layer 11b and the second active layer 12b are susceptible to the effects of heat generation, and therefore, it is particularly effective to reduce the effects of heat generation by switching the active layer that emits light.

[0047] (Variation) FIG. 6 is a plan view showing a light emitting device according to a modified example of the first embodiment. FIG. 7 is a cross-sectional view showing a light emitting device according to a modified example of the first embodiment. FIG. 7 shows a cross section taken along line VII-VII in FIG. 6 and 7, the light emitting device 100A according to the modification of the first embodiment differs from the light emitting device 100 in the shapes of the first opening 16 and the second opening 17 and the positions of the first connecting portion 31a and the second connecting portion 32a. In other respects, the light emitting device 100A is the same as the light emitting device 100 described above.

[0048] In the light emitting element 100A, the second opening 17 has a semicircular shape in plan view. Furthermore, in the light emitting element 100A, the second connection portion 32a is not surrounded by the first connection portion 31a.

[0049] In the light-emitting element 100A, the second opening 17 is also positioned so as to overlap the first opening 16 in a planar view, the first electrode 31 is positioned inside the first opening 16, and the second electrode 32 is positioned inside the first opening 16 and the second opening 17, thereby reducing the bias in the light emission distribution between the first active layer 11b and the second active layer 12b.

[0050] (Second embodiment) FIG. 8 is a plan view illustrating a light emitting device according to the second embodiment. FIG. 9 is a cross-sectional view illustrating a light emitting device according to the second embodiment. FIG. 9 shows a cross section taken along line IX-IX shown in FIG. 8 and 9, the light emitting device 200 according to the second embodiment is different from the above-described light emitting device 100 mainly in that the semiconductor laminate 10 further includes a third opening 18 and a third electrode 33. In other respects, the light emitting device 200 has substantially the same structure as the above-described light emitting device 100.

[0051] 8 and 9, in a plan view, the semiconductor laminate 10 has a first region 10x and a second region 10y. The second region 10y does not overlap with the first region 10x in a plan view. The first opening 16 and the second opening 17 are located in the first region 10x. The third opening 18 is located in the second region 10y. The third opening 18 does not overlap with the first opening 16 and the second opening 17 in a plan view.

[0052] The third opening 18 is disposed contiguously with the first p-type semiconductor layer 11a and the first active layer 11b. The third opening 18 is a hole that penetrates the first p-type semiconductor layer 11a and the first active layer 11b in the Z direction. In the light-emitting device 200, the third opening 18 is disposed contiguously with the first p-type semiconductor layer 11a, the first active layer 11b, and the first n-type semiconductor layer 11c. In the light-emitting device 200, the third opening 18 is a hole that penetrates the first p-type semiconductor layer 11a and the first active layer 11b in the Z direction and reaches the first n-type semiconductor layer 11c. The third opening 18 does not penetrate the first n-type semiconductor layer 11c. In the light-emitting device 200, the semiconductor stack 10 has a plurality of third openings 18. In the light-emitting device 200, the semiconductor stack 10 has at least one third opening 18.

[0053] In the light emitting element 200, the shape of the third opening 18 is a perfect circle in a plan view. In a plan view, the shape of the third opening 18 may be a semicircle, an ellipse, a polygon, or the like.

[0054] The third electrode 33 electrically connects the second pad electrode 22 and the first n-type semiconductor layer 11c. The third electrode 33 is disposed inside the third opening 18. The third electrode 33 is connected to the first electrode 31. The third electrode 33 is substantially the same electrode as the first electrode 31, except that it is disposed inside the third opening 18. In other words, the third electrode 33 is an electrode that corresponds to the first electrode 31 in the second region 10y. In the light-emitting element 200, the third electrode 33 and the first n-type semiconductor layer 11c are electrically connected by being in contact with each other at the third connection portion 33a. The material of the third electrode 33 may be the same as the material of the first electrode 31.

[0055] 8, the semiconductor laminate 10 has one central region 10a, two intermediate regions 10b, and two outer regions 10c in a planar view. The central region 10a is located midway between the first pad electrode 21 and the second pad electrode 22 in a planar view. The central region 10a includes, for example, the center of the semiconductor laminate 10 in a planar view. The intermediate region 10b is located between the central region 10a and the first pad electrode 21 and between the central region 10a and the second pad electrode 22. The outer regions 10c are located between the intermediate region 10b and the first pad electrode 21 and between the intermediate region 10b and the second pad electrode 22.

[0056] In a plan view, a diagonal line DG of the light emitting element 200 passing through the first pad electrode 21 and the second pad electrode 22, which overlaps with the semiconductor laminate 10, is defined as a first line segment LS. Four straight lines perpendicular to the first line segment LS are defined as a first line IL1, a second line IL2, a third line IL3, and a fourth line IL4, from the first pad electrode 21 side. The first line segment LS is divided into five equal parts by the first line IL1, the second line IL2, the third line IL3, and the fourth line IL4. The central region 10a is a region of the semiconductor laminate 10 located between the second line IL2 and the third line IL3 in a plan view. The intermediate region 10b is a region of the semiconductor laminate 10 located between the first line IL1 and the second line IL2 and between the third line IL3 and the fourth line IL4 in a plan view. The outer region 10c is a region of the semiconductor laminate 10 that is located, in a plan view, between the first line IL1 and the outer edge 10e of the semiconductor laminate 10 and between the fourth line IL4 and the outer edge 10e of the semiconductor laminate 10. The outer region 10c is located more outer than the intermediate region 10b with respect to the center of the semiconductor laminate 10.

[0057] The second region 10y is located, for example, in the central region 10a. In the light-emitting element 200, the second region 10y is located in the central region 10a, but not in the intermediate region 10b or the outer region 10c. That is, in the light-emitting element 200, the third electrode 33 is in contact with the first n-type semiconductor layer 11c in the central region 10a, but not in contact with the first n-type semiconductor layer 11c in the intermediate region 10b or the outer region 10c. In addition, in the light-emitting element 200, the first region 10x is located in the central region 10a, the intermediate region 10b, and the outer region 10c. That is, in the light-emitting element 200, the first electrode 31 is in contact with the first n-type semiconductor layer 11c in the central region 10a, the intermediate region 10b, and the outer region 10c. In the light-emitting element 200, the second electrode 32 is in contact with the second n-type semiconductor layer 12c in the central region 10a, the intermediate region 10b, and the outer region 10c.

[0058] Furthermore, in the light emitting element 200, a plurality of first openings 16 and a plurality of third openings 18 are alternately arranged in the central region 10a. The arrangement of the first openings 16 and the third openings 18 is not limited to this, and, for example, two or more third openings 18 may be arranged between two first openings 16, or a portion between two first openings 16 where one third opening 18 is arranged and a portion between two first openings 16 where two or more third openings 18 are arranged may be included.

[0059] Furthermore, in the light-emitting element 200, a plurality of second openings 17 and a plurality of third openings 18 are alternately arranged in the central region 10a. The arrangement of the second openings 17 and the third openings 18 is not limited to this, and, for example, two or more third openings 18 may be arranged between two second openings 17, or a portion where one third opening 18 is arranged between two second openings 17 and a portion where two or more third openings 18 are arranged between two second openings 17 may be included.

[0060] Thus, in the light-emitting element 200, the first opening 16 and the second opening 17 are located in the first region 10x, the third opening 18 is located in the second region 10y that does not overlap with the first region 10x in a planar view, and the third electrode 33 is disposed inside the third opening 18. In the case of the light-emitting element 200 using a semiconductor stack in which the second n-type semiconductor layer 12c, the second active layer 12b, the second p-type semiconductor layer 12a, the first n-type semiconductor layer 11c, the first active layer 11b, and the first p-type semiconductor layer 11a are formed in this order on a growth substrate, the first p-type semiconductor layer 11a, the first active layer 11b, and the first n-type semiconductor layer 11c are likely to have poorer crystallinity and be darker than the second p-type semiconductor layer 12a, the second active layer 12b, and the second n-type semiconductor layer 12c. Therefore, by arranging a third electrode 33 that contacts the first n-type semiconductor layer 11c separately from the first electrode 31, the area of ​​the electrode that contacts the first n-type semiconductor layer 11c can be increased, thereby improving the emission intensity when the first active layer 11b is made to emit light.

[0061] Furthermore, the central region 10a, where the distance between the first pad electrode 21 and the second pad electrode 22 is greater than in the intermediate region 10b or the outer region 10c, is likely to have a lower current density than in the intermediate region 10b or the outer region 10c. Therefore, by arranging the third opening 18 (third electrode 33) in the second region 10y located in the central region 10a, it is possible to improve the emission intensity in the central region 10a, where the current density is likely to be lower than in the intermediate region 10b or the outer region 10c. This reduces the bias in the emission distribution within the plane of the semiconductor laminate 10.

[0062] (Variation) FIG. 10 is a plan view showing a light emitting device according to a modified example of the second embodiment. 10, in a light emitting device 200A according to a modification of the second embodiment, in plan view, the main difference from the light emitting device 200 is the arrangement of the first opening 16, the second opening 17, and the third opening 18. In other respects, the light emitting device 200A has substantially the same structure as the light emitting device 200 described above.

[0063] In the light-emitting element 200A, the second region 10y is located in the central region 10a, but is not located in the intermediate region 10b or the outer region 10c. That is, in the light-emitting element 200, the third electrode 33 is in contact with the first n-type semiconductor layer 11c in the central region 10a, but is not in contact with the first n-type semiconductor layer 11c in the intermediate region 10b or the outer region 10c. In the light-emitting element 200A, the first region 10x is located in the intermediate region 10b and the outer region 10c, but is not located in the central region 10a. That is, in the light-emitting element 200A, the first electrode 31 is in contact with the first n-type semiconductor layer 11c in the intermediate region 10b and the outer region 10c, but is not in contact with the first n-type semiconductor layer 11c in the central region 10a. In the light emitting element 200A, the second electrode 32 is in contact with the second n-type semiconductor layer 12c in the intermediate region 10b and the outer region 10c, but is not in contact with the second n-type semiconductor layer 12c in the central region 10a.

[0064] In the case of the light-emitting element 200A, when the light-emitting element 200A uses a semiconductor stack in which the second n-type semiconductor layer 12c, the second active layer 12b, the second p-type semiconductor layer 12a, the first n-type semiconductor layer 11c, the first active layer 11b, and the first p-type semiconductor layer 11a are formed in this order on a growth substrate, by disposing the third electrode 33 inside the third opening 18, the light emission intensity when the first active layer 11b is made to emit light can be improved.

[0065] (Third embodiment) FIG. 11 is a plan view illustrating a light emitting device according to the third embodiment. 11, the light emitting device 300 according to the third embodiment differs from the light emitting device 100 mainly in the area sizes of the first opening 16 and the second opening 17 in plan view. In other respects, the light emitting device 300 has substantially the same structure as the light emitting device 100 described above.

[0066] 11, in a plan view, the semiconductor laminate 10 has a central region 10a, an intermediate region 10b, and an outer region 10c. The positional relationship between the central region 10a, the intermediate region 10b, and the outer region 10c in the light emitting element 300 is the same as the positional relationship between the central region 10a, the intermediate region 10b, and the outer region 10c in the light emitting element 200 described above.

[0067] The first opening 16 has a plurality of first central openings 16a, a plurality of first intermediate openings 16b, and a plurality of first outer openings 16c. The plurality of first central openings 16a are each located in the central region 10a. The plurality of first intermediate openings 16b are each located in the intermediate region 10b. The plurality of first outer openings 16c are each located in the outer region 10c.

[0068] The second opening 17 has a plurality of second central openings 17a, a plurality of second intermediate openings 17b, and a plurality of second outer openings 17c. The plurality of second central openings 17a are each located in the central region 10a. The plurality of second intermediate openings 17b are each located in the intermediate region 10b. The plurality of second outer openings 17c are each located in the outer region 10c.

[0069] In the light emitting device 300, the areas of the first central openings 16a are each larger than the areas of the first intermediate openings 16b in a plan view. Also, the areas of the first intermediate openings 16b are each larger than the areas of the first outer openings 16c in a plan view.

[0070] In the light emitting device 300, the areas of the multiple first central openings 16a are the same in a plan view. In the light emitting device 300, the areas of the multiple first intermediate openings 16b are the same in a plan view. In the light emitting device 300, the areas of the multiple first outer openings 16c are the same in a plan view. In a plan view, the areas of the multiple first central openings 16a may be different from each other. In a plan view, the areas of the multiple first intermediate openings 16b may be different from each other. In a plan view, the areas of the multiple first outer openings 16c may be different from each other.

[0071] Here, the total area of ​​the first electrode 31 and the first n-type semiconductor layer 11c in each of the plurality of first central openings 16a in plan view is defined as a total area S SUM In addition, the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in each of the first intermediate openings 16b in plan view is defined as a total area S SUM In addition, the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in each of the first outer openings 16c in plan view is defined as a total area S SUM In the light emitting element 300, the total area S SUM a is the total area S SUM b is larger than (S SUM a>S SUM b). Also, the total area S SUM b is the total area S SUM c (S SUM b>S SUM c).

[0072] In the light emitting device 300, the areas of the second central openings 17a are each larger than the areas of the second intermediate openings 17b in a plan view. Also, the areas of the second intermediate openings 17b are each larger than the areas of the second outer openings 17c in a plan view.

[0073] In the light emitting device 300, the areas of the multiple second central openings 17a are the same in a plan view. In the light emitting device 300, the areas of the multiple second intermediate openings 17b are the same in a plan view. In the light emitting device 300, the areas of the multiple second outer openings 17c are the same in a plan view. In a plan view, the areas of the multiple second central openings 17a may be different from each other. In a plan view, the areas of the multiple second intermediate openings 17b may be different from each other. In a plan view, the areas of the multiple second outer openings 17c may be different from each other.

[0074] Here, in a plan view, the area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at one of the second central openings 17a is defined as area S2a. Furthermore, in a plan view, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at one of the first central openings 16a is defined as area S1a. Furthermore, in a plan view, the area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at one of the second intermediate openings 17b is defined as area S2b. Furthermore, in a plan view, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at one of the first intermediate openings 16b is defined as area S1b. Furthermore, in a plan view, the area where the second electrode 32 and the second n-type semiconductor layer 12c contact each other at one of the second outer openings 17c is defined as area S2c. In addition, the area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other at one of the plurality of first outer openings 16c in plan view is defined as area S1c. In the light-emitting element 300, the ratio of area S1a to area S2a (S1a / S2a) is the same as the ratio of area S1b to area S2b (S1b / S2b) and the ratio of area S1c to area S2c (S1c / S2c) (S1a / S2a=S1b / S2b=S1c / S2c).

[0075] Moreover, the central region 10a is likely to have a lower current density than the intermediate region 10b. Moreover, the intermediate region 10b is likely to have a lower current density than the outer region 10c. Therefore, in the light emitting device 300, the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first central opening 16a) located in the central region 10a (total area S SUMa) is calculated by dividing the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first intermediate opening 16b) located in the intermediate region 10b (total area S SUM b) and make it larger than the total area S SUM b is the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first outer opening 16c) located in the outer region 10c (total area S SUM c) is set to be larger than that of the outer regions 10c. This increases the current density in the intermediate region 10b, which tends to have a lower current density than the outer regions 10c, and further increases the current density in the central region 10a, which tends to have a lower current density than the intermediate region 10b. This reduces the bias in the light emission distribution within the plane of the semiconductor laminate 10.

[0076] In addition, in the light-emitting device 300, the ratio of the contact area between the electrode and the semiconductor layer at each opening in the central region 10a (S1a / S2a) is the same as the ratio of the contact area between the electrode and the semiconductor layer at each opening in the intermediate region 10b (S1b / S2b) and the ratio of the contact area between the electrode and the semiconductor layer at each opening in the outer region 10c (S1c / S2c). This reduces the bias in current density at each opening, and reduces deterioration of the semiconductor layer.

[0077] (Variation) FIG. 12 is a plan view illustrating a light emitting device according to a modified example of the third embodiment. 12, the light emitting device 300A according to the modification of the third embodiment is different from the light emitting device 300 mainly in the area sizes of the first opening 16 and the second opening 17 in a plan view. In other respects, the light emitting device 300A has substantially the same structure as the light emitting device 300 described above.

[0078] As with the light emitting device 300 described above, in the light emitting device 300A, the areas of the first central openings 16a are each larger than the areas of the first intermediate openings 16b in a plan view. Furthermore, the areas of the first intermediate openings 16b are each larger than the areas of the first outer openings 16c in a plan view.

[0079] On the other hand, in the light emitting element 300A, the areas of the second central openings 17a are the same as the areas of the second intermediate openings 17b and the second outer openings 17c in plan view.

[0080] In the light-emitting element 300A, the ratio of the area S1a to the area S2a (S1a / S2a) is greater than the ratio of the area S1b to the area S2b (S1b / S2b) (S1a / S2a>S1b / S2b). Also, the ratio of the area S1b to the area S2b (S1b / S2b) is greater than the ratio of the area S1c to the area S2c (S1c / S2c) (S1b / S2b>S1c / S2c).

[0081] In addition, the total area S SUM a is the total area S SUM b is larger than (S SUM a>S SUM b). Also, the total area S SUM b is the total area S SUM c (S SUM b>S SUM c).

[0082] Also in the light emitting element 300A, the areas of the multiple first central openings 16a are the same in a plan view. Also in the light emitting element 300A, the areas of the multiple first intermediate openings 16b are the same in a plan view. Also in the light emitting element 300A, the areas of the multiple first outer openings 16c are the same in a plan view. In a plan view, the areas of the multiple first central openings 16a may be different from each other. In a plan view, the areas of the multiple first intermediate openings 16b may be different from each other. In a plan view, the areas of the multiple first outer openings 16c may be different from each other.

[0083] Also in the light emitting element 300A, the areas of the second central openings 17a are the same in a plan view. Also in the light emitting element 300A, the areas of the second intermediate openings 17b are the same in a plan view. Also in the light emitting element 300A, the areas of the second outer openings 17c are the same in a plan view. Also in the light emitting element 300A, the areas of the second central openings 17a may be different in a plan view. Also in the plan view, the areas of the second intermediate openings 17b may be different in a plan view. Also in the plan view, the areas of the second outer openings 17c may be different in a plan view.

[0084] In the light emitting device 300A, the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first central opening 16a) located in the central region 10a (total area S SUM a) is calculated by dividing the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first intermediate opening 16b) located in the intermediate region 10b (total area S SUM b) and make it larger than the total area S SUM b is the total area where the first electrode 31 and the first n-type semiconductor layer 11c contact each other in the first opening 16 (first outer opening 16c) located in the outer region 10c (total area S SUM This makes it possible to reduce the bias in the light emission distribution within the plane of the semiconductor laminate 10.

[0085] In the light emitting device 300A, the ratio of the contact area between the electrode and the semiconductor layer at each opening in the central region 10a (S1a / S2a) is set to be larger than the ratio of the contact area between the electrode and the semiconductor layer at each opening in the middle region 10b (S1b / S2b). Furthermore, the ratio of the contact area between the electrode and the semiconductor layer at each opening in the middle region 10b (S1b / S2b) is set to be larger than the ratio of the contact area between the electrode and the semiconductor layer at each opening in the outer region 10c (S1c / S2c). This reduces the bias in the light emission distribution within the surface of the semiconductor laminate 10.

[0086] (Manufacturing method) 13 to 17 are cross-sectional views illustrating a part of the method for manufacturing the light-emitting element according to the first embodiment. In the method for manufacturing the light-emitting element 100, first, a semiconductor stack 10 having a plurality of first openings 16 is formed on a growth substrate 80. Next, an interlayer electrode 25, a connection electrode 35, and an interlayer insulating film 50 are formed on the semiconductor stack 10. Next, a first electrode 31 is formed on the interlayer insulating film 50 and inside the first openings 16. Through these steps, a structure in which the first electrode 31 is formed in the first openings 16 is prepared, as shown in FIG.

[0087] Next, as shown in FIG. 14, a part of the first electrode 31 and a part of the semiconductor stack 10 located inside the first opening 16 are removed to form a second opening 17.

[0088] Next, as shown in FIG. 15, an insulating layer 45 is formed on the first electrode 31 and inside the second opening 17.

[0089] Next, as shown in FIG. 16, part of the insulating layer 45 is removed to expose part of the semiconductor laminate 10.

[0090] 17, the second electrode 32 is formed on the exposed semiconductor stack 10 and on the insulating layer 45. Next, the lower electrode 23 is formed on the second electrode 32.

[0091] Embodiments may include the following features.

[0092] (Configuration 1) a semiconductor laminate including a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a first opening disposed contiguously with the first p-type semiconductor layer and the first active layer, and a second opening disposed at a position overlapping with the first opening in a plan view and contiguously with the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, and the second active layer; a first electrode disposed inside the first opening and electrically connected to the first n-type semiconductor layer; a second electrode disposed inside the first opening and the second opening and electrically connected to the second n-type semiconductor layer; an insulating layer disposed between the first electrode and the second electrode and in contact with the first electrode and the second electrode; A light-emitting element comprising:

[0093] (Configuration 2) The light-emitting element described in configuration 1, wherein, in a planar view, the area where the first electrode and the first n-type semiconductor layer contact in the first opening is larger than the area where the second electrode and the second n-type semiconductor layer contact in the second opening.

[0094] (Configuration 3) The light-emitting element according to configuration 1 or 2, wherein, in a planar view, a second connection portion where the second electrode and the second n-type semiconductor layer contact in the second opening is surrounded by a first connection portion where the first electrode and the first n-type semiconductor layer contact in the first opening.

[0095] (Configuration 4) In a plan view, the semiconductor laminate has a first region and a second region that does not overlap with the first region, the first opening and the second opening are located in the first region, the semiconductor stack further includes the third opening located in the second region and arranged continuously with the first p-type semiconductor layer and the first active layer, 4. The light-emitting device according to any one of configurations 1 to 3, further comprising a third electrode disposed inside the third opening and electrically connected to the first n-type semiconductor layer.

[0096] (Configuration 5) a first pad electrode electrically connected to the first p-type semiconductor layer; a second pad electrode electrically connected to the second n-type semiconductor layer; Furthermore, In a plan view, the semiconductor laminate has a central region located midway between the first pad electrode and the second pad electrode, intermediate regions located between the central region and the first pad electrode and between the central region and the second pad electrode, and outer regions located between the intermediate region and the first pad electrode and between the intermediate region and the second pad electrode, 5. The light-emitting element of claim 4, wherein the second region is located in the central region.

[0097] (Configuration 6) a first pad electrode electrically connected to the first p-type semiconductor layer; a second pad electrode electrically connected to the second n-type semiconductor layer; Furthermore, In a plan view, the semiconductor laminate has a central region located midway between the first pad electrode and the second pad electrode, intermediate regions located between the central region and the first pad electrode and between the central region and the second pad electrode, and outer regions located between the intermediate region and the first pad electrode and between the intermediate region and the second pad electrode, the first opening includes a plurality of first central openings located in the central region, a plurality of first intermediate openings located in the intermediate region, and a plurality of first outer openings located in the outer region; a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first central openings is larger than a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first intermediate openings in a plan view; The light-emitting element according to any one of configurations 1 to 5, wherein, in a planar view, the total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first intermediate openings is greater than the total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first outer openings.

[0098] (Configuration 7) the second openings include a plurality of second central openings located in the central region, a plurality of second intermediate openings located in the intermediate region, and a plurality of second outer openings located in the outer region; 7. The light-emitting element according to claim 6, wherein, in a plan view, a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first central openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second central openings is the same as a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second outer openings to an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first outer openings.

[0099] (Configuration 8) the second openings include a plurality of second central openings located in the central region, a plurality of second intermediate openings located in the intermediate region, and a plurality of second outer openings located in the outer region; in a plan view, a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first central openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second central openings is larger than a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second intermediate openings, The light-emitting element according to configuration 6, wherein, in a planar view, a ratio of an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of second outer openings is greater than a ratio of an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of first outer openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second outer openings.

[0100] (Configuration 9) 9. The light-emitting device according to any one of configurations 1 to 8, wherein the area of ​​the second active layer is larger than the area of ​​the first active layer in a plan view.

[0101] As described above, according to the embodiment, a light emitting device is provided that can reduce the bias in the light emission distribution between the first active layer and the second active layer.

[0102] The above-described embodiments are examples of realizing the present invention, and the present invention is not limited to these embodiments. For example, the present invention also includes embodiments in which some components or steps are added, deleted, or modified in the above-described embodiments. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0103] 10: Semiconductor laminate 10a: Central area 10b: Middle area 10c: Outer area 10e: outer edge 10x: 1st area 10y: 2nd area 11a: first p-type semiconductor layer 11b: 1st active layer 11c: first n-type semiconductor layer 12a: second p-type semiconductor layer 12b: 2nd active layer 12c: Second n-type semiconductor layer 13: Middle class 16: First opening 16a: 1st central opening 16b: 1st intermediate opening 16c: 1st outer opening 17: Second opening 17a: 2nd central opening 17b: 2nd intermediate opening 17c: 2nd outer opening 18: Third opening 21: First pad electrode 22: Second pad electrode 23: Lower electrode 25: Interlayer electrode 31: 1st electrode 31a: First connection part 32:Second electrode 32a: Second connection part 33: Third electrode 33a: Third connection part 35: Connection electrode 45: Insulating layer 50: Interlayer insulating film 55:Protective film 80: Growth substrate 100, 100A, 200, 200A, 300, 300A: Light-emitting element DG: Diagonal IL1~IL4: 1st~4th line LS: First line segment

Claims

1. a semiconductor laminate including a first p-type semiconductor layer, a first active layer disposed on the first p-type semiconductor layer, a first n-type semiconductor layer disposed on the first active layer, an intermediate layer disposed on the first n-type semiconductor layer, a second p-type semiconductor layer disposed on the intermediate layer, a second active layer disposed on the second p-type semiconductor layer, and a second n-type semiconductor layer disposed on the second active layer, the semiconductor laminate having a first opening disposed contiguously with the first p-type semiconductor layer and the first active layer, and a second opening disposed at a position overlapping with the first opening in a plan view and contiguously with the first n-type semiconductor layer, the intermediate layer, the second p-type semiconductor layer, and the second active layer; a first electrode disposed inside the first opening and electrically connected to the first n-type semiconductor layer; a second electrode disposed inside the first opening and the second opening and electrically connected to the second n-type semiconductor layer; an insulating layer disposed between the first electrode and the second electrode and in contact with the first electrode and the second electrode; A light-emitting element comprising:

2. 2. The light-emitting element according to claim 1, wherein, in a planar view, an area where the first electrode and the first n-type semiconductor layer contact each other in the first opening is larger than an area where the second electrode and the second n-type semiconductor layer contact each other in the second opening.

3. 2. The light-emitting element according to claim 1, wherein, in a planar view, a second connection portion where the second electrode and the second n-type semiconductor layer contact in the second opening is surrounded by a first connection portion where the first electrode and the first n-type semiconductor layer contact in the first opening.

4. In a plan view, the semiconductor laminate has a first region and a second region that does not overlap with the first region, the first opening and the second opening are located in the first region, the semiconductor stack further includes the third opening located in the second region and arranged continuously with the first p-type semiconductor layer and the first active layer, The light-emitting element according to claim 1 , further comprising a third electrode disposed inside the third opening and electrically connected to the first n-type semiconductor layer.

5. a first pad electrode electrically connected to the first p-type semiconductor layer; a second pad electrode electrically connected to the second n-type semiconductor layer; Furthermore, In a plan view, the semiconductor laminate has a central region located midway between the first pad electrode and the second pad electrode, intermediate regions located between the central region and the first pad electrode and between the central region and the second pad electrode, and outer regions located between the intermediate region and the first pad electrode and between the intermediate region and the second pad electrode, The light-emitting device of claim 4 , wherein the second region is located in the central region.

6. a first pad electrode electrically connected to the first p-type semiconductor layer; a second pad electrode electrically connected to the second n-type semiconductor layer; Furthermore, In a plan view, the semiconductor laminate has a central region located midway between the first pad electrode and the second pad electrode, intermediate regions located between the central region and the first pad electrode and between the central region and the second pad electrode, and outer regions located between the intermediate region and the first pad electrode and between the intermediate region and the second pad electrode, the first opening includes a plurality of first central openings located in the central region, a plurality of first intermediate openings located in the intermediate region, and a plurality of first outer openings located in the outer region; a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first central openings is larger than a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first intermediate openings in a plan view; 2. The light-emitting element according to claim 1, wherein, in a planar view, a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first intermediate openings is greater than a total area where the first electrode and the first n-type semiconductor layer contact each other in each of the plurality of first outer openings.

7. the second openings include a plurality of second central openings located in the central region, a plurality of second intermediate openings located in the intermediate region, and a plurality of second outer openings located in the outer region; 7. The light-emitting element according to claim 6, wherein, in a planar view, a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first central openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second central openings is the same as a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second outer openings to an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first outer openings.

8. the second openings include a plurality of second central openings located in the central region, a plurality of second intermediate openings located in the intermediate region, and a plurality of second outer openings located in the outer region; in a plan view, a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first central openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second central openings is larger than a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second intermediate openings, 7. The light-emitting element according to claim 6, wherein, in a planar view, a ratio of an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of first intermediate openings to an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of second outer openings is greater than a ratio of an area where the first electrode and the first n-type semiconductor layer contact in one of the plurality of first outer openings to an area where the second electrode and the second n-type semiconductor layer contact in one of the plurality of second outer openings.

9. 9. The light-emitting device according to claim 1, wherein an area of ​​said second active layer is larger than an area of ​​said first active layer in a plan view.

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