Input / output circuit

Abstract

To enable a reduction of the number of input terminals to which a single-ended signal is input.SOLUTION: An input / output circuit comprises: a differential amplifier circuit configured to amplify a difference between a first input signal input to a first input terminal and a second input signal input to a second input terminal and output an amplified differential signal as a differential amplification signal; a mode designation signal input terminal configured to input a mode designation signal for designating which mode of the test mode and the normal mode is to be operated; and an output circuit that is connected to the first input terminal and an output terminal of the differential amplifier circuit, outputs a single-ended signal input to the first input terminal when the mode designation signal indicates the test mode, and outputs the differential amplification signal output from the differential amplifier circuit when the mode designation signal indicates the normal mode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The disclosed technology relates to an input / output circuit. [Background technology]

[0002] Patent Document 1 discloses an input / output circuit having a first load having one end coupled to a first reference voltage, a first MOS transistor having a drain end coupled to the other end of the first load, a second load having one end coupled to the first reference potential, a second MOS transistor having a drain end coupled to the other end of the second load, a third MOS transistor having a source end or a drain end connected between the source end of the first MOS transistor and the source end of the second MOS transistor, a first constant current source coupled between the source end of the first MOS transistor and a second reference potential, and a second constant current source coupled between the source end of the second MOS transistor and the second reference potential.

[0003] Patent Document 2 discloses a pin electronics circuit that receives a plurality of differential or single-ended input signals output from a device under test, the pin electronics circuit having a first input terminal provided for each channel to which the input signal of the corresponding channel is input, a second input terminal to which the input signal of the adjacent channel is input, and a strobe terminal to which a strobe signal from a timing generator of the corresponding channel is input, the pin electronics circuit having a comparator unit configured to be able to generate a first comparison signal obtained by comparing the signal of the first input terminal with a threshold voltage and latching it at the timing of the strobe signal, and a second comparison signal obtained by comparing the signal of the first input terminal with the signal of the second input terminal and latching it at the timing of the strobe signal, and the pin electronics circuit being configured to be able to switch between a mode in which each input signal is evaluated as a single-ended signal and a mode in which the input signals of the two adjacent channels are evaluated as differential signals for each of the two adjacent channels.

[0004] Patent Document 3 discloses a single-ended input / differential-ended output amplifier circuit including an input for receiving an input signal, an amplifier for amplifying the input signal including the first input into an amplified signal, a first gate connected to the first output, a first transistor for receiving the amplified signal having a first first terminal connected to the second output and a first second terminal connected to a first node, a second transistor having a second gate, a second first terminal connected to a third input and a second second terminal connected to the first node, a second capacitor connected between the second output and the second gate, a first resistor connected between the second output and a voltage source, a second resistor connected between the third output and the voltage source, and a single-ended input / differential-ended output conversion circuit for converting the amplified signal into a differential signal pair, the single-ended input / differential-ended output conversion circuit including a current source connected between the first node and ground.

[0005] Patent Document 4 discloses a circuit in which a compensation circuit is connected between a single-ended voltage input of a single-ended-differential amplifier circuit and a bias terminal of a differential stage, and a current that offsets a signal tail current is supplied to the bias terminal of the differential stage.

[0006] Patent Document 5 discloses an external input terminal that receives a single input signal, a first operational amplifier that receives the single input signal as an input to its inverting input terminal, a first feedback circuit provided between the output terminal and inverting input terminal of the first operational amplifier, a first reference voltage source, a first voltage divider circuit that divides a first reference voltage signal output from the first reference voltage source and outputs the divided signal to the non-inverting input terminal of the first operational amplifier, a second operational amplifier that receives an output signal from the first operational amplifier as an input to its inverting input terminal, a second feedback circuit provided between the output terminal and inverting input terminal of the second operational amplifier, a second reference voltage source, and the second reference voltage source. a second voltage divider circuit that divides a second reference voltage signal output from the first operational amplifier and outputs the voltage to the non-inverting input terminal of the second operational amplifier, a first external output terminal connected to the output terminal of the first operational amplifier, and a second external output terminal connected to the output terminal of the second operational amplifier, wherein the first reference voltage signal and the second reference voltage signal are set, or the circuit constants of the first voltage divider circuit and the second voltage divider circuit are set, so that the voltage value applied to the non-inverting input terminal of the second operational amplifier is twice the voltage value applied to the non-inverting input terminal of the first operational amplifier. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-239225 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-20924 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-235938 [Patent Document 4] Japanese Patent Application Publication No. 6-177668 [Patent Document 5] Japanese Patent Application Laid-Open No. 2008-5104 Summary of the Invention [Problem to be solved by the invention]

[0008] LSIs that convert video signals to a format suitable for the display and output them may use an MCP (Multi Chip Package) configuration that mounts large-capacity DRAM to support high resolution. When signals are exchanged between MCP chips at high speed, low-amplitude differential signals are used as strobe signals. When signals are exchanged at low speed, such as when reading the ID of an embedded chip during testing, large-amplitude single-ended signals are used.

[0009] In MCP semiconductor devices, the number of pads that can be probed with a tester during testing is limited. Also, if an input terminal dedicated to single-ended signals is provided for testing, the chip area of ​​the IO section will increase, which will increase costs.

[0010] The disclosed technology has been made to solve the above-mentioned problems, and aims to provide an input / output circuit that can reduce the number of input terminals to which single-ended signals are input. [Means for solving the problem]

[0011] An input / output circuit according to a first aspect includes a differential amplifier circuit that amplifies the difference between a first input signal input to a first input terminal and a second input signal input to a second input terminal and outputs the result as a differentially amplified signal; a mode designation signal input terminal to which a mode designation signal that designates whether the circuit will operate in a test mode or a normal mode is input; and an output circuit that is connected to the first input terminal and an output terminal of the differential amplifier circuit, and that outputs the single-ended signal input to the first input terminal when the mode designation signal indicates the test mode, and outputs the differentially amplified signal output from the differential amplifier circuit when the mode designation signal indicates the normal mode.

[0012] An input / output circuit according to a second aspect includes a differential amplifier circuit that amplifies the difference between a first input signal input to a first input terminal and a second input signal input to a second input terminal and outputs the result as a differentially amplified signal; a mode designation signal input terminal to which a mode designation signal that designates whether the circuit will operate in a test mode or a normal mode is input; and a switching circuit that is provided between the second input terminal and the differential amplifier circuit and that, when the mode designation signal indicates the test mode, disconnects the second input terminal from an input terminal of the differential amplifier circuit so that a single-ended signal input to the first input terminal is output from the differential amplifier circuit, and, when the mode designation signal indicates the normal mode, connects the second input terminal to the input terminal of the differential amplifier circuit so that the differentially amplified signal is output from the output terminal of the differential amplifier circuit. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view of a semiconductor device. [Figure 2] FIG. 2 is a circuit diagram of an input / output circuit according to the first embodiment. [Figure 3A] FIG. 4 is a waveform diagram of a single-ended signal input to a first input terminal. [Figure 3B] 3 is a waveform diagram of a first input signal input to a first input terminal and a second input signal input to a second input terminal. FIG. [Figure 4] FIG. 10 is a circuit diagram of an input / output circuit according to a second embodiment. [Figure 5] FIG. 10 is a circuit diagram of an input / output circuit according to a third embodiment. [Figure 6] FIG. 10 is a circuit diagram of an input / output circuit according to a fourth embodiment. [Figure 7] FIG. 4 is a waveform diagram of a single-ended signal input to a first input terminal. [Figure 8] FIG. 10 is a circuit diagram of an input / output circuit according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings.

[0015] First Embodiment

[0016] 1 is a plan view of a semiconductor device 10. The semiconductor device 10 is, as an example, an LSI that converts a video signal into a format suitable for a display and outputs the converted signal. The semiconductor device 10 employs an MCP configuration that includes a large-capacity DRAM to support high-resolution video signals.

[0017] Specifically, as shown in FIG. 1, the semiconductor device 10 includes analog circuits 14A, 14B, 14C, and 14D, IO circuits 16A, 16B, 16C, 16D, 16E, and 16F, and a logic circuit 18 mounted on a base chip 12. A DRAM 20 is mounted on the logic circuit 18. IO circuits 22A and 22B, which are data transmission sources, are mounted on the DRAM 20. The IO circuits 16A and 22A are connected by a signal line 24A, and the IO circuits 16B and 22B are connected by a signal line 24B. In the following description, the IO circuits 16A and 16B will be referred to as the IO circuit 16 when they are not distinguished from each other. The IO circuits 22A and 22B will be referred to as the IO circuit 22 when they are not distinguished from each other.

[0018] A low-amplitude differential signal is used as a strobe signal when signals are exchanged at high speed between the IO circuit 16 and the IO circuit 22. On the other hand, when signals are exchanged at low speed, such as when reading the ID of an embedded chip in test mode, a large-amplitude single-ended signal is used.

[0019] 2 shows the configuration of an IO circuit 16-1 according to the first embodiment. As shown in FIG. 2, the IO circuit 16-1, which is an example of an input / output circuit, includes a differential amplifier circuit 32, a mode designation signal input terminal 34, an enable signal output circuit 36, and an output circuit 38.

[0020] The differential amplifier circuit 32 amplifies the difference between the first input signal input to the first input terminal QS and the second input signal input to the second input terminal QSB, and outputs the amplified signal as a differentially amplified signal.

[0021] A mode designation signal tmode, which designates whether the semiconductor device 10 operates in a test mode or a normal mode, is input to the mode designation signal input terminal 34. The mode designation signal tmode is output, for example, from the logic circuit 18. Here, the normal mode is a mode in which the semiconductor device 10 operates while performing its original functions. The test mode is a mode in which, for example, the semiconductor device 10 is tested to determine whether there are any abnormalities in its operation.

[0022] In this embodiment, in the normal mode, a low level is input to the mode designation signal input terminal 34 as the mode designation signal tmode, and in the test mode, a high level is input to the mode designation signal input terminal 34 as the mode designation signal tmode.

[0023] In the normal mode, the first input signal is input from the IO circuit 22 to the first input terminal QS, and the second input signal is input from the IO circuit 22 to the second input terminal QSB.

[0024] In the test mode, a single-ended signal is input to the first input terminal QS from the IO circuit 22. That is, the first input terminal QS is used as an input terminal shared by both differential amplification and testing.

[0025] The enable signal output circuit 36 ​​outputs an enable signal to the differential amplifier circuit 32. The enable signal turns on the differential amplifier circuit 32 when the mode designation signal tmode indicates the normal mode, and turns off the differential amplifier circuit 32 when the mode designation signal tmode indicates the test mode. The enable signal output circuit 36 ​​is, for example, configured with a NOT circuit.

[0026] The output circuit 38 is connected to the first input terminal QS and the output terminal of the differential amplifier circuit 32, and when the mode designation signal tmode indicates the test mode, outputs the single-ended signal input to the first input terminal QS to the logic circuit 18, and when the mode designation signal tmode indicates the normal mode, outputs the differentially amplified signal output from the output terminal of the differential amplifier circuit 32 to the logic circuit 18.

[0027] Specifically, the output circuit 38 is configured by, for example, AND circuits 40A and 40B and an OR circuit 42.

[0028] The AND circuit 40A outputs to the OR circuit 42 the logical product of the mode designation signal tmode and the first input signal input to the first input terminal QS.

[0029] The AND circuit 40B outputs the logical product of the enable signal output from the enable signal output circuit 36 ​​and the differentially amplified signal output from the differential amplifier circuit 32 to the OR circuit 42.

[0030] The OR circuit 42 outputs to the logic circuit 18 the logical sum of the output signal output from the AND circuit 40A and the output signal output from the AND circuit 40B.

[0031] Therefore, when the mode designation signal tmode is at a high level, i.e., when the test mode is selected, the AND circuit 40A outputs the single-ended signal input to the first input terminal QS of the differential amplifier circuit 32 to the OR circuit 42. Also, in the test mode, the enable signal output circuit 36 ​​outputs a low level, which is the inverse of the mode designation signal tmode, to the differential amplifier circuit 32 and the AND circuit 40A. This turns off the differential amplifier circuit 32 and prevents it from operating. Also, since a low level signal is input from the enable signal output circuit 36, the AND circuit 40B outputs a low level to the OR circuit 42. Therefore, the OR circuit 42 outputs the single-ended signal input to the first input terminal QS to the logic circuit 18.

[0032] 3A shows the waveform of a single-ended signal input to the first input terminal QS in test mode. As shown in FIG. 3A, in test mode, a single-ended signal with a relatively large amplitude is input to the first input terminal QS. A fixed high or low level is input to the second input terminal QSB.

[0033] On the other hand, when the mode designation signal tmode is at a low level, i.e., when the normal mode is selected, the AND circuit 40A outputs a low level to the OR circuit 42 regardless of whether the signal input to the first input terminal QS is at a high level or a low level. Furthermore, when the test mode is selected, the enable signal output circuit 36 ​​outputs a high level to the differential amplifier circuit 32 and the AND circuit 40B. This turns on the differential amplifier circuit 32 and activates it. Furthermore, since a high level signal is input from the enable signal output circuit 36, the AND circuit 40B outputs the differentially amplified signal output from the differential amplifier circuit 32 to the OR circuit 42. Therefore, the OR circuit 42 outputs the differentially amplified signal to the logic circuit 18.

[0034] 3B shows the waveforms of the first input signal input to the first input terminal QS and the second input signal input to the second input terminal QSB in the normal mode. As shown in FIG. 3B, in the normal mode, the first input signal and the second input signal, each having a relatively small amplitude, are input to the first input terminal QS and the second input terminal QSB, respectively.

[0035] In this way, in this embodiment, instead of providing a dedicated input terminal to which a single-ended signal is input in test mode, the input terminal is also used to input a signal in normal mode, thereby reducing the number of input terminals and the number of terminals to which a tester probe is inserted during testing.

[0036] Furthermore, in the test mode, the differential amplifier circuit 32 is turned off and does not operate, so that power consumption in the test mode can be reduced.

[0037] Second Embodiment

[0038] Next, a second embodiment will be described. Note that the same parts as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0039] 4 shows an IO circuit 16-2 according to the second embodiment. The IO circuit 16-2 has a configuration in which a dummy circuit 38A is added to the IO circuit 16 described in the first embodiment.

[0040] The dummy circuit 38A has the same configuration as the output circuit 38, and is made up of AND circuits 50A and 50B and an OR circuit 52.

[0041] One input terminal of the AND circuit 50A is connected to the second input terminal QSB, and a second input signal is input thereto. The other input terminal of the AND circuit 50A and the two input terminals of the AND circuit are connected to the power supply Vss. The output terminal of the OR circuit 52 is open and not connected to anything.

[0042] Since the output circuit 38 and the dummy circuit 38A have the same configuration, they also have the same parasitic capacitance. By connecting the dummy circuit 38A, which has the same parasitic capacitance as the output circuit 38, to the second input terminal QSB in this way, load symmetry is achieved when the first input signal and the second input signal are input as differential signals to the differential amplifier circuit 32.

[0043] <Third embodiment>

[0044] Next, a third embodiment will be described. Note that the same parts as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0045] In the third embodiment, when the mode designation signal tmode indicates the test mode, a first single-ended signal is input to the first input terminal QS, and a second single-ended signal different from the first single-ended signal is input to the second input terminal QSB.

[0046] Fig. 5 shows an IO circuit 16-3 according to the third embodiment. The IO circuit 16-3 differs from the IO circuit 16 of Fig. 1 described in the first embodiment in the configuration of an output circuit 38B.

[0047] Specifically, the output circuit 38B has a configuration in which an AND circuit 40C and an OR circuit 42A are added to the output circuit 38 described in the first embodiment.

[0048] The AND circuit 40C outputs the logical product of the second single-ended signal output from the second input terminal QSB and the mode designation signal tmode to the OR circuit 42A.

[0049] The OR circuit 42A outputs to the logic circuit 18 the logical sum of the output signal output from the AND circuit 40C and the output signal output from the AND circuit 40B.

[0050] Therefore, when the mode designation signal tmode indicates the test mode, the output circuit 38B outputs the first single-ended signal input to the first input terminal QS and the second single-ended signal input to the second input terminal QSB to the logic circuit 18.

[0051] In this way, the IO circuit 16-3 can output different types of first and second single-ended signals to the logic circuit 18.

[0052] <Fourth embodiment>

[0053] Next, a fourth embodiment will be described. Note that the same parts as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0054] In the fourth embodiment, the test modes include a first test mode and a second test mode.

[0055] 6 shows an IO circuit 16-4 according to the fourth embodiment. The IO circuit 16-4 includes, as mode designation signal input terminals, a first mode designation signal input terminal 34 to which a first mode designation signal tmode is input and a second mode designation signal input terminal 34A to which a second mode designation signal tmode2 is input.

[0056] When the logic circuit 18 operates the IO circuit 16-4 in the first test mode, it sets the first mode designation signal tmode1 to a high level and sets the second mode designation signal tmode2 to a low level.

[0057] Furthermore, when the logic circuit 18 operates the IO circuit 16-4 in the second test mode, it sets the second mode designation signal tmode2 to a high level and sets the first mode designation signal tmode1 to a low level.

[0058] Furthermore, when the logic circuit 18 operates the IO circuit 16-4 in the normal mode, it sets the first mode designation signal tmode1 and the second mode designation signal tmode2 to a low level.

[0059] In addition, the IO circuit 16-4 is configured such that an enable signal output circuit 36A is provided instead of the enable signal output circuit 36 ​​of the IO circuit 16 described in the first embodiment, and an AND circuit 40C is added to the output circuit 38.

[0060] The enable signal output circuit 36A is configured with a NOR circuit. That is, the enable signal output circuit 36A outputs the NOR of the first mode designation signal tmode1 input to the first mode designation signal input terminal 34 and the second mode designation signal tmode2 input to the second mode designation signal input terminal 34A to the differential amplifier circuit 32 and the AND circuit 40B.

[0061] Therefore, in the first test mode, that is, when the first mode designation signal tmode1 is at a high level and the second mode designation signal tmode2 is at a low level, the enable signal output circuit 36A outputs a low level to the differential amplifier circuit 32 and the AND circuit 40B.

[0062] Similarly, in the second test mode, that is, when the second mode designation signal tmode2 is at a high level and the first mode designation signal tmode1 is at a low level, the enable signal output circuit 36A outputs a low level to the differential amplifier circuit 32 and the AND circuit 40B.

[0063] In the normal mode, that is, when the first mode designation signal tmode1 and the second mode designation signal tmode2 are at a low level, the enable signal output circuit 36A outputs a high level to the differential amplifier circuit 32 and the AND circuit 40B.

[0064] Therefore, the output circuit 38 is connected to the first input terminal QS, the second input terminal QSB, and the output terminal of the differential amplifier circuit 32, and when the combination of the first mode designation signal tmode1 and the second mode designation signal tmode2 indicates the first test mode, it outputs the single-ended signal input to the first input terminal QS to the logic circuit 18, when the combination of the first mode designation signal tmode1 and the second mode designation signal tmode2 indicates the second test mode, it outputs the single-ended signal input to the second input terminal QSB to the logic circuit 18, and when the combination of the first mode designation signal tmode1 and the second mode designation signal tmode2 indicates the normal mode, it outputs the differentially amplified signal output from the output terminal of the differential amplifier circuit 32 to the logic circuit 18.

[0065] The waveform of the first single-ended signal input to the first input terminal QS in the first test mode is the same as the waveform shown in Figure 3A. Figure 7 shows the waveform of the second single-ended signal input to the second input terminal QSB in the second test mode. A fixed high or low level is input to the first input terminal QS. The waveforms of the first input signal input to the first input terminal QS and the second input signal input to the second input terminal QSB in the normal mode are the same as the waveforms shown in Figure 3B.

[0066] As described above, in the fourth embodiment, compared to the case where dedicated input terminals for inputting two single-ended signals are provided, it is possible to reduce the number of terminals and the circuit area, and also to reduce the number of terminals to which probes of a tester are inserted during testing.

[0067] Fifth Embodiment

[0068] Next, a fifth embodiment will be described. Note that the same parts as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0069] 8 shows an IO circuit 16-5 according to the fifth embodiment. The IO circuit 16-5 includes a switching circuit 60 and a reference voltage generating circuit 62.

[0070] The switching circuit 60 is provided between the second input terminal QSB and the differential amplifier circuit 32, and when the mode designation signal tmode indicates the test mode, it cuts off the connection between the second input terminal QSB and the input terminal of the differential amplifier circuit 32 so that the single-ended signal input to the first input terminal QS is output from the differential amplifier circuit 32, and when the mode designation signal tmode indicates the normal mode, it switches the connection state between the second input terminal QSB and the input terminal of the differential amplifier circuit 32 so that the second input terminal QSB and the input terminal of the differential amplifier circuit 32 are connected so that the differentially amplified signal is output from the output terminal of the differential amplifier circuit 32.

[0071] Specifically, the switching circuit 60 includes a first switching circuit 60A and a second switching circuit 60B.

[0072] The first switching circuit 60A is provided between the second input terminal QSB and the differential amplifier circuit 32. The first switching circuit 60A is turned on when a high level is input from the enable signal output circuit 36, i.e., when the mode designation signal tmode is at a low level indicating normal mode, and is turned off when a low level is input from the enable signal output circuit 36, i.e., when the mode designation signal tmode is at a high level indicating test mode. Therefore, in normal mode, the first switching circuit 60A outputs the second input signal input to the second input terminal QSB to the differential amplifier circuit 32. On the other hand, in test mode, the first switching circuit 60A is turned off and cuts off the connection between the second input terminal QSB and the input terminal of the differential amplifier circuit 32, so that it does not output anything.

[0073] The second switching circuit 60B is provided between the reference voltage generating circuit 62 and the differential amplifier circuit 32. The second switching circuit 60B is turned off when the mode specifying signal tmode is at a low level indicating normal mode, and is turned on when the mode specifying signal tmode is at a high level indicating test mode. Therefore, in test mode, the second switching circuit 60B outputs the reference voltage Vref output from the reference voltage generating circuit 62 to the differential amplifier circuit 32. On the other hand, in normal mode, the second switching circuit 60B is turned off, disconnecting the reference voltage generating circuit 62 from the input terminal of the differential amplifier circuit 32 and therefore not outputting anything.

[0074] The waveform of the first single-ended signal input to the first input terminal QS in the test mode is the same as the waveform shown in Fig. 3A. Moreover, the waveforms of the first input signal input to the first input terminal QS and the second input signal input to the second input terminal QSB in the normal mode are the same as the waveforms shown in Fig. 3B.

[0075] Because the IO circuit 16-5 has the above-described configuration, the number of terminals can be reduced and the circuit area can be reduced compared to when a dedicated terminal for inputting a single-ended signal is provided. Furthermore, the number of terminals to which a tester probe is attached during testing can be reduced. Furthermore, because the differential amplifier circuit 32 operates even in test mode, the single-ended signal input to the first input terminal QS during test mode can be a small-amplitude signal and a high-speed signal.

[0076] It should be noted that the configurations, operations, etc. of the input / output circuits described in the above embodiments are merely examples, and needless to say, they can be modified according to circumstances within the scope of the present disclosure. [Explanation of symbols]

[0077] 10 Semiconductor device 16-1, 16-2, 16-3, 16-4, 16-5 IO circuit 18 Logic Circuits 32 Differential amplifier circuit 34 Mode specification signal input terminal 36, 36A Enable signal output circuit 38, 38B output circuit 38A Dummy Circuit 60 Switching circuit QS First input terminal QSB second input terminal

Claims

1. a differential amplifier circuit that amplifies a difference between a first input signal input to a first input terminal and a second input signal input to a second input terminal, and outputs the amplified difference signal as a differential amplified signal; a mode designation signal input terminal to which a mode designation signal is inputted to designate whether the device operates in a test mode or a normal mode; an output circuit connected to the first input terminal and an output terminal of the differential amplifier circuit, and configured to output a single-ended signal input to the first input terminal when the mode designation signal indicates the test mode, and to output the differentially amplified signal output from the differential amplifier circuit when the mode designation signal indicates the normal mode; An input / output circuit comprising:

2. A dummy circuit having the same configuration as the output circuit is connected to the second input terminal.

2. The input / output circuit according to claim 1.

3. when the mode designation signal indicates the test mode, a first single-ended signal is input to the first input terminal and a second single-ended signal is input to the second input terminal; When the mode designation signal indicates the test mode, the output circuit outputs a first single-ended signal input to the first input terminal and a second single-ended signal input to the second input terminal.

2. The input / output circuit according to claim 1.

4. the test modes include a first test mode and a second test mode; the mode designation signal input terminal includes a first mode designation signal input terminal to which a first mode designation signal is input and a second mode designation signal input terminal to which a second mode designation signal is input; the output circuit is connected to the first input terminal, the second input terminal, and the output end of the differential amplifier circuit, and outputs a single-ended signal input to the first input terminal when a combination of the first mode designation signal and the second mode designation signal indicates the first test mode, outputs a single-ended signal input to the second input terminal when a combination of the first mode designation signal and the second mode designation signal indicates the second test mode, and outputs the differentially amplified signal output from the output end of the differential amplifier circuit when a combination of the first mode designation signal and the second mode designation signal indicates the normal mode.

2. The input / output circuit according to claim 1.

5. an enable signal output circuit that outputs an enable signal to the differential amplifier circuit, the enable signal turning on the differential amplifier circuit when the mode designation signal indicates the normal mode and turning off the differential amplifier circuit when the mode designation signal indicates the test mode; 5. The input / output circuit according to claim 1, comprising:

6. a differential amplifier circuit that amplifies a difference between a first input signal input to a first input terminal and a second input signal input to a second input terminal, and outputs the amplified difference signal as a differential amplified signal; a mode designation signal input terminal to which a mode designation signal is inputted to designate whether the device operates in a test mode or a normal mode; a switching circuit that is provided between the second input terminal and the differential amplifier circuit, and that, when the mode designation signal indicates the test mode, interrupts the connection between the second input terminal and the input end of the differential amplifier circuit so that a single-ended signal input to the first input terminal is output from the differential amplifier circuit, and, when the mode designation signal indicates the normal mode, switches the connection state between the second input terminal and the input end of the differential amplifier circuit so that the second input terminal and the input end of the differential amplifier circuit are connected so that the differentially amplified signal is output from the output end of the differential amplifier circuit; An input / output circuit comprising:

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