Semiconductor device

Abstract

To provide a semiconductor device which enables reduction of noise caused by leakage current leaking to the outside while improving heat radiation performance of the device.SOLUTION: A semiconductor device A10 includes a first insulator layer 11, a first heat radiation layer 15, a first conductive layer 21, a second insulator layer 12, a second conductive layer 22, a third insulator layer 13, a second heat radiation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 has electric continuity with the first conductive layer 21 and is located at the opposite side of the first insulator layer 11 with reference to the first conductive layer 21. The second semiconductor element 32 has electric continuity with the second conductive layer 22 and is located between the second insulator layer 12 and the second conductive layer 22 in a first direction z. The second semiconductor element 32 has electric continuity with the first semiconductor element 31. The first conductive layer 21 includes a portion located between the first insulator layer 11 and the second insulator layer 12 in the first direction z.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, semiconductor devices incorporating multiple semiconductor elements having switching functions, such as MOSFETs and IGBTs, have been widely known. Such semiconductor devices are mainly used for power conversion. Patent Document 1 discloses an example of a semiconductor device incorporating multiple semiconductor elements having switching functions. In this semiconductor device, multiple wiring layers (metal patterns 4a, 4b) are arranged on the surface of an insulating substrate. Furthermore, in this semiconductor device, multiple wiring relay regions are arranged on the surface of the insulating substrate. Each of the multiple wiring relay regions, together with the multiple wiring layers, constitutes a conductive path of the semiconductor device.

[0003] The semiconductor device has a parasitic capacitance associated with one of the multiple wiring relay areas, which outputs AC power converted by the multiple semiconductor elements, and the insulating substrate that supports it. Voltage changes over time are relatively significant in the wiring relay area. When a conductor such as a heat sink is joined to the insulating substrate, such voltage changes and the parasitic capacitance cause leakage current from the heat sink. If the leakage current becomes larger, there is concern about noise affecting the surrounding area of ​​the semiconductor device. Therefore, a method for suppressing leakage current to the outside is desired. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-158787

[0005] [overview] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce noise caused by leakage current to the outside while improving the heat dissipation performance of the device.

[0006] The present disclosure provides a semiconductor device comprising: a first insulating layer; a first heat dissipation layer located on one side of the first insulating layer in a first direction; a first conductive layer located opposite the first heat dissipation layer relative to the first insulating layer; a second insulating layer located opposite the first insulating layer relative to the first conductive layer; a second conductive layer located opposite the first conductive layer relative to the second insulating layer; a third insulating layer located opposite the second insulating layer relative to the second conductive layer; a second heat dissipation layer located opposite the second conductive layer relative to the third insulating layer; a first semiconductor element located opposite the first insulating layer relative to the first conductive layer; and a second semiconductor element located between the second insulating layer and the second conductive layer in the first direction. The first semiconductor element has a first electrode and a second electrode electrically connected to the first conductive layer. The second semiconductor element has a third electrode electrically connected to the second electrode and a fourth electrode electrically connected to the second conductive layer. The second electrode and the third electrode have different polarities, and the first conductive layer includes a portion located between the first insulating layer and the second insulating layer in the first direction.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, showing the sealing resin through which the second heat dissipation layer, the third insulating layer, the second conductive layer, and the fourth insulating layer are not shown. [Figure 3] FIG. 3 is a plan view corresponding to FIG. 2, showing the second power terminal in perspective and omitting the fourth conductive layer. [Figure 4] FIG. 4 is a bottom view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. 5, showing the first semiconductor element and its vicinity. [Figure 11] FIG. 11 is a partially enlarged view of FIG. 5, showing the second semiconductor element and its vicinity. [Figure 12] FIG. 12 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, showing the sealing resin and omitting the second heat dissipation layer and the third insulating layer. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, showing the sealing resin and omitting the second heat dissipation layer, the third insulating layer, the second conductive layer, and the fourth insulating layer. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. [Figure 20] FIG. 20 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, showing the sealing resin and omitting the second heat dissipation layer, the third insulating layer, the second conductive layer, and the fourth insulating layer. [Figure 21]FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure, showing the sealing resin and omitting the second heat dissipation layer, the third insulating layer, the second conductive layer, and the fourth insulating layer. [Figure 24] FIG. 24 is a plan view corresponding to FIG. 23, showing the second power terminal in perspective and omitting the fourth conductive layer. [Figure 25] FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. [Figure 27] FIG. 27 is a plan view of the semiconductor device according to the sixth embodiment of the present disclosure, showing the sealing resin and omitting the second heat dissipation layer and the third insulating layer. [Figure 28] FIG. 28 is a cross-sectional view taken along line XXVIII-XXVIII in FIG. [Figure 29] FIG. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG.

[0009] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0010] [First embodiment] 1 to 11, a semiconductor device A10 according to a first embodiment of the present disclosure will be described. The semiconductor device A10 includes a first insulating layer 11 to a fourth insulating layer 14, a first heat dissipation layer 15, a second heat dissipation layer 16, a first conductive layer 21 to a fourth conductive layer 24, a first semiconductor element 31, a second semiconductor element 32, a first power terminal 41, a second power terminal 42, a third power terminal 43, and a sealing resin 60. The semiconductor device A10 further includes a first signal wiring 25 to a fourth signal wiring 28, a first signal terminal 44 to a fourth signal terminal 47, a plurality of first conductive members 481, a plurality of second conductive members 482, a third conductive member 483, a plurality of first wires 51 to a plurality of fourth wires 54, and a fifth wire 55 to an eighth wire 58. For ease of understanding, Fig. 2 shows a perspective view of the sealing resin 60 and omits the second heat dissipation layer 16, the third insulating layer 13, the second conductive layer 22, and the fourth insulating layer 14. For ease of understanding, Fig. 3 shows a perspective view of the second power terminal 42 compared to Fig. 2 and omits the fourth conductive layer 24. In Figs. 2 and 3, the outline of the penetrated sealing resin 60 is shown by an imaginary line (two-dot chain line). In Fig. 3, the penetrated second power terminal 42 is shown by an imaginary line.

[0011] In the description of the semiconductor device A10, for convenience, the normal direction to the first mounting surface 111 of the first insulating layer 11, which will be described later, is referred to as the "first direction z." The direction perpendicular to the first direction z is referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y." Furthermore, in the description of the semiconductor device A10, "overlapping" refers to two different elements, and includes cases where one element entirely overlaps the other, as well as cases where one element partially overlaps the other.

[0012] The semiconductor device A10 converts DC power applied to the first power terminal 41 and the second power terminal 42 into AC power using a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The converted AC power is input to a power supply target such as a motor from a third power terminal 43. The semiconductor device A10 constitutes part of a power conversion circuit such as an inverter.

[0013] As shown in FIGS. 5 to 8, the sealing resin 60 covers the plurality of first semiconductor elements 31 and the plurality of second semiconductor elements 32. The sealing resin 60 has electrical insulating properties. The sealing resin 60 is made of a material containing, for example, black epoxy resin. The sealing resin 60 has a top surface 61, a bottom surface 62, a first side surface 63, a second side surface 64, a third side surface 65, and a fourth side surface 66.

[0014] 5 to 8, the top surface 61 faces the same side in the first direction z as a first mounting surface 111 of the first insulating layer 11, which will be described later. The bottom surface 62 faces the opposite side to the top surface 61 in the first direction z.

[0015] As shown in FIGS. 1 and 4 to 6, the first side surface 63 and the second side surface 64 face opposite each other in the second direction x. The first side surface 63 and the second side surface 64 are connected to the top surface 61 and the bottom surface 62, respectively. As shown in FIGS. 1, 4, 7, and 8, the third side surface 65 and the fourth side surface 66 face opposite each other in the third direction y. The third side surface 65 and the fourth side surface 66 are connected to the top surface 61 and the bottom surface 62, respectively.

[0016] As shown in FIGS. 5 to 9, the first insulating layer 11 carries the first conductive layer 21, the first signal wiring 25, and the second signal wiring 26. The first insulating layer 11 is made of, for example, ceramics containing aluminum nitride (AlN). Alternatively, the first insulating layer 11 may be made of, for example, a material containing resin. The first insulating layer 11 has a first mounting surface 111 facing one side in the first direction z. The first mounting surface 111 faces the same side as the top surface 61 of the sealing resin 60 in the first direction z. The first mounting surface 111 is covered with the sealing resin 60.

[0017] As shown in FIGS. 5 to 9, the first heat dissipation layer 15 is located on one side of the first insulating layer 11 in the first direction z. The first heat dissipation layer 15 is bonded to the first insulating layer 11. As shown in FIG. 4, the first heat dissipation layer 15 is exposed to the outside from the bottom surface 62 of the sealing resin 60. When the semiconductor device A10 is in use, a heat sink (not shown) is bonded to the first heat dissipation layer 15. The first heat dissipation layer 15 contains copper. As viewed in the first direction z, the first heat dissipation layer 15 is located inward from the periphery 111A of the first mounting surface 111 of the first insulating layer 11. As viewed in the first direction z, the first heat dissipation layer 15 overlaps the first conductive layer 21 and the third conductive layer 23.

[0018] As shown in FIGS. 5 to 9 , the first conductive layer 21 is located on the opposite side of the first heat dissipation layer 15 from the first insulating layer 11 in the first direction z. The first conductive layer 21 is bonded to the first mounting surface 111 of the first insulating layer 11. The first conductive layer 21 has a plurality of first semiconductor elements 31 mounted thereon. The first conductive layer 21 contains copper. The first conductive layer 21 is covered with a sealing resin 60. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z.

[0019] As shown in FIGS. 5 to 9 , the second insulating layer 12 is located on the opposite side of the first insulating layer 11 in the first direction z with the first conductive layer 21 as a reference. The second insulating layer 12 carries the third conductive layer 23, the third signal wiring 27, and the fourth signal wiring 28. The second insulating layer 12 is laminated on the first conductive layer 21. The second insulating layer 12 is made of a material containing, for example, a resin. As shown in FIG. 3 , the second insulating layer 12 is located inward from the periphery 111A of the first mounting surface 111 of the first insulating layer 11 when viewed in the first direction z. The second insulating layer 12 has a second mounting surface 121 facing the same side as the first mounting surface 111 in the first direction z. The second mounting surface 121 is covered with a sealing resin 60.

[0020] As shown in FIGS. 5 to 9 , the second conductive layer 22 is located on the opposite side of the first conductive layer 21 in the first direction z with the second insulating layer 12 as the reference. As viewed in the first direction z, the second conductive layer 22 overlaps the first conductive layer 21. The second conductive layer 22 contains copper. The second conductive layer 22 is covered with a sealing resin 60. As viewed in the first direction z, the second conductive layer 22 includes a portion overlapping the first conductive layer 21 and a portion located outward from the first conductive layer 21.

[0021] As shown in FIGS. 5 to 9 , the third insulating layer 13 is located on the opposite side of the second insulating layer 12 in the first direction z with the second conductive layer 22 as a reference. The third insulating layer 13 is made of ceramics containing aluminum nitride, for example. Alternatively, the third insulating layer 13 may be made of a material containing resin, for example. The third insulating layer 13 is covered with a sealing resin 60. The second conductive layer 22 is bonded to the third insulating layer 13.

[0022] As shown in FIGS. 5 to 9, the second heat dissipation layer 16 is located on the opposite side of the third insulating layer 13 from the second conductive layer 22 in the first direction z. The second heat dissipation layer 16 is bonded to the third insulating layer 13. As shown in FIG. 1, the second heat dissipation layer 16 is exposed to the outside from a top surface 61 of the sealing resin 60. When the semiconductor device A10 is in use, a heat sink (not shown) is bonded to the second heat dissipation layer 16. The composition of the second heat dissipation layer 16 includes copper. When viewed in the first direction z, the second heat dissipation layer 16 overlaps the second conductive layer 22 and the fourth conductive layer 24.

[0023] As shown in FIGS. 5, 6, 8, and 9, the third conductive layer 23 is bonded to the second mounting surface 121 of the second insulating layer 12. Therefore, the third conductive layer 23 is located on the opposite side of the first conductive layer 21 from the second insulating layer 12 in the first direction z. The third conductive layer 23 carries a plurality of second semiconductor elements 32. The third conductive layer 23 contains copper. The third conductive layer 23 is covered with a sealing resin 60. As viewed in the first direction z, the entire third conductive layer 23 overlaps the first conductive layer 21 and the second conductive layer 22. A predetermined gap is provided between the third conductive layer 23 and the second conductive layer 22 in the first direction z.

[0024] As shown in FIGS. 5 to 7, the fourth insulating layer 14 is located on the opposite side of the second conductive layer 22 from the third insulating layer 13 in the first direction z. The fourth insulating layer 14 is laminated on the second conductive layer 22. The fourth insulating layer 14 is made of a material containing, for example, a resin. The fourth insulating layer 14 is covered with a sealing resin 60. The second conductive layer 22 includes a portion located between the third insulating layer 13 and the fourth insulating layer 14 in the first direction z.

[0025] As shown in FIGS. 5 to 7 , the fourth conductive layer 24 is located on the opposite side of the fourth insulating layer 14 from the second conductive layer 22 in the first direction z. The fourth conductive layer 24 is bonded to the fourth insulating layer 14. The fourth conductive layer 24 contains copper. The fourth conductive layer 24 is covered with a sealing resin 60. As viewed in the first direction z, the fourth conductive layer 24 entirely overlaps the first conductive layer 21 and the second conductive layer 22. As viewed in the first direction z, the fourth conductive layer 24 overlaps the third conductive layer 23. A predetermined distance is provided between the fourth conductive layer 24 and the first conductive layer 21 in the first direction z.

[0026] As shown in FIGS. 5 and 6 , the first signal wiring 25 is bonded to the first mounting surface 111 of the first insulating layer 11. Therefore, the first signal wiring 25 is located on the opposite side of the first heat dissipation layer 15 from the first insulating layer 11 in the first direction z. As shown in FIG. 3 , the first signal wiring 25 is located on the opposite side of the second semiconductor elements 32 from the first semiconductor elements 31 in the second direction x. The first signal wiring 25 extends in the third direction y. The first signal wiring 25 contains copper. The first signal wiring 25 is covered with a sealing resin 60.

[0027] As shown in FIGS. 5 and 6 , the second signal wiring 26 is bonded to the first mounting surface 111 of the first insulating layer 11. Therefore, the second signal wiring 26 is located on the opposite side of the first heat dissipation layer 15 from the first insulating layer 11 in the first direction z. The second signal wiring 26 is located between the first conductive layer 21 and the first signal wiring 25 in the second direction x. The second signal wiring 26 extends in the third direction y. The second signal wiring 26 contains copper. The second signal wiring 26 is covered with a sealing resin 60.

[0028] As shown in FIGS. 5 and 6 , the third signal wiring 27 is bonded to the second mounting surface 121 of the second insulating layer 12. Therefore, the third signal wiring 27 is located on the opposite side of the first conductive layer 21 from the second insulating layer 12 in the first direction z. As shown in FIG. 3 , the third signal wiring 27 is located on the opposite side of the first semiconductor elements 31 from the multiple second semiconductor elements 32 in the second direction x. The third signal wiring 27 extends in the third direction y. The third signal wiring 27 contains copper. The third signal wiring 27 is covered with a sealing resin 60. When viewed in the first direction z, the third signal wiring 27 overlaps the first conductive layer 21.

[0029] As shown in FIGS. 5 and 6 , the fourth signal wiring 28 is bonded to the second mounting surface 121 of the second insulating layer 12. Therefore, the fourth signal wiring 28 is located on the opposite side of the fourth insulating layer 14 from the second insulating layer 12 in the first direction z. The fourth signal wiring 28 is located between the third conductive layer 23 and the third signal wiring 27 in the second direction x. The fourth signal wiring 28 extends in the third direction y. The fourth signal wiring 28 contains copper. The fourth signal wiring 28 is covered with a sealing resin 60. When viewed in the first direction z, the fourth signal wiring 28 overlaps the first conductive layer 21.

[0030] As shown in FIGS. 5 to 7 , the multiple first semiconductor elements 31 are located on the opposite side of the first conductive layer 21 in the first direction z with the first conductive layer 21 as a reference. The multiple first semiconductor elements 31 are bonded to the first conductive layer 21 while facing the first conductive layer 21 in the first direction z. Each of the multiple first semiconductor elements 31 is the same element. The multiple first semiconductor elements 31 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Alternatively, the multiple first semiconductor elements 31 may be field-effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) or bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). In the description of the semiconductor device A10, the multiple first semiconductor elements 31 are n-channel MOSFETs with a vertical structure. The multiple first semiconductor elements 31 include a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC) as a composition. The plurality of first semiconductor elements 31 are arranged along the third direction y.

[0031] As shown in FIG. 10, each of the plurality of first semiconductor elements 31 has a first electrode 311 , a second electrode 312 and a first control electrode 313 .

[0032] As shown in FIG. 10 , the first electrode 311 faces the first conductive layer 21. A current corresponding to the power before being converted by the first semiconductor element 31 flows through the first electrode 311. That is, the first electrode 311 corresponds to the drain of the first semiconductor element 31. The first electrode 311 is conductively bonded to the first conductive layer 21 via a conductive bonding layer 39. As a result, the first electrode 311 of each of the multiple first semiconductor elements 31 is electrically connected to the first conductive layer 21. The conductive bonding layer 39 is, for example, solder. Alternatively, the conductive bonding layer 39 may be a sintered body of metal particles. In this case, the metal particles contain, for example, silver (Ag).

[0033] 10 , the second electrode 312 is located on the opposite side to the first electrode 311 in the first direction z. A current corresponding to the power converted by the first semiconductor element 31 flows through the second electrode 312. In other words, the second electrode 312 corresponds to the source of the first semiconductor element 31.

[0034] 10, the first control electrode 313 is located on the same side as the second electrode 312 in the first direction z. A gate voltage for driving the first semiconductor element 31 is applied to the first control electrode 313. As shown in FIG. 2, the area of ​​the first control electrode 313 is smaller than the area of ​​the second electrode 312 when viewed in the first direction z.

[0035] As shown in FIGS. 5, 6, and 8, the multiple second semiconductor elements 32 are located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. The multiple second semiconductor elements 32 are bonded to the third conductive layer 23 while facing the third conductive layer 23 in the first direction z. Each of the multiple second semiconductor elements 32 is the same element as each of the multiple first semiconductor elements 31. Therefore, the multiple second semiconductor elements 32 are n-channel type MOSFETs with a vertical structure. The multiple second semiconductor elements 32 are arranged along the third direction y.

[0036] As shown in FIG. 11, each of the plurality of second semiconductor elements 32 has a third electrode 321, a fourth electrode 322 and a second control electrode 323.

[0037] 11 , the third electrode 321 faces the third conductive layer 23. A current corresponding to the power before being converted by the second semiconductor element 32 flows through the third electrode 321. That is, the third electrode 321 corresponds to the drain of the second semiconductor element 32. The polarity of the third electrode 321 is different from the polarity of the second electrode 312 of the first semiconductor element 31. The third electrode 321 is conductively bonded to the third conductive layer 23 via a conductive bonding layer 39. As a result, the third electrode 321 of each of the multiple second semiconductor elements 32 is electrically connected to the third conductive layer 23.

[0038] 11 , the fourth electrode 322 is located on the opposite side to the third electrode 321 in the first direction z. A current corresponding to the power converted by the second semiconductor element 32 flows through the fourth electrode 322. In other words, the fourth electrode 322 corresponds to the source of the second semiconductor element 32.

[0039] 11, the second control electrode 323 is located on the same side as the fourth electrode 322 in the first direction z. A gate voltage for driving the second semiconductor element 32 is applied to the second control electrode 323. As shown in FIG. 2, the area of ​​the second control electrode 323 is smaller than the area of ​​the fourth electrode 322 when viewed in the first direction z.

[0040] As shown in FIGS. 5 to 7 , the multiple first conductive members 481 are located between the multiple first semiconductor elements 31 and the fourth conductive layer 24 in the first direction z. As shown in FIGS. 7 and 10 , one side of each of the multiple first conductive members 481 in the first direction z is conductively bonded to the second electrode 312 of each of the multiple first semiconductor elements 31 via the conductive bonding layer 39. The other side of each of the multiple first conductive members 481 in the first direction z is conductively bonded to the fourth conductive layer 24 via the conductive bonding layer 39. As a result, the second electrode 312 of each of the multiple first semiconductor elements 31 is electrically connected to the fourth conductive layer 24. The multiple first conductive members 481 are covered with a sealing resin 60. Each of the multiple first conductive members 481 is a metal block. The metal block contains copper.

[0041] As shown in FIGS. 5, 6, and 8, the multiple second conductive members 482 are located between the multiple second semiconductor elements 32 and the second conductive layer 22 in the first direction z. As shown in FIGS. 8 and 11, one side of each of the multiple second conductive members 482 in the first direction z is individually conductively bonded to the fourth electrode 322 of each of the multiple second semiconductor elements 32 via the conductive bonding layer 39. The other side of each of the multiple second conductive members 482 in the first direction z is conductively bonded to the second conductive layer 22 via the conductive bonding layer 39. As a result, the second electrode 312 of each of the multiple second semiconductor elements 32 is electrically connected to the second conductive layer 22. The multiple second conductive members 482 are covered with a sealing resin 60. Each of the multiple second conductive members 482 is a metal block. The metal block contains copper.

[0042] As shown in FIGS. 5 , 6 , and 9 , the third conductive member 483 is located between the third conductive layer 23 and the fourth conductive layer 24 in the first direction z. As shown in FIG. 9 , one side of the third conductive member 483 in the first direction z is conductively bonded to the third conductive layer 23 via the conductive bonding layer 39. The other side of the third conductive member 483 in the first direction z is conductively bonded to the fourth conductive layer 24 via the conductive bonding layer 39. This establishes electrical continuity between the fourth conductive layer 24 and the third conductive layer 23. Furthermore, the second electrode 312 of each of the multiple first semiconductor elements 31 is conductively connected to the third electrode 321 of each of the multiple second semiconductor elements 32 via the fourth conductive layer 24, the third conductive member 483, and the third conductive layer 23. As viewed in the first direction z, the third conductive member 483 overlaps the first conductive layer 21 and the second conductive layer 22. 3, when viewed in the first direction z, the area of ​​the third conductive member 483 is larger than the area of ​​each of the multiple first conductive members 481 and the area of ​​each of the multiple second conductive members 482. The third conductive member 483 is covered with a sealing resin 60. The third conductive member 483 is a metal block. The metal block contains copper.

[0043] As shown in FIGS. 3 and 7 , the first power terminal 41 is conductively bonded to the first conductive layer 21. As a result, the first power terminal 41 is electrically connected to the first conductive layer 21 and the first electrodes 311 of the multiple first semiconductor elements 31. A portion of the first power terminal 41 protrudes to the outside from the third side surface 65 of the sealing resin 60. The first power terminal 41 is a P terminal (positive electrode) to which DC power, which is the target of power conversion, is applied. The first power terminal 41 contains copper. A first mounting hole 411 is provided in the first power terminal 41. The first mounting hole 411 is exposed to the outside from the sealing resin 60. The first mounting hole 411 penetrates the first power terminal 41 in the first direction z.

[0044] As shown in FIG. 8 , the second power terminal 42 is conductively bonded to the second conductive layer 22. As a result, the second power terminal 42 is electrically connected to the second conductive layer 22 and the fourth electrodes 322 of the plurality of second semiconductor elements 32. A portion of the second power terminal 42 protrudes to the outside from the third side surface 65 of the sealing resin 60. The second power terminal 42 is an N terminal (negative electrode) to which DC power to be converted is applied. The second power terminal 42 contains copper. A second mounting hole 421 is provided in the second power terminal 42. The second mounting hole 421 is exposed to the outside from the sealing resin 60. The second mounting hole 421 penetrates the second power terminal 42 in the first direction z.

[0045] As shown in FIGS. 3 and 9 , the third power terminal 43 is conductively bonded to the third conductive layer 23. As a result, the third power terminal 43 is electrically connected to the third conductive layer 23 and the fourth conductive layer 24, the second electrodes 312 of the multiple first semiconductor elements 31, and the third electrodes 321 of the multiple second semiconductor elements 32. A portion of the third power terminal 43 protrudes to the outside from a fourth side surface 66 of the sealing resin 60. AC power converted by the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 is output from the third power terminal 43. The third power terminal 43 contains copper. A third mounting hole 431 is provided in the third power terminal 43. The third mounting hole 431 is exposed to the outside from the sealing resin 60. The third mounting hole 431 penetrates the third power terminal 43 in the first direction z.

[0046] As shown in FIGS. 3 and 5 , the first signal terminal 44 is located on the opposite side of the second signal wiring 26 from the first signal wiring 25 in the second direction x. The first signal terminal 44 is electrically connected to the first control electrodes 313 of each of the multiple first semiconductor elements 31. A gate voltage for driving the multiple first semiconductor elements 31 is applied to the first signal terminal 44. The first signal terminal 44 is a metal lead containing copper. The first signal terminal 44 includes a portion that protrudes to the outside from the first side surface 63 of the sealing resin 60. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0047] As shown in FIGS. 3 and 10 , each of the multiple first wires 51 is conductively bonded to the first control electrode 313 of each of the multiple first semiconductor elements 31 and the first signal wiring 25. As shown in FIGS. 3 and 5 , the third wire 53 is conductively bonded to the first signal terminal 44 and the first signal wiring 25. This allows the first signal terminal 44 to be electrically connected to the first control electrode 313 of each of the multiple first semiconductor elements 31. The multiple first wires 51 and the third wire 53 are covered with a sealing resin 60. The composition of each of the multiple first wires 51 and the third wire 53 includes gold (Au). Alternatively, the composition of each of the multiple first wires 51 and the third wire 53 may include either aluminum or copper.

[0048] As shown in FIGS. 3 and 6 , the second signal terminal 45 is located on the opposite side of the second signal wiring 26 in the second direction x with respect to the first signal wiring 25. The second signal terminal 45 is located next to the first signal terminal 44 in the third direction y. The second signal terminal 45 is electrically connected to the second electrodes 312 of the multiple first semiconductor elements 31. A voltage having the same potential as the voltage applied to the second electrodes 312 of the multiple first semiconductor elements 31 is applied to the second signal terminal 45. The second signal terminal 45 is a metal lead containing copper. The second signal terminal 45 includes a portion protruding from the first side surface 63 of the sealing resin 60 to the outside. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0049] As shown in FIG. 3 , each of the multiple second wires 52 is conductively bonded to the second electrode 312 of each of the multiple first semiconductor elements 31 and the second signal wiring 26. As shown in FIGS. 3 and 6 , the fourth wire 54 is conductively bonded to the second signal terminal 45 and the second signal wiring 26. As a result, the second signal terminal 45 is electrically connected to the second electrode 312 of each of the multiple first semiconductor elements 31. The multiple second wires 52 and the fourth wire 54 are covered with a sealing resin 60. The composition of each of the multiple second wires 52 and the fourth wire 54 includes gold. Alternatively, the composition of each of the multiple second wires 52 and the fourth wire 54 may include either aluminum or copper.

[0050] As shown in FIGS. 3 and 5 , the third signal terminal 46 is located on the opposite side of the fourth signal wiring 28 in the second direction x with respect to the third signal wiring 27. The third signal terminal 46 is electrically connected to the second control electrodes 323 of each of the multiple second semiconductor elements 32. A gate voltage for driving the multiple second semiconductor elements 32 is applied to the third signal terminal 46. The third signal terminal 46 is a metal lead containing copper. The third signal terminal 46 includes a portion that protrudes to the outside from the second side surface 64 of the sealing resin 60. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0051] As shown in FIGS. 3 and 11 , each of the plurality of fifth wires 55 is conductively bonded to the second control electrode 323 of each of the plurality of second semiconductor elements 32 and the third signal wiring 27. As shown in FIGS. 2 and 5 , the seventh wire 57 is conductively bonded to the third signal terminal 46 and the third signal wiring 27. This allows the third signal terminal 46 to be electrically connected to the second control electrode 323 of each of the plurality of second semiconductor elements 32. The plurality of fifth wires 55 and the seventh wire 57 are covered with a sealing resin 60. The composition of each of the plurality of fifth wires 55 and the seventh wire 57 includes gold. Alternatively, the composition of each of the plurality of fifth wires 55 and the seventh wire 57 may include either aluminum or copper.

[0052] As shown in FIGS. 3 and 6 , the fourth signal terminal 47 is located on the opposite side of the fourth signal wiring 28 in the second direction x with respect to the third signal wiring 27. The fourth signal terminal 47 is located next to the third signal terminal 46 in the third direction y. The fourth signal terminal 47 is electrically connected to the fourth electrodes 322 of the second semiconductor elements 32. A voltage having the same potential as the voltage applied to the fourth electrodes 322 of the second semiconductor elements 32 is applied to the fourth signal terminal 47. The fourth signal terminal 47 is a metal lead containing copper. The fourth signal terminal 47 includes a portion protruding from the second side surface 64 of the sealing resin 60 to the outside. This portion includes a portion extending in the first direction z and a portion extending in the second direction x.

[0053] As shown in FIG. 3 , each of the sixth wires 56 is conductively bonded to the fourth electrode 322 of each of the second semiconductor elements 32 and the fourth signal wiring 28. As shown in FIGS. 3 and 6 , the eighth wire 58 is conductively bonded to the fourth signal terminal 47 and the fourth signal wiring 28. This allows the fourth signal terminal 47 to be electrically connected to the fourth electrode 322 of each of the second semiconductor elements 32. The sixth wires 56 and the eighth wire 58 are covered with a sealing resin 60. The sixth wires 56 and the eighth wires 58 each contain gold. Alternatively, the sixth wires 56 and the eighth wires 58 may each contain either aluminum or copper.

[0054] Next, the effects of the semiconductor device A10 will be described.

[0055] The semiconductor device A10 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 from the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. With this configuration, in the semiconductor device A10, heat generated by each of the first semiconductor element 31 and the second semiconductor element 32 is efficiently dissipated to the outside via the first heat dissipation layer 15 and the second heat dissipation layer 16. Furthermore, in the semiconductor device A10, a first parasitic capacitance C1 is formed, in which the conductive path between the second electrode 312 and the third electrode 321 and the first conductive layer 21 serve as conductor layers, and the second insulating layer 12 serves as a dielectric layer. This configuration suppresses leakage current from the first conductive layer 21 to the outside via the first insulating layer 11 in the semiconductor device A10. Therefore, with this configuration, it is possible to reduce noise caused by leakage current to the outside while improving the heat dissipation performance of the semiconductor device A10.

[0056] In the semiconductor device A10, an additional parasitic capacitance is formed with the first heat dissipation layer 15 and the first conductive layer 21 as conductor layers and the first insulating layer 11 as a dielectric layer. However, because there is almost no voltage change over time in the first conductive layer 21, the charge stored in the additional parasitic capacitance is almost zero. Therefore, even when the semiconductor device A10 includes the first heat dissipation layer 15, leakage current from the first conductive layer 21 to the outside via the first insulating layer 11 can be suppressed.

[0057] The semiconductor device A10 further includes a third conductive layer 23 located on the opposite side of the second insulating layer 12 from the first conductive layer 21. The third conductive layer 23 is electrically connected to the second electrode 312 of the first semiconductor element 31 and the third electrode 321 of the second semiconductor element 32. When viewed in the first direction z, the third conductive layer 23 overlaps the first conductive layer 21. With this configuration, the third conductive layer 23 corresponds to one of the conductor layers of the first parasitic capacitance C1 described above. This more appropriately ensures the capacitance of the first parasitic capacitance C1, thereby effectively reducing noise caused by leakage current to the outside.

[0058] The semiconductor device A10 further includes a fourth insulating layer 14 located on the opposite side of the second conductive layer 22 from the third insulating layer 13. The second conductive layer 22 includes a portion located between the third insulating layer 13 and the fourth insulating layer 14 in the first direction z. With this configuration, the semiconductor device A10 forms a second parasitic capacitance C2, in which the conductive path between the second electrode 312 and the third electrode 321 and the second conductive layer 22 serve as conductor layers and the fourth insulating layer 14 serves as a dielectric layer. This allows the semiconductor device A10 to suppress leakage current from the second conductive layer 22 to the outside via the third insulating layer 13.

[0059] The semiconductor device A10 further includes a fourth conductive layer 24 located on the opposite side of the fourth insulating layer 14 from the second conductive layer 22. The fourth conductive layer 24 is electrically connected to the third conductive layer 23. As viewed in the first direction z, the second conductive layer 22 overlaps the fourth conductive layer 24. With this configuration, the fourth conductive layer 24 corresponds to one conductor layer of the second parasitic capacitance C2 described above. This more appropriately ensures the capacitance of the second parasitic capacitance C2, thereby effectively reducing noise caused by leakage current to the outside.

[0060] The semiconductor device A10 further includes a third signal wiring 27 that is electrically connected to the second control electrode 323 of the second semiconductor element 32. The third signal wiring 27 is located on the opposite side of the second insulating layer 12 from the first conductive layer 21. When viewed in the first direction z, the third signal wiring 27 overlaps the first conductive layer 21. This configuration makes it possible to suppress external leakage current caused by voltage changes in the third signal wiring 27 over time.

[0061] When viewed in the first direction z, the second conductive layer 22 overlaps the first conductive layer 21. By adopting this configuration, it is possible to reduce the parasitic inductance in the semiconductor device A10.

[0062] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 12 to 14. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 12 shows a perspective view of the sealing resin 60, and does not illustrate the second heat dissipation layer 16 and the third insulating layer 13. In Figure 12, the outline of the sealing resin 60 is shown by imaginary lines.

[0063] In the semiconductor device A20, the configuration of the first conductive layer 21 differs from that of the semiconductor device A10.

[0064] As shown in FIGS. 13 and 14, the first conductive layer 21 includes a portion overlapping the second conductive layer 22 and a portion positioned outward from the second conductive layer 22 when viewed in the first direction z.

[0065] Next, the effects of the semiconductor device A20 will be described.

[0066] The semiconductor device A20 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 with respect to the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. Therefore, with this configuration, the semiconductor device A20 can also improve its heat dissipation performance while reducing noise caused by leakage current to the outside. Furthermore, the semiconductor device A20 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0067] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 15 to 19. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and redundant description will be omitted. For ease of understanding, FIG. 15 shows a view through the sealing resin 60, and omits the second heat dissipation layer 16, the third insulating layer 13, the second conductive layer 22, and the fourth insulating layer 14. In FIG. 15, the outline of the sealing resin 60 is shown by imaginary lines.

[0068] In the semiconductor device A30, the configurations of the first conductive layer 21 and the second conductive layer 22 are different from those of the semiconductor device A10.

[0069] As shown in FIGS. 16, 18, and 19, the first conductive layer 21 includes a first layer 21A and a second layer 21B spaced apart from each other in the first direction z. The first layer 21A is bonded to the first mounting surface 111 of the first insulating layer 11. The second layer 21B is located on the opposite side of the second insulating layer 12 from the third conductive layer 23, the third signal wiring 27, and the fourth signal wiring 28 in the first direction z. The second layer 21B is bonded to the second insulating layer 12. The second layer 21B is conductively bonded to the first layer 21A via a conductive bonding layer 39. As viewed in the first direction z, the first layer 21A includes a portion overlapping the second layer 21B and a portion located outward of the second layer 21B. The first electrode 311 of each of the multiple first semiconductor elements 31 is conductively bonded to the first layer 21A.

[0070] As shown in FIG. 16, the third conductive layer 23, the third signal wiring 27, and the fourth signal wiring 28 are each entirely overlapped with the first layer 21A and the second layer 21B.

[0071] As shown in FIGS. 16, 17, and 19, the second conductive layer 22 includes a third layer 22A and a fourth layer 22B that are spaced apart from each other in the first direction z. As viewed in the first direction z, the area of ​​the fourth layer 22B is smaller than the area of ​​the third layer 22A. The third layer 22A is bonded to the third insulating layer 13. The fourth layer 22B is located on the opposite side of the fourth conductive layer 24 from the fourth insulating layer 14 in the first direction z. The fourth layer 22B is bonded to the fourth insulating layer 14. The fourth layer 22B is conductively bonded to the fourth layer 22B via a conductive bonding layer 39. As viewed in the first direction z, the third layer 22A includes a portion overlapping the fourth layer 22B and a portion located outward of the fourth layer 22B. As shown in FIGS. 16 and 18, the plurality of second conductive members 482 are conductively bonded to the third layer 22A.

[0072] As shown in FIG. 16, the entire fourth conductive layer 24 overlaps the third layer 22A and the fourth layer 22B when viewed in the first direction z.

[0073] Next, the effects of the semiconductor device A30 will be described.

[0074] The semiconductor device A30 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 from the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. Therefore, with this configuration, the semiconductor device A30 can also improve its heat dissipation performance while reducing noise caused by leakage current to the outside. Furthermore, the semiconductor device A30 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0075] In the semiconductor device A30, the first conductive layer 21 includes a first layer 21A and a second layer 21B spaced apart from each other in the first direction z. The first layer 21A is bonded to the first insulating layer 11. The second layer 21B is bonded to the second insulating layer 12. The second layer 21B is conductively bonded to the first layer 21A. This configuration allows one element including the first insulating layer 11, the first heat dissipation layer 15, and the first layer 21A, and the other element including the second insulating layer 12, the second layer 21B, and the third conductive layer 23, to be easily obtained from a laminated substrate. A laminated substrate formed by active metal brazing (AMB), for example, can be used as the laminated substrate. This improves the manufacturing efficiency of the semiconductor device A30.

[0076] As viewed in the first direction z, the third conductive layer 23 overlaps the first layer 21A and the second layer 21B. This configuration more appropriately ensures the capacitance of the first parasitic capacitance C1 described above, effectively reducing noise caused by leakage current to the outside.

[0077] In the semiconductor device A30, the second conductive layer 22 includes a third layer 22A and a fourth layer 22B that are spaced apart from each other in the first direction z. The third layer 22A is bonded to the third insulating layer 13. The fourth layer 22B is bonded to the fourth insulating layer 14. The fourth layer 22B is conductively bonded to the third layer 22A. This configuration allows one element including the third insulating layer 13, the second heat dissipation layer 16, and the third layer 22A, and the other element including the fourth insulating layer 14, the fourth layer 22B, and the fourth conductive layer 24 to be easily obtained from a laminated substrate. This improves the manufacturing efficiency of the semiconductor device A30.

[0078] As viewed in the first direction z, the fourth conductive layer 24 overlaps the third layer 22A and the fourth layer 22B. This configuration more appropriately ensures the capacitance of the second parasitic capacitance C2 described above, effectively reducing noise caused by leakage current to the outside.

[0079] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 20 to 22. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and redundant description will be omitted. For ease of understanding, FIG. 20 shows a perspective view of the sealing resin 60, and omits illustration of the second heat dissipation layer 16, the third insulating layer 13, the second conductive layer 22, and the fourth insulating layer 14. In FIG. 20, the outline of the sealing resin 60 is shown by imaginary lines.

[0080] In the semiconductor device A40, the configurations of the first conductive layer 21, the third signal wiring 27, and the fourth signal wiring 28 are different from those of the semiconductor device A30 described above.

[0081] 21 and 22, the area of ​​each of the first layer 21A and the second layer 21B of the first conductive layer 21 is smaller than the corresponding area in the semiconductor device A30 when viewed in the first direction z. Accordingly, the area of ​​the second insulating layer 12 is reduced compared to that in the semiconductor device A30 when viewed in the first direction z.

[0082] 20 to 22, the third signal wiring 27 and the fourth signal wiring 28 are joined to the first mounting surface 111 of the first insulating layer 11. Therefore, in the first direction z, the first conductive layer 21 does not exist between the first insulating layer 11 and the third signal wiring 27 and the fourth signal wiring 28.

[0083] Next, the effects of the semiconductor device A40 will be described.

[0084] The semiconductor device A40 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 with respect to the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. Therefore, with this configuration, the semiconductor device A40 can also improve its heat dissipation performance while reducing noise caused by leakage current to the outside. Furthermore, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0085] In the semiconductor device A40, the third signal wiring 27 and the fourth signal wiring 28 are joined to the first insulating layer 11. This configuration makes it possible to reduce the dimensions of the second insulating layer 12 and the first layer 21A and second layer 21B of the first conductive layer 21. This allows for a reduction in the manufacturing cost of the semiconductor device A40.

[0086] Fifth Embodiment A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 23 to 26. In these figures, elements identical or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and redundant description will be omitted. For ease of understanding, FIG. 23 shows a perspective view of the sealing resin 60 and omits the second heat dissipation layer 16, the third insulating layer 13, the second conductive layer 22, and the fourth insulating layer 14. For ease of understanding, FIG. 24 shows a perspective view of the second power terminal 42 and omits the fourth conductive layer 24, in comparison with FIG. 23. In FIGS. 23 and 24, the outline of the sealing resin 60 is shown by imaginary lines. In FIG. 24, the second power terminal 42 is shown by imaginary lines.

[0087] In the semiconductor device A50, the configurations of the first conductive layer 21, the first signal wiring 25, and the second signal wiring 26 differ from those of the semiconductor device A30 described above.

[0088] 24 to 26, the area of ​​each of the first layer 21A and the second layer 21B of the first conductive layer 21 is larger than the corresponding area in the semiconductor device A30 when viewed in the first direction z. Accordingly, the area of ​​the second insulating layer 12 is larger than that in the semiconductor device A30 when viewed in the first direction z.

[0089] 24 to 26, the first signal wiring 25 and the second signal wiring 26 are bonded to the second mounting surface 121 of the second insulating layer 12. The first signal wiring 25 is located between the plurality of first semiconductor elements 31 and the third conductive member 483 in the second direction x. The second signal wiring 26 is located between the first signal wiring 25 and the third conductive member 483 in the second direction x. When viewed in the first direction z, the first signal wiring 25 and the second signal wiring 26 overlap the first layer 21A and the second layer 21B of the first conductive layer 21, respectively.

[0090] Next, the effects of the semiconductor device A50 will be described.

[0091] The semiconductor device A50 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 with respect to the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. Therefore, with this configuration, the semiconductor device A50 can also improve its heat dissipation performance while reducing noise caused by leakage current to the outside. Furthermore, the semiconductor device A50 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0092] The semiconductor device A50 further includes a first signal wiring 25 that is electrically connected to the first control electrode 313 of the first semiconductor element 31. The first signal wiring 25 is located on the opposite side of the second insulating layer 12 from the first layer 21A and the second layer 21B of the first conductive layer 21. When viewed in the first direction z, the first signal wiring 25 overlaps the first layer 21A and the second layer 21B. This configuration makes it possible to suppress external leakage current caused by voltage changes in the first signal wiring 25 over time.

[0093] Sixth Embodiment A semiconductor device A60 according to a sixth embodiment of the present disclosure will be described with reference to Figures 27 to 29. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 27 shows a perspective view of the sealing resin 60, and does not illustrate the second heat dissipation layer 16 and the third insulating layer 13. In Figure 27, the outline of the sealing resin 60 is shown by imaginary lines.

[0094] In the semiconductor device A60, the configurations of the first conductive layer 21 and the second conductive layer 22 differ from those of the semiconductor device A10.

[0095] 28 and 29, when viewed in the first direction z, the first conductive layer 21 entirely overlaps the second conductive layer 22. The second conductive layer 22 entirely overlaps the first conductive layer 21.

[0096] Next, the effects of the semiconductor device A60 will be described.

[0097] The semiconductor device A60 includes a first insulating layer 11, a first heat dissipation layer 15, a first conductive layer 21, a second insulating layer 12, a second conductive layer 22, a third insulating layer 13, a second heat dissipation layer 16, a first semiconductor element 31, and a second semiconductor element 32. The first semiconductor element 31 is located on the opposite side of the first insulating layer 11 with respect to the first conductive layer 21. The second semiconductor element 32 is located between the second insulating layer 12 and the second conductive layer 22 in the first direction z. A second electrode 312 of the first semiconductor element 31 is electrically connected to a third electrode 321 of the second semiconductor element 32. The first conductive layer 21 includes a portion located between the first insulating layer 11 and the second insulating layer 12 in the first direction z. Therefore, with this configuration, the semiconductor device A60 can also improve its heat dissipation performance while reducing noise caused by leakage current to the outside. Furthermore, the semiconductor device A60 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0098] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0099] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] A first insulating layer (11); a first heat dissipation layer (15) located on one side of the first insulating layer (11) in a first direction; a first conductive layer (21) located on the opposite side of the first insulating layer (11) from the first heat dissipation layer (15); a second insulating layer (12) located on the opposite side of the first insulating layer (11) with respect to the first conductive layer (21); a second conductive layer (22) located on the opposite side of the second insulating layer (12) from the first conductive layer (21); a third insulating layer (13) located on the opposite side of the second insulating layer (12) with respect to the second conductive layer (22); a second heat dissipation layer (16) located on the opposite side of the third insulating layer (13) from the second conductive layer (22); a first semiconductor element (31) having a first electrode (311) and a second electrode (312) and located on the opposite side of the first insulating layer (11) with respect to the first conductive layer (21); a second semiconductor element (32) having a third electrode (321) and a fourth electrode (322) and positioned between the second insulating layer (12) and the second conductive layer (22) in the first direction; The polarity of the second electrode (312) and the polarity of the third electrode (321) are different from each other, The first electrode (311) is electrically connected to the first conductive layer (21), The second electrode (312) is electrically connected to the third electrode (321), The fourth electrode (322) is electrically connected to the second conductive layer (22), The semiconductor device (A10) includes a portion of the first conductive layer (21) located between the first insulating layer (11) and the second insulating layer (12) in the first direction. [Appendix 2] The device further includes a third conductive layer (23) located on the opposite side of the second insulating layer (12) from the first conductive layer (21), the third conductive layer (23) is electrically connected to the second electrode (312) and the third electrode (321); The semiconductor device (A10) according to appendix 1, wherein the third conductive layer (23) overlaps the first conductive layer (21) when viewed in the first direction. [Appendix 3] A semiconductor device (A20) described in Appendix 2, wherein, when viewed in the first direction, the second conductive layer (22) includes a portion overlapping the first conductive layer (21) and a portion located outward from the first conductive layer (21). [Appendix 4] A semiconductor device (A20) described in Appendix 3, wherein, when viewed in the first direction, the first conductive layer (21) includes a portion overlapping the second conductive layer (22) and a portion located outward from the second conductive layer (22). [Appendix 5] The device further includes a fourth insulating layer (14) located on the opposite side of the second conductive layer (22) from the third insulating layer (13), A semiconductor device (A10) according to Appendix 2, wherein the second conductive layer (22) includes a portion located between the third insulating layer (13) and the fourth insulating layer (14) in the first direction. [Appendix 6] The semiconductor device further includes a fourth conductive layer (24) located on the opposite side of the fourth insulating layer (14) from the second conductive layer (22), the fourth conductive layer (24) is electrically connected to the third conductive layer (23), The semiconductor device (A10) according to appendix 5, wherein the second conductive layer (22) overlaps the fourth conductive layer (24) when viewed in the first direction. [Appendix 7] A semiconductor device (A10) described in Appendix 6, wherein, when viewed in the first direction, the entire third conductive layer (23) and the entire fourth conductive layer (24) overlap the entire first conductive layer (21) and the entire second conductive layer (22). [Appendix 8] The semiconductor device (A10) according to appendix 7, wherein the fourth conductive layer (24) overlaps the third conductive layer (23) when viewed in the first direction. [Appendix 9] the third conductive layer (23) is bonded to the second insulating layer (12); the fourth conductive layer (24) is bonded to the fourth insulating layer (14); the first electrode (311) is located on the opposite side of the second electrode (312) in the first direction and is conductively joined to the first conductive layer (21); A semiconductor device (A10) described in Appendix 8, wherein the third electrode (321) is located on the opposite side of the fourth electrode (322) in the first direction and is conductively connected to the third conductive layer (23). [Appendix 10] The device further includes a first conductive member (481) conductively connected to the second electrode (312) and the fourth conductive layer (24), The semiconductor device (A10) according to appendix 9, wherein the first conductive member (481) is located between the second electrode (312) and the fourth conductive layer (24) in the first direction. [Appendix 11] The device further includes a second conductive member (482) conductively connected to the fourth electrode (322) and the second conductive layer (22), The semiconductor device (A10) according to appendix 10, wherein the second conductive member (482) is located between the fourth electrode (322) and the second conductive layer (22) in the first direction. [Appendix 12] The device further includes a third conductive member (483) conductively joined to the third conductive layer (23) and the fourth conductive layer (24), The semiconductor device (A10) according to appendix 11, wherein the third conductive member (483) is located between the third conductive layer (23) and the fourth conductive layer (24) in the first direction. [Appendix 13] A semiconductor device (A10) according to Appendix 12, wherein, when viewed in the first direction, the area of ​​the third conductive member (483) is larger than the area of ​​each of the first conductive member (481) and the second conductive member (482). [Appendix 14] Further provided with a first signal wiring (25), the first semiconductor element (31) has a first control electrode (313) located on the same side as the second electrode (312) in the first direction; The semiconductor device (A10) according to appendix 9, wherein the first control electrode (313) is electrically connected to the first signal wiring (25). [Appendix 15] the first signal wiring (25) is located on the opposite side of the second insulating layer (12) from the first conductive layer (21); The semiconductor device (A50) according to appendix 14, wherein the first signal wiring (25) overlaps the first conductive layer (21) when viewed in the first direction. [Appendix 16] the first conductive layer (21) includes a first layer (21A) and a second layer (21B) spaced apart from each other in the first direction; the first layer (21A) is bonded to the first insulating layer (11); the second layer (21B) is bonded to the second insulating layer (12); The semiconductor device (A30) according to appendix 9, wherein the second layer (21B) is conductively joined to the first layer (21A). [Appendix 17] The semiconductor device (A30) according to appendix 16, wherein the first electrode (311) is conductively joined to the first layer (21A). [Appendix 18] the second conductive layer (22) includes a third layer (22A) and a fourth layer (22B) spaced apart from each other in the first direction; the third layer (22A) is bonded to the third insulating layer (13); the fourth layer (22B) is bonded to the fourth insulating layer (14); The semiconductor device (A30) according to appendix 17, wherein the fourth layer (22B) is conductively joined to the third layer (22A). [Appendix 19] The semiconductor device (A30) described in Appendix 18, wherein, when viewed in the first direction, the third layer (22A) includes a portion overlapping the fourth layer (22B) and a portion located outward from the fourth layer (22B). [Appendix 20] further comprising a sealing resin (60) that covers the first semiconductor element (31) and the second semiconductor element (32); 20. The semiconductor device (A10) according to any one of appendixes 2 to 19, wherein the first heat dissipation layer (15) and the second heat dissipation layer (16) are exposed from the sealing resin (60). [Appendix 21] The first signal wiring (25) is located on the opposite side of the first insulating layer (11) from the first heat dissipation layer (15), The semiconductor device (A10) according to appendix 14, wherein the first signal wiring (25) is joined to the first insulating layer (11). [Appendix 22] Further provided with a third signal wiring (27), the second semiconductor element (32) has a second control electrode (323) located on the same side as the fourth electrode (322) in the first direction, The semiconductor device (A10) according to appendix 14, wherein the second control electrode (323) is electrically connected to the third signal wiring (27). [Appendix 23] the third signal wiring (27) is located on the opposite side of the second insulating layer (12) from the first conductive layer (21); The semiconductor device (A10) according to appendix 22, wherein the third signal wiring (27) overlaps the first conductive layer (21) when viewed in the first direction. [Appendix 24] the third signal wiring (27) is located on the opposite side of the first insulating layer (11) from the first heat dissipation layer (15), The semiconductor device (A40) according to appendix 22, wherein the third signal wiring (27) is joined to the first insulating layer (11). [Appendix 25] The semiconductor device (A30) according to appendix 16, wherein the first heat dissipation layer (15) is bonded to the first insulating layer (11). [Appendix 26] The semiconductor device (A30) according to appendix 18, wherein the second heat dissipation layer (16) is bonded to the third insulating layer (13). [Appendix 27] The power supply further includes a plurality of power terminals (41, 42, 43) that are individually connected to the first conductive layer (21), the second conductive layer (22), and the third conductive layer (23), The semiconductor device (A10) according to Appendix 20, wherein the plurality of power terminals (41, 42, 43) are exposed from the sealing resin (60). [Appendix 28] The semiconductor device (A10) according to appendix 2, wherein the second conductive layer (22) overlaps the first conductive layer (21) when viewed in the first direction. [Appendix 29] The semiconductor device (A60) according to Appendix 28, wherein the first conductive layer (21) entirely overlaps the second conductive layer (22) when viewed in the first direction. [Appendix 30] The semiconductor device (A60) according to Appendix 29, wherein the second conductive layer (22) entirely overlaps the first conductive layer (21) when viewed in the first direction. [Explanation of symbols]

[0100] A10 to A60: Semiconductor device 11 to 14: First insulating layer to fourth insulating layer 111: First mounting surface 111A: Periphery 121: Second mounting surface 15,16: 1st heat dissipation layer, 2nd heat dissipation layer 21 to 24: First conductive layer to fourth conductive layer 21A, 21B: 1st layer, 21B 22A, 22B: 3rd layer, 4th layer 25-28: 1st signal wiring to 4th signal wiring 31: First semiconductor element 311,312: 1st electrode, 2nd electrode 313: First control electrode 32: Second semiconductor element 321,322: 3rd electrode, 4th electrode 323: Second control electrode 39: Conductive bonding layer 41: 1st power terminal 411: First mounting hole 42: 2nd power terminal 421: Second mounting hole 43: 3rd power terminal 431: Third mounting hole 44~47: 1st signal terminal ~ 4th signal terminal 481, 482, 483: First conductive member, second conductive member, third conductive member 51-58: 1st wire to 8th wire 60: Sealing resin 61: Top 62: Bottom 63~66: 1st to 4th side z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. a first insulating layer; a first heat dissipation layer located on one side of the first insulating layer in a first direction; a first conductive layer located on the opposite side of the first insulating layer from the first heat dissipation layer; a second insulating layer located on the opposite side of the first insulating layer with respect to the first conductive layer; a second conductive layer located on the opposite side of the second insulating layer from the first conductive layer; a third insulating layer located on the opposite side of the second insulating layer with respect to the second conductive layer; a second heat dissipation layer located on the opposite side of the third insulating layer from the second conductive layer; a first semiconductor element having a first electrode and a second electrode and located on the opposite side of the first insulating layer with respect to the first conductive layer; a second semiconductor element having a third electrode and a fourth electrode and positioned between the second insulating layer and the second conductive layer in the first direction; the polarity of the second electrode and the polarity of the third electrode are different from each other, the first electrode is electrically connected to the first conductive layer; the second electrode is electrically connected to the third electrode; the fourth electrode is electrically connected to the second conductive layer, The semiconductor device, wherein the first conductive layer includes a portion located between the first insulating layer and the second insulating layer in the first direction.

2. a third conductive layer located on the opposite side of the second insulating layer from the first conductive layer; the third conductive layer is electrically connected to the second electrode and the third electrode; The semiconductor device according to claim 1 , wherein the third conductive layer overlaps the first conductive layer when viewed in the first direction.

3. 3 . The semiconductor device according to claim 2 , wherein, when viewed in the first direction, the second conductive layer includes a portion overlapping the first conductive layer and a portion positioned outward from the first conductive layer.

4. 4. The semiconductor device according to claim 3, wherein, when viewed in the first direction, the first conductive layer includes a portion overlapping the second conductive layer and a portion positioned outward from the second conductive layer.

5. a fourth insulating layer located on the opposite side of the second conductive layer from the third insulating layer, The semiconductor device according to claim 2 , wherein said second conductive layer includes a portion located between said third insulating layer and said fourth insulating layer in said first direction.

6. a fourth conductive layer located on the opposite side of the fourth insulating layer from the second conductive layer; the fourth conductive layer is electrically connected to the third conductive layer, The semiconductor device according to claim 5 , wherein the second conductive layer overlaps the fourth conductive layer when viewed in the first direction.

7. 7. The semiconductor device according to claim 6, wherein the third conductive layer and the fourth conductive layer entirely overlap the first conductive layer and the second conductive layer, respectively, when viewed in the first direction.

8. The semiconductor device according to claim 7 , wherein the fourth conductive layer overlaps the third conductive layer when viewed in the first direction.

9. the third conductive layer is bonded to the second insulating layer; the fourth conductive layer is bonded to the fourth insulating layer; the first electrode is located on the opposite side to the second electrode in the first direction and is conductively joined to the first conductive layer; 9. The semiconductor device according to claim 8, wherein said third electrode is located on the opposite side to said fourth electrode in said first direction and is conductively joined to said third conductive layer.

10. a first conductive member conductively connected to the second electrode and the fourth conductive layer; The semiconductor device according to claim 9 , wherein the first conductive member is located between the second electrode and the fourth conductive layer in the first direction.

11. a second conductive member conductively connected to the fourth electrode and the second conductive layer; The semiconductor device according to claim 10 , wherein the second conductive member is located between the fourth electrode and the second conductive layer in the first direction.

12. a third conductive member conductively connected to the third conductive layer and the fourth conductive layer; The semiconductor device according to claim 11 , wherein the third conductive member is located between the third conductive layer and the fourth conductive layer in the first direction.

13. The semiconductor device according to claim 12 , wherein an area of ​​the third conductive member is larger than an area of ​​each of the first conductive member and the second conductive member when viewed in the first direction.

14. Further comprising a first signal wiring, the first semiconductor element has a first control electrode located on the same side as the second electrode in the first direction; The semiconductor device according to claim 9 , wherein the first control electrode is electrically connected to the first signal wiring.

15. the first signal wiring is located on the opposite side of the second insulating layer from the first conductive layer, The semiconductor device according to claim 14 , wherein the first signal wiring overlaps the first conductive layer when viewed in the first direction.

16. the first conductive layer includes a first layer and a second layer spaced apart from each other in the first direction; the first layer is bonded to the first insulating layer; the second layer is bonded to the second insulating layer; The semiconductor device according to claim 9 , wherein the second layer is conductively joined to the first layer.

17. The semiconductor device according to claim 16 , wherein the first electrode is conductively connected to the first layer.

18. the second conductive layer includes a third layer and a fourth layer spaced apart from each other in the first direction; the third layer is bonded to the third insulating layer; the fourth layer is bonded to the fourth insulating layer; 18. The semiconductor device according to claim 17, wherein the fourth layer is conductively joined to the third layer.

19. 19 . The semiconductor device according to claim 18 , wherein, when viewed in the first direction, the third layer includes a portion overlapping the fourth layer and a portion positioned outward from the fourth layer.

20. further comprising a sealing resin that covers the first semiconductor element and the second semiconductor element; 20. The semiconductor device according to claim 2, wherein said first heat dissipation layer and said second heat dissipation layer are exposed from said sealing resin.

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