Power supply device and image forming apparatus

Abstract

To provide a one-transformer type power supply device, capable of reducing a power consumption in an energy saving mode.SOLUTION: A power supply 130 includes: a primary rectification smoothing circuit 132 that rectifies and smoothes an AC voltage to output a smoothed voltage; a primary-secondary conversion part 133 that insulates the smoothed voltage and converts the smoothed voltage into a power output voltage in a first mode; and a DC-DC converter 136 that steps down the power output voltage to a logic output voltage. In a second mode in which a power consumption is lower than that in a first mode, the primary-secondary conversion part 133 converts the smoothed voltage to the logic output voltage instead of the power output voltage, and the DC-DC converter 136 stops operating in the second mode, outputs the power output voltage and the logic output voltage in the first mode, and outputs the logic output voltage in the second mode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power supply device and an image forming apparatus. [Background technology]

[0002] Conventionally, there are image forming apparatuses that operate in a normal mode and an energy-saving mode that consumes less power than the normal mode. The power supplies for such image forming apparatuses are classified into two types: a two-transformer type with two transformers and a single-transformer type with one transformer.

[0003] Image forming devices are equipped with a transformer that converts AC (Alternating Current) from a commercial power source into DC (Direct Current). Two-transformer types are equipped with a main power supply (DC 24V) for normal mode and a sub-power supply (DC 5V) for energy-saving mode. On the other hand, one-transformer types are equipped with only a main power supply and generate a stepped-down voltage (e.g., DC 5V) using a step-down DC-DC converter. The single-transformer type does not have a sub-power supply, making it advantageous for smaller size. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2022-39229 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the single-transformer type does not have a sub-power supply, which means that power consumption is high in energy-saving mode.

[0006] Therefore, one or more aspects of the present disclosure aim to reduce power consumption in an energy saving mode in a single-transformer type power supply device. [Means for solving the problem]

[0007] A power supply device according to one embodiment of the present disclosure includes a rectifying and smoothing unit that rectifies and smoothes an AC voltage to output a smoothed voltage, a conversion unit that is insulated from the supply side of the AC voltage and that converts the smoothed voltage into a power output voltage in a first mode, and a step-down unit that steps down the power output voltage to a logic output voltage that is a voltage lower than the power output voltage, wherein in a second mode that consumes less power than the first mode, the conversion unit converts the smoothed voltage into the logic output voltage instead of the power output voltage, and the step-down unit stops operating in the second mode, and in the first mode, outputs the power output voltage and the logic output voltage, and in the second mode, outputs the logic output voltage.

[0008] An image forming apparatus according to one aspect of the present disclosure is characterized by including the power supply device described above. [Effects of the Invention]

[0009] According to one or more aspects of the present disclosure, it is possible to reduce power consumption in an energy saving mode in a single transformer type power supply. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration of an image forming apparatus according to first and second embodiments. [Figure 2] 2 is a block diagram showing the configuration of a control system of the image forming apparatus according to the first embodiment. FIG. [Figure 3] 3 is a circuit diagram showing a detailed configuration of a power supply according to the first embodiment. FIG. [Figure 4] 10A to 10H are time charts showing signals and voltages when the image forming apparatus according to the first embodiment transitions to a sleep mode. [Figure 5] 10A to 10H are time charts showing signals and voltages when the image forming apparatus according to the first embodiment returns from a sleep mode. [Figure 6] FIG. 10 is a block diagram showing the configuration of a control system of an image forming apparatus according to a second embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a detailed configuration of a power supply according to a second embodiment. [Figure 8] 10A to 10I are time charts showing signals and voltages when the image forming apparatus according to the second embodiment transitions to a sleep mode and an OFF mode. [Figure 9] 10A to 10I are time charts showing signals and voltages when the image forming apparatus according to the second embodiment returns from the OFF mode. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiment 1 FIG. 1 is a cross-sectional view schematically showing the configuration of an image forming apparatus 10 according to the first embodiment. The image forming apparatus 10 includes an image forming main body that is broadly divided into a paper feed section 20 as a medium supply section, an image forming section 30, a fixing section 50, and a paper discharge section 60 as a medium discharge section. Here, the configuration of the image forming apparatus 10 will be described in the order of the printing operation, which is an image forming operation.

[0012] The paper feed section 20 includes a paper cassette 21, a pickup roller 22, and registration rollers 23, 24, 25, and 26. The paper cassette 21 stores paper as a medium. The pickup roller 22 picks up a sheet of paper from the paper cassette 21 . The registration rollers 23 , 24 , 25 , and 26 transport the sheet of paper picked up by the pickup roller 22 to the image forming unit 30 .

[0013] When forming a color image, the image forming unit 30 is divided into process colors. For example, as shown in Fig. 1, the image forming unit 30 includes a black (K) process unit 31K, a yellow (Y) process unit 31Y, a magenta (M) process unit 31M, and a cyan (C) process unit 31C.

[0014] Each of the process units 31K, 31Y, 31M, and 31C is configured in the same manner except for the color of the toner, which is the developer, that is used. Therefore, in the following, when there is no need to particularly distinguish between each of the process units 31K, 31Y, 31M, and 31C, each of the process units 31K, 31Y, 31M, and 31C will also be referred to as process unit 31. Here, the configuration will be explained using the process unit 31K.

[0015] The process unit 31K includes a photosensitive drum 32, a charging roller 33, a developing roller 34 in contact with the photosensitive drum 32, and a toner supply roller 35 in contact with the developing roller 34.

[0016] The photosensitive drum 32 is an image carrier that carries an image. The charging roller 33 is a charging unit that uniformly charges the photosensitive drum 32 . The developing roller 34 is a developing unit that supplies toner to the electrostatic latent image formed on the photosensitive drum 32, thereby forming a toner image as a developer image on the photosensitive drum 32. The toner supply roller 35 is a supply unit that supplies toner to the developing roller 34 .

[0017] The process units 31K, 31Y, 31M, and 31C are provided with LED heads 36K, 36Y, 36M, and 36C corresponding to the respective colors. Because the LED heads 36K, 36Y, 36M, and 36C are configured similarly, when there is no need to particularly distinguish between the LED heads 36K, 36Y, 36M, and 36C, the LED heads 36K, 36Y, 36M, and 36C are also referred to as LED heads 36.

[0018] The LED head 36 is an exposure unit that is disposed above the photosensitive drum 32 and forms an electrostatic latent image on the photosensitive drum 32 by performing exposure corresponding to the color for which it is responsible.

[0019] The process units 31K, 31Y, 31M, and 31C are provided with toner cartridges 37K, 37Y, 37M, and 37C, respectively, for storing toner of the respective colors. Toner cartridges 37K, 37Y, 37M, and 37C are configured similarly except for the color of the toner they contain. Therefore, when there is no need to particularly distinguish between toner cartridges 37K, 37Y, 37M, and 37C, each of toner cartridges 37K, 37Y, 37M, and 37C will also be referred to as toner cartridge 37.

[0020] Below the process units 31K, 31Y, 31M, and 31C, there are provided a conveyor belt 40, a drive roller 41, a driven roller 42, and transfer rollers 43K, 43Y, 43M, and 43C.

[0021] The conveyor belt 40 is stretched between a drive roller 41 and a driven roller 42, and moves in accordance with the rotation of the drive roller 41. As a result, the conveyor belt 40 conveys a sheet of paper from the paper feed unit 20 in the direction of the fixing unit 50.

[0022] The drive roller 41 is rotated by receiving power from a motor (not shown). The driven roller 42 rotates following the conveyor belt 40 which runs in accordance with the rotation of the drive roller 41 .

[0023] Transfer rollers 43K, 43Y, 43M, and 43C are arranged below process units 31K, 31Y, 31M, and 31C, respectively, and transfer the toner images formed in process units 31K, 31Y, 31M, and 31C, respectively, onto a sheet of paper transported by transport belt 40. When there is no need to particularly distinguish between the transfer rollers 43K, 43Y, 43M, and 43C, each of the transfer rollers 43K, 43Y, 43M, and 43C will also be referred to as the transfer roller 43.

[0024] The fixing unit 50 includes a heating roller 51, a heater 52, a temperature detection sensor 53, and a pressure roller . The heating roller 51 is a roller that melts the toner image transferred onto a sheet of paper conveyed by the conveyor belt 40 and fixes it onto the sheet of paper. The heater 52 is disposed inside the heating roller 51 and is a heat source that generates heat. The temperature detection sensor 53 detects the surface temperature of the heating roller 51. As the temperature detection sensor 53, for example, a thermistor can be used. The pressure roller 54 presses a sheet of paper conveyed by the conveyor belt 40 toward the heating roller 51 . The sheet of paper on which the toner image has been fixed in the fixing section 50 is fed to the paper discharge section 60 .

[0025] The paper discharge section 60 includes discharge rollers 61 and 62 for discharging a sheet of paper from the fixing section 50 to the outside of the image forming apparatus 10 .

[0026] FIG. 2 is a block diagram showing the configuration of a control system of the image forming apparatus 10 according to the first embodiment. The control system of the image forming apparatus 10 includes a main control block 110, a sub-control block 120, and a power supply .

[0027] In the normal mode, which is the first mode, the main control block 110 controls the processing in the image forming apparatus 10. In particular, the main control block 110 controls the processing of operating the image forming main body to form an image on a medium. The main control block 110 includes a main control unit 111, a ROM (Read Only Memory) 112, a RAM (Random Access Memory) 113, a temperature detection unit 114, a sensor on / off circuit 115, a high-voltage power supply 116, a head control unit 117, and an actuator drive unit 118.

[0028] The main control unit 111 is a device such as a processor that operates according to a program written in a ROM 112. The main control unit 111 has a built-in counter for measuring time. The ROM 112 is a non-volatile memory that stores programs and data such as setting data.

[0029] The RAM 113 is a volatile memory that stores and reads data. The temperature detection unit 114 performs resistance voltage division on the output of the temperature detection sensor 53 inside the fixing unit 50 and outputs a temperature detection signal to the main control unit 111 .

[0030] The sensor on / off circuit 115 is made up of transistors, and turns on or off the power supplied to the various sensors 101 in accordance with a sensor off signal from the main control unit 111. For example, except during warm-up of the device after power is turned on or during printing performed in response to an instruction from the host HO or the like, the sensor on / off circuit 115 basically turns off the power supplied to the various sensors 101 because the sensor off signal is output from the main control unit 111.

[0031] The high-voltage power supply 116 is a power supply that applies a high voltage to the photosensitive drum 32 and various rollers of the image forming unit 30 shown in FIG. The head control unit 117 is a control unit that controls the on / off of the LED head 36 shown in FIG. The actuator driving unit 118 is a dedicated driver that outputs a driving signal to the actuator 102 based on a logic signal output from the main control unit 111 .

[0032] The various sensors 101 include paper path sensors (not shown) for detecting paper position, which are arranged in the paper feed section 20, image forming section 30, fixing section 50, and paper discharge section 60, as well as sensors for correcting image density and color misalignment.

[0033] The actuator 102 refers to motors, clutches, solenoids, and cooling fans (not shown) that are arranged in the paper feed unit 20, image forming unit 30, fixing unit 50, and paper discharge unit 60 and are driven by the actuator drive unit 118 described above. The various sensors 101 and actuators 102 are also elements included in the image forming main body.

[0034] The sub-control block 120 controls the processing of the image forming apparatus 10 in a normal mode and a low power consumption mode that consumes less power than the normal mode. In the low power consumption mode, the image forming apparatus does not perform the process of forming an image on a medium, thereby consuming less power than the normal mode. For example, in the low power consumption mode, power consumption is reduced by not energizing the heater 52 of the fixing unit 50. In the first embodiment, it is assumed that the sleep mode is set as the low power consumption mode. The sleep mode is also referred to as the second mode. The sub-control block 120 includes a DC 5V on / off switch 121 and a sub-control unit 122 .

[0035] The DC 5V on / off switch 121 uses a semiconductor FET (Field Effect Transistor) and a transistor, or a relay, and turns on and off the DC 5V output from the power supply 130 via the sub-controller 122.

[0036] The sub-controller 122 is a microcomputer for the low power consumption mode, and outputs a low power consumption mode signal such as a SLEEP-P signal indicating whether the sleep mode is on or off, in other words, whether the sleep mode is on or off. The transition to the low power consumption mode occurs after a set time has elapsed, or in conjunction with the on / off of the mechanical switch 103 pressed by the user, and the on / off of the mechanical switch 103 enables the transition to or return from the low power consumption mode.

[0037] The power supply 130 is a power supply device that includes a heater on / off circuit 131, a primary rectifying and smoothing circuit 132, a primary-secondary conversion unit 133, a voltage feedback unit 134, a DC 24V on / off switch 135, a DC-DC converter 136, a brown-in / out circuit 137, and a bypass circuit 138. The power supply 130 operates on an AC voltage output from a commercial power supply CPS.

[0038] The heater on / off circuit 131 is a circuit that turns on and off the heater 52 inside the fixing unit 50 in accordance with a heater on / off signal output from the main control unit 111 . The primary rectifying and smoothing circuit 132 is a rectifying and smoothing unit that rectifies and smoothes the AC voltage supplied from the commercial power supply CPS. The smoothed voltage that is the voltage smoothed by the primary rectifying and smoothing circuit 132 is provided to the primary-secondary conversion unit 133.

[0039] The primary-secondary conversion unit 133 supplies a DC voltage to the main control block 110. The primary-secondary conversion unit 133 is insulated from the commercial power supply CPS, which is the AC voltage supply side, and in normal mode, converts the smoothed voltage from the primary rectifying smoothing circuit 132 into a power output voltage, and in sleep mode, which is a second mode in which power consumption is lower than in the normal mode, converts the smoothed voltage into a logic output voltage, which is a voltage lower than the power output voltage, instead of the power output voltage.

[0040] In this case, 24V DC is supplied as the power output voltage, but the control unit may step down the DC 24V and supply it to the logic unit. Also, there may be multiple winding outputs on the secondary side, which may generate DC voltages in addition to the DC 24V. Also, here, 5V DC is supplied as the logic output voltage.

[0041] DC-DC converter 136 is a step-down unit that steps down the voltage output from primary-secondary conversion unit 133. Here, DC-DC converter 136 steps down DC 24V as a power output voltage to DC 5V as a logic output voltage. An IC (Integrated Circuit) is generally used as DC-DC converter 136, and in this embodiment, the DC-DC converter is referred to as including peripheral circuits. It should be noted that the DC-DC converter 136 stops operating in the low power consumption mode.

[0042] The type of DC voltage output from the power supply 130 may be determined by the configuration of the control side at the subsequent stage, and a DC 3.3V output is also common. In this embodiment, the voltages output from the power supply 130 to the control side at the subsequent stage are DC 24 V and DC 5 V. DC 24 V is the voltage output to the power section such as the actuator 102, and DC 5 V is the voltage output to the logic section.

[0043] The brown in / out circuit 137 detects the input voltage to the DC-DC converter 136, in other words, the output voltage of the primary-secondary conversion unit 133, and turns the output on and off using the IC function of the DC-DC converter 136 at a certain threshold.

[0044] The voltage feedback unit 134 is a circuit that detects the voltage output from the primary-secondary conversion unit 133 and feeds back the result of the detection to the primary-secondary conversion unit 133 . The DC 24V on / off switch 135 is a switch that turns on and off the DC 24V output from the power supply 130 in accordance with the SLEEP-P signal output from the sub-controller 122. The DC 24V on / off switch 135 is configured by a relay or an FET.

[0045] The bypass circuit 138 is a circuit that causes the output of the primary-secondary conversion unit 133 to bypass the DC-DC converter 136 in accordance with the SLEEP-P signal output from the sub-control unit 122 . In other words, the bypass circuit 138 is a bypass unit that outputs DC 5V as the logic output voltage converted by the primary-secondary conversion unit 133 by bypassing the DC-DC converter 136 in the sleep mode.

[0046] FIG. 3 is a circuit diagram showing a detailed configuration of the power supply 130 according to the first embodiment. The power supply 130 includes a heater on / off circuit 131, a primary rectifying and smoothing circuit 132, a primary-secondary conversion unit 133, a voltage feedback unit 134, a DC 24V on / off switch 135, a DC-DC converter 136, a brown-in / out circuit 137, and a bypass circuit 138, as shown in FIG. 2 , as well as a protection element 140, a filter 141, a filter 142, an inrush prevention circuit 143, a secondary rectifying and smoothing circuit 144, a DC 5V protection circuit 145, a filter 146, a DC 24V protection circuit 147, a secondary filter 148, and an AC zero-cross detection circuit 149.

[0047] The protection element 140 is composed of a fuse for overcurrent protection or a varistor for lightning surge protection. The filter 141 is generally composed of a common or normal choke coil and a capacitor. The capacitor is composed of an X capacitor placed between LINE and NEUTRAL, and a Y capacitor placed between LINE or NEUTRAL and FG (Frame Ground). The filter 142 is disposed after the heater on / off circuit 131. The configuration of the filter 142 is similar to the configuration of the filter 141.

[0048] The heater on / off circuit 131 is made up of a triac and a phototriac. The heater on / off circuit 131 may also be equipped with a relay for protection. The heater on / off circuit 131 turns the phototriac on and off in accordance with a heater on / off signal from the main control unit 111, and by turning the triac on and off, energizes the heater 52 inside the fixing unit 50.

[0049] The inrush prevention circuit 143 is a circuit that suppresses inrush current when charging the electrolytic capacitor 132b of the primary rectifying and smoothing circuit 132. A thermistor is an inexpensive component of the inrush prevention circuit 143. However, because thermistors cannot suppress inrush current at high temperatures, the inrush prevention circuit 143 may be a circuit that combines a resistor with a triac or relay, which is a switching element.

[0050] The primary rectifying and smoothing circuit 132 includes a rectifying diode 132a and an electrolytic capacitor 132b. The rectifier diode 132a is made up of four diodes, and generally uses an element called a bridge diode containing four elements. The electrolytic capacitor 132b smoothes the voltage rectified by the rectifier diode 132a.

[0051] The primary-secondary conversion unit 133 includes a transformer 133a, a main FET 133b, a snubber circuit 133c, a power supply control unit 133d, an auxiliary winding rectifying and smoothing circuit 133e, and a voltage clamp circuit 133f.

[0052] The transformer 133a electrically and physically insulates the primary side from the secondary side, and also has the function of transforming the voltage input from the commercial power supply CPS. The main FET 133b is a so-called switching FET that turns on and off the power supplied to the primary winding of the transformer 133a.

[0053] The snubber circuit 133c is a circuit that suppresses spike voltages when the main FET 133b is turned off. The snubber circuit 133c is often composed of a fast recovery diode, a resistor, and a capacitor. In addition, a Zener diode may be used as the snubber circuit to reduce power consumption.

[0054] The power supply control unit 133d determines the on-duty of the gate voltage of the main FET 133b mainly based on the feedback result of the secondary-side DC output voltage. In this embodiment, the power supply control unit 133d is a separately excited IC, but it can also be made into a self-excited IC by utilizing an auxiliary winding voltage, which will be described later.

[0055] The auxiliary winding rectifying and smoothing circuit 133e rectifies and smoothes the auxiliary winding output voltage, which serves as the power supply voltage for the power supply control unit 133d. The auxiliary winding rectifying and smoothing circuit 133e is composed of a rectifying diode and an electrolytic capacitor. The voltage clamp circuit 133f is composed of a Zener diode, a rectifier diode, a transistor, and a resistor, and is a circuit that clamps the voltage when the auxiliary winding output voltage exceeds the absolute maximum rating of the power supply control unit 133d.

[0056] The secondary rectifying and smoothing circuit 144 rectifies and smoothes the secondary winding output voltage from the transformer 133a. In Fig. 3, the secondary rectifying and smoothing circuit 144 employs a flyback system that produces a single winding output of DC 24V, and includes a rectifying diode and an electrolytic capacitor.

[0057] The voltage feedback section 134 includes a shunt regulator 134a, a photocoupler 134b, and a DC 24V set voltage conversion transistor 134c.

[0058] The shunt regulator 134a is an IC that has a reference voltage and sets the DC output voltage using surrounding voltage dividing resistors. When the actual voltage rises or falls below the set voltage, the shunt regulator 134a turns on and off the photocoupler 134b connected to the shunt regulator 134a and feeds back the result to the power supply control unit 133d, thereby stabilizing the set voltage.

[0059] The DC 24V set voltage conversion transistor 134c is turned on and off in accordance with the SLEEP-P signal from the sub-controller 122, and changes the peripheral voltage dividing resistance value of the shunt regulator 134a, thereby changing the set voltage of the shunt regulator 134a. This allows the DC voltage output from the primary-secondary conversion unit 133 to be changed.

[0060] As described above, the primary-secondary conversion unit 133 switches the output voltage between DC 24V, which is the power output voltage, and DC 5V, which is the logic output voltage, in accordance with the SLEEP-P signal.

[0061] The DC 24V protection circuit 147 is equipped with an overvoltage detection circuit and an overcurrent detection circuit. The overvoltage protection circuit is composed of a Zener diode and a photocoupler, and when an overvoltage is detected, the primary-side power supply control unit 133d stops switching in a latched or intermittent manner. When an overvoltage is detected, the auxiliary winding voltage also rises, so the primary-side power supply control unit 133d can also detect an overvoltage. The overcurrent detection circuit has various circuit configurations, such as current detection, DC output voltage droop detection, and fuses. As with overvoltage detection, the power supply control unit 133d can also detect overcurrent.

[0062] The secondary filter 148 is an LC filter. The secondary filter 148 does not necessarily need to be installed. The DC 24V on / off switch 135 is a switch that is turned on and off by a SLEEP-P signal from the sub-controller 122. The DC 24V on / off switch 135 is made up of a semiconductor or a relay.

[0063] The DC-DC converter 136 receives an input of 24V DC voltage from the secondary rectifying and smoothing circuit 144 and outputs a 5V DC voltage. The type of DC-DC converter 136, whether it is a drop type or a switching type, and its switching frequency are generally determined based on the load current. Here, the DC-DC converter 136 is assumed to be a switching type. Furthermore, the DC-DC converter 136 is often a DC-DC converter IC with an on / off function in its external terminal; in this embodiment, such an external terminal is referred to as an ENABLE terminal. Furthermore, the input terminal of the DC-DC converter 136 is referred to as an IN terminal, and its output terminal is referred to as an OUT terminal.

[0064] The brown-in / out circuit 137 includes a brown-in / out Zener diode 137a, a front-stage transistor 137b, and a rear-stage transistor 137c. The collector terminal of the rear-stage transistor 137c and the ENABLE terminal of the DC-DC converter 136 are connected.

[0065] The DC 5V protection circuit 145 has the same configuration as the DC 24V protection circuit 147. When connecting to the power supply control unit 133d, a photocoupler (not shown) is required, but there are also cases where a single photocoupler is used in common for the outputs of the DC 24V protection circuit 147 and the DC 5V protection circuit 145. The filter 146 may be configured similarly to the second order filter 148 and is not necessarily required.

[0066] The bypass circuit 138 includes a bypass circuit FET 138a as a switch, a rectifier diode 138b, and a Zener diode 138c.

[0067] The drain terminal and source terminal of the bypass circuit FET 138a are connected to the IN terminal and OUT terminal, respectively, of the DC-DC converter. The gate terminal of the bypass circuit FET 138a is connected to the IN terminal of the DC-DC converter. The gate terminal of the bypass circuit FET 138a also receives the SLEEP-P signal from the sub-control unit 122. As a result, the bypass circuit FET 138a functions as a switch that turns off the connection line from the primary-secondary conversion unit 133 in the normal mode, and turns on the connection line from the primary-secondary conversion unit 133 in the sleep mode. This on / off switching is performed in accordance with the SLEEP-P signal.

[0068] The rectifier diode 138b is connected to the drain and source terminals of the bypass circuit FET 138a. Furthermore, a rectifier diode 138d is connected between the OUT terminal of the DC-DC converter 136 and the bypass circuit FET 138a. The rectifier diode 138d may be a Schottky barrier diode.

[0069] In the first embodiment, the semiconductor bypass circuit FET 138a is used as the switch of the bypass circuit 138, but the first embodiment is not limited to this example. For example, a relay may be used as the switch of the bypass circuit 138.

[0070] 4A to 4H are time charts showing signals and voltages when the image forming apparatus 10 according to the first embodiment transitions to the sleep mode. 4A to 4H show signals and voltages when the image forming apparatus 10 transitions from an initial mode in which it is preparing to print, a print mode in which it is printing, or a standby mode in which it is waiting to print, to a sleep mode. Here, the initial mode, print mode, and standby mode are normal modes. The horizontal axis in FIGS. 4(A) to 4(H) represents time.

[0071] 4A shows the SLEEP-P signal. The SLEEP-P signal is a signal output from the sub-control unit 122, and has a P polarity, so it is Lo in normal mode and Hi in sleep mode. The SLEEP-P signal may also have an N polarity.

[0072] 4B shows the voltage input to the IN terminal of the DC-DC converter 136. In other words, it is the output voltage of the secondary rectifying and smoothing circuit 144. FIG. 4C shows the voltage input to the ENABLE terminal of the DC-DC converter 136.

[0073] FIG. 4(D) shows the voltage output from the DC-DC converter 136. FIG. 4(E) shows the voltage output from the bypass circuit FET 138a of the bypass circuit 138. FIG. 4(F) shows the voltage output from the Zener diode 138c arranged on the output side of the bypass circuit FET 138a of the bypass circuit 138.

[0074] FIG. 4G shows DC 5V output from the power supply 130. FIG. 4(H) shows DC 24V output from the power supply 130.

[0075] First, in the initial mode, print mode, or standby mode, the SLEEP-P signal output from the sub-controller 122 is Lo, as shown in Fig. 4(A). As a result, a voltage of DC 24V is output from the secondary rectifying smoothing circuit 144 and input to the IN terminal of the DC-DC converter 136, as shown in Fig. 4(B).

[0076] Furthermore, since the Zener voltage of the brown-in-out Zener diode 137a of the brown-in-out circuit 137 is set to be higher than DC 5V, a voltage of 24V is output from the secondary rectifying smoothing circuit 144, and as a result, the front-stage transistor 137b of the brown-in-out circuit 137 is turned on and the rear-stage transistor 137c is turned off, and as shown in Figure 4(C), the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Hi. As a result, the voltage output from the DC-DC converter 136 becomes 5V, as shown in FIG. 4(D).

[0077] Furthermore, since the SLEEP-P signal output from the sub-control unit 122 is Lo, the gate terminal of the bypass circuit FET 138a becomes Lo, the drain-source voltage becomes off, and the voltage output from the bypass circuit FET 138a of the bypass circuit 138 becomes 0V, as shown in FIG. 4(E). Furthermore, since the front-stage transistor 137b of the brown-in / out circuit 137 is turned on and the rear-stage transistor 137c is turned off, the voltage output from the Zener diode 138c also becomes 0V, as shown in FIG. 4(F).

[0078] As a result of the above, as shown in Figure 4(G), DC 5V is output from the power supply 130 to the sub-control block 120, and as shown in Figure 4(H), DC 24V is output from the power supply 130 to the main control block 110.

[0079] At time t01, when the sub-control unit 122 determines to transition to sleep mode after a set time has elapsed or when the user presses the mechanical switch 103, the sub-control unit 122 sets the SLEEP-P signal to Hi, as shown in Figure 4(A).

[0080] As a result, the DC 24V set voltage conversion transistor 134c, which changes the shunt regulator voltage dividing resistor of the voltage feedback unit 134, turns on, changing the set voltage of the shunt regulator 134a. The set voltage may be any value, but as an example, in this embodiment, it is set to DC 5V. By changing the set voltage of the shunt regulator 134a from DC 24V to DC 5V, as shown in FIG. 4(B), the DC 24V output from the secondary rectifying and smoothing circuit 144 drops, and at time t02, it becomes DC 5V and is maintained at that voltage.

[0081] Furthermore, since the Zener voltage of the brown-in-out Zener diode 137a of the brown-in-out circuit 137 is set to be higher than DC 5V, a voltage of 5V is output from the secondary rectifying smoothing circuit 144, and as a result, the front-stage transistor 137b of the brown-in-out circuit 137 is turned off and the rear-stage transistor 137c is turned on, and as shown in Figure 4(C), the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Lo. As a result, the voltage output from the DC-DC converter 136 drops from 5V, as shown in FIG. 4(D).

[0082] Furthermore, since the SLEEP-P signal output from the sub-control unit 122 becomes Hi, the gate terminal of the bypass circuit FET 138a becomes Hi, the drain-source voltage turns on, and as shown in FIG. 4(E), the voltage output from the bypass circuit FET 138a of the bypass circuit 138 rises from 0V, drops from time t03, and remains at 5V from time t04. Furthermore, since the front-stage transistor 137b of the brown in / out circuit 137 is turned off and the rear-stage transistor 137c is turned on, the voltage output from the Zener diode 138c also rises from 0V and becomes 5V at time t02, as shown in Figure 4(F).

[0083] As a result of the above, as shown in Figure 4(G), DC 5V is output from the power supply 130 to the sub-control block 120, and as shown in Figure 4(H), the voltage supplied from the power supply 130 to the main control block 110 decreases from DC 24V at time t01 and becomes 0V at time T02.

[0084] 5A to 5H are time charts showing signals and voltages when the image forming apparatus 10 according to the first embodiment returns from the sleep mode. Figures 5(A) to (H) show the signals and voltages when the image forming device 10 transitions from sleep mode to initial mode in which it is preparing to print, to print mode in which it is performing printing operations, or to standby mode in which it is waiting to print. The horizontal axes in FIGS. 5(A) to 5(H) represent time, and the vertical axes in FIGS. 5(A) to 5(H) are the same as the vertical axes in FIGS. 4(A) to 4(H).

[0085] First, in the sleep mode, according to the time charts shown in Figures 4(A) to (H), the SLEEP-P signal output from the sub-controller 122 is Hi, as shown in Figure 5(A). As a result, a voltage of DC 5V is output from the secondary rectifying smoothing circuit 144 and input to the IN terminal of the DC-DC converter 136, as shown in Figure 5(B). Furthermore, as shown in FIG. 5(C), the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Lo, as shown in FIG. 5(D), the voltage output from the DC-DC converter 136 becomes 0 V, as shown in FIG. 5(E), the voltage output from the bypass circuit FET 138a of the bypass circuit 138 becomes 5 V, and as shown in FIG. 5(F), the voltage output from the Zener diode 138c becomes 5 V. As shown in Figure 5(G), DC 5V is output from the power supply 130 to the sub-control block 120, and as shown in Figure 5(H), the output power from the power supply 130 to the main control block 110 is 0V.

[0086] At time t11, when the sub-control unit 122 determines to return from sleep mode, for example, when the user presses the mechanical switch 103, the sub-control unit 122 sets the SLEEP-P signal to Lo, as shown in FIG. 5(A).

[0087] As a result, the DC24V setting voltage conversion transistor 134c, which changes the shunt regulator voltage dividing resistance of the voltage feedback unit 134, is turned off, and the setting voltage of the shunt regulator 134a is changed to DC24V. As shown in FIG. 5(B), the DC5V output from the secondary rectifying smoothing circuit 144 rises and becomes DC24V at time t12, and that voltage is maintained.

[0088] Furthermore, the Zener voltage of the brown-in-out Zener diode 137a of the brown-in-out circuit 137 is set to be higher than DC 5V, and when the voltage from the secondary rectifying smoothing circuit 144 rises to 24V and reaches the Zener voltage, the front-stage transistor 137b of the brown-in-out circuit 137 turns on and the rear-stage transistor 137c turns off, and as a result, the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Hi, as shown in FIG. 5(C). As a result, the voltage output from the DC-DC converter 136 rises from 0V, as shown in FIG. 5(D).

[0089] The Zener voltage is arbitrary and is determined by the ENABLE function of the DC-DC converter 136 used and peripheral constants.

[0090] When the SLEEP-P signal input to the gate voltage of the bypass circuit FET 138a of the bypass circuit 138 becomes Lo, the drain-source voltage of the bypass circuit FET 138a is turned off, but it does not immediately turn off due to the surrounding CR time constant. Therefore, as shown in Figure 5(E), the voltage output from the bypass circuit FET 138a of the bypass circuit 138 rises from 5V, drops from time t13, and reaches 0V from time t15.

[0091] However, since it is clamped by the Zener voltage of the Zener diode 138c, the voltage output from the Zener diode 138c remains at 5V as shown in FIG. 5(F).

[0092] At time t12, as shown in Fig. 5(B), the voltage output from the secondary rectifying smoothing circuit 144 reaches 24 V and is then maintained at 24 V. As a result, as shown in Fig. 5(H), the voltage supplied from the power supply 130 to the main control block 110 becomes DC 24 V.

[0093] At time t15, the output from the bypass circuit FET 138a of the bypass circuit 138 reaches 0 V and is then maintained at 0 V. However, as shown in Fig. 5(D), the output of the DC-DC converter 136 is maintained at 5 V, and therefore, a DC 5 V output is maintained from the power supply 130 to the sub-control block 120, as shown in Fig. 5(G).

[0094] As described above, according to the first embodiment, when transitioning to sleep mode, DC-DC converter 136 is stopped, and the voltage of primary-secondary conversion unit 133 is reduced from DC 24V to DC 5V, and the output from primary-secondary conversion unit 133 is supplied to sub-control block 120, bypassing DC-DC converter 136, thereby reducing unnecessary power consumption of the power supply circuit and increasing overall power supply efficiency. In other words, in embodiment 1, in normal mode, DC 24V is output as the power output voltage and DC 5V is output as the logic output voltage from power supply 130, and in sleep mode, DC 5V is output as the logic output voltage from power supply 130.

[0095] Here, in the first embodiment, the gate voltage of the bypass circuit FET 138a is switched by switching the SLEEP-P signal between Hi and Lo, but the first embodiment is not limited to this example. For example, although not shown, it is also possible to connect the output of the rear-stage transistor 137c of the brown-in / out circuit 137 to the gate of the bypass circuit FET 138a to switch the gate voltage. The polarity can be changed by adding a configuration using a transistor and a resistor.

[0096] Embodiment 2 As shown in FIG. 1, the configuration of image forming apparatus 11 according to the second embodiment is roughly divided into paper feed section 20, image forming section 30, fixing section 50, and paper discharge section 60. The paper feed section 20, image forming section 30, fixing section 50 and paper discharge section 60 of the image forming apparatus 11 of embodiment 2 are similar to the paper feed section 20, image forming section 30, fixing section 50 and paper discharge section 60 of the image forming apparatus 10 of embodiment 1.

[0097] FIG. 6 is a block diagram showing the configuration of a control system of image forming apparatus 11 according to the second embodiment. The control system of image forming apparatus 11 according to embodiment 2 differs from the control system of image forming apparatus 10 according to embodiment 1 in sub-control block 220 and power supply 230. The following mainly describes the differences.

[0098] In the second embodiment, the sub-controller 222 of the sub-control block 220 outputs an OFF mode signal indicating whether the OFF mode, which is a low power consumption mode that consumes even less power than the Sleep mode, is on or off, in other words, whether the OFF mode is on or off. The OFF mode signal is input to the bypass circuit 238 and the primary-secondary conversion unit 233 of the power supply 230. The OFF mode is also referred to as the third mode. In the second embodiment, in the OFF mode, the operation of the primary-secondary conversion unit 233 is also stopped to further reduce power consumption. The sleep mode is a mode in which power supply to the main control block 110 is stopped and power is supplied only to the sub-control block 220. The off mode is a mode in which the DC 5V on / off switch 121 of the sub-control block 220 is turned off and power is supplied only to a microcomputer (not shown) inside the sub-controller 222. As a result, the OFF mode consumes less power than the Sleep mode.

[0099] In the second embodiment, AC power input from commercial power supply CPS is also input to off-mode energy saving circuit 250 of power supply 230. The output of off-mode energy saving circuit 250 is input to bypass circuit 238.

[0100] FIG. 7 is a circuit diagram showing a detailed configuration of the power supply 230 according to the second embodiment. Power supply 230 in embodiment 2 is different from power supply 130 in embodiment 1 in that it has a primary-secondary conversion unit 233 and a bypass circuit 238, and further has an off-mode energy-saving circuit 250 added. The following mainly describes the differences.

[0101] The primary-secondary conversion unit 233 includes a transformer 133a, a main FET 133b, a snubber circuit 133c, a power supply control unit 233d, an auxiliary winding rectifying and smoothing circuit 133e, and a voltage clamp circuit 133f.

[0102] The transformer 133a, the main FET 133b, the snubber circuit 133c, the auxiliary winding rectifying and smoothing circuit 133e, and the voltage clamp circuit 133f of the primary-secondary conversion unit 233 in the second embodiment are similar to the transformer 133a, the main FET 133b, the snubber circuit 133c, the auxiliary winding rectifying and smoothing circuit 133e, and the voltage clamp circuit 133f of the primary-secondary conversion unit 133 in the first embodiment.

[0103] Similar to the power supply control unit 133d of the first embodiment, the power supply control unit 233d determines the on-duty of the gate voltage of the main FET 133b mainly based on the feedback result of the DC output voltage on the secondary side.

[0104] Furthermore, when the OFF mode signal from the sub-controller 222 indicates the OFF mode, the power supply controller 233d stops processing, in other words, stops switching on the main FET 133b, thereby stopping the operation of the primary-secondary converter 233. As a result, the voltage output from the primary-secondary converter 233 becomes 0 V, and the power consumption in the primary-secondary converter 233 becomes zero.

[0105] The off-mode energy-saving circuit 250 is an output unit that includes two capacitors connected in series to each of two AC voltage supply paths, and outputs DC 5V as a logic output voltage by rectifying, smoothing, and clamping the voltage discharged from the two capacitors. The off-mode energy-saving circuit 250 is connected in parallel to the primary-secondary conversion unit 233. For example, the off-mode energy saving circuit 250 includes a capacitor 250a, a capacitor 250b, a bridge diode 250c, a Zener diode 250d, and an electrolytic capacitor 250e.

[0106] The capacitor 250a is connected to the LINE side of the output of the protection element 140 of the power supply 130, and is connected to a bridge diode 250c made up of four diodes in the subsequent stage. The capacitor 250b is connected to the NEUTRAL side of the output of the protection element 140 of the power supply 130, and is also connected to the bridge diode 250c in the subsequent stage.

[0107] The bridge diode 250c rectifies the AC input via the capacitors 250a and 250b and outputs the rectified AC. The bridge diode 250c is connected to a Zener diode 250d.

[0108] The Zener diode 250d is provided to prevent overvoltage output and clamp it to DC 5 V. The Zener diode 250d is connected to the electrolytic capacitor 250e.

[0109] The electrolytic capacitor 250e smoothes the output from the bridge diode 250c and outputs the smoothed output. The output of the electrolytic capacitor 250e is connected to the output of the Zener diode 138c of the bypass circuit 238.

[0110] The bypass circuit 238 includes a bypass circuit FET 238a, a rectifier diode 138b, a Zener diode 138c, and a diode 238e. The rectifier diode 138b and the Zener diode 138c of the bypass circuit 238 in the second embodiment are similar to the rectifier diode 138b and the Zener diode 138c of the bypass circuit 138 in the first embodiment.

[0111] The drain terminal and source terminal of the bypass circuit FET 238a are connected to the IN terminal and OUT terminal, respectively, of the DC-DC converter. The gate terminal of the bypass circuit FET 238a is connected to the IN terminal of the DC-DC converter. The gate terminal of the bypass circuit FET 238a also receives the SLEEP-P signal and the OFF mode signal from the sub-controller 222.

[0112] In the second embodiment, the output of off-mode energy saving circuit 250 is connected between Zener diode 138c and rectifier diode 138d via diode 238e.

[0113] As described above, in the second embodiment, in the sleep mode, the output from the primary-secondary conversion unit 233 and the output from the off mode energy saving circuit 250 are input to the bypass circuit 238, and in the off mode, the output from the off mode energy saving circuit 250 is input to the bypass circuit 238, and these are output from the bypass circuit 238. In the second embodiment, in the sleep mode, the output from the primary-secondary conversion unit 233 and the output from the off mode energy saving circuit 250 are connected in parallel to form the output of the power supply 230, thereby obtaining a stable DC output in the sleep mode. In addition, in the OFF mode, the primary-secondary conversion unit 233 is stopped and the output from the OFF mode energy saving circuit 250 is used as the output of the power supply 230, thereby making it possible to reduce power consumption more than in the Sleep mode.

[0114] 8A to 8I are time charts showing signals and voltages when the image forming apparatus 10 according to the second embodiment transitions to the sleep mode and the OFF mode. Figures 8(A) to (I) show the signals and voltages when the image forming device 11 transitions from an initial mode in which it is preparing to print, a print mode in which it is performing a printing operation, or a standby mode in which it is waiting to print, to a sleep mode, and then to an OFF mode. The horizontal axis in FIGS. 8(A) to 8(I) represents time.

[0115] 8(A) shows an OFF mode signal. The OFF mode signal is a signal output from the sub-controller 222, and has N polarity, so it is Hi during normal operation and Lo during OFF mode. The OFF mode signal may also have P polarity. FIG. 8(B) shows the SLEEP-P signal.

[0116] 8(C) shows the voltage input to the IN terminal of the DC-DC converter 136. In other words, it is the output voltage of the secondary rectifying and smoothing circuit 144. FIG. 8(D) shows the voltage output from the DC-DC converter 136.

[0117] FIG. 8(E) shows the voltage output from the bypass circuit FET 238a of the bypass circuit 238. FIG. 8(F) shows the voltage output from the Zener diode 138c arranged on the output side of the bypass circuit FET 238a of the bypass circuit 138. FIG. 8(G) shows the voltage across electrolytic capacitor 250e of off-mode energy saving circuit 250.

[0118] FIG. 8(H) shows DC 5V output from the power supply 230. FIG. 8(H) shows DC 24V output from the power supply 230.

[0119] First, in the initial mode, print mode, or standby mode, as shown in Figures 8(A) and 8(B), the OFF mode signal output from the sub-controller 222 is Hi and the SLEEP-P signal is Lo. As a result, as shown in Figure 8(C), a voltage of DC 24V is output from the secondary rectifying smoothing circuit 144 and input to the IN terminal of the DC-DC converter 136.

[0120] The DC-DC converter 136 converts DC 24V into DC 5V, and as shown in FIG. 4(D), the voltage output from the DC-DC converter 136 becomes 5V.

[0121] Furthermore, the SLEEP-P signal output from the sub-controller 222 is Lo, and the OFF mode signal is Hi, but since they are inverted by a known technique and input to the bypass circuit FET 238a, the gate terminal of the bypass circuit FET 138a becomes Lo. As a result, the drain-source voltage of the bypass circuit FET 238a is turned off, and the voltage output from the bypass circuit FET 138a of the bypass circuit 138 becomes 0 V, as shown in FIG. 8(E). Furthermore, since the front-stage transistor 137b of the brown in / out circuit 137 is turned on and the rear-stage transistor 137c is turned off, the voltage output from the Zener diode 138c also becomes 0V, as shown in FIG. 8(F).

[0122] As shown in FIG. 8(G), the voltage output from off-mode energy saving circuit 250 is DC 5V.

[0123] As a result of the above, in normal mode, as shown in Figure 8(H), DC 5V is output from the power supply 230 to the sub-control block 120, and as shown in Figure 8(I), DC 24V is output from the power supply 230 to the main control block 110.

[0124] At time t21, when the sub-control unit 222 determines to transition to sleep mode after a set time has elapsed or when the user presses the mechanical switch 103, the sub-control unit 222 sets the SLEEP-P signal to Hi, as shown in Figure 8(B).

[0125] As a result, the DC 24V set voltage conversion transistor 134c, which changes the shunt regulator voltage dividing resistor of the voltage feedback unit 134, turns on, and the set voltage of the shunt regulator 134a is changed. The set voltage may be any value, but as an example, in this embodiment, it is set to DC 5V. By changing the set voltage of the shunt regulator 134a from DC 24V to DC 5V, as shown in Figure 8(C), the DC 24V output from the secondary rectifying and smoothing circuit 144 drops, and at time t22 it becomes DC 5V and is maintained at that voltage.

[0126] Furthermore, since the Zener voltage of the brown-in-out Zener diode 137a of the brown-in-out circuit 137 is set to be higher than DC 5V, a voltage of 5V is output from the secondary rectifying smoothing circuit 144, turning off the front-stage transistor 137b of the brown-in-out circuit 137 and turning on the rear-stage transistor 137c, and the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Lo. As a result, the voltage output from the DC-DC converter 136 drops from 5V, as shown in FIG. 8(D).

[0127] Furthermore, since the SLEEP-P signal output from the sub-control unit 222 becomes Hi, the gate terminal of the bypass circuit FET 138a becomes Hi, the drain-source voltage turns on, and as shown in Figure 8 (E), the voltage output from the bypass circuit FET 238a of the bypass circuit 238 rises from 0V, drops from time t23, and remains at 5V from time t24. Furthermore, since the front-stage transistor 137b of the brown in / out circuit 137 is turned off and the rear-stage transistor 137c is turned on, the voltage output from the Zener diode 138c also rises from 0V and becomes 5V at time t22, as shown in Figure 8(F).

[0128] In the off-mode energy saving circuit 250, the LINE and NEUTRAL voltages of the output of the protection element 140 of the power supply 130 are capacitor-coupled by the capacitors 250a and 250b, and the voltage is rectified by the bridge diode 250c consisting of four diodes in the subsequent stage, clamped to 5V by the Zener diode 250d, and smoothed by the electrolytic capacitor 250e to be output. As a result, the output from the off-mode energy saving circuit 250 is DC 5V, as shown in Fig. 8(G).

[0129] As a result, in sleep mode, as shown in Figure 8(H), DC 5V is output from power supply 230 to sub-control block 120, and as shown in Figure 8(I), the voltage supplied from power supply 230 to main control block 110 drops from DC 24V at time t21 and becomes 0V at time T22.

[0130] At time t25, when the sub-control unit 222 determines that a transition to another low power consumption mode, the OFF mode, has occurred due to the passage of a set time or the user pressing the mechanical switch 103, the sub-control unit 222 sets the OFF mode signal to Lo, as shown in Figure 8(A).

[0131] When the OFF mode signal becomes Lo, the power supply control unit 233d of the primary-secondary conversion unit 233 stops operating, and switching is stopped, so that the DC 5V output from the secondary rectification smoothing circuit 144 drops to 0V at time t26, as shown in Figure 8(C), and that voltage is maintained.

[0132] At time t26, the voltage output from the secondary rectifying smoothing circuit 144 becomes 0V, and therefore, as shown in FIG. 8(E), the voltage output from the bypass circuit FET 238a of the bypass circuit 238 also becomes 0V, and as shown in FIG. 8(F), the voltage output from the Zener diode 138c also becomes 0V.

[0133] As described above, in the OFF mode, the operation of the primary-secondary conversion unit 233 is also stopped, thereby further reducing power consumption.

[0134] 9A to 9I are time charts showing signals and voltages when the image forming apparatus 11 according to the second embodiment returns from the OFF mode. Figures 9(A) to (I) show the signals and voltages when the image forming device 11 transitions from OFF mode to Sleep mode, and from Sleep mode to Initial mode in which it prepares for printing, Print mode in which it performs printing, or Standby mode in which it waits for printing. The horizontal axes in FIGS. 9(A) to (I) represent time, and the vertical axes in FIGS. 9(A) to (I) are the same as the vertical axes in FIGS. 8(A) to (I), respectively.

[0135] First, in the OFF mode, according to the time charts shown in Figures 8(A) to 8(I), as shown in Figure 9(A), the OFF mode signal output from the sub-controller 222 is Lo and the SLEEP-P signal is Hi. As a result, as shown in Figure 9(C), the voltage from the secondary rectifying smoothing circuit 144 is 0V. As a result, the voltage input to the IN terminal of DC-DC converter 136 also becomes 0 V, and as shown in Fig. 9(D), the voltage output from DC-DC converter 136 also becomes 0 V, and as shown in Fig. 9(E), the voltage output from bypass circuit FET 138a of bypass circuit 138 also becomes 0 V. Furthermore, as shown in Fig. 9(F), the voltage output from Zener diode 138c also becomes 0 V.

[0136] However, as shown in Figure 9(G), the output from the off-mode energy saving circuit 250 is DC 5V. Therefore, in the sleep mode, as shown in Figure 9(H), DC 5V is output from the power supply 230 to the sub-control block 120. However, as shown in Figure 9(I), the output power from the power supply 230 to the main control block 110 is 0V.

[0137] At time t31, when the sub-control unit 222 determines that the mode is to be restored from the OFF mode, for example, when the user presses the mechanical switch 103, the sub-control unit 222 sets the OFF mode signal to Hi, as shown in FIG. 9(A).

[0138] As a result, the power supply control unit 233d of the primary-secondary conversion unit 233 starts operating and performs switching, and as shown in Figure 9(C), the output from the primary-secondary conversion unit 233 increases to DC 5V.

[0139] Since the voltage output from the secondary rectifying smoothing circuit 144 is 5V, the voltage output from the bypass circuit FET 238a of the bypass circuit 238 also becomes 5V, as shown in FIG. 9(E), and the voltage output from the Zener diode 138c also becomes 5V, as shown in FIG. 9(F). As shown in FIG. 9(G), the output from the off-mode energy saving circuit 250 is maintained at DC 5V.

[0140] As a result, in the sleep mode, the OFF mode signal output from the sub-controller 222 is Hi, and the SLEEP-P signal is also Hi, as shown in Figure 9(A) and Figure 9(B). As a result, a voltage of DC 5V is output from the secondary rectifying smoothing circuit 144 and input to the IN terminal of the DC-DC converter 136, as shown in Figure 9(C). Also, as shown in FIG. 9(D), the voltage output from the DC-DC converter 136 becomes 0V, as shown in FIG. 9(E), the voltage output from the bypass circuit FET 138a of the bypass circuit 138 becomes 5V, and as shown in FIG. 9(F), the voltage output from the Zener diode 138c also becomes 5V. Furthermore, as shown in FIG. 9(G), the output from the off mode energy saving circuit 250 is held at DC 5V.

[0141] As shown in Figure 9(H), DC 5V is output from the power supply 230 to the sub-control block 120, and as shown in Figure 9(I), the output power from the power supply 230 to the main control block 110 is 0V.

[0142] At time t32, when the sub-control unit 222 determines to return from sleep mode, for example by the user pressing the mechanical switch 103, the sub-control unit 222 sets the SLEEP-P signal to Lo, as shown in FIG. 9(B).

[0143] As a result, the DC24V setting voltage conversion transistor 134c, which changes the shunt regulator voltage dividing resistance of the voltage feedback unit 134, is turned off, and the setting voltage of the shunt regulator 134a is changed to DC24V. As shown in FIG. 9C, the DC5V output from the secondary rectifying smoothing circuit 144 rises and becomes DC24V at time t33, and that voltage is maintained.

[0144] In addition, the Zener voltage of the brown-in-out Zener diode 137a of the brown-in-out circuit 137 is set to be higher than DC 5V, and when the voltage from the secondary rectifying smoothing circuit 144 rises to 24V and reaches the Zener voltage, the front-stage transistor 137b of the brown-in-out circuit 137 turns on and the rear-stage transistor 137c turns off, and the voltage input to the ENABLE terminal of the DC-DC converter 136 becomes Hi. 9(D), the voltage output from DC-DC converter 136 rises from 0 V. Then, at time t35, the voltage output from DC-DC converter 136 becomes 5 V and is maintained at that voltage.

[0145] The Zener voltage is arbitrary and is determined by the ENABLE function of the DC-DC converter 136 used and peripheral constants.

[0146] When the SLEEP-P signal input to the gate voltage of the bypass circuit FET 238a of the bypass circuit 238 becomes Lo, the drain-source voltage of the bypass circuit FET 238a is turned off, but it does not immediately turn off due to the surrounding CR time constant. Therefore, as shown in Figure 9(E), the voltage output from the bypass circuit FET 238a of the bypass circuit 238 rises from 5V, drops from time t34, and reaches 0V from time t36.

[0147] However, since it is clamped by the Zener voltage of the Zener diode 138c, the voltage output from the Zener diode 138c remains at 5 V, as shown in Fig. 9(F), and then starts to decrease from time t36, and thereafter becomes 0 V.

[0148] At time t33, as shown in Fig. 9(C), the voltage output from the secondary rectifying smoothing circuit 144 reaches 24 V and is then maintained at 24 V. As a result, as shown in Fig. 9(I), the voltage supplied from the power supply 230 to the main control block 110 becomes DC 24 V.

[0149] At time t36, the output from bypass circuit FET 238a of bypass circuit 238 reaches 0 V and is then maintained at 0 V. However, as shown in Fig. 9(D), the output of DC-DC converter 136 is maintained at 5 V, and further as shown in Fig. 9(G), the output from off mode energy saving circuit 250 is also maintained at DC 5 V, so an output of DC 5 V is maintained from power supply 230 to sub-control block 120 as shown in Fig. 9(I).

[0150] As described above, according to the second embodiment, when transitioning to sleep mode, the operation of the DC-DC converter 136 is stopped, the power output voltage is converted to a logic output voltage, and this is bypassed to the sub-control block 220, and when transitioning to OFF mode, the operation of the primary-secondary conversion unit 233 is stopped, thereby making it possible to reduce unnecessary power consumption of the power supply circuit and improve overall power supply efficiency. In other words, in embodiment 2, in normal mode, DC 24V is output as the power output voltage and DC 5V is output as the logic output voltage from power supply 230, and in sleep mode and OFF mode, DC 5V is output as the logic output voltage from power supply 230.

[0151] The above-described first and second embodiments have been described using a printer, particularly a tandem four-color printer, as an example, but the first and second embodiments are not limited to this example. The first and second embodiments may also be used for other image forming devices, such as a printer with five or more colors, a printer with less than four colors, a monochrome printer, or a copying machine. [Explanation of symbols]

[0152] 10,11 image forming device, 20 paper feed unit, 30 image forming unit, 50 fixing unit, 60 paper discharge unit, 110 main control block, 120,220 sub control block, 130,230 power supply, 131 heater on / off circuit, 132 primary rectification smoothing circuit, 133,233 primary-secondary conversion unit, 134 voltage feedback unit, 135 DC24V on / off switch, 136 DC-DC converter, 137 brown in / out circuit, 138,238 bypass circuit, off mode energy saving circuit.

Claims

1. a rectifying and smoothing unit that rectifies and smoothes the AC voltage to output a smoothed voltage; a converter that is insulated from a supply side of the AC voltage and converts the smoothed voltage into a power output voltage in a first mode; a step-down unit that steps down the power output voltage to a logic output voltage that is a voltage lower than the power output voltage, In a second mode in which power consumption is lower than that in the first mode, the conversion unit converts the smoothed voltage into the logic output voltage instead of the power output voltage; the step-down unit stops operating in the second mode, In the first mode, the power output voltage and the logic output voltage are output, and in the second mode, the logic output voltage is output. A power supply device comprising:

2. The converter further includes an output section that includes two capacitors connected in series to the two supply paths of the AC voltage, and outputs the logic output voltage by rectifying and smoothing the voltage discharged from the two capacitors, and is connected in parallel with the conversion section; In a third mode in which power consumption is lower than that in the second mode, the operation of the conversion unit is also stopped, and the logic output voltage is output from the output unit.

2. The power supply device according to claim 1,

3. a bypass unit that, in the second mode, outputs the logic output voltage converted by the conversion unit by bypassing the step-down unit; 3. The power supply device according to claim 1 or 2,

4. The bypass unit has a switch that turns off the connection line from the conversion unit in the first mode and turns on the connection line from the conversion unit in the second mode.

4. The power supply device according to claim 3,

5. The switch is a relay.

5. The power supply device according to claim 4,

6. The switch is a semiconductor.

5. The power supply device according to claim 4,

7. The switch is turned on or off according to a signal that turns on or off the second mode.

5. The power supply device according to claim 4,

8. The conversion unit switches the output voltage between the power output voltage and the logic output voltage in accordance with a signal that turns on or off the second mode.

2. The power supply device according to claim 1,

9. The power supply device according to any one of claims 1, 2 and 8 is provided. An image forming apparatus comprising:

10. The power supply device according to claim 3 is provided. An image forming apparatus comprising:

11. The power supply device according to claim 4 is provided. An image forming apparatus comprising:

12. The power supply device according to claim 5 is provided. An image forming apparatus comprising:

13. The power supply device according to claim 6 is provided. An image forming apparatus comprising:

14. The power supply device according to claim 7 is provided. An image forming apparatus comprising:

Images