Power supply control circuit, switching power supply including power supply control circuit, and electronic apparatus including switching power supply

Abstract

To provide a switching power supply that prevents an occurrence of noise and an electronic apparatus including the same.SOLUTION: In an electronic apparatus 300, a power supply control circuit 201 includes a reference voltage generating circuit 10, a slope voltage generation circuit 9 that generates a slope voltage Vsl, and a drive control circuit 11 that turns on a switching element SW1 when the maximum off period arrives. When a specific condition is satisfied, the drive control circuit 11 applies an offset to the slope voltage Vsl, shortens the maximum off period, or shortens the maximum off period while applying the offset to the slope voltage Vsl.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a power supply control circuit, a switching power supply including a power supply control circuit, and an electronic device including a switching power supply. [Background technology]

[0002] Switching power supplies are used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2024-3305

[0005] [overview] However, conventional switching power supplies have room for improvement in terms of noise.

[0006] The power supply control circuit disclosed in this specification controls a transformer that forms an isolated switching power supply and includes a switch element, a reference voltage generation circuit, a slope voltage generation circuit, and a drive control circuit. The switch element is configured to turn on / off a primary current flowing through the transformer. The reference voltage generation circuit is configured to generate a reference voltage by sampling and holding a switch voltage appearing at one end of the transformer during an off period of the switch element. The slope voltage generation circuit is configured to generate a slope voltage that fluctuates relative to a reference voltage during the off period. The drive control circuit is configured to turn on the switch element when the reference voltage and the slope voltage match during the off period, or when the off period reaches a maximum off period while they do not match. The drive control circuit applies an offset to the slope voltage, or shortens the maximum off period, or shortens the maximum off period while applying an offset to the slope voltage, when a specific condition is met.

[0007] The switching power supply disclosed in this specification includes a power supply control circuit having the above-described configuration, a transformer configured to transmit a primary current flowing on the primary side to the secondary side as a secondary current while isolating the primary current, and an output transistor configured to be turned on / off by a drive voltage appearing on the secondary side in accordance with the secondary current.

[0008] The electronic device disclosed in this specification includes a switching power supply having the above-described configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a switching power supply 1. [Figure 2] FIG. 2 is a timing chart showing an example of output feedback control by the power supply control circuit 201. In FIG. [Figure 3] FIG. 3 is a timing chart showing ringing (surge) of the switch voltage Vsw. [Figure 4]FIG. 4 is a block diagram showing the configuration of the drive control circuit 11 of the switching power supply 1 according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram showing the configuration of the first reference voltage generating circuit 24. As shown in FIG. [Figure 6] FIG. 6 is a timing chart showing the application of the offset ofs by the offset circuit 22. In FIG. [Figure 7] FIG. 7 is a diagram showing the configuration of a drive control circuit 11 according to the second embodiment. [Figure 8] FIG. 8 is a timing chart showing the timing of on / off control of the drive signal G1 according to the second embodiment. [Figure 9] FIG. 9 is a timing chart showing the on / off control of the drive signal G1 when the switch element SW1 is forcibly turned on three or more times in succession.

[0010] [Detailed explanation] <Basic configuration> Fig. 1 is a diagram showing the overall configuration of a switching power supply 1. First, a configuration that serves as a comparative example of the present disclosure will be described using Fig. 1. Note that this configuration example includes components common to the switching power supply 1 of the present disclosure. For this reason, the configuration of this comparative example is assigned the same reference numerals as the components common to the switching power supply 1 of the present disclosure, which will be described later.

[0011] As shown in FIG. 1, the switching power supply 1 of this configuration example is an isolated DC / DC converter (a so-called flyback power supply) that converts a DC input voltage VIN supplied to the primary circuit system into a desired DC output voltage VOUT and supplies it to the secondary circuit system (in this figure, an isolated gate driver 202) while electrically insulating the primary circuit system (GND1 system) from the secondary circuit system (GND2 system).

[0012] The isolated gate driver 202 drives a high-side output transistor 210 and a low-side output transistor 211 in response to an output voltage VOUT supplied from the switching power supply 1. The high-side output transistor 210 and the low-side output transistor 211 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0013] The following describes the basic configuration of the switching power supply 1. The switching power supply 1 includes a transformer TR1, a diode D1, a capacitor C1, a resistor R1, and a power supply control circuit 201.

[0014] The transformer TR1 electrically isolates the primary circuit system from the secondary circuit system and transmits the primary current flowing through the primary circuit system to the secondary circuit system as a secondary current. The transformer TR1 has a primary winding L1 and a secondary winding L2. The primary winding L1 and the secondary winding L2 are insulated from each other and electromagnetically coupled with each other in opposite polarities.

[0015] A first end of the primary winding L1 is connected to an application terminal of the input voltage VIN. A second end of the primary winding L1 is connected to a first end of the resistor R1. A first end of the secondary winding L2 is connected to an anode of the diode D1. A cathode of the diode D1 is connected to a first end of the capacitor C1. A second end of the secondary winding L2 and a second end of the capacitor C1 are connected to a ground terminal GND2 of the secondary circuit system.

[0016] When an input voltage Vin is applied to the primary winding L1, an induced voltage is generated in the secondary winding L2 according to the input voltage Vin. The induced voltage generated in the secondary winding L2 is rectified by the diode D1, smoothed by the capacitor C1, and converted into an output voltage Vout. The output voltage Vout is output from the connection node between the cathode of the diode D1 and the first end of the capacitor C1.

[0017] The power supply control circuit 201 has a plurality of external terminals (terminals T1 to T4 in this figure) as means for establishing communication with the outside. The power supply control circuit 201 also has a switch element SW1, a reference voltage generation circuit 10, and a drive control circuit 11.

[0018] Terminal T1 is connected to a first end of primary winding L1 and to a terminal to which input voltage VIN is applied. Terminal T2 is connected to a first end of resistor R1. Terminal T3 is connected to a second end of primary winding L1 and to a second end of resistor R1. Terminal T4 is connected to ground terminal GND1 of the primary circuit system via resistor R2.

[0019] The switch element SW1 is an N-channel MOSFET. The drain terminal of the switch element SW1 is connected to the primary winding L1 via the terminal T3. The source terminal of the switch element SW1 is connected to the ground terminal GND1. The gate terminal of the switch element SW1 is connected to the driver 14, which will be described later. The switch element SW1 is turned on / off in response to a drive signal G1 input to its gate terminal.

[0020] The reference voltage generating circuit 10 generates the reference voltage Vref by sampling the terminal voltage VFB appearing at the terminal T2 during the off period Toff of the switch element SW1. The specific configuration of the reference voltage generating circuit 10 is as follows.

[0021] The reference voltage generating circuit 10 includes a voltage detecting circuit 101 and a sample / hold circuit 102.

[0022] The voltage detection circuit 101 is connected to terminals T1, T2, and T4. The voltage detection circuit 101 generates a monitor voltage V0 (=I0×R2) that corresponds to the monitor current IO and the resistor R2 by flowing a monitor current I0 that corresponds to the inter-terminal voltage (=VIN-VFB) between the terminals T1 and T2 to the terminal T4.

[0023] The sample / hold circuit 102 is connected to the terminal T4. The sample / hold circuit 102 samples the monitor voltage V0 at a predetermined timing and generates a reference voltage Vref based on the sampled monitor voltage V0. The sample / hold circuit 102 inputs the reference voltage Vref to the non-inverting input terminal (+) of the comparator 12.

[0024] The slope voltage generation circuit 9 generates a slope voltage Vsl. The slope voltage Vsl is a slope waveform obtained by dulling a pulse signal. For example, the slope voltage Vsl can be a slope waveform that rises at the timing of the rising edge of the pulse signal and falls at the timing of the falling edge. The slope voltage generation circuit 9 inputs the slope voltage Vsl to the inverting input terminal (-) of the comparator 12.

[0025] The drive control circuit 11 turns on / off the switch element SW1 in accordance with the reference voltage Vref and the slope voltage Vsl. The specific configuration of the drive control circuit 11 is as follows.

[0026] The drive control circuit 11 includes a slope voltage generating circuit 9, a comparator 12, a controller 13, and a driver .

[0027] The comparator 12 compares the reference voltage Vref with the slope voltage Vsl and generates a comparison signal S1 according to the comparison result. For example, when the slope voltage Vsl is less than the reference voltage Vref, the comparator 12 causes the comparison signal S1 to fall to a low level. Conversely, when the slope voltage Vsl is greater than the reference voltage Vref, the comparator 12 causes the comparison signal S1 to rise to a high level.

[0028] The controller 13 receives the comparison signal S1 from the comparator 12, generates a control signal S2 according to the comparison signal S1, and controls the on / off of the switch element SW1. Specifically, the controller 13 determines the on timing of the switch element SW1 using a pulse edge (e.g., a falling edge) of the comparison signal S1 as a trigger. The controller 13 also determines the off timing of the switch element SW1 using the lapse of a predetermined on-period Ton after the switch element SW1 is turned on as a trigger.

[0029] The controller 13 also has a function of forcibly turning on the switch element SW1 when the off-period Toff of the switch element SW1 reaches a predetermined maximum off-period MAXoff. The maximum off-period MAXoff is set to be longer than a normal switching period (e.g., 2.8 μS). For example, the maximum off-period MAXoff is set to be the period from when the drive signal G1 falls from high level to low level until 350 μS has elapsed.

[0030] The driver 14 generates a drive signal G1 for the switch element SW1 in response to the control signal S2. For example, the driver 14 raises the drive signal G1 to high level when the switch element SW1 is to be turned on, turning on the switch element SW1. Conversely, the driver 14 raises the drive signal G1 to low level when the switch element SW1 is to be turned off, turning off the switch element SW1.

[0031] Although FIG. 1 illustrates only the power supply control circuit 201 that controls the power to drive the high-side output transistor 210, a power supply control circuit equivalent to the power supply control circuit 201 is provided as a power supply control circuit that controls the power to drive the low-side output transistor 211 (not shown).

[0032] <Basic operation> We will now briefly explain the basic operation of the switching power supply 1. During the on-period Ton of the switch element SW1, a primary current flows from the input voltage VIN application terminal to the ground terminal GND1 via the primary winding L1 and the switch element SW1. Therefore, electrical energy is stored in the primary winding L1.

[0033] On the other hand, during the off period Toff of the switch element SW1, an induced voltage is generated in the secondary winding L2 magnetically coupled to the primary winding L1, and a secondary current flows from the secondary winding L2 to the ground terminal GND2 via the diode D1 and the capacitor C1. At this time, an output voltage VOUT is output, which is obtained by rectifying and smoothing the induced voltage of the secondary winding L2.

[0034] Thereafter, the switching element SW1 is turned on / off to repeat the same switching output operation as above.

[0035] As described above, the switching power supply 1 of this embodiment can generate a desired output voltage VOUT from the input voltage VIN while electrically insulating the primary circuit system from the secondary circuit system.

[0036] <Output feedback control> FIG. 2 is a timing chart showing an example of output feedback control by the power supply control circuit 201, and depicts, from top to bottom, the output voltage VOUT, the switch voltage Vsw, the monitor voltage V0, the operating state of the sample / hold circuit 102, the reference voltage Vref, the slope voltage Vsl, and the drive signal G1.

[0037] 2, at time t1, when the drive signal G1 falls from high to low, the switch element SW1 switches from on to off. As a result, the switch voltage Vsw starts to rise from low to high. At this time, the output voltage VOUT changes from a falling state to an rising state.

[0038] During the off period Toff (=times t1 to t4) of the switch element SW1, a monitor voltage V0 is generated according to the inter-terminal voltage (=VIN-Vsw) between the terminals T1 and T2. The monitor voltage V0 corresponds to the flyback voltage of the transformer TR1 (and thus information on the output voltage VOUT) contained in the switch voltage Vsw.

[0039] Between times t2 and t3, the reference voltage Vref is generated (updated) by sample / hold processing of the monitor voltage V0.

[0040] At time t4, the slope voltage Vsl exceeds the reference voltage Vref, and the drive signal G1 rises from low to high, switching the switch element SW1 from off to on. As a result, the switch voltage Vsw begins to decrease from high to low. At this time, the output voltage VOUT changes from increasing to decreasing.

[0041] The above series of output feedback controls are repeated after time t4, resulting in a stabilized output voltage VOUT.

[0042] As shown in the figure, at the timing (=time t1) when the switch voltage Vsw rises from low level to high level, ringing (surge) occurs in the switch voltage Vsw due to the leakage inductance of the transformer TR1.

[0043] Therefore, in order to avoid interfering with the output feedback control, it is desirable that the voltage detection circuit 101 sets a delay time Ta (time t1 to t2 in this figure, for example, a maximum of 270 ns) to remove ringing (surge) from the switch voltage Vsw and generate the monitor voltage V0.

[0044] In addition, in the power supply control circuit 201, a sampling mask period Tb (times t1 to t2 in this figure, e.g., a minimum of 150 ns) and a sampling end time Tc (times t1 to t3 in this figure, e.g., a minimum of 300 ns) are set starting from the turn-off timing of the switch element SW1 so that a stable voltage value of the monitor voltage V0 can be read by the sample / hold circuit 102.

[0045] During the sampling mask period Tb, the sampling process of the monitor voltage V0 by the sample / hold circuit 102 is internally masked. The sampling end time Tc determines the timing at which the sampling of the monitor voltage V0 ends (= the hold timing). Therefore, the sampling process of the monitor voltage V0 is performed from the end of the sampling mask period Tb until the sampling end time Tc has elapsed (times t2 to t3 in this figure).

[0046] <Considerations regarding ringing (surge) of switch voltage Vsw> 3 is a timing chart showing ringing (surge) of the switch voltage Vsw, which depicts, from top to bottom, the monitor voltage V0, the reference voltage Vref, the slope voltage Vsl, and the drive signal G1.

[0047] 3 correspond to times t1, t3, and t4 in the timing chart shown in FIG. 2. That is, time t4 is the timing at which the slope voltage Vsl matches the reference voltage Vref in a normal switching cycle. The maximum off period MAXoff is depicted as the period from time t1 to time t5.

[0048] As shown in FIG. 3, when a relatively large ringing (surge) occurs in the switch voltage Vsw, the ringing (surge) may remain in the sampled monitor voltage V0 even at time t3 after the sampling end time Tc has elapsed.

[0049] In this case, the reference voltage Vref may be set higher than the maximum value of the slope voltage Vsl. As a result, the slope voltage Vsl remains lower than the reference voltage Vref even after time t4, and the drive signal G1 remains low. This lengthens the off period Toff of the switch voltage Vsw, disrupting the switching cycle. In this situation, the isolated switching power supply 1, which performs output feedback control using only the primary circuit, may experience unstable switching behavior, which in turn may cause the output voltage VOUT to become unstable.

[0050] As described above, the controller 13 has a function of forcibly turning on the switch voltage Vsw when the maximum off period MAXoff has elapsed. Therefore, when time t5 arrives after the maximum off period MAXoff has elapsed, the drive signal G1 rises to a high level, and the switch element SW1 is forcibly turned on. However, the maximum off period MAXoff (=300 μS) is set to be relatively long compared to the normal switching period (=2.8 μS). Therefore, if the controller 13 were to forcibly turn on the switch element SW1, there is a risk that the disruption of the switching period of the switch element SW1 would become apparent.

[0051] <Regarding the switching power supply 1 according to the first embodiment of the present disclosure> In contrast, the switching power supply of the present disclosure is capable of suppressing the above-mentioned problems. The following describes a switching power supply 1 of the present disclosure. Note that this corresponds to the switching power supply 1 described above, and the same reference numerals are used to designate common components, and descriptions thereof will be omitted.

[0052] The drive control circuit 11 of the switching power supply 1 according to the first embodiment of the present disclosure is configured to add an offset ofs to the slope voltage Vsl when a predetermined condition (hereinafter simply referred to as a "specific condition") is satisfied.

[0053] The specific condition can be set to at least one of the following: (1) the voltage value of the reference voltage Vref is greater than the maximum value of the slope voltage Vsl excluding the offset, (2) the off period Toff exceeds a predetermined time Td (e.g., 3.5 μS), or (3) both (1) and (2) are satisfied. Here, an example will be described in which the specific condition is set to (1) the voltage value of the reference voltage Vref is greater than the maximum value of the slope voltage Vsl excluding the offset.

[0054] 4 is a block diagram showing the configuration of the drive control circuit 11 of the switching power supply 1 according to the first embodiment of the present disclosure. As shown in FIG. 4, the drive control circuit 11 includes a slope voltage generation circuit 9 and an offset circuit 22.

[0055] The slope voltage generating circuit 9 includes a voltage fluctuation control circuit 20, a resistor R5, a base voltage generating circuit 21, and an offset circuit 22.

[0056] The first reference voltage generating circuit 24 generates a predetermined first reference voltage V3.

[0057] The voltage fluctuation control circuit 20 receives the input of the turn-on signal S3 (=fluctuation voltage) and controls the voltage fluctuation of the slope voltage Vsl in accordance with the turn-on signal S3. The turn-on signal S3 is a pulse signal that is generated to be at a high level when the switch element SW1 is turned on and at a low level when the switch element SW1 is turned off. The turn-on signal S3 can be generated by the controller 13, for example, and input to the slope voltage generating circuit 9. The specific configuration of the voltage fluctuation control circuit 20 is as follows.

[0058] The voltage fluctuation control circuit 20 includes resistors R3 and R4, a capacitor C2, transistors N1, P1, and P2, and an operational amplifier OP1.

[0059] A first terminal of the resistor R3 is connected to the terminal to which the turn-on signal S3 is applied. A second terminal of the resistor R3, together with a first terminal of the capacitor C2, is connected to the non-inverting input terminal (+) of the operational amplifier OP1. A second terminal of the capacitor C2 is connected to the ground terminal GND1. The resistor R3 and the capacitor C2 function as an RC circuit that smooths and blunts the pulse waveform of the turn-on signal S3. A voltage V1, which is the turn-on signal S3 smoothed by this RC circuit, is generated at the connection node between the resistor R3 and the capacitor C2.

[0060] The transistor N1 is an N-channel MOSFET. The gate terminal of the transistor N1 is connected to the output terminal of the operational amplifier OP1. The source terminal of the transistor N1 is connected to the inverting input terminal (-) of the operational amplifier OP1 together with the first terminal of the resistor R4. The second terminal of the resistor R4 is connected to the ground terminal GND1. A voltage V2 is generated at the connection node between the transistor N1 and the resistor R4. The voltage value of the voltage V2 is determined based on the current value of the current I1 flowing from the transistor N1 to the resistor R4 and the resistance value of the resistor R4.

[0061] The operational amplifier OP1 generates a control signal S4 corresponding to the difference between voltages V1 and V2. As described above, the output terminal of the operational amplifier OP1 is connected to the inverting input terminal (-) of the transistor N1, forming a feedback loop. This causes the operational amplifier OP1 to control the control signal S4 (and, by extension, the driving of the transistor N1) so that the voltage V1 input to the non-inverting input terminal (+) and the voltage V2 input to the inverting input terminal (-) match (i.e., create an imaginary short).

[0062] The transistors P1 and P2 are P-channel MOSFETs. The drain terminal of the transistor P1 is connected to the drain terminal of the transistor N1, its own gate terminal, and the gate terminal of the transistor P2. The source terminals of the transistors P1 and P2 are both connected to the terminal to which the reference voltage Vcc is applied. The drain terminal of the transistor P2 is connected to the first terminal of the resistor R5.

[0063] The transistors P1 and P2 form a current mirror circuit. The above-mentioned current I1 (= the current flowing to the ground terminal GND1 via the reference voltage Vcc, the transistor P1, the transistor N1, and the resistor R4) is mirrored and flows through the transistor P2 as a mirror current I2.

[0064] The base voltage generating circuit 21 includes resistors R6 and R7, a capacitor C3, a first reference voltage generating circuit 24, and an operational amplifier OP2 (differential amplifier circuit).

[0065] The first terminal of resistor R6, together with the first terminal of resistor R3, is connected to the terminal to which turn-on signal S3 is applied. The second terminal of resistor R6, together with the first terminal of resistor R7 and the first terminal of capacitor C3, is connected to the non-inverting input terminal (+) of operational amplifier OP2. The second terminal of resistor R7, together with the second terminal of capacitor C3 and the second terminal of resistor R5, is connected to the output terminal of operational amplifier OP2.

[0066] The first reference voltage generating circuit 24 is connected to the inverting input terminal (-) of the operational amplifier OP2. The first reference voltage generating circuit 24 generates a first reference voltage V3 and inputs it to the inverting input terminal (-) of the operational amplifier OP2. The first reference voltage V3 is a predetermined constant voltage.

[0067] The operational amplifier OP2 generates a control signal S4 according to the difference between the turn-on signal S3 input via the resistor R6 and the first reference voltage V3. The output terminal of the operational amplifier OP2 is connected to the second terminal of the resistor R4.

[0068] <Generation of the slope voltage Vsl> When the turn-on signal S3 is at a high level, the voltage V1 rises. Then, the operational amplifier OP1 controls the driving of the transistor N1 so as to create an imaginary short circuit. Specifically, the conductivity of the transistor N1 is increased to increase the current value of the current I1, and the voltage value of the voltage V2 is increased so as to approach the voltage value of the voltage V1.

[0069] On the other hand, when the turn-on signal S3 is at a low level, the voltage V1 drops. Similarly, the operational amplifier OP1 controls the operation of the transistor N1 so as to create an imaginary short circuit. Specifically, the conductivity of the transistor N1 is decreased, the current value of the current I1 is decreased, and the voltage value of the voltage V2 is decreased so as to approach the voltage value of the voltage V1.

[0070] In this way, when the turn-on signal S3 is at a high level, the current I1 rises, and when the turn-on signal S3 is at a low level, the current I1 falls. As described above, the current I1 is mirrored as the mirror current I2 by the current mirror circuit formed by the transistors P1 and P2.

[0071] The mirror current I2 flows through the resistor R5. As described above, the second terminal of the resistor R5 is connected to the output terminal of the operational amplifier OP2. Therefore, a slope voltage Vsl (=I2×R5+S4) is generated at the connection node between the transistor P2 and the resistor R5, with a voltage corresponding to the mirror current I2 and the resistance value of the resistor R5 being added to the control signal S4.

[0072] As described above, the mirror current I2 (=current I1) fluctuates so as to alternately rise and fall in response to the voltage value of the turn-on signal S3, and therefore the slope voltage Vsl also has a slope-like waveform that alternately rises and falls in response to the turn-on signal S3.

[0073] <Regarding the offset circuit 22> The offset circuit 22 is configured to add an offset ofs to the slope voltage Vsl when a specific condition is satisfied. The offset circuit 22 has the following specific configuration.

[0074] The offset circuit 22 includes a constant current source 23 (=current generating circuit), an offset control circuit 35, and a switch SW2.

[0075] The constant current source 23 generates a predetermined offset current I3. The output terminal of the constant current source 23 is connected to a first terminal of the switch SW2. The second terminal of the switch SW2 is connected to the connection node between the drain terminal of the transistor P2 and the resistor R5. The switch SW2 is configured to receive a drive signal S5 from the offset control circuit 35 and to be turned on / off in response to the drive signal S5.

[0076] The offset control circuit 35 generates a drive signal S5 and controls the on / off of the switch SW2. More specifically, the offset control circuit 35 raises the drive signal S5 to a high level when a specific condition is met. Conversely, if the specific condition is not met, the offset control circuit 35 maintains the drive signal S5 at a low level.

[0077] As described above, the specific condition here is that the voltage value of the reference voltage Vref is greater than the maximum value of the slope voltage Vsl excluding the offset. The offset control circuit 35 determines whether the specific condition is met, for example, as follows.

[0078] The offset control circuit 35 monitors the voltage V1, and if the turn-on signal S3 does not rise to a high level for a predetermined time (= if the voltage V1 does not rise for a predetermined time), it determines that the value of the reference voltage Vref is greater than the maximum value of the slope voltage Vsl and the switch element SW1 does not turn on (= the turn-on signal S3 does not rise to a high level), determining that the above-mentioned specific condition is met, and raises the drive signal S5 to a high level.

[0079] The switch SW2 is in a conductive state (ON) when the logic level of the drive signal S5 is high, and is in a non-conductive state (OFF) when the logic level of the drive signal S5 is low.

[0080] When the switch SW2 is in a conductive state, an offset current I3 flows from the constant current source 23 to the connection node between the transistor P2 and the resistor R5. As a result, the offset current I3 is combined with the mirror current I2, increasing the current flowing into the resistor R5. This increases the slope voltage Vsl, i.e., an offset ofs is applied to the slope voltage Vsl.

[0081] Furthermore, the offset control circuit 35 according to this embodiment may be configured to input the drive signal S5 to the first reference voltage generation circuit 24. When this configuration is adopted, the configuration for causing the offset current I3 to flow into the resistor R5 may also be provided or may be omitted.

[0082] When this configuration is employed, the first reference voltage generating circuit 24 changes the voltage value of the first reference voltage V3 between a first logic level and a second logic level in accordance with the drive signal S5.

[0083] In this case, for example, when a specific condition is not satisfied and the offset control circuit 35 sets the drive signal S5 to a low level (= a state in which the offset ofs is not applied to the slope voltage Vsl), the first reference voltage generation circuit 24 sets the voltage value of the first reference voltage V3 to the first logical level.

[0084] On the other hand, when a specific condition is satisfied and the offset control circuit 35 raises the drive signal S5 to a high level, the first reference voltage generation circuit 24 drops the voltage value of the first reference voltage V3 to a second logic level that is a constant voltage lower than the first logic level. When the voltage value of the first reference voltage V3 drops to the second logic level, the voltage value of the control signal S4 is raised and the slope voltage Vsl increases (= an offset ofs is applied to the slope voltage Vsl).

[0085] 5 is a diagram showing the configuration of the first reference voltage generating circuit 24. As shown in FIG. 5, in the above-described case, the first reference voltage generating circuit 24 is a voltage dividing circuit including variable resistors Rv1 and Rv2. A first terminal of the variable resistor Rv1 is connected to a terminal to which a reference voltage Vcc is applied. A second terminal of the variable resistor Rv1 is connected to a first terminal of the variable resistor Rv2. A second terminal of the variable resistor Rv2 is connected to a ground terminal GND1. The variable resistors Rv1 and Rv2 are configured so that their resistance values ​​can be changed in response to the input of a drive signal S5.

[0086] The first reference voltage V3 is generated at the connection node between the variable resistors Rv1 and Rv2. The first reference voltage V3 has a voltage value corresponding to the voltage division ratio determined by the variable resistors Rv1 and Rv2. As described above, when adding an offset to the slope voltage Vsl, the offset circuit 22 inputs the drive signal S5 to the variable resistors Rv1 and Rv2 and controls the voltage division ratio so that the voltage value of the first reference voltage V3 becomes the second logic level.

[0087] <Regarding offset timing control> 6 is a timing chart showing the application of the offset ofs by the offset circuit 22. Times t1, t3, and t4 shown in FIG. 6 are the same as those shown in FIGS.

[0088] 6, when a relatively large ringing (surge) occurs in the switch voltage Vsw, the ringing (surge) remains in the sampled monitor voltage V0 even at time t3 after the sampling end time Tc has elapsed.Furthermore, suppose that the reference voltage Vref is set higher than the slope voltage Vsl excluding the offset ofs.

[0089] Even in this case, at time t4' when the offset circuit 22 determines that the specific condition is satisfied, the offset ofs is applied to the slope voltage Vsl. This causes the slope voltage Vsl to match the reference voltage Vref. Therefore, the drive signal G1 rises to a high level, and the switch element SW1 is turned on.

[0090] As described above, the power supply control circuit 201 of this embodiment applies an offset to the slope voltage Vsl when a specific condition is satisfied, so that the slope voltage Vsl coincides with the reference voltage Vref. This makes it possible to forcibly turn on the switch element SW1 even if a relatively large ringing (surge) occurs in the switch voltage Vsw and the ringing (surge) remains in the sampled monitor voltage V0. This prevents the off period Toff of the switch voltage Vsw from becoming longer, making the switching period less likely to be disrupted. This in turn prevents the output voltage VOUT from becoming unstable. Furthermore, it also prevents the disruption of the switching period of the switch element SW1 from becoming apparent.

[0091] <Regarding the Switching Power Supply 1 According to the Second Embodiment> Next, a description will be given of a second embodiment of the switching power supply 1. The following will focus on differences from the first embodiment, and the same components as those in the first embodiment will be given the same reference numerals and will not be described.

[0092] The drive control circuit 11 of the switching power supply 1 according to the second embodiment of the present disclosure is configured to temporarily shorten the maximum off period MAXoff when a specific condition is met.

[0093] For convenience, the normal maximum off period MAXoff that is not shortened will be referred to as the "normal maximum off period MAXoff1," and the shortened maximum off period MAXoff will be referred to as the "reduced maximum off period MAXoff2." In addition, the following description will be given taking as an example a case where the specific condition is set as (2) the off period Toff exceeding a predetermined time Td (for example, 3.5 μS).

[0094] 7 is a diagram showing the configuration of a drive control circuit 11 according to the second embodiment. As shown in FIG.

[0095] The forced-on control circuit 25 is connected to the driver 14. The forced-on control circuit 25 generates a forced-on signal S6 and inputs it to the driver 14.

[0096] The forced-on control circuit 25 raises the forced-on signal S6 to high level when the normal maximum off period MAXoff1 arrives while the specific conditions are not satisfied, and also raises the forced-on signal S6 to high level when the reduced maximum off period MAXoff2 arrives while the specific conditions are satisfied.

[0097] When the driver 14 detects that the force-on signal S6 has risen to a high level, it raises the drive signal G1 to a high level to turn on the switch element SW1 regardless of the logic level of the control signal S2. When the force-on signal S6 is at a low level, the driver 14 controls the on / off of the switch element SW1 using the drive signal G1 based on the control signal S2, as described above.

[0098] <Detailed Configuration of the Forced-ON Control Circuit 25> The forced-on control circuit 25 includes a second reference voltage generating circuit 27, a charging voltage generating circuit 28, and a comparator 29 (comparison circuit).

[0099] The second reference voltage generating circuit 27 generates a second reference voltage V6 and inputs it to the non-inverting input terminal (+) of the comparator 29. The second reference voltage generating circuit 27 sets the voltage value of the second reference voltage V6 to a high voltage setting value (first setting value) when a specific condition is not satisfied, and sets the voltage value of the second reference voltage V6 to a low voltage setting value (second setting value) when the specific condition is satisfied. The detailed configuration of the second reference voltage generating circuit 27 will be described later.

[0100] The charging voltage generation circuit 28 generates a charging voltage V5 and inputs it to the inverting input terminal (-) of the comparator 29. The charging voltage generation circuit 28 increases the voltage value of the charging voltage V5 from a predetermined initial value (e.g., the ground voltage GND1) at a constant rate during the off period Toff of the switch element SW1. The charging voltage generation circuit 28 also resets the voltage value of the charging voltage V5 to its initial value when the switch element SW1 is turned on. The initial value of the charging voltage V5 is lower than the high voltage setting value and the low voltage setting value. The detailed configuration of the charging voltage generation circuit 28 will be described later.

[0101] The comparator 29 compares the second reference voltage V6 with the charging voltage V5 and generates a force-on signal S6 according to the comparison result. Specifically, when the voltage value of the second reference voltage V6 is higher than the charging voltage V5, the comparator 29 sets the force-on signal S6 to low level. Conversely, when the voltage value of the charging voltage V5 is higher than the second reference voltage V6, the comparator 29 raises the force-on signal S6 to high level.

[0102] <Operation of the forced-on control circuit 25> Suppose that a relatively large ringing (surge) occurs in the switch voltage Vsw, and that the ringing (surge) remains in the monitor voltage V0 sampled at time t3 after the sampling end time Tc has elapsed, and furthermore, that the reference voltage Vref is set higher than the maximum value of the slope voltage Vsl.

[0103] In this case, as described above, the slope voltage Vsl does not match the reference voltage Vref, and the off period Toff of the switch element SW1 continues. During this off period Toff, the charging voltage V5 is charged and the voltage value continues to rise.

[0104] Here, when the specific condition is not satisfied, as described above, the second reference voltage V6 is set to the high voltage setting value. Until the voltage value of the charging voltage V5 reaches the high voltage setting value, the comparator 29 maintains the forced-on signal S6 at a low level. When the voltage value of the charging voltage V5 exceeds the high voltage setting value, the comparator 29 raises the forced-on signal S6 to a high level. This forces the switch element SW1 to be turned on. By forcing the switch element SW1 to be turned on, the charging voltage V5 is reset to its initial value (=ground voltage GND1).

[0105] On the other hand, when a specific condition is satisfied, as described above, the second reference voltage V6 is set to the low voltage setting value. Until the voltage value of the charging voltage V5 reaches the low voltage setting value, the comparator 29 maintains the forced-on signal S6 at a low level. When the voltage value of the charging voltage V5 exceeds the low voltage setting value, the comparator 29 raises the forced-on signal S6 to a high level. This forces the switch element SW1 to be turned on. By forcing the switch element SW1 to be turned on, the charging voltage V5 is reset to its initial value (=ground voltage GND1).

[0106] In this way, depending on whether the specific condition is satisfied, the second reference voltage generation circuit 27 sets the voltage value of the second reference voltage V6 to either a high voltage setting value or a low voltage setting value. As a result, when the specific condition is not satisfied, the off period Toff of the switching element SW1, and therefore the charging period of the charging voltage V5, is longer than when the specific condition is satisfied. In other words, when the specific condition is satisfied, the maximum off period MAXoff until the switching element SW1 is forcibly turned on is shortened from the normal maximum off period MAXoff1 to the shortened maximum off period MAXoff2.

[0107] Then, if the switch element SW1 is forcibly turned on twice in succession due to the lapse of the reduced maximum off period MAXoff2, the maximum off period MAXoff is extended from the reduced maximum off period MAXoff2 to the normal maximum off period MAXoff1. Therefore, when the next (=third) reduced maximum off period MAXoff2 has elapsed, the switch element SW1 is not forcibly turned on even if the specific condition is satisfied. Then, when the normal maximum off period MAXoff1 has elapsed thereafter, the switch element SW1 is forcibly turned on.

[0108] <Detailed Configuration of Second Reference Voltage Generation Circuit 27> The second reference voltage generating circuit 27 includes a counter circuit 26, an inverter 30, a transistor N1, and resistors R8 to R10.

[0109] Counter circuit 26 is configured to detect whether the number of consecutive occurrences of reduced maximum off-period MAXoff2 has reached two, and to generate count voltage V7 according to the detection result. When the number of consecutive occurrences of reduced maximum off-period MAXoff2 has not reached two, counter circuit 26 sets count voltage V7 to low level. Conversely, when the number of consecutive occurrences of reduced maximum off-period MAXoff2 has reached two, counter circuit 26 raises count voltage V7 to high level. The specific configuration of counter circuit 26 is as follows.

[0110] The counter circuit 26 includes D flip-flops 26 a and 26 b and a NAND gate 31 .

[0111] The input terminal (D) of the D flip-flop 26a is connected to the terminal to which the reference voltage Vcc is applied. The output terminal (Q) of the D flip-flop 26a is connected to the input terminal (D) of the D flip-flop 26b. The reset input terminal (R) of the D flip-flop 26a, together with the reset input terminal (R) of the D flip-flop 26b, is connected to the output terminal of the NAND gate 31. The output terminal (Q) of the D flip-flop 26b is connected to the input terminal of the inverter 30. The D flip-flops 26a and 26b are configured as negative logic and are reset when a low-level signal is input to the reset input terminal (R).

[0112] A first input terminal of the NAND gate 31 is connected to a terminal to which the comparison signal S1 is applied, and a second input terminal of the NAND gate 31 is connected to the output terminal of the D flip-flop 26b.

[0113] During the off period Toff of the switch element SW1, when the shortened maximum off period MAXoff2 arrives once and the comparator 29 raises the forced on signal S6 to a high level as described above, the input terminal (D) of the D flip-flop 26a is fixed to a high level value (the voltage value of the reference voltage Vcc), and a high level voltage is output from the output terminal (Q) of the D flip-flop 26a. At this time, the voltage value of the input terminal (D) of the D flip-flop 26b is a low level, and a low level count voltage V7 is output from the output terminal (Q) of the D flip-flop 26b.

[0114] Thereafter, when the second shortened maximum off period MAXoff2 arrives without the switch element SW1 being turned on, the comparator 29 again raises the forced on signal S6 to high level in the manner described above, whereupon the input terminal (D) of the D flip-flop 26b is fixed to a high level value (the voltage value of the output terminal (Q) of the D flip-flop 26a, the voltage value of the reference voltage Vcc), and a high level count voltage V7 is output from the output terminal (Q) of the D flip-flop 26b.

[0115] As described above, the D flip-flops 26a and 26b are configured with negative logic. Therefore, when the comparison signal S1 and the forced-on signal S6 both become high, the voltage values ​​at the input terminals (D) of the D flip-flops 26a and 26b are reset. Specifically, this is the case, for example, as follows.

[0116] For example, when the comparison signal S1 rises to high level while the force-on signal S6 is maintained at high level (i.e., when the slope voltage Vsl exceeds the reference voltage Vref), the NAND gate 31 drops the reset signal SR to low level. This resets the voltage values ​​at the input terminals (D) of the D flip-flops 26a and 26b (the count number is reset), and the count voltage V7 drops to low level. Note that, as described above, when the comparison signal S1 rises to high level, the charging voltage V5 is reset to an initial value lower than the high voltage setting value and the low voltage setting value, causing the force-on signal S6 to go low level. Therefore, the reset signal SR drops to low level, resetting the voltage values ​​at the input terminals (D), and then the reset signal SR rises to high level again.

[0117] On the other hand, the voltage values ​​at the input terminals (D) of the D flip-flops 26a and 26b are not reset but maintained when at least one of the comparison signal S1 and the forced-on signal S6 is at a low level. Specifically, this is the case, for example, as follows.

[0118] For example, when the slope voltage Vsl is lower than the reference voltage Vref, the comparison signal S1 goes low. Even if the slope voltage Vsl exceeds the reference voltage Vref and the comparison signal S1 rises to a high level, the charging voltage V5 is reset to an initial value lower than the high voltage setting value and the low voltage setting value, as described above, and the forced-on signal S6 goes low. In these cases, the voltage values ​​at the input terminals (D) of the D flip-flops 26a and 26b are not reset. This concludes the description of the counter circuit 26.

[0119] The transistor N2 is an N-channel MOSFET. The gate terminal of the transistor N2 is connected to the output terminal of the inverter 30. The drain terminal of the transistor N2 is connected to the first terminal of the resistor R8. The source terminal of the transistor N2 is connected to the second terminal of the resistor R8.

[0120] The inverter 30 receives the count voltage V7 and outputs a voltage obtained by inverting the logical level of the count voltage V7 to control the on / off of the transistor N2. Specifically, when the count voltage V7 is at a low level, the inverter 30 inputs a high-level output voltage to the gate terminal of the transistor N2 to turn the transistor N2 on. Conversely, when the count voltage V7 is at a high level, the inverter 30 inputs a low-level output voltage to the gate terminal of the transistor N2 to turn the transistor N2 off.

[0121] A second terminal of the resistor R8 is connected to the ground terminal GND1. A first terminal of the resistor R9 is connected to the first terminal of the resistor R8. A second terminal of the resistor R9, together with a first terminal of the resistor R10, is connected to the non-inverting input terminal (+) of the comparator 29. A second terminal of the resistor R10 is connected to the terminal to which the reference voltage Vcc is applied. The resistance value of the resistor R8 is larger than the value of the on-resistance of the transistor N2.

[0122] When the transistor N2 is in the off state, a second reference voltage V6 is generated at the connection node n1 (= the non-inverting input terminal (+) of the comparator 29) between the resistors R9 and R10, which corresponds to the voltage division ratio of the combined resistance of the resistors R8 and R9 and the resistor R10. When the transistor N2 is in the off state, the voltage value of the second reference voltage V6 is a high voltage setting value.

[0123] When the transistor N2 is on, a second reference voltage V6 is generated at the connection node n1 according to the voltage division ratio of the combined resistance of the on-resistance of the transistor N2 and the resistor R9 to the resistor R10. When the transistor N2 is on, the voltage value of the second reference voltage V6 is the low voltage setting value.

[0124] The charging voltage generating circuit 28 includes a constant current source 32, a capacitor C4, and a switch SW3. The constant current source 32 is connected between an application terminal of a reference voltage Vcc and a first terminal of the capacitor C4. The first terminal of the capacitor C4 is connected to the non-inverting input terminal (-) of the comparator 29. The second terminal of the capacitor C4 is connected to a first terminal of the switch SW3. The second terminal of the switch SW3 is connected to the ground terminal GND1.

[0125] When switch SW3 is in the off state, a charging current I4 flows from constant current source 32 to capacitor C4. This charges capacitor C4. A charging voltage V5 corresponding to the amount of charge in capacitor C4 is generated at the first terminal of capacitor C4 (= the non-inverting input terminal (-) of comparator 29).

[0126] The switch SW3 is turned on when the switch element SW1 is turned on, and is off during the off period Toff of the switch element SW1. When the switch SW3 is turned on, the charge in the capacitor C4 is discharged to the ground terminal GND1. As a result, the charge voltage V5 is reset to its initial value (=ground voltage GND1).

[0127] <Controlling the extension of the maximum off period MAXoff> As described above, when the number of consecutive forced ONs of the switch element SW1 due to the lapse of the shortened maximum OFF period MAXoff2 is one or less, the count voltage V7 becomes low. Then, the output voltage of the inverter 30 becomes high, turning on the transistor N1. At this time, the voltage value of the second reference voltage V6 becomes a voltage value (=low voltage setting value) according to the voltage division ratio of the combined resistance of the resistor R9 and the ON resistance of the transistor N1 to the resistor R10.

[0128] As described above, when the number of consecutive forced-on cycles of switch element SW1 due to the lapse of the reduced maximum off period MAXoff2 reaches two, count voltage V7 goes high. This causes the output voltage of inverter 30 to go low, turning off transistor N1. At this time, the value of second reference voltage V6 is raised to a voltage value (= high voltage setting value) that corresponds to the voltage division ratio of resistor R10 to the combined resistance of resistors R9 and R8. This lengthens the charging period of charging voltage V5, extending the maximum off period MAXoff from reduced maximum off period MAXoff2 to normal maximum off period MAXoff1.

[0129] <Regarding control of drive signal G1 according to the second embodiment> 8 is a timing chart showing the timing of on / off control of the drive signal G1 according to the second embodiment. From top to bottom, Fig. 8 depicts the monitor voltage V0, the reference voltage Vref, the slope voltage Vsl, and the drive signal G1. Note that this description deals with the case where the forced on of the switch element SW1 due to the lapse of the reduced maximum off period MAXoff2 is executed only once.

[0130] When the sampling end time Tc elapses from time 21 and time t22 arrives, the reference voltage Vref is set based on the monitor voltage V0 at that time. At this time, the reference voltage Vref is set higher than the maximum value of the slope voltage Vsl. Therefore, at time t23, when the predetermined time Td (e.g., 3.5 μS) specified as the specific condition has elapsed, the slope voltage Vsl has not reached the reference voltage Vref, and the off period Toff of the switch element SW1 is longer than usual. This means that the specific condition is satisfied.

[0131] Then, at time t24, when the reduced maximum off-period MAXoff2 has elapsed since time t21, the drive control circuit 11 raises the drive signal G1 to high level, as described above, which forcibly turns on the switch element SW1.

[0132] Thereafter, at the preset off timing of the switch element SW1 (time t25 in this figure), the drive signal G1 falls to low level. When the sampling end time Tc has elapsed from time t25 and time t26 has arrived, the reference voltage Vref is set based on the monitor voltage V0 at that time.

[0133] As shown in the figure, assume that at time t26, the reference voltage Vref is set lower than the maximum value of the slope voltage Vsl. In this case, the slope voltage Vsl exceeds the reference voltage Vref at time t26. However, at this time, the drive control circuit 11 (more specifically, the controller 13 and the driver 14) controls the drive signal G1 to maintain a low level until time t27, when a predetermined time has elapsed. After time t27, the same control is repeated.

[0134] 9 is a timing chart showing the on / off control of the drive signal G1 when the switch element SW1 is forcibly turned on three or more times in succession. From top to bottom, FIG. 9 depicts the monitor voltage V0, the reference voltage Vref, the slope voltage Vsl, and the drive signal G1. The time periods t21 to t25 shown in this diagram are the same as the time periods t21 to t25 described above. Using this diagram, we will explain the control when the switch element SW1 is forcibly turned on two times in succession due to the lapse of the reduced maximum off period MAXoff2.

[0135] From time t21 to time t24, the switch element SW1 is forcibly turned on by the reduced maximum off period MAXoff2 in the manner described above.

[0136] Thereafter, at the preset off timing of the switch element SW1 (time t25 in this figure), the drive signal G1 falls to a low level. When the sampling end time Tc has elapsed from time t25 and time t26' arrives, the reference voltage Vref is set based on the monitor voltage V0 at that time.

[0137] At this time, assume that the reference voltage Vref is again set higher than the maximum value of the slope voltage Vsl, as shown in FIG. 9. At time t27', a predetermined time Td (=3.5 μS) has elapsed since time t26', the slope voltage Vsl has not reached the reference voltage Vref, and the off period Toff of the switch element SW1 is longer than usual. This means that the specific condition is again satisfied. Then, at time t28, when the reduced maximum off period MAXoff2 has elapsed, the drive signal G1 rises to a high level, and the switch element SW1 is forcibly turned on.

[0138] At this time, the counter circuit 26 counts the number of consecutive forced ONs of the switch element SW1 as two, and the voltage value of the second reference voltage V6 is raised to the high voltage setting.

[0139] Thereafter, at the preset off timing of the switch element SW1 (time t29 in this figure), the drive signal G1 falls to low level. When the sampling end time Tc has elapsed from time t29 and time t26' arrives, the reference voltage Vref is set based on the monitor voltage V0 at that time.

[0140] At this time, it is assumed that the reference voltage Vref is set higher than the maximum value of the slope voltage Vsl as shown in Fig. 8. Therefore, similar to the times t23 and t27', the specific condition is satisfied again.

[0141] As described above, the second reference voltage V6 is set to a high voltage value. That is, at time t30, which is the time when the normal maximum off period MAXoff1 has elapsed since time t29, the drive signal G1 rises to a high level, and the switch element SW1 is forcibly turned on.

[0142] As described above, the power supply control circuit 201 of this embodiment can shorten the maximum off period MAXoff from the normal maximum off period MAXoff1 to the shortened maximum off period MAXoff2 when certain conditions are satisfied. Therefore, even if a relatively large ringing (surge) occurs in the switch voltage Vsw and the reference voltage Vref is set to exceed the maximum value of the slope voltage Vsl, the switch element SW1 can be forcibly turned on after the shortened maximum off period MAXoff2 has elapsed. This prevents the off period Toff of the switch voltage Vsw from becoming longer, making the switching period less likely to be disrupted. This in turn prevents the output voltage VOUT from becoming unstable. Furthermore, it prevents the disruption of the switching period of the switch element SW1 from becoming apparent.

[0143] Furthermore, after the switch element SW1 is forcibly turned on when the reduced maximum off period MAXoff2 has elapsed, even if the next set reference voltage Vref is lower than the slope voltage Vsl, the drive signal G1 is not raised to a high level but is maintained at a low level for a predetermined time (from time t26 to time t27 shown in FIG. 8), thereby preventing the off period Toff of the switch element SW1 from becoming excessively short.

[0144] <Modification> The present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, the configuration of the power supply control circuit 201 according to the first embodiment may be combined with the configuration of the power supply control circuit 201 according to the second embodiment. That is, when a specific condition is satisfied, an offset may be applied to the slope voltage Vsl, and the maximum off period MAXoff may be shortened from the normal maximum off period MAXoff1 to the shortened maximum off period MAXoff2.

[0145] Furthermore, one of the specific conditions described above is that (1) the voltage value of the reference voltage Vref is greater than the maximum value of the slope voltage Vsl excluding the offset. However, this "maximum value of the slope voltage Vsl" may be replaced with another predetermined value.

[0146] The switching power supply 1 can be installed in applications such as in-vehicle equipment (for example, an electric compressor and a main inverter), consumer equipment, industrial machinery, or electronic equipment 300 installed in these.

[0147] <Additional Notes> The power supply control circuit (201) disclosed in the specification is a power supply control circuit (201) that controls a transformer (TR1) that forms an isolated switching power supply, and includes a switch element (SW1) configured to turn on / off a primary current flowing through the transformer (TR1), a reference voltage generation circuit (10) configured to sample and hold a switch voltage appearing at one end of the transformer (TR1) during an off period (Toff) of the switch element (SW1) to generate a reference voltage (Vref), and a slope voltage generation circuit (10) configured to generate a slope voltage (Vsl) that fluctuates relatively to the reference voltage (Vref) during the off period (Toff). (9) and a drive control circuit (11) configured to turn on the switch element (SW1) when the reference voltage (Vref) and the slope voltage (Vsl) match during the off period (Toff), or when the off period (Toff) reaches the maximum off period (MAXoff) while they do not match, wherein the drive control circuit (11) is configured to impart an offset (ofs) to the slope voltage (Vsl), or shorten the maximum off period (MAXoff), or shorten the maximum off period (MAXoff) while imparting the offset (ofs) to the slope voltage (Vsl) when a specific condition is satisfied (first configuration).

[0148] In the power supply control circuit (201) according to the first configuration, the drive control circuit (11) may be configured to include: a current generating circuit (23) configured to generate an offset current (I3); and an offset circuit (22) connected between an output terminal of the current generating circuit (23) and an output terminal of the slope voltage generating circuit (9), configured to feed the offset current (I3) into the slope voltage generating circuit (9) when a specific condition is satisfied, thereby imparting an offset (ofs) corresponding to the offset current (I3) to the slope voltage (Vsl) (second configuration).

[0149] In the power supply control circuit (201) according to the first or second configuration, the slope voltage generation circuit (9) includes a differential amplifier circuit (OP2) configured to generate a variable voltage (S3) whose voltage value fluctuates in synchronization with a switch voltage (Vsw) and a slope voltage (Vsl) according to the difference between the variable voltage (S3) and a first reference voltage (V3), and a voltage fluctuation control circuit (20) configured to control fluctuations in the slope voltage (Vsl) according to the variable voltage (S3), and the drive control circuit (11) is preferably configured to add an offset (ofs) to the first reference voltage (V3) when a specific condition is satisfied (third configuration).

[0150] In a power supply control circuit (201) according to any one of the first to third configurations, a drive control circuit (11) includes a charging voltage generation circuit (28) configured to generate a charging voltage (V5) such that the voltage value rises from a predetermined initial value at a constant rate during an off period (Toff) and the voltage value is reset to the initial value during an on period (Ton) of a switch element (SW1), a second reference voltage generation circuit (27) configured to generate a second reference voltage (V6), and a second reference voltage generation circuit (27) configured to compare the second reference voltage (V6) with the charging voltage (V5) during the off period (Toff) and generate an on signal (S6) according to the comparison result. and a comparator circuit (29) configured to drive the switch element (SW1), wherein the second reference voltage generating circuit (27) sets the logic level of the second reference voltage (V6) to a first set value when a specific condition is not satisfied, and sets the logic level of the second reference voltage (V6) to a second set value when the specific condition is satisfied, and the switch element (SW1) is configured to turn on / off according to the logic level of the on signal (S6), and the first logic level has a voltage value higher than the initial value, and the second logic level has a voltage value higher than the initial value and lower than the first logic level (fourth configuration).

[0151] The power supply control circuit (201) according to any one of the first to fourth configurations may be configured so that the specific condition is at least one of the following: when the voltage value of the reference voltage (Vref) generated by sample-and-holding is greater than the maximum value of the slope voltage (Vsl) excluding the offset (ofs); when a predetermined period shorter than the maximum off period (MAXoff) has elapsed as the off period (Toff); or when the switch element (SW1) has been turned on after the maximum off period (MAXoff) has elapsed consecutively (fifth configuration).

[0152] The switching power supply (1) disclosed in the specification comprises a power supply control circuit (201) according to any one of the first to fifth configurations, a transformer (TR1) configured to transmit a primary current flowing on the primary side to the secondary side as a secondary current while isolating the primary current, and output transistors (210, 211) configured to be turned on / off by a drive voltage appearing on the secondary side in response to the secondary current (sixth configuration).

[0153] The electronic device includes the switching power supply (1) according to the sixth configuration (seventh configuration). [Explanation of symbols]

[0154] 1. Switching power supply 9 Slope voltage generation circuit 10 Reference voltage generation circuit 11 Drive control circuit 12 Comparators 13 Controller 14 Drivers 20 Variable voltage generating circuit 21 Base voltage generation circuit 22 Offset circuit 23 Constant current source 24 First reference voltage generating circuit 25 Forced-on control circuit 26 Counter Circuit 26a, 26b D flip-flop 27 Second reference voltage generation circuit 28 Charging voltage generation circuit 29 Comparator 30 inverters 31 NAND gates 32 Constant current source 35 Offset control circuit 101 Voltage detection circuit 102 Sample / Hold Circuit 201 Power supply control circuit 202 Isolated Gate Driver 210 High-side output transistor 211 Low-side output transistor C1~C4 capacitors D1 Diode G1 drive signal GND1 Ground terminal GND2 Ground terminal I0 Monitor current I1 current I2 Mirror current I3 offset current I4 charging current L1 Primary winding L2 Secondary winding MAXoff Maximum off period MAXoff1 Normal maximum off period MAXoff2 Shortened maximum off period OP1, OP2 operational amplifiers N1 and N2 transistors P1 and P2 transistors R1~R10 Resistors Rv1, Rv2 variable resistors S1 Comparison signal S2 control signal S3 turn-on signal S4 control signal S5 drive signal S6 Forced on signal SR Reset signal SW1 Switch element SW2 switch SW3 switch T1~T4 terminals TR1 transformer Ta delay time Tb Sampling mask period Tc Sampling end time Td predetermined time Toff Off period Ton On period V0 monitor voltage V1, V2 voltage V3 First reference voltage V4 voltage V5 Charging voltage V6 Second reference voltage V7 Count voltage VFB pin voltage VIN Input voltage VOUT Output voltage Vcc reference voltage Vref Reference voltage Vsl Slope voltage Vsw Switch voltage

Claims

1. A power supply control circuit for controlling a transformer forming an isolated switching power supply, a switch element configured to turn on / off a primary current flowing through the transformer; a reference voltage generating circuit configured to generate a reference voltage by sampling and holding a switching voltage appearing at one end of the transformer during an off period of the switching element; a slope voltage generating circuit configured to generate a slope voltage that fluctuates relatively to the reference voltage during the off period; a drive control circuit configured to turn on the switch element when the reference voltage and the slope voltage match during the off period, or when the off period reaches a maximum off period while not matching; Including, When a specific condition is met, the drive control circuit adding an offset to the slope voltage; or reducing the maximum off period; Alternatively, a power supply control circuit that shortens the maximum off period while applying the offset to the slope voltage.

2. The drive control circuit includes: a current generating circuit configured to generate an offset current; an offset circuit connected between an output terminal of the current generating circuit and an output terminal of the slope voltage generating circuit, configured to cause the offset current to flow into the slope voltage generating circuit when the specific condition is satisfied, and to impart the offset corresponding to the offset current to the slope voltage; The power supply control circuit of claim 1 , comprising:

3. The slope voltage generating circuit comprises: a first reference voltage generating circuit configured to generate a first reference voltage; a differential amplifier circuit configured to generate the slope voltage in accordance with a difference between a fluctuating voltage whose voltage value fluctuates in synchronization with the switch voltage and the first reference voltage; a voltage fluctuation control circuit configured to control a fluctuation of the slope voltage in response to the fluctuating voltage; Including, The power supply control circuit according to claim 1 , wherein the drive control circuit applies the offset to the first reference voltage when the specific condition is satisfied.

4. The drive control circuit includes: a charging voltage generating circuit configured to generate a charging voltage such that a voltage value increases from a predetermined initial value at a constant rate during the off-period and the voltage value is reset to the initial value during the on-period of the switch element; a second reference voltage generating circuit configured to generate a second reference voltage; a comparison circuit configured to compare the second reference voltage with the charging voltage during the off period, and generate an on signal according to a comparison result to drive the switch element; Including, the second reference voltage generating circuit sets the logic level of the second reference voltage to a first set value when the specific condition is not satisfied, and sets the logic level of the second reference voltage to a second set value when the specific condition is satisfied; the switch element is configured to be turned on / off in response to a logic level of the on signal; the first set value is a voltage value higher than the initial value, 2. The power supply control circuit according to claim 1, wherein the second set value has a voltage value higher than the initial value and lower than the first set value.

5. The specific conditions are: When the voltage value of the reference voltage generated by sample and hold is greater than the maximum value of the slope voltage excluding the offset, Or, when a predetermined period shorter than the maximum off period has elapsed as the off period, Or, when the switch element is continuously turned on due to the lapse of the maximum off period, 5. The power supply control circuit according to claim 1, wherein the power supply control circuit is at least one of the above.

6. a power supply control circuit according to claim 1; the transformer configured to transfer the primary current flowing on the primary side as a secondary current to the secondary side while insulating it; an output transistor configured to be turned on / off by a drive voltage appearing on the secondary side in response to the secondary current; A switching power supply comprising:

7. An electronic device comprising the switching power supply according to claim 6.

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