DC-DC converter

Abstract

To provide a technique to reduce power loss while ensuring ZVS operations in a DAB converter when different voltages are applied to two full-bridge circuits.SOLUTION: A DC-DC converter has a configuration in which two full-bridge circuits are connected via a transformer and an inductor. A control circuit performs soft switching control of two switching elements in two legs of the two full-bridge circuits. Each switching element includes a parasitic capacitance, or an external capacitor connected in parallel. The control circuit provides dead time at switching timing of the two switching elements in the legs. The values of an inductor current IL at switching timing before and after a zero-cross point are set on the basis of an applied voltage to a full-bridge circuit on the side where switching is performed. In this way, unnecessary conduction time of a diode is reduced, and power loss is reduced, while ensuring ZVS operations.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present invention relates to a DC-DC converter. [Background technology]

[0002] In power conversion devices such as DC-DC converters, zero-volt switching (hereinafter referred to as ZVS) is used to reduce switching losses and transmit power with high efficiency, as well as to reduce noise, suppress switching surges, and use inexpensive elements with low voltage resistance.

[0003] Patent Document 1 discloses a method for performing ZVS operation with simple control and reducing switching loss by maintaining the current (inductor current) during switching at a constant level or higher when there is a voltage imbalance between the primary and secondary sides of a DAB (dual active bridge) converter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-5332 Summary of the Invention [Problem to be solved by the invention]

[0005] In this method, the DAB is driven to balance losses by matching the current value during primary switching with the current value during secondary switching. However, this method has the drawback of increasing the effective value of the inductor current. When the inductor current is large, copper loss in the inductor and transformer and conduction loss in the switching elements increase. In addition, there is a concern that when the switching elements are turned off while a large inductor current is flowing, a high dv / dt occurs, which could increase switching losses.

[0006] The charging and discharging energy to the parallel capacitor of the switching element varies depending on the DC voltage applied to the full-bridge circuit. Therefore, if the applied voltages are different between the primary-side full-bridge circuit and the secondary-side full-bridge circuit, setting the inductor current separately for each full-bridge circuit can reduce power loss and improve overall efficiency.

[0007] Therefore, an object of the present invention is to provide a technology for reducing power loss while ensuring ZVS operation when different voltages are applied to the primary-side full-bridge circuit and the secondary-side full-bridge circuit in a DAB converter. [Means for solving the problem]

[0008] In order to solve the above problems, a first invention of the present application provides a transformer including a primary full bridge circuit having two legs each including two switching elements, a secondary full bridge circuit having two legs each including two switching elements, a primary winding connected to the primary full bridge circuit, and a secondary winding connected to the secondary full bridge circuit and magnetically coupled to the primary winding, an inductance component connected in series to the primary winding or the secondary winding, and a control circuit for soft-switching control of the switching elements of the primary full bridge circuit and the secondary full bridge circuit, wherein the switching elements of the primary full bridge circuit and the secondary full bridge circuit each include a capacitor which is a parasitic capacitance or an external capacitor connected in parallel, and the control circuit controls the on / off of the two switching elements for each of the legs. At the switching timing for switching off, a dead time is provided in which both of the two switching elements of the legs are turned off; at a first switching timing, which is the switching timing immediately before the zero crossing point at which the polarity of the inductor current flowing through the transformer and the equivalent inductor of the inductance component is reversed, the switching elements of the legs of the primary side full bridge circuit are switched on and off; at a second switching timing, which is the switching timing immediately after the zero crossing point, the switching elements of the legs of the secondary side full bridge circuit are switched on and off; the absolute value of the value of the inductor current at the first switching timing is set based on the voltage applied to the primary side full bridge circuit, and the absolute value of the value of the inductor current at the second switching timing is set based on the voltage applied to the secondary side full bridge circuit.

[0009] A second invention of the present application is a DC-DC converter of the first invention, wherein the absolute value of the inductor current at the first switching timing is set so that the energy stored in the equivalent inductor is equal to or greater than the energy stored in the two capacitors included in the two switching elements that switch on and off at the first switching timing.

[0010] A third aspect of the present invention is the DC-DC converter of the second aspect, wherein the value of the inductor current at the first switching timing is I L1 , the input voltage of the primary side full bridge circuit is Vx, the capacitances of the two capacitors included in the two switching elements that switch on and off at the first switching timing are C1, the inductance of the equivalent inductor is L, and the correction coefficient is α.

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[0011] A fourth aspect of the present invention is the DC-DC converter of the second aspect, wherein the value of the inductor current at the first switching timing is I L1 , the input voltage of the primary side full bridge circuit is Vx, the input voltage of the secondary side full bridge circuit is Vy, the capacitances of the two capacitors included in the two switching elements that switch on and off at the first switching timing are C1, the inductance of the equivalent inductor is L, and the correction coefficient is α.

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[0012] A fifth invention of the present application is a DC-DC converter according to any one of the first to fourth inventions, wherein the absolute value of the inductor current at the second switching timing is set so that the energy stored in the equivalent inductor is equal to or greater than the energy stored in the two capacitors included in the two switching elements that switch on and off at the second switching timing.

[0013] A sixth aspect of the present invention is the DC-DC converter of the fifth aspect, wherein the value of the inductor current at the second switching timing is I L2, the input voltage of the secondary side full bridge circuit is Vy, the capacitances of the two capacitors included in the two switching elements that switch on and off at the second switching timing are C2, the inductance of the equivalent inductor is L, and the correction coefficient is α.

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[0014] A seventh aspect of the present invention is the DC-DC converter of the fifth aspect, wherein the value of the inductor current at the second switching timing is I L2 , the input voltage of the primary side full bridge circuit is Vx, the input voltage of the secondary side full bridge circuit is Vy, the capacitances of the two capacitors included in the two switching elements that switch on and off at the second switching timing are C2, the inductance of the equivalent inductor is L, and the correction coefficient is α.

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[0015] An eighth aspect of the present invention is the DC-DC converter of any one of the first to fourth aspects, wherein the dead time at the first switching timing is different from the dead time at the second switching timing. [Effects of the Invention]

[0016] According to the first to eighth aspects of the present invention, it is possible to reduce the effective value of the transformer current and reduce power loss while ensuring ZVS operation.

[0017] In particular, according to the eighth aspect of the present invention, the unnecessary conduction time of the diode can be further reduced, and power loss can be further reduced. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a circuit diagram of a DC-DC converter according to an embodiment of the present invention. [Figure 2] FIG. 2 is a timing chart of a DC-DC converter. [Figure 3] FIG. 2 is a timing chart of a DC-DC converter. [Figure 4] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 5] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 6] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 7] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 8] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 9] FIG. 2 is a diagram for explaining a current path in a DC-DC converter. [Figure 10] 10A and 10B are diagrams for explaining the control of the voltage output period and switching frequency of the full-bridge circuit relative to the output power when switching between the output angle modulation mode and the frequency modulation mode. [Figure 11] 10 is a diagram showing an example of a voltage value of a capacitor in a switching operation when the inductor current is the same at the first switching timing and the second switching timing. FIG. [Figure 12] 12 is a diagram showing an example of an inductor current in the switching operation of the example of FIG. 11 and the first embodiment. FIG. [Figure 13] FIG. 4 is a diagram showing an example of voltage values ​​of a capacitor in a switching operation according to the first embodiment. [Figure 14] FIG. 10 is a diagram showing an example of a voltage value of a capacitor in a switching operation of the second embodiment. [Figure 15] FIG. 10 is a diagram showing another example of the voltage value of the capacitor in the switching operation of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following, a dual active bridge (DAB) converter (hereinafter referred to as a DC-DC converter) will be described as an example of a "DC-DC converter" of the present invention.

[0020] <1. DC-DC converter circuit configuration> 1 is a circuit diagram of a DC-DC converter 1 according to this embodiment. In this embodiment, the operation of the DC-DC converter 1 will be described assuming that the input / output terminals IO11 and IO12, i.e., the first full-bridge circuit 10, are the primary side that receives power, and the input / output terminals IO21 and IO22, i.e., the second full-bridge circuit 20, are the secondary side that outputs power. However, it is also possible to use the second full-bridge circuit 20 as the primary side and the first full-bridge circuit 10 as the secondary side.

[0021] The DC-DC converter 1 includes a pair of input / output terminals IO11 and IO12, and a pair of input / output terminals IO21 and IO22. A DC power supply E1 is connected to the pair of input / output terminals IO11 and IO12. A DC power supply E2 is connected to the pair of input / output terminals IO21 and IO22.

[0022] DC-DC converter 1 transforms the power supply voltage of DC power supply E1 input from input / output terminals IO11 and IO12 and outputs it from input / output terminals IO21 and IO22. DC-DC converter 1 can also transform the power supply voltage E2 of the DC power supply input from input / output terminals IO21 and IO22 and output it from input / output terminals IO11 and IO12. In other words, DC-DC converter 1 is a converter capable of bidirectional power transmission.

[0023] The DC-DC converter 1 includes a first full-bridge circuit 10, a second full-bridge circuit 20, and a transformer T.

[0024] The transformer T includes a first winding n1 and a second winding n2. The first winding n1 and the second winding n2 are magnetically coupled. The first winding n1 is connected to input / output terminals IO11 and IO12 via a first full-bridge circuit 10. The second winding n2 is connected to input / output terminals IO21 and IO22 via a second full-bridge circuit 20.

[0025] The first full-bridge circuit 10 has a first leg 11 in which switching element Q11 and switching element Q12 are connected in series, and a second leg 12 in which switching element Q13 and switching element Q14 are connected in series. Diodes D11, D12, D13, and D14 and capacitors C11, C12, C13, and C14 are connected in parallel to the switching elements Q11, Q12, Q13, and Q14. The switching elements Q11 to Q14 are MOS-FETs. However, the switching elements Q11 to Q14 may also be IGBTs or JFETs, etc. The diodes D11 to D14 may be real elements or parasitic diodes. The capacitors C11 to C14 may also be real elements, parasitic capacitances, or a combination of parasitic capacitances and real elements.

[0026] Both ends of the first winding n1 of the transformer T are connected to the midpoints of the first leg 11 and the second leg 12. An inductor L1 is provided between the first winding n1 of the transformer T and the midpoint of the first leg 11. However, the inductor L1 only needs to be connected in series with the first winding n1 or the second winding n2, and its location can be changed as appropriate. For example, the inductor L1 may be provided between the first winding n1 and the midpoint of the second leg 12. Furthermore, the inductor L1 may be a real element, a leakage inductance of the transformer T, or a combination of a real element and a leakage inductance.

[0027] The second full-bridge circuit 20 has a third leg 21 in which switching element Q21 and switching element Q22 are connected in series, and a fourth leg 22 in which switching element Q23 and switching element Q24 are connected in series. Diodes D21, D22, D23, and D24 and capacitors C21, C22, C23, and C24 are connected in parallel to switching elements Q21, Q22, Q23, and Q24. Switching elements Q21 to Q24 are MOS-FETs. However, switching elements Q21 to Q24 may also be IGBTs or JFETs, etc. Diodes D21 to D24 may be real elements or parasitic diodes. Capacitors C21 to C24 may also be real elements, parasitic capacitances, or a combination of parasitic capacitances and real elements.

[0028] Both ends of the second winding n2 of the transformer T are connected to the midpoints of the third leg 21 and the fourth leg 22. The inductor L1 may be provided between the second winding n2 and the midpoint of the third leg 21 or the fourth leg 22.

[0029] The gate terminals of the switching elements Q11 to Q14 and the switching elements Q21 to Q24 are connected to the control circuit 30.

[0030] Control circuit 30 controls the switching of switching elements Q11-Q14 and Q21-Q24 based on target values ​​such as a target voltage value, a target current value, or a target power value input from an external device. Specifically, control circuit 30 includes a command controller 31, a control value calculation unit 32, and a switching control unit 33. Command controller 31 outputs a current command value and a power command value based on the target values ​​and passes them to control value calculation unit 32. Control value calculation unit 32 calculates various control values, such as voltage output periods τ1 and τ2, switching frequency f, and phase difference δ of full-bridge circuits 10 and 20 (described below), based on the current command value and the power command value. Then, switching control unit 33 inputs switching signals to switching elements Q11-Q14 and Q21-Q24 to turn them ON / OFF, based on the control values ​​calculated by control value calculation unit 32.

[0031] In this way, the control circuit 30 controls the switching of each of the switching elements Q11-Q14 and Q21-Q24 so that the output of the DC-DC converter 1 matches the target value. In this embodiment, the control circuit 30 soft-switches each of the switching elements Q11-Q14 and Q21-Q24 to reduce switching loss.

[0032] <2. Soft switching operation> The soft switching operation of each of the switching elements Q11 to Q14 and Q21 to Q24 will be described below. Note that in this embodiment, a 3-level DAB control is employed.

[0033] The DC-DC converter 1 transfers power from one of the input / output terminals IO11, IO12 and the input / output terminals IO21, IO22 to the other, or from the other to the other. In the following description, the input / output terminals IO11, IO12 are the input side (primary side), and the input / output terminals IO21, IO22 are the output side (secondary side).

[0034] In other words, in the following description, the first full-bridge circuit 10 is referred to as the "primary-side full-bridge circuit," the second full-bridge circuit 20 as the "secondary-side full-bridge circuit," the first winding n1 as the primary-side winding, and the second winding n2 as the secondary-side winding. Also, the inductor L1 is referred to as the "inductance component connected in series to the primary-side winding or the secondary-side winding."

[0035] Figures 2 and 3 are timing charts of the DC-DC converter 1. Figures 4 to 9 are diagrams for explaining current paths in the DC-DC converter 1. In Figures 4 to 9, the second full-bridge circuit 20 is simplified, and the inductor L1 and transformer T in Figure 1 are represented by an equivalent inductor L.

[0036] Fig. 2 shows a timing chart of the switching elements Q11 to Q14 of the first full-bridge circuit 10, the voltage V1 of the first full-bridge circuit 10, and the voltage V2 of the second full-bridge circuit 20. Fig. 3 shows a timing chart of the switching elements Q21 to Q24 of the second full-bridge circuit 20, the voltage V1 of the first full-bridge circuit 10, and the voltage V2 of the second full-bridge circuit 20.

[0037] The voltage V1 of the first full-bridge circuit 10 is the voltage between the midpoint between the switching elements Q11 and Q12 and the midpoint between the switching elements Q13 and Q14, as shown in FIG. 1. The voltage V2 of the second full-bridge circuit 20 is the voltage between the midpoint between the switching elements Q21 and Q22 and the midpoint between the switching elements Q23 and Q24. This example describes the case where the absolute values ​​of V1 and V2 are the same during the voltage output periods τ1 and τ2. L is the inductor current flowing through the inductor L (see FIGS. 4 to 9).

[0038] The control circuit 30 provides a phase difference and controls the switching of the first full-bridge circuit 10 and the second full-bridge circuit 20. Hereinafter, the phase difference between the first full-bridge circuit 10 and the second full-bridge circuit 20 is represented by δ. The control circuit 30 performs phase-shift PWM control at a switching frequency f (cycle 1 / f) in each of the first full-bridge circuit 10 and the second full-bridge circuit 20.

[0039] 2 and 3, in the switching of the first full-bridge circuit 10 and the second full-bridge circuit 20, for two switching elements arranged in the same leg, one switching element is turned off and the other switching element is turned on at the same switching timing. At one switching timing, a dead time is provided in which both of the two switching elements in the leg to be switched are turned off. That is, after one switching element in the leg to be switched is turned off, the other switching element is turned on after the dead time has elapsed.

[0040] During this dead time, a capacitor connected in parallel to the switching element that has been turned off is charged, and a capacitor connected in parallel to the switching element that will be turned on after the dead time is discharged. Since the switching element is turned on after the discharge is complete, soft switching can be performed.

[0041] In the examples of FIGS. 2 and 3, one switching period has eight switching timings at which the switching elements are switched on and off: times t1, t2, t3, t4, t5, t6, t7, and t8.

[0042] At time t1, switching element Q13 in the second leg 12 of the first full-bridge circuit 10 is turned off, and switching element Q14 is turned on. At time t2, switching element Q22 in the third leg 21 of the second full-bridge circuit 20 is turned off, and switching element Q21 is turned on. At time t3, switching element Q23 in the fourth leg 22 of the second full-bridge circuit 20 is turned off, and switching element Q24 is turned on. At time t4, switching element Q11 in the first leg 11 of the first full-bridge circuit 10 is turned off, and switching element Q12 is turned on.

[0043] At time t5, switching element Q14 of the second leg 12 of the first full-bridge circuit 10 is turned off, and switching element Q13 is turned on. At time t6, switching element Q21 of the third leg 21 of the second full-bridge circuit 20 is turned off, and switching element Q22 is turned on. At time t7, switching element Q24 of the fourth leg 22 of the second full-bridge circuit 20 is turned off, and switching element Q23 is turned on. At time t8, switching element Q12 of the first leg 11 of the first full-bridge circuit 10 is turned off, and switching element Q11 is turned on.

[0044] The following describes the switching control of the switching elements Q11 to Q14 of the first full-bridge circuit 10, with reference to FIGS. 4 to 9. The second full-bridge circuit 20 is switched so that the voltage V2 has the waveform shown in FIGS. 2 and 3, and the description thereof can be similar to that of the first full-bridge circuit 10. Therefore, for ease of explanation, FIGS. 4 to 9 only show the current path on the first full-bridge circuit 10 side. Note that in each figure, each switching element is represented by a simplified circuit symbol.

[0045] (t1~t4) During the period from t1 to t4, the switching elements Q11 and Q14 are on, and the switching elements Q12 and Q13 are off.

[0046] In this case, current flows from DC power supply E1 through switching element Q11, inductor L, second full-bridge circuit 20, switching element Q14, and DC power supply E1 in this order, as shown in Fig. 4. Voltage V1 during this period is Hi.

[0047] At timing t4, after the switching element Q11 is turned off, there is a dead time, and then the switching element Q12 is turned on. During this dead time, both the switching elements Q11 and Q12 are off. At this time, due to the nature of the inductor L, an inductor current I Lcontinues to flow, so as shown in Figure 5, current flows from each of capacitors C11 and C12 to inductor L. In other words, capacitor C11 is charged and capacitor C12 is discharged. When capacitor C12 is discharged, the drain-source voltage of switching element Q12 is zero. At this time, if switching element Q12 is turned on, ZVS is achieved.

[0048] (t4~t5) During the period from t4 to t5, switching elements Q12 and Q14 are on, and switching elements Q11 and Q13 are off. In this case, as shown in Figure 6, current flows from switching elements Q14 and Q12 to the path of inductor L. Voltage V1 at this time is zero.

[0049] At timing t5, after switching element Q14 is turned off, there is a dead time, and then switching element Q13 is turned on. During this dead time, as explained in Figure 5, capacitor C14 charges and capacitor C13 discharges. With capacitor C13 discharged, the drain-source voltage of switching element Q13 is zero. If switching element Q13 is turned on at this time, ZVS will occur.

[0050] (t5~t8) During the period from t5 to t8, switching elements Q12 and Q13 are on, and switching elements Q11 and Q14 are off. Immediately after switching element Q13 is turned on at timing t5, as shown in FIG. 7, current flows through the path of DC power supply E1, switching element Q12, inductor L, second full-bridge circuit 20, switching element Q13, and DC power supply E1. This current flows back to DC power supply E1. After that, when the current flowing through inductor L becomes 0 A, current begins to flow through the path of DC power supply E1, switching element Q13, second full-bridge circuit 20, inductor L, switching element Q12, and DC power supply E1, as shown in FIG. 8. During this period, voltage V1 has the opposite polarity to that during the period from t1 to t4.

[0051] At timing t8, after switching element Q12 is turned off, there is a dead time, and then switching element Q11 is turned on. Then, as explained in FIG. 5, capacitor C12 charges and capacitor C11 discharges. As capacitor C11 is discharged, the drain-source voltage of switching element Q11 becomes zero. At this time, turning on switching element Q11 results in ZVS.

[0052] (t8~t1) During the period from t8 to t1, switching elements Q11 and Q13 are on, and switching elements Q12 and Q14 are off. In this case, current flows through the path of inductor L, switching element Q11, and switching element Q13, as shown in Figure 9. Voltage V1 at this time is zero.

[0053] At timing t1, after switching element Q13 is turned off, a dead time is provided and then switching element Q14 is turned on. Then, as explained in FIG. 5, capacitor C13 charges and capacitor C14 discharges. With capacitor C14 discharged, the drain-source voltage of switching element Q14 is zero. At this time, turning on switching element Q14 results in ZVS. Then, a transition to the state shown in FIG. 4 occurs.

[0054] By controlling the switching as described above, the voltage V1 transitions as shown in the waveforms in Figures 2 and 3. Furthermore, by controlling the control circuit 30 controlling the switching of the second full-bridge circuit 20, the voltage V2 transitions as shown in the waveforms in Figures 2 and 3. As described above, the first full-bridge circuit 10 and the second full-bridge circuit 20 are controlled to switch with a phase difference δ, so the phase difference between the rising edge of the voltage V1 and the rising edge of the voltage V2 is δ.

[0055] <3. Conventional soft switching operation> Below, we will explain the inductor current settings that were performed to achieve conventional soft switching operation for three control modes: output angle modulation mode, frequency modulation mode, and phase control mode, as specific control mode examples.

[0056] <3-1. Output angle modulation mode> First, the output angle modulation mode will be described. Here, the polarity reversal period during which the voltage V1 and the voltage V2 have opposite polarities to each other is defined as τ c The voltage output period of the first full-bridge circuit 10 is represented by τ1. The voltage output period of the second full-bridge circuit 20 is represented by τ2. c (See Figure 2 for both) are times expressed in degrees (radians). In this example, τ1 = τ2, and τ1 = τ2 = τ.

[0057] When the DC-DC converter 1 is outputting low power, the control circuit 30 controls the output of the DC-DC converter 1 in an output angle modulation mode. In the output angle modulation mode, the control circuit 30 controls the switching frequency f and the polarity reversal period τ c is fixed, and τ1 and τ2 are changed so that the output power from the DC-DC converter 1 becomes the target value.

[0058] τ1 is changed by controlling the phase of each switching element of the first full-bridge circuit 10. Also, τ2 is changed by controlling the phase of each switching element of the second full-bridge circuit 20.

[0059] A fixed value of τ c is set so that each switching element can be ZVS. c must satisfy the condition of the following equation (5).

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[0060] Also, I ref is the inductor current I L is the threshold current value. As mentioned above, for example, if the drain-source voltage of switching element Q12 is zero after capacitor C11 charges and capacitor C12 discharges during the dead time at timing t4 (Figure 5), then switching element Q12 will turn on in ZVS mode. In other words, as long as the energy of inductor L is at least equal to or greater than the energy stored in capacitors C11 and C12, switching element Q12 can be turned on in ZVS mode. For this to occur, the following equation (6) must be true:

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[0061] In equation (6), I L is the inductor current flowing through the inductor L. C is the capacitance of each of the capacitors C11 to C14. Then, equation (6) is transformed into the following equation (7). Note that α in equation (7) is a correction coefficient, and an appropriate value is set as necessary. Here, α=1.

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[0062] Inductor current I L is equal to or greater than α·Vx·√(2C / L) in equation (7), ZVS of the switching element Q12 is possible. ref can be expressed as α·Vx√(2C / L). That is, the threshold current I refis set to be equal to or greater than the energy stored in the two capacitors C11 and C12 of the leg in which the switching element Q12 that performs switching is located. At each timing when the switching element is turned on, |I L |≧|I ref If the condition | is satisfied, ZVS of each switching element is possible. Also, as shown in equation (7), the threshold current I ref varies as the input voltage Vx of the first full-bridge circuit 10 varies.

[0063] Next, when the output power of the DC-DC converter 1 is represented by P and τ1=τ2=τ, the power P can be expressed by the following equation (8).

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[0064] In equation (8), Vx and Vy are known. c is expressed by the above equation (5). Furthermore, power P is the target value to be output from the DC-DC converter 1, and is known. Therefore, when the target value of the power to be output from the DC-DC converter 1 is given, τ (=τ1 = τ2) can be calculated from the inverse function of equation (8).

[0065] The control circuit 30 controls the switching of the first full-bridge circuit 10 and the second full-bridge circuit 20 so that τ1 and τ2 become the τ obtained from equation (8). As a result, the DC-DC converter 1 outputs the target power P.

[0066] As described above, in the output angle modulation mode, the switching frequency f is constant, so the increase in switching loss due to an increase in the switching frequency can be suppressed. Furthermore, since the switching frequency does not increase, heat generation in the elements, especially inductor L, can be reduced.

[0067] In addition, the inductor L has a threshold current I ref Inductor current I LBy passing this current, ZVS of each switching element of the first full-bridge circuit 10 and the second full-bridge circuit 20 can be realized.

[0068] <3-2. Frequency modulation mode> Next, the frequency modulation mode will be described.

[0069] The above equation (8) is in the form of a quadratic function with respect to τ. Therefore, τ has two solutions for power P. Therefore, a single τ is specified using a predetermined algorithm. For example, the solution may be found near the peak of the quadratic function. In this case, the frequency can be suppressed, and heat generation can be reduced. Alternatively, the solution may be found at a position away from the peak of the quadratic function. In particular, the following equation (9) describes a suitable calculation formula for τ that can be applied to the above algorithm.

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[0070] In the frequency modulation mode, the output power of the DC-DC converter 1 is represented by P, τ1 and τ2 are equal and represented by τ (=τ1=τ2), and τ c Using tc, which is expressed in terms of time, the power P can be expressed by the following equation (10).

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[0071] In equation (10), Vx and Vy are known, and τ c is expressed by the above equation (3), and τ fix is τ expressed by equation (9). Furthermore, power P is the target value to be output from the DC-DC converter 1 and is known. Therefore, ω can be calculated using the inverse function of equation (10). Then, the switching frequency f can be calculated from ω.

[0072] The control circuit 30 controls the switching of each switching element of the first full-bridge circuit 10 and the second full-bridge circuit 20 at a switching frequency f obtained from equation (10), thereby causing the DC-DC converter 1 to output a target power P.

[0073] In frequency modulation mode, decreasing the switching frequency f increases the output power. In other words, when trying to increase the output power in frequency modulation mode, the switching frequency f does not increase. This prevents the increase in switching loss that would otherwise occur with an increase in switching frequency. Furthermore, because the switching frequency does not increase, heat generation in the elements, especially inductor L, can be reduced.

[0074] Also, as in the output angle modulation mode, a threshold current I ref Inductor current I L By passing this current, ZVS of each switching element of the first full-bridge circuit 10 and the second full-bridge circuit 20 can be realized.

[0075] As described above, in frequency modulation mode, it is possible to suppress the increase in switching loss caused by an increase in the switching frequency. Furthermore, since the switching frequency does not increase, it is possible to reduce heat generation in elements, especially inductor L. In addition, it is possible to achieve ZVS for each switching element, which allows for highly efficient power conversion. This control does not require complex control, so ZVS operation can be performed with simple control, reducing switching loss.

[0076] <3-3. Phase control mode> Next, the phase control mode will be described.

[0077] In phase control mode, the phase of the voltage on the first winding n1 side and the voltage on the second winding n2 side is changed while the voltage output period τ and switching frequency f of the full bridge circuits 10 and 20 are kept constant. In other words, the phase difference δ between V1 and V2 is changed. The phase difference δ can be changed by changing the phase difference between each switching element of the first full bridge circuit 10 and each switching element of the second full bridge circuit 20.

[0078] In the phase control mode, the output power P is expressed by the following equation (11): n in equation (11) is the turns ratio between the first winding n1 and the second winding n2.

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[0079] As can be seen from equation (11), the output power P can be controlled by changing the phase difference δ between the first full-bridge circuit 10 and the second full-bridge circuit 20.

[0080] If phase control mode is implemented in the light load region where output power is small, a high switching frequency is required, which is not suitable. In the heavy load region where output power is large, if output angle modulation mode or frequency modulation mode is implemented, problems such as a low frequency and an increase in reactive current occur, but such a deterioration in efficiency does not occur in phase control mode.

[0081] <3-4. Selecting the control mode according to the output power of the DC-DC converter> The control circuit 30 selects which of the above control modes to execute when controlling the output power of the DC-DC converter 1. By switching between the above control modes according to the output power (power command value), switching loss and heat generation by the inductor L can be efficiently reduced.

[0082] FIG. 10 is a diagram showing the change in voltage output period τ (τ1=τ2=τ) and switching frequency f with respect to output power P when switching between the output angle modulation mode and the frequency modulation mode according to the output power P. In FIG. 10, the voltage output period τ is indicated by a solid line, and the switching frequency f is indicated by a dotted line. In the example of FIG. 10, the control circuit 30 controls the output power to be equal to or higher than the threshold power P T If the output power P is less than the threshold power P, the output angle modulation mode is executed. T If so, execute frequency modulation mode.

[0083] As described above, in the output angle modulation mode, the switching frequency f is constant, and as τ increases, the output power P increases, as shown in Figure 10. On the other hand, in the frequency modulation mode, the voltage output period τ is constant, and as the switching frequency f decreases, the output power P increases.

[0084] For this reason, in normal operation, the control circuit 30 switches the control mode between three load regions: a light load region, a medium load region, and a heavy load region, depending on the output power P. Specifically, the control circuit 30 calculates the output power P to be output based on the input target power value. Then, the control circuit 30 selects the control mode depending on which output power range of the light load region, medium load region, or heavy load region the output power P belongs to.

[0085] In the light load region, the control circuit 30 executes the output angle modulation mode by setting the switching frequency f not to increase, thereby suppressing an increase in switching loss. In the medium load region, the control circuit 30 executes the frequency modulation mode, which can reduce the switching frequency f as the target power increases. In the heavy load region, the control circuit 30 executes the phase difference control mode, which changes the phase difference δ between V1 and V2 while keeping the voltage output period τ and switching frequency f constant.

[0086] In this way, the control circuit 30 can perform appropriate control that suppresses switching loss and heat generation in the inductor L by switching the control mode according to the target power.

[0087] In normal operation, the control circuit 30 may switch the control mode between two regions, a light load region and a heavy load region, depending on the value of the output power P. In this case, for example, the control circuit 30 executes the output angle modulation mode in the light load region and the frequency modulation mode in the heavy load region. Alternatively, the control circuit 30 executes the output angle modulation mode in the light load region and the phase difference control mode in the heavy load region.

[0088] 4. First Embodiment As described above, in the conventional soft switching operation, the threshold current I ref Inductor current I L By supplying the current, ZVS of each switching element of the first full-bridge circuit 10 and the second full-bridge circuit 20 is realized.

[0089] This method ensures ZVS, but the inductor current I L The effective value of increases, and copper loss in the inductor L and transformer T and conduction loss in the switching elements Q11 to Q14 and Q21 to Q24 increase. Furthermore, when the switching elements Q11 to Q14 and Q21 to Q24 are turned off, there is a concern that loss due to high dv / dt will increase. For this reason, the inductor current I L It is desirable to reduce the effective value of

[0090] As shown in Figures 2 and 3, the inductor current I LThe polarity inversion period includes a zero-crossing point where the polarity of the signal is inverted. Here, the switching timings immediately before the zero-crossing point, ie, time t1 and time t5, are referred to as first switching timings. The switching timings immediately after the zero-crossing point, ie, time t2 and time t6, are referred to as second switching timings.

[0091] In the following, a switching element that is turned off at a certain switching timing will be referred to as switching element Qoff, and a switching element that is turned on will be referred to as switching element Qon. For example, at timing t1, switching element Q13 will be switching element Qoff, and switching element Q14 will be switching element Qon. At timing t2, switching element Q22 will be switching element Qoff, and switching element Q21 will be switching element Qon.

[0092] In the above description of conventional soft switching operation, the input voltage Vx and the output voltage Vy are the same, so in equation (8), the condition τ = τ1 = τ2 is used. In the example of FIG. 11 and the first and second embodiments described below, the input voltage Vx and the output voltage Vy are different. Therefore, τ1 and τ2 are different. In this case, τ1 and τ2 for outputting the target power P can be calculated using the following equations (12) to (16), etc.

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[0093] In the above equations (13) to (16), Ia is the inductor current I at the first switching timing L is the absolute value of I b is the inductor current I at the second switching timing L In equation (13), I c =I a =I b By doing so, an operation equivalent to the soft switching operation of the example of FIG. 11 can be obtained.

[0094] FIG. 11 shows the inductor current I at the first switching timing and the second switching timing when the input voltage Vx and the output voltage Vy are different. L The absolute value of the same value I c 11 shows an example of voltage values ​​during dead time of capacitors Coff and Con connected in parallel to two switching elements Qoff and Qon of the leg that performs switching, assuming that: The upper part of Fig. 11 shows the voltage values ​​of capacitors Coff and Con at the first switching timing, and the lower part of Fig. 11 shows the voltage values ​​of capacitors Coff and Con at the second switching timing.

[0095] 11, the input voltage Vx is greater than the output voltage Vy. That is, the voltage applied to the first full-bridge circuit 10 is greater than the voltage applied to the second full-bridge circuit 20. When the voltages applied to the two full-bridge circuits are different, the voltage values ​​charged and discharged by each capacitor are also different.

[0096] At times t1 and t5, which are the first switching timings, both capacitors Coff and Con are capacitors of the first full-bridge circuit 10. Therefore, as shown in the upper part of Fig. 11, at the start of the dead time, the voltage value of capacitor Coff is 0 and the voltage value of capacitor Con is Vx. Then, during the dead time, capacitor Coff is charged to the voltage value Vx, and capacitor Con is discharged to the voltage value 0.

[0097] At the second switching timings of time t2 and time t6, both capacitors Coff and Con are capacitors of the second full-bridge circuit 20. Therefore, as shown in the lower part of Fig. 11, at the start of the dead time, the voltage value of capacitor Coff is 0 and the voltage value of capacitor Con is Vy. Then, during the dead time, capacitor Coff is charged to the voltage value Vy, and capacitor Con is discharged to the voltage value 0.

[0098] When the first switching timing is time t1, the switching elements Qoff and Qon are respectively switching elements Q13 and Q14, and when the first switching timing is time t5, the switching elements Qoff and Qon are respectively switching elements Q14 and Q13. When the second switching timing is time t2, the switching elements Qoff and Qon are respectively switching elements Q22 and Q21, and when the second switching timing is time t6, the switching elements Qoff and Qon are respectively switching elements Q21 and Q22.

[0099] In the conventional soft switching operation, as shown in Figs. 2 and 3, the inductor current I L The absolute values ​​of I ref Above a predetermined value I c Therefore, the charging rate of the capacitor Coff and the discharging rate of the capacitor Con are approximately the same at the first switching timing and the second switching timing.

[0100] 11, when Vx>Vy, the charging and discharging of the capacitors Coff and Con at the second switching timing is completed earlier than the charging and discharging of the capacitors Coff and Con at the first switching timing. In this case, if the same dead time is set at the first switching timing and the second switching timing, there is a problem that an unnecessary conduction period occurs in the diodes connected in parallel to the switching elements Qoff and Qon between the completion of charging and discharging at the second switching timing and the end of the dead time.

[0101] FIG. 12 is a diagram showing an example of inductor current in the soft switching operation of the example of FIG. 11 and this embodiment. The upper part of FIG. 12 shows the inductor current in the soft switching operation of the example of FIG. 11. The middle part of FIG. 12 shows the inductor current in the soft switching operation of this embodiment. The lower part of FIG. 12 is a diagram comparing the inductor current in the soft switching operation of this embodiment and the example of FIG. 11. In the lower part of FIG. 12, the inductor current in the soft switching operation of this embodiment is shown by a solid line, and the inductor current in the conventional soft switching operation is shown by a dashed line. Note that in the lower part of FIG. 12, the predetermined value I c and the predetermined value I a This represents the case where and are the same.

[0102] As shown in FIG. 12, in the soft switching operation of the example of FIG. 11, the inductor current I L The absolute value of I ref Above a predetermined value I c is.

[0103] In contrast, in the soft switching operation of the first embodiment, the inductor current I L1 The absolute value of is a predetermined value I that satisfies equation (1). bHere, C1 is the capacitance of two capacitors Coff and Con included in two switching elements that are switched on and off at the first switching timing.

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[0104] As a result, the inductor current I L1 The absolute value of the value of is set so that the energy stored in the equivalent inductor L is equal to or greater than the energy stored in the two capacitors Coff and Con included in the two switching elements that switch on and off at the first switching timing. As a result, at the first switching timing, the turning on of the switching element Qon is ZVS.

[0105] In addition, in the soft switching operation of the first embodiment, the inductor current I L2 The absolute value of is a predetermined value I that satisfies equation (3). c Here, C2 is the capacitance of two capacitors Coff and Con included in two switching elements that are switched on and off at the second switching timing.

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[0106] As a result, the absolute value of the inductor current at the second switching timing I L2 is set so that the energy stored in the equivalent inductor L is equal to or greater than the energy stored in the two capacitors Coff and Con included in the two switching elements that switch on and off at the second switching timing. As a result, at the second switching timing, the turning on of the switching element Qon is ZVS.

[0107] In the first embodiment, |I a |>|I bThat is, in this embodiment, the inductor current I L2 The absolute value of the value of I b is the inductor current I at the first switching timing L1 The absolute value of the value of I a Therefore, the inductor current I L2 The value of does not need to be set to an excessively large value that is matched to the full bridge circuit side (in this case, the first full bridge circuit 10 side on the primary side) to which a larger applied voltage is applied.

[0108] For this reason, I c =I a In this case, as shown in the lower part of FIG. 12, the inductor current I L is the inductor current value I L In other words, the inductor current I L Therefore, the power loss can be reduced.

[0109] 13 is a diagram showing an example of voltage values ​​during dead time of capacitors Coff and Con connected in parallel to two switching elements Qoff and Qon of the leg that performs switching at the first switching timing and the second switching timing of the soft switching operation of this embodiment. The upper part of Fig. 13 shows the voltage values ​​of capacitors Coff and Con at the first switching timing, and the lower part of Fig. 13 shows the voltage values ​​of capacitors Coff and Con at the second switching timing.

[0110] In the soft switching operation of this embodiment, the inductor current I L2 The absolute value of the value of I b is the inductor current I at the first switching timing L1 The absolute value of the value of I a11. Therefore, the charge / discharge rate at the second switching timing is slower than the charge / discharge rate at the first switching timing. As a result, the time required for charge / discharge at the second switching timing is longer than in the conventional case, compared to FIG. 11. As a result, even if the dead time at the first switching timing and the dead time at the second switching timing are set to the same period, the unnecessary conduction period of the diodes connected in parallel to the switching elements Qoff and Qon can be shortened.

[0111] In this way, in the first embodiment, the effective value of the inductor current can be suppressed as shown in Fig. 12. Furthermore, in the first embodiment, the occurrence of unnecessary conduction periods in the diode connected in parallel to the switching element can be suppressed as shown in Fig. 13. As a result, the occurrence of power loss in the diode can be suppressed.

[0112] 5. Second Embodiment Fig. 14 is a diagram showing an example of voltage values ​​during dead time of capacitors Coff and Con connected in parallel to two switching elements Qoff and Qon of a leg that performs switching at first switching timings and second switching timings of soft switching operation of the second embodiment. Fig. 15 is a diagram showing another example of voltage values ​​during dead time of capacitors Coff and Con connected in parallel to two switching elements Qoff and Qon of a leg that performs switching at first switching timings and second switching timings of soft switching operation of the second embodiment. The upper parts of Fig. 14 and Fig. 15 show voltage values ​​of capacitors Coff and Con at the first switching timing, and the lower parts of Fig. 14 and Fig. 15 show voltage values ​​of capacitors Coff and Con at the second switching timing.

[0113] In the second embodiment, similar to the first embodiment, the values ​​of the inductor current at the first switching timing and the second switching timing are set based on the voltages applied to each full-bridge circuit, and in addition, the dead time at the first switching timing and the dead time at the second switching timing are different.

[0114] In this embodiment, the following equations (2) and (4) different from those in the first embodiment are used to calculate the inductor current I at the first switching timing (time t1 and time t5). L1 and the inductor current I at the second switching timing (time t2 and time t6) L2 Calculate the absolute value of

[0115] That is, in the soft switching operation of the second embodiment, the inductor current I L1 The absolute value of is a predetermined value that satisfies the formula (2). In addition, in the soft switching operation of the second embodiment, the inductor current I L2 The absolute value of is a predetermined value that satisfies the formula (4).

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[0116] The above equations (2) and (4) are more accurate than the equations (1) and (3) used in the first embodiment, taking into account both the primary side input voltage Vx and the secondary side output voltage Vy.

[0117] 11 and 13, the length of the dead time is set to match the charge / discharge time of the capacitors Coff and Con at the first switching timing, and as a result, while the charge / discharge of the capacitors Coff and Con at the second switching timing is completed within the dead time period, unnecessary conduction time of the diode occurs. Therefore, in this embodiment, the length of the dead time at the first switching timing and the length of the dead time at the second switching timing are set separately.

[0118] In the example of FIG. 14, the dead time at the second switching timing is shorter than the dead time at the first switching timing. As a result, the conduction time of the diodes that remained shortened in the example of FIG. 13 of the first embodiment can be eliminated as shown in FIG. 14.

[0119] Also, the capacitance C1 of the capacitors Coff, Con at the second switching timing may be larger than the capacitance C2 of the capacitors Coff, Con at the first switching timing, and C1Vx < C2Vy. In such a case, as shown in FIG. 15, when the inductor current I L is set based on the applied voltage Vx to the first full-bridge circuit 10 and the applied voltage Vy to the second full-bridge circuit 20 respectively, the charge and discharge time of the capacitors Coff, Con at the second switching timing may be longer than the charge and discharge time of the capacitors Coff, Con at the first switching timing.

[0120] In the example of FIG. 15, the dead time at the second switching timing is longer than the dead time at the first switching timing. As a result, the conduction time of the diodes can be eliminated at both the first switching timing and the second switching timing. Thus, in the second embodiment, the generation of a wasteful conduction period in the diodes connected in parallel with the switching elements can be further suppressed. As a result, while suppressing the effective value of the inductor current, the generation of power loss in the diodes can be further suppressed.

[0121] <6. Modification Example> As described above, one embodiment of the present invention has been described, but the present invention is not limited to the above-described embodiment.

[0122] In the above embodiment, the input / output terminals IO11 and IO12 are described as the input side, and the input / output terminals IO21 and IO22 are described as the output side. However, the DC-DC converter 1 is capable of bidirectional power transmission. Therefore, it is possible to configure the input / output terminals IO11 and IO12 as the output side, and the input / output terminals IO21 and IO22 as the input side. In that case, the first full-bridge circuit 10 becomes a secondary-side full-bridge circuit, and the second full-bridge circuit 20 becomes a primary-side full-bridge circuit. In this case, the same explanation as in the above embodiment can be applied, and therefore the explanation will be omitted. Note that the DC-DC converter 1 does not have to be bidirectional.

[0123] In the above embodiment, the polarity reversal period τ c In the above embodiment, the value of is set to a fixed value, but it may be a variable value. In the above embodiment, as long as the value is set to be equal to or greater than the fixed value, the ZVS operation can be realized.

[0124] The elements appearing in the above-described embodiments or modifications may be combined as appropriate to the extent that no contradiction occurs. [Explanation of symbols]

[0125] 1 DC-DC converter 10 First full-bridge circuit 11 First Leg 12 Second Leg 20 Second full-bridge circuit 21 Third Leg 22 Fourth Leg 30 Control circuit C11, C12, C13, C14 capacitors C21, C22, C23, C24 capacitors Coff,Con capacitor I L Inductor Current L equivalent inductor L1 inductor Q11, Q12, Q13, Q14 switching elements Q21, Q22, Q23, Q24 switching elements Qoff, Qon: switching elements T transformer Vx Applied voltage to the first full-bridge circuit Vy Applied voltage to the second full-bridge circuit n1 First winding n2 Second winding t1, t2, t3, t4, t5, t6, t7, t8 Switching timing τc Polarity reversal period

Claims

1. a primary-side full-bridge circuit having two legs each including two switching elements; a secondary-side full-bridge circuit having two legs each including two switching elements; a transformer having a primary winding connected to the primary full-bridge circuit and a secondary winding connected to the secondary full-bridge circuit and magnetically coupled to the primary winding; an inductance component connected in series to the primary winding or the secondary winding; a control circuit that performs soft switching control of the switching elements of the primary side full bridge circuit and the secondary side full bridge circuit; Equipped with the switching elements of the primary-side full-bridge circuit and the secondary-side full-bridge circuit each include a capacitor that is a parasitic capacitance or an external capacitor connected in parallel; The control circuit providing a dead time during which both of the two switching elements of each of the legs are turned off at a switching timing for switching on and off the two switching elements of each of the legs; switching on and off the switching elements of the legs of the primary-side full bridge circuit at a first switching timing which is the switching timing immediately before a zero-crossing point at which the polarity of an inductor current flowing through the transformer and the equivalent inductor of the inductance component is reversed; at a second switching timing which is the switching timing immediately after the zero crossing point, switching on and off the switching elements of the legs of the secondary-side full bridge circuit; an absolute value of the inductor current at the first switching timing is set based on at least a voltage applied to the primary-side full-bridge circuit; The DC-DC converter, wherein the absolute value of the inductor current at the second switching timing is set based on at least a voltage applied to a full bridge circuit on the secondary side.

2. 2. The DC-DC converter according to claim 1, a DC-DC converter in which the absolute value of the inductor current at the first switching timing is set so that the energy stored in the equivalent inductor is equal to or greater than the energy stored in the two capacitors included in the two switching elements that switch on and off at the first switching timing.

3. 3. The DC-DC converter according to claim 2, The value of the inductor current at the first switching timing is I Ｌ１ , the input voltage of the primary side full bridge circuit is Vx, the capacitances of the two capacitors included in the two switching elements that switch on and off at the first switching timing are respectively C １ , where the inductance of the equivalent inductor is L and the correction coefficient is α, [Equation 1] A DC-DC converter that satisfies the above requirements.

4. 3. The DC-DC converter according to claim 2, The value of the inductor current at the first switching timing is I Ｌ１ , the input voltage of the primary side full bridge circuit is Vx, the input voltage of the secondary side full bridge circuit is Vy, the capacitances of the two capacitors included in the two switching elements that switch on and off at the first switching timing are respectively C １ , where the inductance of the equivalent inductor is L and the correction coefficient is α, [Equation 2] A DC-DC converter that satisfies the above requirements.

5. 5. The DC-DC converter according to claim 1, a DC-DC converter in which the absolute value of the inductor current at the second switching timing is set so that the energy stored in the equivalent inductor is equal to or greater than the energy stored in the two capacitors included in the two switching elements that switch on and off at the second switching timing.

6. 6. The DC-DC converter according to claim 5, The value of the inductor current at the second switching timing is I Ｌ２ , the input voltage of the secondary side full bridge circuit is Vy, the capacitances of the two capacitors included in the two switching elements that switch on and off at the second switching timing are respectively C ２ , where the inductance of the equivalent inductor is L and the correction coefficient is α, [Equation 3] A DC-DC converter that satisfies the above requirements.

7. 6. The DC-DC converter according to claim 5, The value of the inductor current at the second switching timing is I Ｌ２ , the input voltage of the primary side full bridge circuit is Vx, the input voltage of the secondary side full bridge circuit is Vy, and the capacitances of the two capacitors included in the two switching elements that switch on and off at the second switching timing are respectively C ２ , where the inductance of the equivalent inductor is L and the correction coefficient is α, [Equation 4] A DC-DC converter that satisfies the above requirements.

8. 5. The DC-DC converter according to claim 1, The DC-DC converter, wherein the dead time at the first switching timing is different from the dead time at the second switching timing.

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