Method for manufacturing semiconductor device and semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device and the semiconductor device that suppress the lifting of an insulating layer while minimizing the reduction in material selection flexibility.SOLUTION: A semiconductor device 10 has a semiconductor substrate 14, a passivation film 13 formed on the semiconductor substrate 14, an insulating layer 16 composed of insulating material formed on the passivation film 13, rewiring 20 formed on the insulating layer 16, and an anti-lifting pattern 30 formed from the same material as the rewiring 20 on the insulating layer 16, filled into an opening penetrating the insulating layer 16, and covering at least a portion of the end face of the insulating layer 16.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a WL-CSP (Wafer Level Chip Scale Package) semiconductor device and a manufacturing method thereof. The semiconductor device is subjected to a packaging process in the wafer state, and individual chip-sized packages are cut out by dicing.

[0003] Generally, in WL-CSP semiconductor devices, a passivation film (surface protection film) is formed on the surface of a semiconductor substrate, and an insulating layer is laminated on top of that. However, if there is a problem with the adhesion between the passivation film and the insulating layer, there is a concern that the insulating layer will peel off from the passivation film. For this reason, Patent Document 1 attempts to cover the chip edge with a package resin layer. Furthermore, Patent Document 2 attempts to improve adhesion by selecting materials for the passivation film and the insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-42807 A [Patent Document 2] JP 2007-42807 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, simply covering the chip edge with a resin layer may not be sufficient to prevent peeling or lifting. Also, improving adhesion through material selection reduces the freedom of material selection.

[0006] An object of the present disclosure is to provide a semiconductor device manufacturing method that suppresses floating of an insulating layer and suppresses a decrease in the degree of freedom in material selection, and a semiconductor device. [Means for solving the problem]

[0007] The semiconductor device according to the present disclosure includes a semiconductor substrate, a passivation film formed on the semiconductor substrate, an insulating layer made of an insulating material formed on the passivation film, rewiring formed on the insulating layer, and a floating prevention pattern formed on the insulating layer from the same material as the rewiring, filling an opening penetrating the insulating layer, and covering at least a portion of an end face of the insulating layer.

[0008] In the semiconductor device according to the present disclosure, a floating prevention pattern is formed on the insulating layer using the same material as the rewiring. The floating prevention pattern fills the opening penetrating the insulating layer and covers at least a portion of the end surface of the insulating layer. Therefore, the floating prevention pattern sandwiches and presses the insulating layer, preventing it from floating from the passivation film.

[0009] The method for manufacturing a semiconductor device according to the present disclosure includes an insulating layer laminating step of laminating an insulating layer made of an insulating material on a semiconductor substrate on which a passivation film has been formed, and a rewiring forming step of arranging a rewiring resist to form rewiring on the insulating layer, and arranging a lift-prevention pattern resist to form a lift-prevention pattern made of the same material as the rewiring, which is filled in an opening penetrating the insulating layer and covers at least a portion of an end face of the insulating layer.

[0010] In the method for manufacturing a semiconductor device according to the present disclosure, a rewiring resist is applied to form rewiring on an insulating layer, and a lift-prevention pattern resist is applied to form a lift-prevention pattern on the insulating layer using the same material as the rewiring. The lift-prevention pattern fills an opening penetrating the insulating layer and covers at least a portion of an end face of the insulating layer. Therefore, the lift-prevention pattern sandwiches and presses the insulating layer, preventing it from lifting from the passivation film. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a part of a semiconductor substrate before an insulating layer forming step in a manufacturing method of a semiconductor device according to an embodiment of the present invention. [Figure 2] 10 is a cross-sectional view showing a part of a semiconductor substrate in an insulating layer forming step. [Figure 3] FIG. 10 is a cross-sectional view showing a part of a semiconductor substrate in a rewiring formation step (resist formation). [Figure 4] FIG. 10 is a cross-sectional view showing a part of a semiconductor substrate in a rewiring formation step (with resist). [Figure 5] FIG. 10 is a cross-sectional view showing a part of a semiconductor substrate in a rewiring formation step (after removing the resist). [Figure 6] FIG. 10 is a cross-sectional view showing a part of a semiconductor substrate after a post is formed. [Figure 7] FIG. 2 is a cross-sectional view showing a part of the semiconductor substrate after forming a sealing resin layer and solder terminals. [Figure 8] FIG. 1 is a top view showing a part of a semiconductor device according to an embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a modified example of the present embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to another modified example of the present embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to another modified example of the present embodiment. [Figure 12] FIG. 10 is a top view showing a part of a semiconductor device according to another modified example of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, a semiconductor device according to the present disclosure will be described by way of example in which it is applied to a WL-CSP (Wafer Level Chip Scale Package). The drawings merely show the shape, size, and layout of each component part in a schematic manner sufficient to enable understanding of the present disclosure, and are not intended to limit the present disclosure in any way. While the following description may use specific materials, conditions, numerical conditions, etc., these are merely preferred examples and are not intended to limit the present disclosure in any way.

[0013] As shown in Figure 7, the semiconductor device 10 of this embodiment has a semiconductor substrate 14, a pad electrode 12, a passivation film 13, an insulating layer 16, rewiring 20, a lift prevention pattern 30, a sealing resin layer 22, a post 24, and a solder terminal 26.

[0014] The semiconductor substrate 14 is, for example, a substrate containing silicon, and has a pad electrode 12 formed on its surface. The passivation film 13 is, for example, a substrate containing silicon oxide or silicon nitride, and is laminated on the semiconductor substrate 14.

[0015] The insulating layer 16 includes, for example, polyimide, and is laminated on the passivation film 13. On the semiconductor substrate 14, the outer peripheral edge 16A of the insulating layer 16 is disposed outside the outer peripheral edge 13A of the passivation film 13, and the outer peripheral edge 13A of the passivation film 13 is covered with the insulating layer 16.

[0016] The rewiring 20 contains, for example, copper and is formed on the insulating layer 16. Openings 17 and 18 are formed in the passivation film 13 and the insulating layer 16 in portions corresponding to the pad electrode 12. The rewiring 20 is connected to the pad electrode 12 via the openings 17 and 18.

[0017] 8, a floating prevention pattern 30 is formed at the corner of the semiconductor substrate 14. The floating prevention pattern 30 is formed in the same layer and made of the same material as the rewiring 20. The floating prevention pattern 30 is not connected to the rewiring 20, and is connected to the pad electrode 12B via the openings 17 and 18. Note that the pad electrode 12B does not need to be connected to the internal circuit.

[0018] An outer peripheral edge 30A of the lift prevention pattern 30 on the semiconductor substrate 14 is positioned inside the outer peripheral edge 16A of the insulating layer 16, and covers a portion of the end face 16B that is inside the outer peripheral edge 16A of the insulating layer 16. The lift prevention pattern 30 is positioned outside the outer peripheral edge 13A of the passivation film 13. The portions of the lift prevention pattern 30 that are positioned within the openings 17, 18 of the lift prevention pattern 30 are referred to as inner leg portions 32, the portions that cover a portion of the end face 16B of the insulating layer 16 are referred to as outer leg portions 34, and the portion that covers the top surface of the insulating layer 16 is referred to as an upper portion 36.

[0019] A sealing resin layer 22 is formed on the rewiring 20 and the lift-preventing pattern 30. Posts 24, which include copper as an example, are formed on the sealing resin layer 22 in portions corresponding to the rewiring 20. Solder terminals 26 are formed in portions corresponding to the posts 24. The solder terminals 26 are connected to the rewiring 20 via the posts 24.

[0020] Each step of manufacturing the semiconductor device 10 of this embodiment will be described in detail below with reference to FIGS.

[0021] (1) Semiconductor substrate preparation process 1, a semiconductor substrate 14 is prepared on which a pad electrode 12 and a passivation film 13 are formed. An outer peripheral edge 13A of the passivation film 13 is disposed inside the outer peripheral edge of the semiconductor substrate 14, and an opening 17 is formed in the portion corresponding to the pad electrode 12.

[0022] (2) Insulation layer formation process Next, as shown in FIG. 2, an insulating layer 16 is formed on the upper surface of the semiconductor substrate 14 in an insulating layer formation step. As an example, the insulating layer 16 is formed by forming a thermosetting material on the passivation film 13 and patterning it by photolithography. At this time, the outer peripheral edge 16A of the insulating layer 16 is positioned outside the outer peripheral edge 13A of the passivation film 13 on the semiconductor substrate 14. Thereafter, a thermosetting process is performed to heat and harden the thermosetting material to form the insulating layer 16.

[0023] (5) Rewiring formation process Next, as shown in FIG. 3, a resist R is formed to form the rewiring 20 and the floating prevention pattern 30. The semiconductor substrate 14 on which the resist R has been formed is plated with a material containing copper, for example, to form the rewiring 20 and the floating prevention pattern 30, as shown in FIG. 4. The plating is performed so that the rewiring 20 is connected to the pad electrode 12 and the floating prevention pattern 30 is connected to the pad electrode 12B. The plating is also performed so that the outer leg portions 34 of the floating prevention pattern 30 cover the end surface 16B of the insulating layer 16 and the outer peripheral edge 30A of the floating prevention pattern 30 is positioned closer to the inner periphery of the semiconductor substrate 14 than the outer peripheral edge 16A of the insulating layer 16. Thereafter, as shown in FIG. 5, the used resist R is removed.

[0024] (6) Thereafter, as shown in Fig. 6, posts 24 are formed on the rewiring 20. Then, as shown in Fig. 7, the insulating layer 16, the rewiring 20, and the lift prevention pattern 30 are covered with a sealing resin layer 22, and solder terminals 26 are formed on the posts 24.

[0025] In the semiconductor device 10 of this embodiment, the outer leg portions 34 of the lift-preventing pattern 30 cover the end surface 16B of the insulating layer 16, the inner leg portions 32 are arranged in the openings 17 and 18 so as to contact the pad electrode 12B, and the upper portion 36 covers the insulating layer 16. Therefore, the lift-preventing pattern 30 sandwiches and presses the insulating layer 16, suppressing lift-up from the passivation film 13.

[0026] Furthermore, in the semiconductor device 10 of this embodiment, the outer peripheral edge 16A of the insulating layer 16 is disposed closer to the outer periphery of the semiconductor substrate 14 than the outer peripheral edge 13A of the passivation film 13, so that the interface between the passivation film 13 and the insulating layer 16 is covered by the insulating layer 16. Therefore, the floating of the insulating layer 16 from the passivation film 13 can be further suppressed.

[0027] Furthermore, in the semiconductor device 10 of this embodiment, the outer peripheral edge 30A of the lift prevention pattern 30 is located closer to the inner periphery of the semiconductor substrate 14 than the outer peripheral edge 16A of the insulating layer 16. Therefore, it is possible to prevent the lift prevention pattern 30, which is made of a metal such as copper, from coming into contact with other wiring or the like.

[0028] Furthermore, in the semiconductor device 10 of this embodiment, the outer peripheral edge 30A of the lift-preventing pattern 30 is located closer to the outer periphery of the semiconductor substrate 14 than the outer peripheral edge 13A of the passivation film 13. Therefore, the outer leg portions 34 can press the insulating layer 16 against the surface of the semiconductor substrate 14, and lift-up of the insulating layer 16 from the passivation film 13 can be further suppressed.

[0029] Furthermore, in the semiconductor device 10 of this embodiment, the lifting prevention patterns 30 are arranged at the corners of the semiconductor device 10. These corners are particularly prone to concentration of stress on the semiconductor device 10, and are also areas where lifting of the insulating layer 16 from the passivation film 13 is likely to occur. Therefore, lifting of the insulating layer 16 can be effectively suppressed at these corners.

[0030] <Variation 1> In the above embodiment, an example was described in which the outer peripheral end 16A of the insulating layer 16 is positioned closer to the outer periphery of the semiconductor substrate 14 than the outer peripheral end 13A of the passivation film 13. However, as shown in FIG. 9, the outer peripheral end 16A of the insulating layer 16 may also be positioned closer to the inner periphery of the semiconductor substrate 14 than the outer peripheral end 13A of the passivation film 13.

[0031] In this case, it is preferable that the outer peripheral edge 30A of the lift prevention pattern 30 is formed closer to the inner periphery of the semiconductor substrate 14 than the outer peripheral edge 13A of the passivation film 13.

[0032] <Variation 2> In the above embodiment, the semiconductor device 10 has been described as an example in which the outer peripheral end 30A of the anti-floating pattern 30 is positioned closer to the inner periphery of the semiconductor substrate 14 than the outer peripheral end 16A of the insulating layer 16. However, as shown in FIG. 10, the outer peripheral end 30A of the anti-floating pattern 30 may also be positioned closer to the outer periphery of the semiconductor substrate 14 than the outer peripheral end 16A of the insulating layer 16.

[0033] <Variation 3> The semiconductor device 10 of the above embodiment has the pad electrode 12B, and the inner leg portion 32 of the lift-off prevention pattern 30 is in contact with the pad electrode 12B, but the pad electrode 12B may not be formed.

[0034] In this case, as shown in FIG. 11, the passivation film 13 is disposed in the portion corresponding to the pad electrode 12B (without the opening 17 formed), and the insulating layer of the lift-off prevention pattern 30 comes into contact with the passivation film 13.

[0035] <Variation 4> In the semiconductor device 10 of the above embodiment, the lift prevention pattern 30 is disposed at the corner of the semiconductor device 10, but it may be provided not only at the corner but also at a plurality of locations near the corner as shown in FIG.

[0036] [Other embodiments] The above describes one embodiment of the present disclosure, but the present disclosure is not limited to the above, and it goes without saying that various modifications can be made to the present disclosure without departing from the spirit of the present disclosure.

[0037] For example, although the insulating layer 16 in the above embodiment contains polyimide, it may be formed of an insulating material that does not contain polyimide.

[0038] Furthermore, in the above embodiment, the rewiring 20 and the lift-preventing pattern 30 are made of copper, but they may be made of other metal materials (conductive materials) than copper.

[0039] Furthermore, the semiconductor device 10 may have a configuration other than the WL-CSP.

[0040] Further preferred aspects of the present disclosure will be described below.

[0041] (Appendix 1) a semiconductor substrate; a passivation film formed on the semiconductor substrate; an insulating layer made of an insulating material formed on the passivation film; a rewiring formed in the insulating layer; a lift-preventing pattern formed on the insulating layer using the same material as the rewiring, filling an opening penetrating the insulating layer, and covering at least a portion of an end surface of the insulating layer; having Semiconductor device.

[0042] (Appendix 2) an outer peripheral edge of the insulating layer is disposed closer to the outer periphery of the semiconductor substrate than an outer peripheral edge of the passivation film; 2. The semiconductor device according to claim 1.

[0043] (Appendix 3) an outer peripheral edge of the lift prevention pattern is disposed closer to an inner peripheral side of the semiconductor substrate than an outer peripheral edge of the insulating layer; 3. The semiconductor device according to claim 2.

[0044] (Appendix 4) an outer peripheral edge of the lift prevention pattern is disposed closer to the outer periphery of the semiconductor substrate than an outer peripheral edge of the passivation film; 4. The semiconductor device according to claim 3.

[0045] (Appendix 5) a pad electrode is formed in a portion of the passivation film corresponding to the opening; the lift-off prevention pattern is in contact with the pad electrode; The semiconductor device according to any one of Supplementary Notes 1 to 4.

[0046] (Appendix 6) the lift-preventing pattern is disposed at the outer circumferential corners of the semiconductor substrate; 6. The semiconductor device according to any one of appendices 1 to 5.

[0047] (Appendix 7) an insulating layer laminating step of laminating an insulating layer made of an insulating material on the semiconductor substrate on which the passivation film has been formed; a rewiring forming process in which a rewiring resist is disposed to form a rewiring on the insulating layer, and a lift-prevention pattern resist is disposed to form a lift-prevention pattern that is filled in an opening penetrating the insulating layer with the same material as the rewiring and covers at least a part of an end surface of the insulating layer; having A method for manufacturing a semiconductor device.

[0048] (Appendix 8) an outer peripheral edge of the insulating layer is formed closer to the outer periphery of the semiconductor substrate than the outer peripheral edge of the passivation film; 8. A method for manufacturing a semiconductor device according to claim 7.

[0049] (Appendix 9) an outer circumferential edge of the lift prevention pattern being formed closer to an inner circumferential side of the semiconductor substrate than an outer circumferential edge of the insulating layer; 9. A method for manufacturing a semiconductor device according to claim 8.

[0050] (Appendix 10) The outer peripheral edge of the lift prevention pattern is formed closer to the outer periphery of the semiconductor substrate than the outer peripheral edge of the passivation film. 10. A method for manufacturing a semiconductor device according to claim 9.

[0051] (Appendix 11) a pad electrode is formed in a portion of the passivation film corresponding to the opening; The lift-off prevention pattern is formed so as to be in contact with the pad electrode. A method for manufacturing a semiconductor device according to any one of appendices 7 to 10.

[0052] (Appendix 12) The lift-preventing pattern is formed on the outer circumferential corners of the semiconductor substrate. 12. A method for manufacturing a semiconductor device according to any one of appendices 7 to 11. [Explanation of symbols]

[0053] 10 Semiconductor device 12, 12B Pad electrode 13 Passivation film 13A Outer edge 14 Semiconductor substrate 16 Insulating layer 16A Outer edge 16B End face 17 Aperture 18 Aperture 20 Rewiring 22 Sealing resin layer 24 posts 26 Solder terminal 30 Anti-floating pattern 30A outer edge

Claims

1. a semiconductor substrate; a passivation film formed on the semiconductor substrate; an insulating layer made of an insulating material formed on the passivation film; a rewiring formed in the insulating layer; a lift-preventing pattern formed on the insulating layer using the same material as the rewiring, filling an opening penetrating the insulating layer, and covering at least a portion of an end surface of the insulating layer; having Semiconductor device.

2. an outer peripheral edge of the insulating layer is disposed closer to the outer periphery of the semiconductor substrate than an outer peripheral edge of the passivation film; The semiconductor device according to claim 1 .

3. an outer peripheral edge of the lift prevention pattern is disposed closer to an inner peripheral side of the semiconductor substrate than an outer peripheral edge of the insulating layer; The semiconductor device according to claim 2 .

4. an outer peripheral edge of the lift prevention pattern is disposed closer to the outer periphery of the semiconductor substrate than an outer peripheral edge of the passivation film; The semiconductor device according to claim 3 .

5. a pad electrode is formed in a portion of the passivation film corresponding to the opening; the lift-off prevention pattern is in contact with the pad electrode; The semiconductor device according to claim 1 .

6. the lift-preventing pattern is disposed at the outer circumferential corners of the semiconductor substrate; The semiconductor device according to any one of claims 1 to 5.

7. an insulating layer laminating step of laminating an insulating layer made of an insulating material on the semiconductor substrate on which the passivation film has been formed; a rewiring forming process in which a rewiring resist is disposed to form a rewiring on the insulating layer, and a lift-prevention pattern resist is disposed to form a lift-prevention pattern that is filled in an opening penetrating the insulating layer with the same material as the rewiring and covers at least a part of an end surface of the insulating layer; having A method for manufacturing a semiconductor device.

8. an outer peripheral edge of the insulating layer is formed closer to the outer periphery of the semiconductor substrate than the outer peripheral edge of the passivation film; The method for manufacturing a semiconductor device according to claim 7 .

9. an outer circumferential edge of the lift prevention pattern being formed closer to an inner circumferential side of the semiconductor substrate than an outer circumferential edge of the insulating layer; The method for manufacturing a semiconductor device according to claim 8 .

10. The outer peripheral edge of the lift prevention pattern is formed closer to the outer periphery of the semiconductor substrate than the outer peripheral edge of the passivation film. The method for manufacturing a semiconductor device according to claim 9 .

11. a pad electrode is formed in a portion of the passivation film corresponding to the opening; The lift-off prevention pattern is formed so as to be in contact with the pad electrode. The method for manufacturing a semiconductor device according to claim 7 .

12. The lift-preventing pattern is formed on the outer circumferential corners of the semiconductor substrate. The method for manufacturing a semiconductor device according to any one of claims 7 to 11.

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