Method and system for vertical gradient freeze 200 mm 8 inch gallium arsenide substrates

Abstract

To provide a method for forming a single crystal gallium arsenide substrate.SOLUTION: The method includes: sealing a charge comprising a polycrystalline gallium arsenide (GaAs) seed crystal, a B2O3 sealing material, and carbon in a crucible; sealing the crucible into a quartz ampoule; performing a vertical gradient freeze crystal growth process by heating the ampoule using a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal is melted; moving a pedestal relative to the crucible, the system operable to control the heating of the multi-zone heating system and the movement of the pedestal; and performing controlled cooling of the multi-zone heating system during growth from the partially melted seed to form a single crystal 200 mm (8 inch) GaAs substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Cross-reference / incorporation by reference to related applications

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 164,378, filed March 22, 2021, which is incorporated herein by reference in its entirety.

[0002]

[0002] Certain embodiments of the present disclosure relate to semiconductor substrates. More particularly, certain embodiments of the present disclosure relate to methods and systems for vertical gradient-freezing 200 mm (8 inch) gallium arsenide (GaAs) substrates. [Background technology]

[0003]

[0003] Semiconductor substrates, particularly III-V semiconductor substrates, are used in the fabrication of electronic and optoelectronic devices, such as, for example, light-emitting diodes (LEDs), lasers, heterojunction bipolar transistors (HBTs), pseudo-morphic high-electron mobility transistors (pHEMTs), etc. Defects in the substrates can reduce yield and increase costs.

[0004]

[0004] Further limitations and drawbacks of conventional and conventional approaches will become apparent to those skilled in the art by comparing such systems with the present disclosure as described below in the present application with reference to the drawings. Summary of the Invention [Means for solving the problem]

[0005]

[0005] A system and / or method for vertical gradient freezing 200 mm (8 inch) gallium arsenide (GaAs) substrates substantially as shown and / or described in connection with at least one of the figures is more fully set forth in the claims.

[0006]

[0006] Various advantages, aspects and novel features of the present disclosure, as well as details of illustrated embodiments thereof, will become more fully understood from the following description and drawings. [Brief explanation of the drawings]

[0007] [Figure 1]

[0007] FIG. 1 illustrates a vertical gradient freezing reactor according to an exemplary embodiment of the present disclosure. [Figure 2]

[0008] 1A-1C illustrate a 200 mm (8 inch) GaAs ingot and the leading and trailing edges of the ingot, according to an exemplary embodiment of the present disclosure. [Figure 3A]

[0009] FIG. 10 shows etch pit density results for 200 mm (8 inch) gallium arsenide wafers manufactured in accordance with embodiments of the present disclosure. [Figure 3B] FIG. 10 shows etch pit density results for 200 mm (8 inch) gallium arsenide wafers manufactured in accordance with embodiments of the present disclosure. [Figure 3C] FIG. 10 shows etch pit density results for 200 mm (8 inch) gallium arsenide wafers manufactured in accordance with embodiments of the present disclosure. [Figure 3D] FIG. 10 shows etch pit density results for 200 mm (8 inch) gallium arsenide wafers manufactured in accordance with embodiments of the present disclosure. [Figure 4A]

[0010] FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 4C] FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 4D]FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 4E] FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 4F] FIG. 1 shows photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5A]

[0011] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5B] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5C] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5D] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5E] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 5F] FIG. 1 illustrates the resistivity distribution of a 200 mm (8 inch) gallium arsenide substrate according to an exemplary embodiment of the present disclosure. [Figure 6]

[0012] 2 illustrates a method for producing GaAs wafers using the vertical gradient freeze furnace 100 shown in FIG. 1. [Figure 7]

[0013] FIG. 1 illustrates a device fabricated on a low etch pit density 200 mm (8 inch) gallium arsenide wafer according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008]

[0014] Particular aspects of the present disclosure can be found in methods and systems for vertical gradient-freezing 200 mm (8 inch) gallium arsenide (GaAs) substrates.

[0009]

[0015] FIG. 1 is a diagram illustrating a vertical gradient freeze reactor according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, a vertical gradient freeze (VGF) system 100 is shown comprising an ampoule 110, a heating coil 120, a crucible 130, and a pedestal 140. Growth can proceed within the ampoule 110 using a seed crystal 101 and a melt 105 in a vertical configuration, with a solid 103 emerging due to very slow cooling of the melt 105 with a boron trioxide BO layer as a sealing material on the melt 105. The crucible 130 may comprise, for example, pyrolytic boron nitride (PBN) and can contain the melt and seed material during processing.

[0010]

[0016] The VGF system 100 includes a configuration for the growth charge, heater, insulation, and pedestal 140, including direct radiation from the heating coil 120 to the cone in the crystal growth charge, i.e., above the height of the seed 101. The pedestal 140 may also include a support for the ampoule 110 on the heating coil 120. Additionally, insulation may be disposed within the pedestal 140 to facilitate inward radial heat flux during growth and heat removal during post-growth processes and cooling. The pedestal 140 for the growth ampoule 110 may include a hollow core below the seed pocket holding the seed crystal 101 to provide a downward conductive heat flow path through the center, further facilitated and more stable by a larger diameter quartz rod to the bottom of the heater. The pedestal 140 may be operable to move vertically to facilitate the growth process or may remain at a fixed height. Additionally, the pedestal 140 may rotate to achieve greater thermal uniformity during heating.

[0011]

[0017] In the VGF process, the seed 101, a polycrystalline charge in the crucible 130 of the ampoule 110, may be heated using a multi-zone furnace, as indicated by the heating coil 120. In an exemplary scenario, a BO sealing material 107 may be placed on top of the melt to reduce loss of crystal growth material, particularly arsenic, due to its higher vapor pressure. Crystal growth is initiated by melting the charge into the seed 101, thereby generating a melt 105, and slowly decreasing the temperature at which the melt 105 in the seed 101 cools. The crystallization process that generates the solid 103 can be precisely controlled by varying the temperature gradient in different zones of the furnace, such as by applying different currents to different parts of the heating coil 120 and / or vertically moving the pedestal 140. Additionally, the pedestal 140 may be rotated during heating and cooling to average out any thermal fluctuations within the heating coil 120. Accordingly, the heating coil 120 may be equipped with a multi-zone heating system capable of different temperatures, heating / cooling rates, and spatial temperature profiles.

[0012]

[0018] The VGF process has several advantages over other processes, such as liquid-encapsulated Czochralski (LEC) and horizontal Bridgman (HB). First, the thermal environment of the crystal and melt is radially symmetric, allowing for precise control of the radially uniform interface and temperature profile. Second, growth at low axial and radial temperature gradients, combined with the diameter control imposed by the crucible and the elimination of the need for large temperature gradients to rapidly freeze the crystal, significantly reduces strain and, therefore, dislocations in the crystal. Third, the liquid-solid interface progresses upward through the melt, initiating crystallization at the seed 101 at the bottom of the crucible 130. The system 100 can be cooler at the bottom and thermally stabilized against convection. During the cooling process, easily adjustable cooling brings the crystal to room temperature at a rate that minimizes strain on the crystal.

[0013]

[0019] Prior to crystal growth, GaAs polycrystalline bodies can be pre-fabricated by double consolidation. This double consolidation process can be performed in a quartz reactor tube, for example, using the boat method. Once polycrystalline GaAs is produced, VGF crystal growth can proceed. Several VGF parameters can be carefully controlled to achieve a low etch pit density (EPD). The first parameter can include the shape of the melt / crystal interface 109, which can be controlled to be recessed relative to the melt, for example, 5-20 mm below the edge of a 200 mm (8 inch) diameter crystal. This can be controlled using different temporal and / or spatial temperature profiles.

[0014]

[0020] Second, the crystallization rate, when controlled by the cooling rate, can be configured to be in the range of 0.1 to 1.0 degrees C / hr. Different solidification rates can be configured in different parts of the ingot. Precise control is desirable because temperature gradients along the growing crystal create stresses in the boule, causing the tip to cool prematurely, and in some cases the tip can be up to 100 degrees Celsius cooler than the tail.

[0015]

[0021] Finally, the temperature gradient at the melt / crystal interface can be configured to be 1-10 degrees C / cm. Again, multi-zone heating can enable precise temperature control throughout the crucible 130. After completion of overall solidification, the heating temperature can be ramped down to room temperature at rates of approximately 0.5-5 degrees C / hr, 1-20 degrees C / hr, and 5-20 degrees C / hr in the different heating zones, respectively. This process results in a low-dislocation, 200 mm (8 inch) diameter GaAs single crystal at least approximately 90 mm long with a cylindrical portion. The wafers described here are n-type doped, although p-type and non-insulating wafers are also possible by the process. While this process is described for a 200 mm (8 inch) diameter ingot, the same process can be used for other diameters (e.g., diameters smaller or larger than 200 mm (8 inch)) using different furnace sizes. The dislocation density resulting from this process is approximately 1000, as shown in Figures 3A-3D. cm -2 Less than 500cm -2 Less than 200cm -2 Less than 100cm -2 Less than 30cm -2 is less than.

[0016]

[0022] In the furnace design shown in FIG. 1 , a specific material combination may be selected for the pedestal 140, allowing the crystal ampoule 110 to adjust its position in the furnace depending on growth requirements to produce crystals at the desired growth location. The pedestal may move vertically, thereby enabling crystal growth by the Vertical Bridgman (VB) method, and may rotate to improve thermal uniformity in the VGF system 100. The pedestal 140 and heating coil 120 enable the growth of high-quality crystals along the vertical direction. In one example, the crystal load weight may be greater than 20 kg, and the effective 200 mm (8 inch) crystal length may be 90 mm or greater. This furnace layout allows for the VGF process to precisely configure heat transfer and temperature gradients during growth and cooling to maintain the appropriate pressure inside the ampoule 110.

[0023] The VGF process disclosed herein enables crystals with low defect densities due to the low temperature gradients that can be maintained during growth. However, even with low gradients, a certain temperature gradient is required at the solid-liquid interface 109 to maintain continuous crystal growth throughout the growth process, and the melt temperature may be high enough to result in high pressures within the ampoule 110. These higher pressures may become undesirable as the ingot diameter increases, causing deformation of the ampoule 110 itself, thereby resulting in potential deviations from stoichiometry and breakage of the crystal, crucible, and / or ampoule. To avoid these issues, a multi-zone heating configuration may be utilized, with heat input from the sides and top of the ampoule 110 / crucible 130; exemplary heating zones are shown in dashed lines in FIG. 1 . In this way, an appropriate temperature gradient for high-quality single crystal growth can be maintained at the growth interface 109 while still maintaining a melt temperature low enough to reduce and / or eliminate ampoule deformation and resulting problems. Additionally, the pedestal 140 allows for effective axial heat transfer, thereby facilitating single crystal growth at larger diameters.

[0017]

[0024] FIG. 2 illustrates a 200 mm (8 inch) GaAs ingot and the leading and trailing edges of that ingot, according to an exemplary embodiment of the present disclosure. Referring to the top image, the 200 mm (8 inch) GaAs ingot or boule is shown having a length greater than 90 mm, while the bottom image shows the unpolished leading and trailing edges of the ingot, respectively, revealing diameter non-uniformities and macroscopic defects such as twin or grain boundaries for an ingot of that length. With vertical movement of the pedestal 140, the furnace design can be "VB-like," allowing for longer crystals with lower EPD; even with movement and a VB-like configuration, crystals can have lower EPDs through proper design of temperature profiles, gradients, and ramp rates during growth.

[0018]

[0025] The pedestal 140 can move up and down vertically. Once the ampoule is initially installed, its position in the heating zone can be adjusted at any time to ensure the crystal is in the best temperature field position. Therefore, this VGF+VB combination method allows for the growth of longer crystals. Compared to a stationary crucible 130 / ampoule 110, this approach does not necessarily lead to higher EPD. This VB+VGF method provides an excellent method for growing high-quality, low-dislocation, large-size GaAs crystals.

[0019]

[0026] 3A-3D show etch pit density results for 200 mm (8 inch) gallium arsenide wafers manufactured according to embodiments of the present disclosure. EPD measurements may be performed according to SEMI M36-0699 and ASTM test method F140-92. FIG. 3A shows EPD results for the leading and trailing wafers from a first 200 mm (8 inch) ingot, with EPD levels measured at 69 points (each point is 0.024 cm). 2 The results are for the seed (tip) and the end. For this ingot, the wafers had an average EPD of 1288 cm at the tip of the ingot. -2 , 71cm at the end -2 This is a significant improvement over existing GaAs substrates.

[0020]

[0027] FIG. 3B shows the EPD results for the leading and trailing wafers from the second ingot, showing a peak at 289 cm -2 EPD of 100cm at the end -2 , indicating a very high quality 200 mm (8 inch) GaAs substrate. Hall measurements on the wafer in Figure 3B resulted in a 3 × 10 EPD at the tip. 17 cm -3 to 4×10 at the end 18 cm -3 The carrier concentration is in the range of 5×10 -3Ω-cm to 2×10 at the end -3 Finally, the Hall mobility was in the 3000 cm Ω-cm range at the tip. 2 / Vsec to 2000cm at the end 2 / V seconds.

[0021]

[0028] FIG. 3C shows the EPD results for the terminal wafer (No. 47 of the third boule), with an average EPD of 28 cm -2 The maximum EPD is 250cm -2 Non-contact electrical measurements of this boule reveal a 6 × 10 17 cm -3 to 1.8×10 at the end 18 cm -3 With a carrier concentration in the range of , the resistivity is 3.4 × 10 at the tip. -3 Ω-cm to 1.7×10 at the end -3 Finally, the Hall mobility was in the range of 2600 cm at the tip. 2 / Vsec to 2000cm at the end 2 / V seconds.

[0022]

[0029] FIG. 3D shows the EPD distribution and image from the nSpec metrology tool for the wafer in FIG. 3C (No. 47 of the third boule), with the EPD at 112 cm -2 The percentage of wafers with zero EPD is about 50% and <1000 cm -2 The area percentage of 0.01% was 97%. The image on the right of Figure 3D shows an optical image of the wafer. The nSpec tool measures the entire wafer surface, as opposed to the EPD distribution in Figure 3C, which is a 69-point measurement.

[0023]

[0030] 4A-4F illustrate photoluminescence measurements of a 200 mm (8 inch) gallium arsenide substrate, according to an exemplary embodiment of the present disclosure. Referring to FIGS. 4A-4F, the emission intensity distribution for different wafers along a 200 mm (8 inch) diameter GaAs boule is shown, showing results for wafers 1, 30, 35, 40, 45, and 47 of that boule.

[0024]

[0031] In the first approximately 10 wafers of the boule, higher intensity signals are evident in four regions located along the wafer periphery at the 3:00, 6:00, 9:00, and 12:00 positions. This increase in intensity may be related to dislocations in those regions at the tip of the boule. The standard deviation of the intensity variation is approximately 20% at the tip, but is approximately 15-20% across the wafer, reducing to approximately 4%.

[0025]

[0032] 5A-5F illustrate resistivity distributions for 200 mm (8 inch) gallium arsenide substrates according to exemplary embodiments of the present disclosure. High and low values ​​are included in the distributions with resistivity in mΩ-cm, and the resistivity variation across each wafer standard deviation is shown below each distribution.

[0026]

[0033] Figures 5A-5C show resistivity plots for three 200 mm (8 inch) GaAs wafers from a boule. The plots show higher resistivity at the 3:00, 6:00, 9:00, and 12:00 positions around the wafer periphery for the leading wafer, similar to the emission intensity results in Figures 4A-4J. Like emission intensity, resistivity variation decreases toward the end of the boule, with a 12% variation, or 3.4-6.5 mΩ-cm, for wafer 5 and a 3% variation, or 2.1-2.5 mΩ-cm, for wafer 70. Has.

[0027]

[0034] Figures 5D-5F show resistivity for three 200 mm (8 inch) wafers from another boule, again showing that resistivity variation decreases for wafers closer to the end of the boule. High and low values ​​are shown in the distribution, ranging from 2.7 to 3.7 mΩ-cm at the leading edge and 1.7 to 1.9 mΩ-cm at the trailing edge, with each corresponding to the variation standard deviation shown below, ranging from 9% for wafer 1 to 3.6% for wafer 47.

[0028]

[0035] 6 is a diagram illustrating a method for producing GaAs wafers using the vertical gradient freeze furnace 100 shown in FIG. 1. This process results in a 1000 cm -2 Less than 500cm -2 Less than 100cm -2 Less than and 30cm -2 200 mm (8 inch) GaAs substrates with an average etch pit density of less than 1000 nm are obtained. This process can be further used to fabricate indium phosphide (InP), gallium phosphide (GaP), or other related III-V compound semiconductors.

[0029]

[0036] In step 601, raw materials arsenic (As), gallium (Ga), and dopants can be obtained, and testing can be performed on the raw materials before placing them in a boat in a quartz tube for double consolidation to produce doped or undoped polycrystalline GaAs. In some examples, the dopant is silicon. In some examples, the dopant includes one or more types of dopants. In some examples, the dopants are optional. A charge is then prepared by placing the polycrystalline GaAs previously produced by double consolidation in a crucible with a seed crystal, an appropriate amount of BO sealing material, and an appropriate amount of dopants, evacuating, and sealing the crucible inside a fused quartz ampoule.

[0030]

[0037] Once the GaAs charge is generated, vertical gradient freeze (VGF) crystal growth occurs in step 603, where an ampoule containing a crucible is heated in a multi-zone heating system in a controlled manner to gradually melt the polycrystalline charge material, including any dopants, from top to bottom until a portion of the seed crystal is melted. Growth can be initiated from the partially melted seed by implementing controlled cooling of the multi-zone heating apparatus. The temporal and spatial temperature profiles are tightly controlled to yield crystals of 200 mm (8 inches) or larger diameter with low EPD.

[0031]

[0038] To achieve low EPD, several VGF parameters are carefully controlled. The first parameter can include the shape of the melt / crystal interface, which can be controlled to be recessed relative to the melt, e.g., 5-15 mm recessed, with the center 5-15 mm below the edge of a 200 mm (8 inch) diameter solidifying crystal. This can be controlled using different temporal and / or spatial temperature profiles. Second, the crystallization rate, as controlled by the cooling rate, can range from 0.1 to 2 degrees C / hr for different portions of the ingot, while applying a temperature gradient between 1 C / cm and 8 C / cm at the melt-crystal interface. The interface shape can be controlled to be slightly recessed relative to the melt by using appropriate cooling rates in a multi-zone heating system. Different solidification rates can be configured for different portions of the ingot. Finally, the temperature gradient at the melt / crystal interface can be configured to be 4-8 degrees C / cm. After completion of solidification of the charge material, application of controlled cooling with appropriate cooling rates of 0.5-5 C / h, 1-10 C / h, and 5-20 C / h for different heating zones to the first 300 C, and then 20-50 C / h to room temperature results in crystals with very low defect density.

[0032]

[0039] Once the VGF crystal is grown (and optionally tested) in step 605, an ingot forming process may be performed, resulting in, for example, a crystal having a desired flatness. A rounded ingot is obtained which can be further tested. Once the ingot is formed, it is sliced ​​into wafers in step 607, which can optionally be tested.

[0033]

[0040] Once the low EPD wafers are sliced ​​from the ingot, they may proceed to wafer processing step 609. An optional wafer annealing process may be performed. In an exemplary annealing process, one or more annealing stages may be used, in which the wafers may be loaded vertically into a horizontal quartz boat and inserted into a horizontal quartz ampoule with arsenic mass. The arsenic mass may be configured to achieve the necessary vapor pressure at the annealing temperature to avoid any arsenic dissociation from the GaAs substrate. The ampoule is then placed under high vacuum (<5E -3 The ampoule and its contents may then be inserted into, for example, a horizontal three-zone furnace, and heating of the ampoule and its contents to the desired set (platform) temperature commences.

[0034]

[0041] Tests may be performed on the wafer to ensure structural and electrical quality. In an exemplary scenario, structural quality may be assessed by x-ray characterization and etch pit density measurements, and x-ray transmission measurements may be utilized to assess the presence of slip dislocations. -2 Less than 500cm -2 Less than 200cm -2 Less than 100cm -2 Less than or even 30cm -2 An average dislocation etch pit density (EPD) of less than 1000 nm can result in a 200 mm (8 inch) GaAs substrate using the process described above. Structural and electrical quality can also be assessed by photoluminescence and Hall measurements.

[0035]

[0042] Once the low-EPD wafers have been annealed and optionally tested, a wafer polishing process may be performed to polish the low-EPD wafers, and the polished wafers may optionally be tested again. Once the wafers are polished, they may be cleaned, after which they may be packaged for shipment to the customer, step 611. The above process may also be used to produce indium phosphide (InP) or other compound semiconductor wafers. The result of this process is a low-EPD 200 mm (8 inch) GaAs wafer.

[0036]

[0043] FIG. 7 illustrates a device fabricated on a 200 mm (8 inch) gallium arsenide wafer with low etch pit density, according to an exemplary embodiment of the present disclosure. Referring to FIG. 7, a 200 mm (8 inch) GaAs wafer 701 is shown that has been fabricated using the process described above and is further processed with electrical and / or optoelectronic devices on dies 703. Also shown is a flat 705 that may be formed during wafer fabrication to indicate, for example, a crystal plane. In another exemplary scenario, a notch may be utilized instead of a flat. The number of dies 703 on wafer 701 can be defined by the area of ​​each die, and the size shown in FIG. 7 is merely an example.

[0037]

[0044] Additionally, die 703 may include optoelectronic elements such as edge-emitting lasers, vertical-cavity surface-emitting lasers (VCSELs), light-emitting diodes (LEDs), including micro-LEDs, and photodetectors, and in some scenarios it is desirable to transmit optical signals through wafer 701. For example, an array of detectors or surface-emitting lasers may be formed on wafer 701, and optical signals may be received and / or transmitted through wafer 701, while readout or control circuitry may be located on those devices.

[0038]

[0045] The above-described process can be utilized to prepare doped substrates, such as silicon-doped substrates, for example, for optoelectronic applications. For example, silicon can be incorporated during crystal growth. Other dopants are also possible. Dislocations in the substrate, as noted above, can reduce device reliability because current can increase the size of defects, which can affect light emission. When smaller devices, such as microLEDs, are fabricated on the substrate, defects can include larger areas of the device, which can detrimentally affect performance, demonstrating the benefits of the low EPD crystals disclosed herein.

[0039]

[0046] Additionally, the process can be used to produce semi-insulating or lightly doped GaAs substrates. Semi-insulating GaAs substrates enable high-speed electronic devices due to their high resistivity, where conductive substrates can cause losses and parasitic capacitance. Exemplary devices include pseudomorphic high-electron mobility transistors (pHEMTs) and heterojunction bipolar transistors.

[0040]

[0047] In an embodiment of the present disclosure, wafers for low etch pit density gallium arsenide crystals with silicon dopants (and / or other suitable dopants) are prepared using a 1000 cm -2 Less than 500cm -2 Less than 200cm -2 Less than 100cm -2 Less than or even 30cm -2 The wafer may have a diameter of 200 mm (8 inches) or greater. The wafer may have an etch pit density of less than 3×10 17 ~4×10 18 cm -3 The wafer may have a dopant concentration in the range of 0.1 to 1.0 μm. The wafer may have a thickness of 500 μm or greater. Photoluminescence measurements may result in a peak intensity standard deviation of less than 5%.

[0041]

[0048] In another embodiment of the present disclosure, a method for low etch pit density gallium arsenide crystals may include sealing a polycrystalline gallium arsenide seed crystal, a BO sealing material, and a charge material including carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth process by heating the ampoule using a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal melts; initiating growth from the partially melted seed by implementing controlled cooling of the multi-zone heating system; applying a temperature gradient of between 1 C / cm and 8 C / cm at the melt-crystal interface; and utilizing a cooling rate in the multi-zone heating system to control the shape of the interface to be recessed relative to the melt to form a solidified gallium arsenide crystal.

[0042]

[0049] The cooling of the multi-zone heating system may be configured at a rate of 0.1-2 C / h. The crucible may be evacuated before sealing it into a quartz ampoule. The solidified charge material may be cooled at rates of 0.5-5 C / h, 1-10 C / h, and 5-20 C / h for different heating zones to the first 300 C, and then at a rate of 20-50 C / h to room temperature. The interface shape may be controlled to be recessed relative to the melt, with the center being no more than 5-15 mm lower than the edge of the solidified crystal. The solidified crystal may have a diameter of 200 mm (8 inches) or more, and may be 1000 cm -2 Less than 500cm -2 Less than 200cm -2 Less than 100cm -2 Less than or even 30cm -2 The wafer may have an etch pit density of less than 3×10. The wafer may have a diameter of 200 mm (8 inches) or greater. 17 ~4×10 18 cm -3 The wafer may have a dopant concentration in the range of 0.1 to 1.0 μm. The wafer may have a thickness of 500 μm or greater. Photoluminescence measurements may result in a peak intensity standard deviation of less than 5%.

[0043]

[0050] In a disclosed example, a vertical gradient freeze system for forming gallium arsenide (GaAs) 200 mm (8 inch) substrates having silicon as a dopant includes a crucible for containing GaAs melt and seed material during the formation process, one or more heating coils disposed in multiple heating zones, and a pedestal that moves relative to the crucible, the system operable to control the heating of the multiple heating zones and the movement of the pedestal to form single crystal GaAs substrates.

[0044]

[0051] In some examples, the ampoule supports the crucible. In examples, the pedestal is operable to move the crucible relative to the heating coil. In examples, the pedestal is operable to rotate relative to the heating coil. In examples, the pedestal is operable to move vertically relative to the heating coil.

[0045]

[0052] In some examples, the heating coil is operable to activate or the pedestal is operable to move to control the shape of the interface between the GaAs melt and the crystal to achieve a low etch pit density (EPD). In examples, the shape is recessed relative to the GaAs melt. In examples, the shape of the interface is recessed by 5-20 mm such that the center is lower than the edge of the substrate by 5-20 mm.

[0046]

[0053] In some examples, a boron trioxide BO layer is placed on the GaAs melt as a sealing material to reduce loss of crystal growth material. In examples, the heating coil is operable to activate or the pedestal is operable to move to control the crystallization rate as controlled by the cooling rate, which may be configured to be in the range of 0.1 to 1.0 degrees C / hr.

[0047]

[0054] In some examples, the heating coil is operable to activate or the pedestal is operable to move to control the temperature gradient at the GaAs melt / crystal interface, which can be configured to be 1-10 degrees C / cm.

[0048]

[0055] In examples, insulation may be placed on or within the pedestal to facilitate inward radial heat flux during growth or heat removal during post-growth processes and cool-down.

[0049]

[0056] In some examples, one or more electronic or optoelectronic devices are formed on a first surface of the surface. In examples, the electronic or optoelectronic devices are one or more of a light emitting diode (LED), a laser, a heterojunction bipolar transistor (HBT), and a pseudo-morphic high-electron mobility transistor (pHEMT). In examples, the substrate is separated into a plurality of dies such that an optical signal from an optoelectronic device of the electronic or optoelectronic devices on the first side of the substrate is transmitted to a second side of the substrate opposite the first side.

[0050]

[0057] In some examples, the substrate is 200 cm -2 In the example, the substrate has an etch pit density of less than 1×10 19 cm -3 In an example, the substrate has a thickness of 300 μm or greater.

[0051]

[0058] In some disclosed examples, a method for forming a single-crystal gallium arsenide substrate includes sealing a charge material including a polycrystalline gallium arsenide (GaAs) seed crystal, a BO sealing material, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth process by heating the ampoule using a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal melts; moving a pedestal relative to the crucible, the system operable to control the heating of the multi-zone heating system and the movement of the pedestal; and performing controlled cooling of the multi-zone heating system during growth from the partially melted seed to form a single-crystal GaAs substrate 200 mm (8 inches).

[0052]

[0059] In some examples, the method further comprises applying a temperature gradient of between 1 C / cm and 8 C / cm at the melt-crystal interface.

[0053]

[0060] In some examples, the method further includes using a cooling rate in a multi-zone heating system to control the shape of the interface so that it is recessed relative to the melt to form a solidified gallium arsenide crystal. In some examples, the shape of the interface is recessed by 5-20 mm such that the center is 5-20 mm lower than the edge of the substrate.

[0054]

[0061] In some examples, moving the pedestal includes moving the crucible relative to the multi-zone heating system. In some examples, moving the pedestal includes rotating the crucible relative to the multi-zone heating system. In some examples, moving the pedestal includes vertically moving the crucible relative to the multi-zone heating system.

[0055]

[0062] In some examples, the method further includes controlling the multi-zone heating system or pedestal movement to control the crystallization rate as controlled by the cooling rate, which may be configured to be in the range of 0.1 to 2.0 degrees C / hr.

[0056]

[0063] In some examples, the method further includes forming one or more electronic or optoelectronic devices on the first surface of the substrate, hi some examples, the electronic or optoelectronic devices are one or more of a light emitting diode (LED), a laser, a heterojunction bipolar transistor (HBT), and a pseudo-morphic high-electron mobility transistor (pHEMT).

[0057]

[0064] In some examples, the method further includes evacuating the crucible before sealing it in the quartz ampoule. In examples, the method further includes cooling the solidified charge material to a first temperature of 300° C. at rates of 0.5-5 C / h, 1-10 C / h, and 5-20 C / h for different heating zones of the multi-zone heating system, and then to room temperature at a rate of 20-50 C / h.

[0058]

[0065] While the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, it is not intended that the disclosure be limited to the particular embodiments disclosed, but rather that the disclosure include all embodiments falling within the scope of the appended claims.

Claims

1. 1. A vertical gradient freeze system for forming gallium arsenide (GaAs) 200 mm (8 inch) substrates having silicon as a dopant, comprising: a crucible for containing the GaAs melt and seed material during the formation process; one or more heating coils arranged in a plurality of heating zones; a pedestal that moves relative to the crucible, the pedestal being operable to control heating of the plurality of heating zones and movement of the pedestal to form a single crystal GaAs substrate. system.

2. The system of claim 1 further comprising an ampoule for supporting the crucible.

3. The system of claim 1 , wherein the pedestal is operable to move the crucible relative to the heating coil.

4. The system of claim 1 , wherein the pedestal is operable to rotate relative to the heating coil.

5. The system of claim 1 , wherein the pedestal is operable to move vertically relative to the heating coil.

6. 2. The system of claim 1, wherein the heating coil is operable to activate or the pedestal is operable to move to control the shape of the interface between the GaAs melt and the crystal to achieve low etch pit density (EPD).

7. The system of claim 6 , wherein the feature is recessed relative to the GaAs melt.

8. 8. The system of claim 7, wherein the shape of the interface is a depression of 5 to 20 mm such that the center is lower than the edge of the substrate by 5 to 20 mm.

9. Boron trioxide B ２ O ３ The system of claim 1 , wherein the layer is disposed on the GaAs melt as a sealing material to reduce loss of crystal growth material.

10. 10. The system of claim 1, wherein the heating coil is operable to activate or the pedestal is operable to move to control the crystallization rate as controlled by a cooling rate that can be configured to be in the range of 0.1 to 1.0 degrees C / hr.

11. 10. The system of claim 1, wherein the heating coil is operable to activate or the pedestal is operable to move to control a temperature gradient at the GaAs melt / crystal interface, which can be configured to be 1-10 degrees C / cm.

12. 10. The system of claim 1, further comprising insulation disposed on or within the pedestal to facilitate inward radial heat flux during growth or heat removal during post-growth processes and cool-down.

13. The system of claim 1 , wherein one or more electronic and / or optoelectronic elements are formed on a first surface of the surface.

14. The electronic or optoelectronic device may be a light emitting diode (LED), a laser, a heterojunction 14. The system of claim 13, wherein the transistor is one or more of a bipolar transistor (HBT), and a pseudo-morphic high-electron mobility transistor (pHEMT).

15. 14. The system of claim 13, wherein the substrate is separated into a plurality of dies such that optical signals from optoelectronic ones of the electronic or optoelectronic devices on a first side of the substrate are transmitted to a second side of the substrate opposite the first side.

16. The substrate is 200 cm －２ 10. The system of claim 1, having an etch pit density of less than 1000 nm.

17. The substrate is 1×10 １９ cm －３ 10. The system of claim 1 having a dopant concentration of at least 1000 .mu.m.

18. The system of claim 1 , wherein the substrate has a thickness of 300 μm or greater.

19. 1. A method for forming a single crystalline gallium arsenide substrate, comprising: a polycrystalline gallium arsenide (GaAs) seed crystal and B ２ O ３ sealing a charge material including a sealing material and carbon into a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth process by heating the ampoule using a multi-zone heating system to gradually melt the charge material until a portion of the seed crystal melts; moving a pedestal relative to the crucible, the system being operable to control the heating of the multi-zone heating system and the movement of the pedestal; performing controlled cooling of the multi-zone heating system during growth from the partially melted seed to form a single crystal 200 mm (8 inch) GaAs substrate; A method comprising:

20. 20. The method of claim 19, further comprising applying a temperature gradient of between 1 C / cm and 8 C / cm at the melt-crystal interface.

21. 20. The method of claim 19, further comprising utilizing a cooling rate in the multi-zone heating system to control the shape of the interface so that it is recessed relative to the melt to form a solidified gallium arsenide crystal.

22. 22. The system of claim 21, wherein the shape of the interface is a recess of 5 to 20 mm such that the center is lower than the edge of the substrate by 5 to 20 mm.

23. 20. The method of claim 19, wherein moving the pedestal moves the crucible relative to the multi-zone heating system.

24. 20. The method of claim 19, wherein moving the pedestal rotates the crucible relative to the multi-zone heating system.

25. 20. The method of claim 19, wherein moving the pedestal moves the crucible vertically relative to the multi-zone heating system.

26. The cooling rate can be configured to range from 0.1 to 2.0 degrees C / hour.

20. The method of claim 19, further comprising controlling the multi-zone heating system or the pedestal movement to control the crystallization rate when heated.

27. 20. The method of claim 19, further comprising forming one or more electronic and / or optoelectronic elements on the first surface of the substrate.

28. 28. The method of claim 27, wherein the electronic or optoelectronic device is one or more of a light emitting diode (LED), a laser, a heterojunction bipolar transistor (HBT), and a pseudo-morphic high-electron mobility transistor (pHEMT).

29. 20. The method of claim 19, including evacuating the crucible before sealing it into the quartz ampoule.

30. 20. The method of claim 19, comprising cooling the solidified charge material to the first 300°C at a rate of 0.5-5 C / h, 1-10 C / h, and 5-20 C / h for different heating zones of the multi-zone heating system, and thereafter to room temperature at a rate of 20-50 C / h.

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