Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. Each of the analog calculator, the first memory circuit, and the second memory circuit includes a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data as digital data to the digital calculator. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data as analog data to the analog calculator. The analog calculator has a function of performing product-sum operation using the second weight data. In at least one transistor including the oxide semiconductor in the channel formation region included in the analog calculator and the second memory circuit, the amount of current flowing between a source and a drain is the amount of current flowing when the transistor operates in a subthreshold region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are becoming widespread. To process large amounts of data at high speed, such electronic devices are subject to active technological development aimed at improving the performance of semiconductor devices. One example of a technology that achieves high performance is the so-called SoC (System on Chip) technology, which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with a CPU. With semiconductor devices that achieve high performance through SoC technology, increased heat generation and power consumption become problems.

[0004] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters become enormous, resulting in an increase in the amount of calculations. Since an increase in the amount of calculations leads to an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Typical architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective in reducing circuit scale and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0006] In AI technology calculations, multiplication and accumulation operations using weight data and input data are repeated a huge number of times, which requires faster calculation processing. A memory cell array must store large amounts of weight data and intermediate data. In a memory cell array that stores large amounts of weight data and intermediate data, the weight data and intermediate data are read out to the calculation circuit via bit lines. As the frequency of reading weight data and intermediate data increases, the bandwidth between the memory cell array and the calculation circuit can become a limiting factor in operating speed.

[0007] Increasing the number of parallel interconnections between the memory cell array and the arithmetic circuit allows the memory cell array and the arithmetic circuit to be connected with a high bandwidth, which is advantageous for speeding up arithmetic processing. However, since the number of interconnections between the arithmetic circuit and the memory cell array increases, there is a risk that the area of ​​the peripheral circuit will increase significantly.

[0008] Furthermore, in AI technology calculations, how to reduce the charge and discharge energy of bit lines is important in achieving low power consumption.

[0009] Shortening the bit lines is an effective way to reduce the charge / discharge energy of the bit lines. However, this requires alternating arrangement of arithmetic circuits and memory cell arrays, which can significantly increase the area of ​​the peripheral circuits. Another technique for shortening the bit lines is to integrate transistors vertically using bonding techniques. However, bonding techniques require large spacing between the electrical connections, which can increase parasitic capacitance and make it difficult to reduce the charge / discharge energy.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.Another object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed.Another object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic accuracy.Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device.Another object is to provide a semiconductor device with a novel structure.

[0011] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a digital computing unit, an analog computing unit, a first memory circuit, and a second memory circuit, wherein the analog computing unit, the first memory circuit, and the second memory circuit each include a transistor having an oxide semiconductor in a channel formation region, the first memory circuit having a function of supplying first weight data as digital data to the digital computing unit, the digital computing unit having a function of performing a product-sum operation using the first weight data, the second memory circuit having a function of supplying second weight data as analog data to the analog computing unit, and the analog computing unit having a function of performing a product-sum operation using the second weight data, and an amount of current flowing between a source and a drain of at least one of the transistors having an oxide semiconductor in a channel formation region, which are included in the analog computing unit and the second memory circuit, is an amount of current flowing when the transistor operates in a subthreshold region.

[0013] In the above, the digital computing unit may be configured to be in an inactive state while the analog computing unit is operating, and the analog computing unit may be configured to be in an inactive state while the digital computing unit is operating.

[0014] In the above, it is preferable that the digital computing unit performs a convolution operation, and it is preferable that the analog computing unit performs a full-connection operation.

[0015] In the above, it is preferable that the digital computing unit includes a transistor having silicon in a channel formation region. Also, in the above, it is preferable that the digital computing unit is provided in a first layer, and the analog computing unit, the first memory circuit, and the second memory circuit are provided in a second layer, and the second layer is provided on the first layer. Also, in the above, it is preferable that the first memory circuit is provided so as to overlap the digital computing unit.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0017] One embodiment of the present invention can provide a semiconductor device with reduced power consumption. Another embodiment of the present invention can provide a semiconductor device with improved arithmetic processing speed. Another embodiment of the present invention can provide a semiconductor device with improved arithmetic accuracy. Another embodiment of the present invention can provide a miniaturized semiconductor device. Another embodiment of the present invention can provide a semiconductor device with a novel structure.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A and 2B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. [Figure 7] 7A and 7B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 9] 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. [Figure 11] 11A, 11B, and 11C are diagrams illustrating configuration examples of semiconductor devices. [Figure 12] FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating a configuration example of a semiconductor device. [Figure 15] 15A and 15B are diagrams illustrating a configuration example of a semiconductor device. [Figure 16] 16A and 16B are diagrams illustrating a configuration example of a semiconductor device. [Figure 17] 17A and 17B are diagrams illustrating a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a diagram illustrating an example of the configuration of a processing system. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of a CPU. [Figure 20] 20A and 20B are diagrams illustrating an example of the configuration of a CPU. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 22] 22A to 22C are cross-sectional views showing examples of the structure of a transistor. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 24] 24A and 24B are cross-sectional views showing examples of the structure of a transistor. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 26] FIG. 26A is a diagram illustrating the classification of IGZO crystal structures, FIG. 26B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 26C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 27] FIG. 27A is a perspective view showing an example of a semiconductor wafer, FIG. 27B is a perspective view showing an example of a chip, and FIGS. 27C and 27D are perspective views showing an example of an electronic component. [Figure 28] FIG. 28 is a perspective view showing an example of an electronic device. [Figure 29] 29A to 29C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0020] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0021] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated to potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, the symbol may be accompanied by an identifying symbol such as "_1", "_2", "[n]", or "[m,n]". For example, the second wiring GL is written as wiring GL[2].

[0025] (Embodiment 1) The structure, operation, and the like of a semiconductor device according to one embodiment of the present invention will be described.

[0026] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0027] 1A and 1B are diagrams illustrating a semiconductor device 100 according to one embodiment of the present invention.

[0028] The semiconductor device 100 includes a digital calculator 101, an analog calculator 102, an oxide semiconductor memory (OS memory) 103, and an oxide semiconductor memory 104. The digital calculator 101 preferably includes a transistor having silicon in a channel formation region (a Si transistor). The analog calculator 102 preferably includes a transistor having an oxide semiconductor in a channel formation region (an OS transistor). The oxide semiconductor memory 103 and the oxide semiconductor memory 104 each include an OS transistor.

[0029] The semiconductor device 100 functions as an accelerator capable of processing multiply-and-accumulate operations, and can selectively use a digital computing unit 101 or an analog computing unit 102 depending on the type of operation. FIG. 1A shows a state in which the digital computing unit 101 is operating, and FIG. 1B shows a state in which the analog computing unit 102 is operating. As shown in FIG. 1A, while the digital computing unit 101 is operating, the analog computing unit 102 is in an inactive state. Also, as shown in FIG. 1B, while the analog computing unit 102 is operating, the digital computing unit 101 is in an inactive state.

[0030] 1A, the digital computing unit 101 performs a multiply-and-accumulate operation using weight data W1 input from the oxide semiconductor memory 103 and input data A1, and outputs the result as output data MAC1. The weight data W1 output from the oxide semiconductor memory 103 is output as digital data.

[0031] The OS transistor provided in the oxide semiconductor memory 103 has an extremely small leakage current, that is, a current flowing between the source and drain in an off state. The oxide semiconductor memory 103 can be used as a nonvolatile memory by holding charge corresponding to data in the memory circuit using the extremely small leakage current characteristic.

[0032] Furthermore, it is preferable to provide the oxide semiconductor memory 103 with a memory circuit that can read stored data without destroying it (non-destructive readout). This allows processing using the same weight data to be performed repeatedly at a high arithmetic processing speed. This allows for faster parallel processing of product-sum operations in a neural network, which involves repeating data read operations many times.

[0033] Furthermore, it is preferable that the input data A1 and the weight data W1 are digital data that are resistant to noise in the digital computing unit 101. This allows the digital computing unit 101 to perform highly accurate arithmetic processing.

[0034] By using the oxide semiconductor memory 103 and the digital computing unit 101 as described above, the semiconductor device 100 can perform highly accurate and high performance arithmetic processing. Therefore, the semiconductor device 100 can efficiently perform processing using the same weight data, as in a convolutional neural network. Note that detailed configurations and specific examples of the oxide semiconductor memory 103 and the digital computing unit 101 will be described in the embodiments described later.

[0035] 1B, the analog computing unit 102 performs a product-sum operation using the weight data W2 input from the oxide semiconductor memory 104 and the input data A2, and outputs the result as output data MAC2. Here, the weight data W2 output from the oxide semiconductor memory 104 is output as analog data.

[0036] The analog computing unit 102 can perform multiplication using a translinear principle that utilizes the subthreshold region. Here, the OS transistors used in the analog computing unit 102 and the oxide semiconductor memory 104 have lower off-state current than Si transistors and can operate over a wider range of gate voltages in the subthreshold region. Therefore, in the analog computing unit 102 and the oxide semiconductor memory 104, the OS transistors can be operated in the subthreshold region with a small current value relatively easily.

[0037] Operating the OS transistor in the subthreshold region, where the current value is small, can reduce the power consumption of the analog computing unit 102 and the oxide semiconductor memory 104. AI technology calculations require repeated multiplication and accumulation operations using weight data and input data an enormous number of times, resulting in enormous power consumption. In particular, fully connected calculations, in which weight data is frequently rewritten, require significantly greater power consumption. By operating the analog computing unit 102 and the oxide semiconductor memory 104 in the subthreshold region, power consumption can be effectively reduced.

[0038] By using the oxide semiconductor memory 104 and the analog computing unit 102 as described above, the semiconductor device 100 can perform arithmetic processing with low power consumption. Therefore, the semiconductor device 100 can perform arithmetic processing in which weight data is frequently rewritten, such as a fully connected calculation, in a power-efficient manner. Note that detailed configurations and specific examples of the oxide semiconductor memory 104 and the analog computing unit 102 will be described in the embodiments described later.

[0039] As described above, the semiconductor device 100 described in this embodiment can operate the digital computing unit 101 when repeatedly performing arithmetic processing using the same weight data, and can operate the analog computing unit 102 when frequently rewriting the weight data. By selectively using the digital computing unit 101 and the analog computing unit 102 in this manner, arithmetic processing with high accuracy, high performance, and low power consumption can be performed as a whole.

[0040] Note that the semiconductor device 100 described in this embodiment can also process multiple calculations in parallel. When the multiple calculations include a repetitive calculation using the same weight data and a calculation in which the weight data is frequently rewritten, the digital calculation unit 101 and the analog calculation unit 102 may be operated in parallel. That is, the repetitive calculation using the same weight data can be processed by the digital calculation unit 101, while the calculation in which the weight data is frequently rewritten can be processed in parallel by the analog calculation unit 102. For example, when performing calculations using a CNN (Convolutional Neural Network) model, the analog calculation unit 102 can process a fully connected calculation, while the digital calculation unit 101 can perform the next convolution calculation in parallel.

[0041] Next, the arrangement of the digital computing unit 101, the analog computing unit 102, the oxide semiconductor memory 103, and the oxide semiconductor memory 104 in the semiconductor device 100 will be described with reference to FIGS. 2A and 2B.

[0042] 2A shows an example in which a digital computing unit 101 is formed on a silicon substrate, and an analog computing unit 102, an oxide semiconductor memory 103, and an oxide semiconductor memory 104 are arranged on the digital computing unit 101. In FIG. 2A, an xy plane is set substantially parallel to the upper surface of the silicon substrate, and an element layer in which the analog computing unit 102, the oxide semiconductor memory 103, and the oxide semiconductor memory 104 are formed is provided above in the z-axis direction. This configuration makes it possible to achieve high integration of the semiconductor device 100 functioning as an accelerator and improve the arithmetic processing speed per unit area. This also makes it possible to miniaturize the semiconductor device 100.

[0043] 2A, it is preferable to provide an oxide semiconductor memory 103 superimposed on the digital computing unit 101. With such a configuration, it is possible to shorten the length of the wiring electrically connecting the oxide semiconductor memory 103 and the digital computing unit 101. As a result, it is possible to improve the processing speed when rewriting the weight data of the digital computing unit 101 and reduce the power consumption in this processing.

[0044] The arrangement of the components of the semiconductor device 100 described in this embodiment is not limited to the arrangement shown in Fig. 2A. For example, as shown in Fig. 2B, an element layer forming the analog computing unit 102 and the oxide semiconductor memory 104 may be stacked on an element layer forming the oxide semiconductor memory 103. With such a configuration, the semiconductor device 100 can be further miniaturized.

[0045] Furthermore, in the above description, a configuration in which Si transistors are used in the digital computing unit 101 has been shown, but the present embodiment is not limited to this, and a configuration in which Si transistors are used in the analog computing unit 102 may also be used.

[0046] Although the above description shows a configuration in which Si transistors are used in the digital computing unit 101 and OS transistors are used in the analog computing unit 102, the present embodiment is not limited to this. For example, both the digital computing unit 101 and the analog computing unit 102 may be configured to use OS transistors.

[0047] In this case, as shown in FIG. 3A , an oxide semiconductor calculator (OS Calculator) 105 and an oxide semiconductor memory (OS Memory) 106 can be arranged on a silicon circuit (Si Circuit) 107. Here, the oxide semiconductor calculator 105 is a calculator formed of OS transistors, and includes both a digital calculator and an analog calculator. The oxide semiconductor memory 106 has a function of supplying weight data to the oxide semiconductor calculator 105. The silicon circuit 107 may have any function, and may function as, for example, a drive circuit, a readout circuit, a memory circuit, or a calculation circuit.

[0048] As shown in FIG. 3A, an element layer for forming an oxide semiconductor computing unit 105 and an oxide semiconductor memory 106 is provided on a silicon substrate.

[0049] The arrangement of the components of the semiconductor device 100 described in this embodiment is not limited to the arrangement shown in FIG. 3A. For example, as shown in FIG. 3B, an element layer forming the oxide semiconductor memory 106 may be stacked on an element layer forming the oxide semiconductor computing unit 105. With such a configuration, the semiconductor device 100 functioning as an accelerator can be highly integrated, and the processing speed per unit area can be improved. This also enables the miniaturization of the semiconductor device 100.

[0050] 4, the semiconductor device 100 can be configured as a semiconductor device having a CPU 110 and a bus 120. With such a configuration, part of the calculations of a program executed by the CPU 110 can be executed by the semiconductor device 100 functioning as an accelerator.

[0051] The CPU 110 has the function of performing general-purpose processing, such as at least one of running an operating system, controlling data, performing various calculations, and executing programs. Here, the CPU 110 has a CPU core 200 and a backup circuit 222. The CPU core 200 corresponds to one or more CPU cores.

[0052] The backup circuit 222 enables the CPU 110 to retain data in the CPU core 200 even if the supply of power supply voltage is stopped. The supply of power supply voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. As the backup circuit 222, for example, an OS memory having an OS transistor is suitable.

[0053] The bus 120 electrically connects the CPU 110 and the semiconductor device 100 functioning as an accelerator. That is, the CPU 110 and the semiconductor device 100 functioning as an accelerator can transmit data via the bus 120.

[0054] The detailed configurations of the CPU 110, CPU core 200, backup circuit 222, and bus 120 will be described in the following embodiments.

[0055] As described above, one embodiment of the present invention can provide a semiconductor device with reduced power consumption. Alternatively, one embodiment of the present invention can provide a semiconductor device with improved arithmetic processing speed. Alternatively, one embodiment of the present invention can provide a semiconductor device with improved arithmetic accuracy. Alternatively, one embodiment of the present invention can provide a miniaturized semiconductor device.

[0056] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0057] (Embodiment 2) In this embodiment, a part of the configuration, operation, and the like of the semiconductor device 100 shown in the previous embodiment will be described.

[0058] 5A is a diagram illustrating a semiconductor device 10 according to one embodiment of the present invention. Here, the semiconductor device 10 is part of the semiconductor device 100 and includes the digital computing unit 101 and the oxide semiconductor memory 103 described in the above embodiment.

[0059] The semiconductor device 10 functions as an accelerator that executes a program (also called a kernel or kernel program) called from a host program. The semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0060] The semiconductor device 10 includes a memory circuit portion 20 (also referred to as a memory cell array), an arithmetic circuit 30, and a switching circuit 40. The arithmetic circuit 30 corresponds to the digital arithmetic unit 101 described in the above embodiment, and the memory circuit portion 20 corresponds to the oxide semiconductor memory 103 described in the above embodiment. The arithmetic circuit 30 and the switching circuit 40 are provided in a layer 11 having transistors in an xy plane in the drawing. The memory circuit portion 20 is provided in a layer 12 having transistors in an xy plane in the drawing.

[0061] The layer 11 includes a transistor having silicon in a channel formation region (a Si transistor). The layer 12 includes a transistor having an oxide semiconductor in a channel formation region (an OS transistor). The layers 11 and 12 are provided in different layers in a direction substantially perpendicular to the xy plane (the z direction in FIG. 5A). Therefore, the semiconductor device 10 shown in FIG. 5B has a stacked structure similar to that of the digital computing unit 101 and the oxide semiconductor memory 103 shown in FIG. 2A or 2B.

[0062] The memory circuit unit 20, which is composed of OS transistors, can be stacked with the arithmetic circuit 30 and the switching circuit 40, which can be composed of Si transistors. That is, the memory circuit unit 20 is provided on the substrate on which the arithmetic circuit 30 and the switching circuit 40 are provided. This allows the memory circuit unit 20 to be arranged without increasing the circuit area. By providing the memory circuit unit 20 on the substrate on which the arithmetic circuit 30 and the switching circuit 40 are provided, the memory capacity required for the arithmetic processing in the semiconductor device 10 functioning as an accelerator can be increased compared to when the memory circuit unit 20, the arithmetic circuit 30, and the switching circuit 40 are arranged on the same layer. The increased memory capacity reduces the number of data transfers required for the arithmetic processing from an external storage device to the semiconductor device, thereby reducing power consumption.

[0063] The memory circuit unit 20 is illustrated as an example of a plurality of memory circuit units 20_1 to 20_4. Each memory circuit unit has a plurality of memory circuits 21. In each of the memory circuit units 20_1 to 20_4, the plurality of memory circuits 21 are connected to the switching circuit 40 via wirings LBL_1 to LBL_4 (also referred to as local bit lines or read bit lines) as illustrated in FIG. 5A.

[0064] The memory circuit 21 may have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory in which memory cells are two-transistor (2T) or three-transistor (3T) gain cells and access transistors are OS transistors. The memory circuit 21 is a memory configured with OS transistors. The layer 12 including the memory circuit 21 may be stacked on the layer 11 including the arithmetic circuit 30 and the switching circuit 40. Since the memory circuit unit 20 including the memory circuit 21 is provided on the layer 11 including the arithmetic circuit 30 and the switching circuit 40, it is possible to reduce the area overhead caused by having the memory circuit unit 20.

[0065] Furthermore, OS transistors have an extremely small leakage current, the current that flows between the source and drain when they are off. NOSRAM can be used as nonvolatile memory by utilizing its extremely small leakage current characteristics to retain a charge corresponding to the data within the memory circuit. NOSRAM is particularly suitable for parallel processing of product-sum operations in neural networks, which require repeated data read operations, because it can read the stored data without destroying it (non-destructive readout).

[0066] The memory circuit 21 is preferably a memory having an OS transistor such as NOSRAM or DOSRAM (hereinafter also referred to as OS memory). Since the band gap of a metal oxide functioning as an oxide semiconductor is 2.5 eV or more, the OS transistor has a very small off-state current. For example, when the voltage between the source and drain is 3.5 V and the temperature is room temperature (25° C.), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 Therefore, the amount of charge leaked from the retention node of the OS memory via the OS transistor is extremely small. Therefore, the OS memory can function as a nonvolatile memory circuit, which enables power gating of the semiconductor device 10.

[0067] A semiconductor device in which transistors are integrated at high density may generate heat due to circuit operation. This heat increases the temperature of the transistor, which can change the characteristics of the transistor, resulting in a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so they are less likely to experience changes in field-effect mobility due to temperature changes and are less likely to experience a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, the use of OS transistors enables stable operation in high-temperature environments.

[0068] Metal oxides suitable for OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical properties, such as field-effect mobility, by adjusting the ratio of elements. Furthermore, the oxide containing indium and zinc may contain one or more elements selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0069] To improve the reliability and electrical characteristics of OS transistors, the metal oxide used in the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0070] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0071] CAC-OS has the function of both allowing electrons (or holes) to flow and preventing electrons from flowing. By separating the electron flow function from the electron blocking function, both functions can be maximized. In other words, using CAC-OS in the channel formation region of an OS transistor can achieve both a high on-state current and an extremely low off-state current.

[0072] Metal oxides have a wide band gap, which makes it difficult for electrons to be excited, and they have a large effective mass for holes. This means that OS transistors are less susceptible to avalanche breakdown and other problems than typical Si transistors. Therefore, for example, hot carrier degradation caused by avalanche breakdown can be suppressed. Suppressing hot carrier degradation allows OS transistors to be driven at a high drain voltage.

[0073] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, they are less susceptible to drain-induced barrier lowering (DIBL), a short-channel effect, compared to inversion-type transistors (typically, Si transistors) with pn junctions. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0074] Because OS transistors have high resistance to short-channel effects, their channel length can be reduced without degrading their reliability, allowing for increased circuit integration. As the channel length decreases, the drain electric field becomes stronger, but as mentioned above, OS transistors are less susceptible to avalanche breakdown than Si transistors.

[0075] Furthermore, because OS transistors have high resistance to short-channel effects, their gate insulating films can be thicker than those of Si transistors. For example, even for miniaturized transistors with channel lengths and widths of 50 nm or less, it may be possible to provide a gate insulating film as thick as about 10 nm. By increasing the gate insulating film thickness, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. Furthermore, by increasing the gate insulating film thickness, leakage current through the gate insulating film can be reduced, leading to a reduction in static current consumption.

[0076] As described above, the semiconductor device 10 can retain data even when the supply of power supply voltage is stopped by including the memory circuit 21, which is an OS memory. This enables power gating of the semiconductor device 10, thereby enabling a significant reduction in power consumption.

[0077] The data stored in the memory circuit 21 is data (weight data) corresponding to weight parameters used in product-sum operations of a neural network. By using digital weight data, the semiconductor device can be made noise-resistant and capable of high-speed operations. The weight data may also be analog data. Since NOSRAM can hold analog potentials, the data can be appropriately converted to digital data and used. The memory circuit 21, which can hold analog data, can hold weight data with a high number of bits without increasing the number of memory circuits.

[0078] The switching circuits 40_1 to 40_4 shown in the figure as an example of the switching circuit 40 have a function of selecting the potentials of the wirings LBL_1 to LBL_4 extending from the memory circuit units 20_1 to 20_4, respectively, and transmitting the selected potentials to the wiring GBL (also referred to as a global bit line). The wiring GBL is connected to the output terminals of the switching circuits 40_1 to 40_4. The switching circuits 40 need to prevent the output potentials of the selected switching circuit 40 and the unselected switching circuits 40 from being simultaneously supplied with each other, thereby preventing a through current from occurring. The switching circuit 40 can be, for example, a three-state buffer whose output potential state is controlled by a control signal. In this configuration example, the selected switching circuit buffers and outputs the input potential to the wiring GBL, and the outputs of the unselected switching circuits have high impedance, preventing the output potentials from being simultaneously supplied. Note that the switching circuit 40 is preferably configured with a Si transistor. This configuration allows for high-speed switching of the connection state.

[0079] The arithmetic circuits 30_1 to 30_4 shown in the figure as examples of the arithmetic circuit 30 have the function of repeatedly executing the same processing, such as a multiply-and-accumulate operation. The input data and weight data input for the multiply-and-accumulate operation in the arithmetic circuit 30 are preferably digital data. Digital data is less susceptible to noise. Therefore, the arithmetic circuit 30 is suitable for performing arithmetic processing that requires highly accurate calculation results. The arithmetic circuit 30 is preferably composed of Si transistors. This configuration allows the arithmetic circuit 30 to be stacked with OS transistors.

[0080] The arithmetic circuits 30_1 to 30_4 are supplied with weight data held in the memory circuit 21 via wirings LBL_1 to LBL_4 and wiring GBL. Furthermore, the arithmetic circuits 30_1 to 30_4 are supplied with input data (A1, A2, A3, A4) input from the outside. The arithmetic circuits 30_1 to 30_4 perform product-sum arithmetic processing using the weight data held in the memory circuit 21 and the input data input from the outside.

[0081] The weight data provided to the arithmetic circuits 30_1 to 30_4 is weight data selected by the plurality of memory circuit units 20_1 to 20_4, switched by the switching circuits 40_1 to 40_4, and provided via the wiring GBL. That is, the arithmetic circuits 30_1 to 30_4 can perform arithmetic processing using the same weight data, such as a product-sum operation. Therefore, the semiconductor device 10 according to one embodiment of the present invention can efficiently perform processing using the same weight data, such as a convolutional neural network.

[0082] Furthermore, the weight data provided to the arithmetic circuits 30_1 to 30_4 can be provided to the wiring GBL by switching data previously provided to the wirings LBL_1 to LBL_4 using the switching circuits 40_1 to 40_4, so that the weight data provided to the wiring GBL can be switched at a speed corresponding to the electrical characteristics of Si transistors. Therefore, even if it takes a long time to read the weight data from the memory circuit portions 20_1 to 20_4 to the wirings LBL_1 to LBL_4, by reading the weight data to the wirings LBL_1 to LBL_4 in advance, the weight data can be switched at high speed for arithmetic processing.

[0083] The wiring LBL extending from the memory circuit unit 20 to the switching circuit 40 is connected to the weight data W data This is the wiring for transmitting the weight data W from the layer 12 to the wiring LBL. data In order to read the data at high speed, it is preferable to shorten the wiring LBL. Also, it is preferable to shorten the wiring LBL in order to reduce the energy consumption associated with charging and discharging. In other words, it is preferable to dispose the switching circuits 40 in a dispersed manner in the xy plane of the layer 11 so as to be close to the wiring LBL (indicated by the arrows extending in the z direction in the drawing) that extend in the z direction.

[0084] The arithmetic circuits 30_1 to 30_4 are configured to be provided for each of the wirings LBL_1 to LBL_4, which are read bit lines of the memory circuit 21, i.e., for each column (column-parallel calculation). This configuration allows parallel calculations of data for the number of columns of wiring LBL. Compared to multiply-and-accumulate operations using a CPU or GPU, column-parallel calculation is not limited by the data bus size (e.g., 32 bits). This significantly increases the parallelism of calculations, thereby improving the efficiency of massive calculations, such as deep neural network learning (AI technology) and scientific and engineering calculations using floating-point arithmetic. Furthermore, because the calculations of data output from the arithmetic circuit 30 can be completed and read, the power consumed by memory access (e.g., data transfer between the arithmetic circuit and memory) can be reduced, suppressing increases in heat generation and power consumption. Furthermore, by shortening the physical distance between the arithmetic circuit 30 and the memory circuit section 20, for example by stacking the layers, the wiring distance can be shortened, thereby reducing the parasitic capacitance generated in the signal lines and enabling lower power consumption.

[0085] 6A, a block diagram including a semiconductor device 10 functioning as an AI accelerator, a CPU 110, and a bus 120 will be described. The CPU 110 and the bus 120 correspond to those shown in the previous embodiment.

[0086] 6A illustrates the semiconductor device 10 described in FIGS. 5A and 5B, as well as a CPU 110 and a bus 120. The CPU 110 has a CPU core 200 and a backup circuit 222. The semiconductor device 10 functioning as an accelerator illustrates a drive circuit 50, memory circuit units 20_1 to 20_N (N is a natural number of 2 or more), a memory circuit 21, a switching circuit 40, and arithmetic circuits 30_1 to 30_N.

[0087] The CPU 110 has the function of performing general-purpose processing such as running an operating system, controlling data, performing various calculations, and running programs. The CPU 110 has a CPU core 200. The CPU core 200 corresponds to one or more CPU cores. The CPU 110 also has a backup circuit 222 that can retain data in the CPU core 200 even if the supply of power voltage is stopped. The supply of power voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power voltage is sometimes called a drive voltage. An OS memory having an OS transistor, for example, is suitable as the backup circuit 222.

[0088] The backup circuit 222, which is configured with OS transistors, can be stacked on the CPU core 200, which can be configured with Si transistors. Because the area of ​​the backup circuit 222 is smaller than the area of ​​the CPU core 200, the backup circuit 222 can be placed on the CPU core 200 without increasing the circuit area. The backup circuit 222 has a function of retaining data in the registers of the CPU core 200. The backup circuit 222 is also referred to as a data retention circuit. Details of the configuration of the CPU core 200 equipped with the backup circuit 222 having OS transistors will also be described in the fifth embodiment.

[0089] The memory circuit units 20_1 to 20_N respectively store weight data W1 to W2 held in the memory circuit 21. N The switching circuit 40 outputs the selected weight data to the weight data W via a line LBL (not shown). SEL The driving circuit 50 outputs the input data A1 to A2 to the arithmetic circuits 30_1 to 30_N via the input data lines. N Output.

[0090] The driving circuit 50 has a function of outputting a signal for controlling the writing and reading of weight data in the memory circuit units 20_1 to 20_N. The driving circuit 50 also has a function of providing input data to the arithmetic circuits 30_1 to 30_N to cause them to execute product-sum operations of the neural network, and a function of holding output data obtained by the product-sum operations of the neural network.

[0091] The bus 120 electrically connects the CPU 110 and the semiconductor device 10. That is, the CPU 110 and the semiconductor device 10 can transmit data via the bus 120.

[0092] FIG. 6B is a diagram for explaining the positional relationship of each component in the semiconductor device 10 shown in FIG. 6A when N is 6.

[0093] The memory circuit units 20_1 to 20_6, which are configured with OS transistors, and the arithmetic circuits 30_1 to 30_6 are electrically connected via wirings LBL_1 to LBL_6 extending in a direction substantially perpendicular to the surface of the substrate on which the drive circuit 50, the switching circuit 40, and the arithmetic circuits 30_1 to 30_6 are provided. Note that "substantially perpendicular" refers to a state in which the wirings are arranged at an angle of 85 degrees or more and 95 degrees or less. Note that in this specification, the X, Y, and Z directions illustrated in Figure 6B and other figures are orthogonal or intersect with each other. Furthermore, the X and Y directions are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0094] Each of the memory circuit units 20_1 to 20_6 includes a memory circuit 21. The memory circuit units 20_1 to 20_6 may be referred to as device memories or shared memories. The memory circuit 21 includes a transistor 22. The semiconductor layer 23 of the transistor 22 may be an oxide semiconductor (metal oxide), thereby forming the memory circuit 21 using the OS transistor described above.

[0095] The memory circuits 21 included in the memory circuit portions 20_1 to 20_6 are connected to wirings LBL_1 to LBL_6, respectively. The wirings LBL_1 to LBL_6 are connected to the switching circuit 40 via wirings extending in the z-direction. The switching circuit 40 is configured to amplify the potential of any one of the wirings LBL_1 to LBL_6 and transmit the amplified potential to the wiring GBL. With this configuration, the weight data to be provided to the wiring GBL can be switched at high speed by controlling the switching circuit 40.

[0096] The arithmetic circuits 30_1 to 30_6 receive weight data input via the wiring GBL and input data A given from the driving circuit 50 via the input data line. IN and performs calculations based on the weight data. Since the memory circuit units 20_1 to 20_6 that hold the weight data can be arranged in the upper layer, the calculation circuits 30_1 to 30_6 can be arranged efficiently. Therefore, the input data lines extending from the drive circuit 50 can be shortened, and the semiconductor device 10 can achieve low power consumption and high speed.

[0097] Next, the advantages of the configuration of FIG. 6B will be described. For the sake of explanation, FIG. 7A shows each configuration of FIG. 6B in a block diagram. Note that the following description will be given assuming that weight data W1 to W6 are read out to wirings LBL_1 to LBL_6 from memory circuits 21 in six memory circuit units 20_1 to 20_6. The switching circuit 40 will be described as switching circuits 40_1 to 40_6 connected to wirings LBL_1 to LBL_6. The weight data selected from the weight data W1 to W6 by the switching circuit 40 and provided to wirings GBL will be weight data W1 to W6. SEL The following description will be given assuming that input data A1 to A6 are given to the arithmetic circuits 30_1 to 30_6, respectively, and output data MAC1 to MAC6 are obtained.

[0098] The wiring LBL_1 to LBL_6 extends vertically and connects the upper and lower layers. Pare shorter than the wires extending in the horizontal direction. Therefore, the parasitic capacitance of the wires LBL_1 to LBL_6 can be reduced, the charge required for charging and discharging the wires can be reduced, and power consumption can be reduced and calculation efficiency can be improved. In addition, reading from the memory circuit 21 to the wires LBL_1 to LBL_6 can be performed at high speed.

[0099] The arithmetic circuits 30_1 to 30_6 can perform arithmetic processing using the same weight data via the wiring GBL. This configuration is suitable for arithmetic processing of a convolutional neural network that performs arithmetic processing using the same weight data.

[0100] 7B shows an example of a circuit configuration applicable to the switching circuit 40 shown in FIG. 7A. The three-state buffer shown in FIG. 7B has a function of amplifying and transmitting the potential of the line LBL to the line GBL in response to a control signal EN. The switching circuit 40 can be considered as a multiplexer. It has a function of selecting one of multiple input signals.

[0101] 8 shows a timing chart for explaining the operation of the configuration described in FIG. 7A. The semiconductor device 10 performs arithmetic processing in response to the toggle operation of the clock signal CLK (for example, times T1 to T7). By configuring the clock signal CLK to have a higher frequency, it is possible to speed up the arithmetic processing.

[0102] When the input data A1 to A6 are switched at high speed to A1a to A111, A2a to A211, A3a to A311, A4a to A411, A5a to A511, and A6a to A611, respectively, as shown in the figure, in response to the clock signal CLK, the data of the wiring GBL that provides the weight data must be switched at high speed.

[0103] In one embodiment of the present invention, weight data selected from the wiring LBL to the wiring GBL by the switching circuit 40 is read in advance onto the wirings LBL_1 to LBL_6, thereby enabling high-speed switching of data on the wiring GBL to which weight data is applied. For example, weight data W1 can be read onto the wiring LBL_1 at time T1, and the switching circuit 40 can be switched at time T6 to output the weight data W1 from the wiring LBL_1 to the wiring GBL. From time T2 to T7 and after time T7, the weight data can be read onto the wiring LBL at different times from the weight data selected on the wiring GBL, thereby enabling switching of the weight data in response to the clock signal CLK.

[0104] FIG. 9A shows a specific example of the configuration of an arithmetic circuit. FIG. 9A illustrates an example of the configuration of an arithmetic circuit 30 that can perform a product-sum operation on input data of 8-bit weight data. FIG. 9A also illustrates a multiplication circuit 24, an addition circuit 25, and a register 26. The 16-bit data multiplied by the multiplication circuit 24 is input to the addition circuit 25. The output of the addition circuit 25 is held in the register 26, and is added to the data multiplied by the multiplication circuit 24 in the addition circuit 25 to perform a product-sum operation. The register is controlled by a clock signal CLK and a reset signal reset_B. Note that the "α" in "17+α" in the figure indicates a carry that occurs when the multiplied data is added. With this configuration, the weight data W SEL and input data A IN It is possible to obtain output data MAC corresponding to the sum-of-products operation with

[0105] 9A illustrates a configuration in which arithmetic processing is performed using 8-bit data, but one embodiment of the present invention can also be applied to a configuration in which 1-bit data is used. This configuration is illustrated in FIG. 9B, similar to FIG. 9A. In the case of 1-bit data, arithmetic processing according to the number of bits can be performed, as illustrated in FIG. 9B.

[0106] 10A is a diagram illustrating an example of a circuit configuration applicable to the memory circuit unit 20 of the semiconductor device 10 of the present invention. Fig. 10A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wirings LBL_1 to LBL_N, which are arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or greater). Also illustrated is a memory circuit 21 connected to each word line and bit line.

[0107] 10B is a diagram illustrating an example of a circuit configuration applicable to the memory circuit 21. The memory circuit 21 includes a transistor 61, a transistor 62, a transistor 63, and a capacitor 64 (also referred to as a capacitor).

[0108] One of the source or drain of the transistor 61 is connected to the write bit line WBL. The gate of the transistor 61 is connected to the write word line WWL. The other of the source or drain of the transistor 61 is connected to one electrode of the capacitance element 64 and the gate of the transistor 62. One of the source or drain of the transistor 62 and the other electrode of the capacitance element 64 are connected to a wiring that applies a fixed potential, such as a ground potential. The other of the source or drain of the transistor 62 is connected to one of the source or drain of the transistor 63. The gate of the transistor 63 is connected to the read word line RWL. The other of the source or drain of the transistor 63 is connected to a wiring LBL. The wiring LBL is connected to a wiring GBL via the switching circuit 40. As described above, the wiring LBL is connected to the switching circuit 40 via a wiring that is provided so as to extend in a direction substantially perpendicular to the surface of the substrate on which the arithmetic circuit 30 is provided.

[0109] The circuit configuration of the memory circuit 21 shown in FIG. 10B corresponds to a three-transistor (3T) gain cell NOSRAM. Transistors 61 to 63 are OS transistors. In an OS transistor, the current flowing between the source and drain in the off state, i.e., the leakage current, is extremely small. NOSRAM can be used as a nonvolatile memory by utilizing its extremely small leakage current characteristic to retain charge corresponding to data within the memory circuit.

[0110] The circuit configuration applicable to the memory circuit 21 of FIG. 10A is not limited to the 3T NOSRAM of FIG. 10B. For example, a circuit equivalent to the DOSRAM illustrated in FIG. 11A may also be used. FIG. 11A illustrates a memory circuit 21A having a transistor 61A and a capacitive element 64A. The transistor 61A is an OS transistor. The memory circuit 21A is illustrated as being connected to a bit line BL, a word line WL, and a back gate line BGL.

[0111] A circuit configuration applicable to the memory circuit 21 of FIG. 10A may be a circuit equivalent to a 2T-type NOSRAM illustrated in FIG. 11B. FIG. 11B illustrates the memory circuit 21B including a transistor 61B, a transistor 62B, and a capacitor 64B. The transistors 61B and 62B are OS transistors. The transistors 61B and 62B may be OS transistors whose semiconductor layers are arranged in different layers or may be OS transistors whose semiconductor layers are arranged in the same layer. The memory circuit 21B is illustrated as being connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, a source line SL, and a back gate line BGL.

[0112] A circuit configuration applicable to the memory circuit 21 of FIG. 10A may be a circuit combining 3T-type NOSRAMs as shown in FIG. 11C. FIG. 11C illustrates a memory circuit 21C including a memory circuit 21_P and a memory circuit 21_N, each capable of holding data of different logic levels. FIG. 11C illustrates a memory circuit 21_P including a transistor 61_P, a transistor 62_P, a transistor 63_P, and a capacitor 64_P, and a memory circuit 21_N including a transistor 61_N, a transistor 62_N, a transistor 63_N, and a capacitor 64_N. Each transistor included in the memory circuit 21_P and the memory circuit 21_N is an OS transistor. Each transistor included in the memory circuit 21_P and the memory circuit 21_N may be an OS transistor having semiconductor layers arranged in different layers or an OS transistor having semiconductor layers arranged in the same layer. The memory circuit 21C is shown as being connected to a write bit line WBL_P, a wiring LBL_P, a write bit line WBL_N, a wiring LBL_N, a write word line WWL, and a read word line RWL. The memory circuit 21C can hold data of different logics, read the data of different logics to the wiring LBL_P and the wiring LBL_N, and output the data to the wiring GBL_P and the wiring GBL_N via the switching circuit 40, as in FIG. 7 etc.

[0113] 11C, an exclusive OR circuit (XOR circuit) may be provided so that data equivalent to the multiplication of data held in the memory circuit 21_P and the memory circuit 21_N is output to the wiring LBL. This configuration can omit the operation equivalent to the multiplication in the arithmetic circuit 30, thereby achieving low power consumption.

[0114] FIG. 12 illustrates the flow of computational processing in a convolutional neural network. FIG. 12 illustrates an input layer 90A, an intermediate layer 90B (also referred to as a hidden layer), and an output layer 90C. The input layer 90A illustrates input data input processing 91 (indicated as “Input” in the figure). The intermediate layer 90B illustrates convolutional computations 92, 93, and 95 (indicated as “Conv.” in the figure) and multiple pooling computations 94 and 96 (indicated as “Pool.” in the figure). The output layer 90C illustrates a fully connected computation 97 (indicated as “Full” in the figure). The computational processing flow in the input layer 90A, intermediate layer 90B, and output layer 90C is merely an example; in actual computational processing in a convolutional neural network, other computations such as softmax computation may be performed.

[0115] 12, the convolutional neural network performs convolution operations 92, 93, and 95 multiple times as shown in FIG. 12. In the convolution operations, the same weight data is used for the operations. Therefore, by applying the configuration of one embodiment of the present invention that performs the operations using the same weight data, it is possible to achieve both high operating speed and low power consumption.

[0116] As described in the above embodiment, the fully coupled arithmetic processing 97 is preferably performed using the analog arithmetic unit 102 and the oxide semiconductor memory 104. The analog arithmetic unit 102 and the oxide semiconductor memory 104 can be operated in a subthreshold region, thereby achieving low power consumption.

[0117] Next, a detailed block diagram of the semiconductor device 10 is shown in FIG.

[0118] Figure 13 illustrates an example configuration of the drive circuit 50 illustrated in Figures 6A and 6B, in addition to the configurations corresponding to the memory circuit section 20, memory circuit 21, arithmetic circuit 30, switching circuit 40, layer 11, and layer 12 described in Figures 5A and 5B, and Figures 6A and 6B.

[0119] FIG. 13 illustrates a controller 71, a row decoder 72, a word line driver 73, a column decoder 74, a write driver 75, a precharge circuit 76, an input / output buffer 81, and an arithmetic control circuit 82 as components corresponding to the drive circuit 50 described in FIGS. 6A and 6B.

[0120] Fig. 14A is a diagram illustrating blocks that control the memory circuit unit 20 for each configuration illustrated in Fig. 13. Fig. 14A illustrates a controller 71, a row decoder 72, a word line driver 73, a column decoder 74, a write driver 75, and a precharge circuit 76.

[0121] The controller 71 processes externally input signals to generate control signals for the row decoder 72 and the column decoder 74. The externally input signals are control signals such as a write enable signal and a read enable signal for controlling the memory circuit unit 20. The controller 71 also inputs and outputs data between the CPU 110 and the semiconductor device 10 via a bus 120.

[0122] The row decoder 72 generates signals for driving the word line driver 73. The word line driver 73 generates signals to be provided to the write word lines WWL and the read word lines RWL. The column decoder 74 generates signals for driving the write driver 75. The write driver 75 generates weight data to be provided to the memory circuit 21. The precharge circuit 76 has the function of precharging the lines LBL and the like. A signal corresponding to the weight data read from the memory circuit 21 of the memory circuit unit 20 is input to the switching circuit 40 via the lines LBL, as described with reference to Figures 6A and 6B, etc.

[0123] FIG. 14B is a diagram illustrating blocks that control the arithmetic circuit 30 and the switching circuit 40 in each configuration shown in FIG.

[0124] The controller 71 processes an input signal from the outside and generates a control signal for the arithmetic control circuit 82. The controller 71 also generates various signals such as an address signal and a clock signal for controlling the arithmetic circuit 30. The arithmetic control circuit 82 processes input data A1 to A2 given to the data input lines in accordance with the control of the controller 71 and the output of the input / output buffer 81. N The arithmetic control circuit 82 outputs a control signal for controlling the switching circuit 40. As described with reference to Figures 6A and 6B, the switching circuit 40 supplies one of the weight data supplied from the plurality of wirings LBL to the plurality of arithmetic circuits 30 via the wiring GBL. The arithmetic circuit 30 generates output data MAC according to the product-sum operation by switching the supplied weight data and input data. The generated output data MAC is temporarily stored as intermediate data in a memory such as an SRAM or a register in the arithmetic control circuit 82 via the input / output buffer 81. The stored intermediate data is re-input to the arithmetic circuit 30.

[0125] Note that it is preferable to use a plurality of semiconductor devices 10 in combination to enable parallel calculation with an increased number of parallel operations, in accordance with an embodiment of the present invention. An example of such a configuration will be described with reference to FIGS. 15A and 15B.

[0126] 15A illustrates a configuration corresponding to the semiconductor device 10 described above, in which semiconductor devices 10_1 to 10_n (n is a number equal to or greater than 2) and a controller 71G that controls and inputs / outputs data between the semiconductor devices 10_1 to 10_n. The controller 71G has an internal memory circuit 60 such as an SRAM. The controller 71G stores output data MAC obtained from the plurality of semiconductor devices 10_1 to 10_n in the memory circuit 60. The output data MAC stored in the memory circuit 60 is then used as input data A in the plurality of semiconductor devices 10_1 to 10_n. IN With this configuration, parallel calculation with an increased number of parallel operations can be performed using a plurality of semiconductor devices.

[0127] 15B, which is a different configuration example from that of FIG. 15A, a controller 71G performs another arithmetic process on the output data held in the memory circuit 60, and outputs the resultant input data as input data A to the plurality of semiconductor devices 10_1 to 10_n. IN _1 to A IN _n as the output. In this configuration, for example, the controller 71G is configured to perform arithmetic processing based on an activation function, pooling processing, normalization processing, etc. on the output data stored in the memory circuit 60. With this configuration, in addition to parallel calculation with an increased number of parallel operations using multiple semiconductor devices, arithmetic processing other than convolution processing can be efficiently performed.

[0128] In the semiconductor device 10, output data MAC corresponding to the calculation result of the arithmetic circuit 30 is input as intermediate data to the arithmetic control circuit 82 using the buffer memory in the input / output buffer 81. The arithmetic control circuit 82 can output this intermediate data again as input data to the arithmetic circuit 30. Therefore, arithmetic processing can be performed without reading data during calculation into a main memory or the like external to the semiconductor device 10. Furthermore, in the semiconductor device 10, electrical connection between the memory circuit unit and the arithmetic circuit can be made via wiring in an opening provided in an insulating film or the like, so the number of parallel connections can be increased by increasing the number of wirings. Therefore, the semiconductor device 10 can perform parallel calculations with a number of bits greater than the data bus width of the CPU 110. Furthermore, the number of times a huge amount of weight data needs to be transferred to and from the CPU 110 can be reduced, thereby achieving low power consumption.

[0129] As described above, one embodiment of the present invention can provide a miniaturized semiconductor device that functions as an accelerator. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator with improved arithmetic processing speed. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator with improved arithmetic accuracy. Alternatively, one embodiment of the present invention can provide a semiconductor device that functions as an accelerator with reduced power consumption. Alternatively, a semiconductor device that functions as an accelerator with a novel structure can be provided.

[0130] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0131] (Embodiment 3) In this embodiment, a part of the structure, operation, and the like of the semiconductor device 100 described in the previous embodiment will be described. The semiconductor device described in this embodiment is part of the semiconductor device 100 and includes the analog computing unit 102 and the oxide semiconductor memory 104 described in the previous embodiment.

[0132] <Configuration example> 16A and 16B show a configuration example of a multiplication cell, which is a semiconductor device according to one embodiment of the present invention. As an example, the multiplication cell is configured to perform multiplication using the translinear principle. As an example, the multiplication cell has a function of retaining first data and, when second data is input to the multiplication cell, a function of outputting the product of the first data and the second data. Here, the first data corresponds to weight data W2 shown in FIG. 1B, and the second data corresponds to input data A2 shown in FIG. 1B.

[0133] 16A includes transistors M1 to M10, a capacitor C1, and a capacitor CG. The circuit MC can be functionally divided into a circuit MC1 including transistors M5 to M10 and a circuit MC2 including transistors M1 to M4 and the capacitor C1. Here, the circuit MC1 corresponds to the analog computing unit 102 described in the above embodiment, and the circuit MC2 corresponds to the oxide semiconductor memory 104 described in the above embodiment.

[0134] The circuits MC1 and MC2 can be provided in the same layer as the analog computing unit 102 and the oxide semiconductor memory 104 shown in Figures 2A and 2B. In Figures 2A and 2B, the area of ​​the analog computing unit 102 and the area of ​​the oxide semiconductor memory 104 are shown as separate areas, but this is not limiting, and a circuit MC that combines the circuits MC1 and MC2 may be provided in an array.

[0135] When the circuits MC are provided in an array, as shown in FIG. 16B , the circuit MC1 may be provided in a layer MCL1 having transistors in the xy plane, and the circuit MC2 may be provided in a layer MCL2 having transistors in the xy plane. The layers MCL1 and MCL2 include transistors having an oxide semiconductor in a channel formation region (OS transistors). The layers MCL1 and MCL2 are provided in different layers in a direction substantially perpendicular to the xy plane (the z direction in FIG. 16B ). This configuration can shorten the wiring that transmits the weight data W2 from the circuit MC2 to the circuit MC1, as shown in FIG. 16B . This can increase the speed of reading the weight data W2 and reduce the power consumption associated with reading the weight data W2.

[0136] The transistors M1 to M10 may be, for example, OS transistors. In particular, the metal oxide contained in the channel formation region of an OS transistor is preferably, for example, an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). Alternatively, the transistors M1 to M10 may be, for example, a transistor having silicon in the channel formation region (a Si transistor). The silicon may be, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or the like. In addition, examples of transistors that can be used other than OS transistors and Si transistors include transistors that contain Ge or the like in the channel formation region, transistors that contain compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe in the channel formation region, transistors that contain carbon nanotubes in the channel formation region, and transistors that contain organic semiconductors in the channel formation region.

[0137] Unless otherwise specified, the transistors M1, M3, and M4 may function as switching elements, for example. That is, the transistors M1, M3, and M4 may function as switching elements when their gates, sources, and drains are appropriately supplied with voltages within a range in which the transistors operate as switching elements. However, one embodiment of the present invention is not limited thereto. For example, at least one of the transistors M1, M3, and M4 may operate in a saturation region or a linear region when on. Alternatively, at least one of the transistors M1, M3, and M4 may operate in a subthreshold region to reduce the amount of current flowing through the transistors. Alternatively, at least one of the transistors M1, M3, and M4 may operate in a linear region, a saturation region, and a subthreshold region. Alternatively, at least one of the transistors M1, M3, and M4 may operate in a linear region and a saturation region, or may operate in a saturation region and a subthreshold region, or may operate in a linear region and a subthreshold region.

[0138] In this specification, the saturation region refers to a region where the gate-source voltage is greater than the threshold voltage and the difference between the gate-source voltage and the threshold voltage is greater than the source-drain voltage. Alternatively, the saturation region refers to a region where the drain current of a transistor remains almost unchanged even when the source-drain voltage is changed. Alternatively, the saturation region refers to a region where the drain current is proportional to the square of the gate-source voltage. Alternatively, the saturation region includes regions that can be considered as the regions described above.

[0139] In this specification, the linear region refers to a region in which the gate-source voltage is greater than the threshold voltage and the difference between the gate-source voltage and the threshold voltage is smaller than the source-drain voltage. Alternatively, the linear region refers to a region in which the channel-forming region acts as a resistor and the drain current of the transistor changes linearly with changes in the source-drain voltage. Alternatively, the linear region includes regions that can be considered as the regions described above.

[0140] In this specification and elsewhere, the term "subthreshold region" refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the term "subthreshold region" refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the term "subthreshold region" refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the term "subthreshold region" refers to the region that can be considered as each of the regions described above.

[0141] The drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with gate voltage, regardless of drain voltage. Circuit operation using the subthreshold current can reduce the effect of drain voltage variations.

[0142] The OS transistor is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 The OS transistor has a drain current per 1 μm of channel width of less than 1.0 × 10 -8 A or less, 1.0×10 -12 A or less, or 1.0 x 10 -15A or less per 1 μm of channel width flows. In other words, OS transistors can operate in the subthreshold region with a wide range of gate voltages. Specifically, the threshold voltage of an OS transistor can be set to V th In the subthreshold region, V th -1.0V or more V th Below, or V th -0.5V or more V th The circuit can operate using gate voltages in the following voltage ranges:

[0143] On the other hand, Si transistors have a large off-state current and operate in a narrow range of gate voltages in the subthreshold region. When using subthreshold current, OS transistors can operate in a wider range of gate voltages than Si transistors. By operating OS transistors in the subthreshold region, where the current is small, the power consumption of the circuit MC can be reduced.

[0144] In this specification and the like, the off region of a transistor refers to a region in which the gate-source voltage is lower than the voltage in the subthreshold region. When the gate-source voltage of a transistor is in the off region, the transistor is in an off state. In this specification and the like, the current that flows when a transistor is in an off state is referred to as an off current or a leakage current.

[0145] Furthermore, unless otherwise specified, each of the transistors M2 and M5 to M10 may operate in the subthreshold region.

[0146] The first terminal of the transistor M1 is electrically connected to the wiring VDE, the second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M2, and the gate of the transistor M1 is electrically connected to the wiring WWLB and the first terminal of the capacitor CG. The first terminal of the transistor M3 is electrically connected to the wiring WDL, and the second terminal of the transistor M3 is electrically connected to the gate of the transistor M2, the second terminal of the capacitor CG, and the first terminal of the capacitor C1. The second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M4, the second terminal of the capacitor C1, the gate of the transistor M5, the first terminal of the transistor M7, and the gate of the transistor M8. The second terminal of the transistor M4 is electrically connected to the wiring VGE, and the gate of the transistor M4 is electrically connected to the wiring WWL. The first terminal of the transistor M5 is electrically connected to the wiring VDE, and the second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M6 and the gate of the transistor M7. The gate of the transistor M6 is electrically connected to the wiring XDL, and the second terminal of the transistor M6 is electrically connected to the wiring VGE. The second terminal of the transistor M7 is electrically connected to the wiring VGE. The first terminal of the transistor M8 is electrically connected to the wiring VDE, and the second terminal of the transistor M8 is electrically connected to the first terminal of the transistor M9 and the gate of the transistor M10. The gate of the transistor M9 is electrically connected to the wiring BDL, and the second terminal of the transistor M9 is electrically connected to the wiring VGE. The first terminal of the transistor M10 is electrically connected to the wiring OL, and the second terminal of the transistor M10 is electrically connected to the wiring VGE.

[0147] The wiring VDE functions as a wiring that applies a constant voltage, for example, a high power supply voltage.

[0148] The wiring VGE functions as a wiring that applies a constant voltage, for example, a low power supply voltage, a ground potential, or the like.

[0149] For example, the wiring WWL functions as a write signal line for writing first data to the circuit MC.

[0150] For example, the line WWLB functions as a line that transmits an inverted signal of the write signal transmitted to the line WWL. Note that the line WWLB may be a line that supplies a variable potential (for example, a high-level potential, a low-level potential, etc.) instead of the inverted signal.

[0151] For example, the wiring WDL functions as a write data line for writing a voltage corresponding to the first data into the circuit MC.

[0152] The wiring XDL functions as, for example, a signal line for inputting a voltage according to the second data to the circuit MC.

[0153] Therefore, the transistor M6, whose gate is electrically connected to the wiring XDL, functions as a current source. As described above, the transistor M6 may operate in the subthreshold region, and therefore a current in the subthreshold region flows between the first terminal and the second terminal of the transistor M6.

[0154] The wiring BDL functions, for example, as a signal line for inputting a voltage to the circuit MC for adjusting the amount of current according to the result of the operation between the first data and the second data.

[0155] Therefore, the transistor M9, whose gate is electrically connected to the wiring BDL, functions as a current source. As described above, the transistor M9 may operate in the subthreshold region, and therefore a current in the subthreshold region flows between the first terminal and the second terminal of the transistor M9.

[0156] The amount of current flowing through the transistor M9 can be, for example, a variable or constant applied to a circuit that performs an operation according to a function system included in a circuit ACTV, which will be described later.

[0157] For example, the wiring OL functions as a wiring for outputting a current according to the product of the first data and the second data.

[0158] <Example of operation> Next, an example of the operation of the circuit MC in Fig. 16A will be described. In this example of operation, the potential applied by the wiring VDE is set to a high power supply potential, and the potential applied by the wiring VGE is set to a ground potential (V GND )

[0159] <<Write operation>> First, an example of the operation of writing first data to the circuit MC will be described.

[0160] A high-level potential is input to the wiring WWL, and the high-level potential is input to the gates of the transistors M3 and M4, turning the transistors M3 and M4 on.

[0161] At this time, the line VGE and the second terminal of the capacitor C1 (the second terminal of the transistor M2) are in a conductive state via the transistor M4, so the potential of the second terminal of the capacitor C1 (the second terminal of the transistor M2) is V GND This becomes:

[0162] At this time, the line WDL and the first terminal of the capacitor C1 (the second terminal of the capacitor CG, the gate of the transistor M2, etc.) are electrically connected via the transistor M3. Here, a signal (hereinafter, a voltage V W ) is transmitted, a voltage V corresponding to the first data is applied to the first terminal of the capacitor C1 (the second terminal of the capacitor CG, the gate of the transistor M2, etc.). W is written.

[0163] Furthermore, an inverted signal of the signal transmitted to the line WWL is input to the line WWLB. Specifically, a low-level potential is input to the line WWLB. Therefore, the low-level potential is applied to the gate of the transistor M1 (the first terminal of the capacitor CG). This turns the transistor M1 into an off state.

[0164] The first terminal of the capacitor C1 (the second terminal of the capacitor CG, the gate of the transistor M2, etc.) has a voltage V W After writing, a low-level potential is input to the wiring WWL. As a result, the low-level potential is input to the gates of the transistors M3 and M4, turning the transistors M3 and M4 off. This also causes the first terminal of the capacitor C1 to be in a floating state, so that the voltage V between the first terminal and the second terminal of the capacitor C1 W -V GND is maintained.

[0165] Strictly speaking, when the potential applied to the gate of the transistor M3 changes from a high-level potential to a low-level potential, the parasitic capacitance between the gate and the second terminal of the transistor M3 reduces the voltage V written to the first terminal of the capacitor C1. W In this specification, for convenience, the voltage V W The voltage stepped down from the voltage V can also be considered to be a voltage according to the first data. WA capacitor CG is provided to prevent a voltage drop. When the potential applied to the gate of transistor M3 changes from a high level potential to a low level potential, that is, when the potential applied by the wiring WWL changes from a high level potential to a low level potential, an inverted signal of the signal transmitted to the wiring WWL is input to the wiring WWLB, and the potential of the wiring WWLB changes from a low level potential to a high level potential. At this time, the potential of the first terminal of the capacitor CG increases from a low level potential to a high level potential, and therefore the potential of the second terminal of the capacitor CG (the first terminal of the capacitor C1, the gate of transistor M2, etc.) is boosted by the capacitive coupling of the capacitor CG, ideally by the potential difference between the high level potential and the low level potential. Here, the boosted potential difference is calculated by multiplying the voltage V due to the parasitic capacitance between the gate and second terminal of transistor M3 by W By making the voltage difference equal to the voltage drop, the voltage V when transistor M3 is turned off W The configuration of the capacitor CG for equalizing the potential difference increased by the capacitive coupling of the capacitor CG with the potential difference decreased by the parasitic capacitance between the gate and the second terminal of the transistor M3 will be described later.

[0166] Alternatively, a low-level potential may be supplied to the wiring WWLB instead of an inverted signal of the signal transmitted to the wiring WWL to turn off the transistor M1, thereby simultaneously storing the first data in the circuit MC and stopping the supply of the high power supply potential to the first terminal of the transistor M2.

[0167] <<Multiplication operation>> Next, an example of the multiplication operation of the first data and the second data in the circuit MC will be described.

[0168] When a high-level potential is input to the wiring WWLB, the transistor M1 is turned on, and a high power supply potential is input to the first terminal of the transistor M2, and a current corresponding to the voltage between the gate and second terminal of the transistor M2 flows between the first and second terminals of the transistor M2. WWhen the transistor M2 operates in the subthreshold region, I W is the amount of current in the current range in the subthreshold region.

[0169] Furthermore, the current flowing between the first terminal and the second terminal of the transistor M2 flows to the wiring VGE via the transistor M7. Here, assuming that the transistor M7 also operates in the subthreshold region, a current of I W At this time, the current I W can be expressed by the following formula:

[0170]

number

[0171] In addition, V M7gs is the voltage between the gate and the second terminal of the transistor M7. M7gs is 0, and is determined by the threshold voltage of the transistor M7, temperature, device structure, etc. J is a correction coefficient determined by the temperature, device structure, etc.

[0172] In addition, a voltage corresponding to the second data is applied to the wiring XDL. X At this time, the voltage between the gate and second terminal of transistor M6 is V X -V GND and V is applied between the first and second terminals of the transistor M6. X -V GND Here, the amount of current flowing between the first terminal and the second terminal of the transistor M6 is I X When the transistor M6 operates in the subthreshold region, I X is the amount of current in the current range in the subthreshold region.

[0173] In addition, the current flowing between the first and second terminals of the transistor M6 is a current flowing from the wiring VDE to the first terminal of the transistor M6 via the transistor M5. Here, assuming that the transistor M5 also operates in the subthreshold region, a current of I X At this time, the current I X can be expressed by the following formula:

[0174]

number

[0175] In addition, V M5gs is the voltage between the gate and the second terminal of the transistor M5. M5gs is 0, and is determined by the threshold voltage of transistor M5, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.2) are assumed to be equal to I0 and J used in equation (1.1), respectively.

[0176] Also, V is connected to the wire BDL as a voltage to adjust the output current. B At this time, the voltage between the gate and second terminal of transistor M9 is V B -V GND and V is applied between the first and second terminals of the transistor M9. B -V GND In addition, the amount of current flowing between the first and second terminals of the transistor M9 is I B When the transistor M9 operates in the subthreshold region, I B is the amount of current in the current range in the subthreshold region.

[0177] Furthermore, the current flowing between the first and second terminals of the transistor M9 is a current flowing from the wiring VDE to the first terminal of the transistor M9 via the transistor M8. Here, assuming that the transistor M8 also operates in the subthreshold region, a current of I B At this time, the current I B can be expressed by the following formula:

[0178]

number

[0179] In addition, V M8gs is the voltage between the gate and the second terminal of the transistor M8. Also, I0 is V M8gs is 0, and is determined by the threshold voltage of transistor M8, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.3) are assumed to be equal to I0 and J used in equations (1.1) and (1.2), respectively.

[0180] The current flowing between the first terminal and the second terminal of the transistor M10 is determined according to the voltage between the gate and the second terminal of the transistor M10. Y When this is done, the current I Y can be expressed by the following formula:

[0181]

number

[0182] In addition, V M10gs is the voltage between the gate and the second terminal of the transistor M10. M10gsis 0, and is determined by the threshold voltage of transistor M10, temperature, device structure, etc. Also, J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.4) are assumed to be equal to I0 and J used in equations (1.1) to (1.3), respectively.

[0183] Consider a closed circuit in the following order: wire VGE, the second terminal of transistor M7, the gate of transistor M7, the second terminal of transistor M5, the gate of transistor M5, the gate of transistor M8, the second terminal of transistor M8, the gate of transistor M10, the second terminal of transistor M10, and wire VGE. In this closed circuit, the following equation holds true according to Kirchhoff's second law (voltage law):

[0184]

number

[0185] Furthermore, by rewriting each voltage term in equation (1.5) using equations (1.1) to (1.4), the following equation is obtained.

[0186]

number

[0187] In other words, the current I that flows between the first and second terminals of the transistor M10 Y I W and I X Therefore, the amount of current I flowing from the wiring OL Y By measuring I W and I X A value corresponding to the product of these can be calculated.

[0188] Note that the configuration of the multiplication cell included in the semiconductor device of one embodiment of the present invention is not limited to the circuit MC illustrated in Fig. 16A. The multiplication cell included in the semiconductor device of one embodiment of the present invention can have a configuration obtained by changing the circuit MC illustrated in Fig. 16A depending on the situation.

[0189] Furthermore, the transistors M1 to M10 shown in FIG. 16A are, for example, n-channel transistors having gates above and below the channel, and each of the transistors M1 to M10 has a first gate and a second gate. For convenience, the present specification and the like distinguishes between the first gate (sometimes referred to as a front gate) and the second gate (sometimes referred to as a back gate), but the first gate and the second gate can be interchanged. Therefore, the term "gate" can be interchanged with the term "back gate" in this specification and the like. Similarly, the term "back gate" can be interchanged with the term "gate." Specifically, the connection configuration in which "the gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0190] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the connection structure of the back gate of the transistor. The back gates of the transistors M1 to M10 in FIG. 16A are illustrated, but the connection structure of the back gates is not illustrated. However, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to each other in order to increase the on-state current of the transistor. Furthermore, in a transistor having a back gate, for example, a wiring electrically connected to an external circuit or the like may be provided so that a fixed potential or a variable potential can be applied to the back gate of the transistor by the external circuit or the like in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor.

[0191] <Configuration example of semiconductor device> Here, a configuration example of a semiconductor device to which the circuit MC shown in FIG. 16A can be applied will be described.

[0192] Fig. 17A is a circuit diagram showing an example of the configuration of a semiconductor device to which the circuit MC of Fig. 16A can be applied. The semiconductor device SDV1 shown in Fig. 17A has, as an example, a circuit WDC, a circuit XDC, a circuit BDC, a circuit WWC, a cell array CA, and a circuit ACTV. The circuit ACTV also has, as an example, circuits ADR[1] to ADR[n].

[0193] As an example, the cell array CA has a plurality of circuits MC shown in Fig. 16A. Specifically, in the cell array CA, the plurality of circuits MC are arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). As an example, Fig. 17A illustrates the following circuits MC within the cell array CA: circuit MC[1,1], circuit MC[m,1], circuit MC[1,n], and circuit MC[m,n].

[0194] The circuit MC[1,1] is electrically connected to the wiring WDL[1], the wiring WWL[1], the wiring WWLB[1], the wiring XDL[1], the wiring BDL[1], and the wiring OL[1]. The circuit MC[m,1] is electrically connected to the wiring WDL[1], the wiring WWL[m], the wiring WWLB[m], the wiring XDL[m], the wiring BDL[m], and the wiring OL[1]. The circuit MC[1,n] is electrically connected to the wiring WDL[n], the wiring WWL[1], the wiring WWLB[1], the wiring XDL[1], the wiring BDL[1], and the wiring OL[n]. In addition, the circuit MC[m,n] is electrically connected to the wiring WDL[n], the wiring WWL[m], the wiring WWLB[m], the wiring XDL[m], the wiring BDL[m], and the wiring OL[n].

[0195] In other words, when i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n, it can be said that the circuit MC[i,j] (not shown in Figure 17A) is electrically connected to the wiring WDL[j], the wiring WWL[i], the wiring WWLB[i], the wiring XDL[i], the wiring BDL[i], and the wiring OL[j].

[0196] Note that the wiring WDL[j] corresponds to the wiring WDL shown in FIG. 16A. The wiring WWL[i] corresponds to the wiring WWL shown in FIG. 16A, and the wiring WWLB[i] corresponds to the wiring WWLB shown in FIG. 16A. The wiring XDL[i] corresponds to the wiring XDL shown in FIG. 16A, and the wiring BDL[i] corresponds to the wiring BDL shown in FIG. 16A. The wiring OL[j] corresponds to the wiring OL shown in FIG. 16A.

[0197] The circuit WDC is electrically connected to the wirings WDL[1] to WDL[n]. The circuit XDC is electrically connected to the wirings XDL[1] to XDL[m]. The circuit BDC is electrically connected to the wirings BDL[1] to BDL[m]. The circuit WWC is electrically connected to the wirings WWL[1] to WWL[m] and the wirings WWLB[1] to WWLB[m]. The circuits ADR[1] to ADR[n] are electrically connected to the wirings OL[1] to OL[n] and the wirings ZL[1] to ZL[n], respectively.

[0198] For example, the circuit WDC functions as a drive circuit that applies a voltage to each of the wirings WDL[1] to WDL[n] according to first data to be written to the circuit MC included in the cell array CA.

[0199] For example, the circuit XDC functions as a drive circuit that applies a voltage to each of the wirings XDL[1] to XDL[m] according to second data to be input to the circuit MC included in the cell array CA.

[0200] As an example, the circuit BDC functions as a driving circuit that applies a voltage to each of the wirings BDL[1] to BDL[m] to adjust the amount of current flowing through the wiring OL according to the calculation result for input to the circuit MC included in the cell array CA.

[0201] For example, the circuit WWC has a function of selecting a circuit MC to which the first data is to be written when writing the first data to each of the wirings WWL[1] to WWL[m] included in the cell array CA. Specifically, when writing the first data to the circuits MC[i,1] to MC[i,n] located in the i-th row of the cell array CA, the circuit WWC applies a high-level potential to the wiring WWL[i] and a low-level potential to the wirings WWL[1] to WWL[m] other than the wiring WWL[i], thereby selecting the circuits MC[i,1] to MC[i,n] to which the first data is to be written.

[0202] For example, the circuit WWC has a function of transmitting an inverted signal of the selection signal transmitted to the wiring WWL[i] to the wiring WWLB[i]. The circuit WWC may transmit a different signal to the wiring WWLB[i] instead of the inverted signal. For example, the circuit WWC may also have a function of inputting a low-level potential to the wiring WWLB[i] when a low-level potential is input to the wiring WWL[i]. This allows the circuit MC in FIG. 16A to retain the first data and stop the supply of the high power supply potential to the first terminal of the transistor M2 simultaneously.

[0203] By the way, when focusing on the j-th column of the cell array CA, the wiring OL has a current amount I output from each of the circuits MC[1,j] to MC[m,j]. Y Here, the current flowing through transistor M2 in circuit MC[i,j] is I W [i,j], and the current flowing through transistor M6 in circuit MC[i,j] is I X [i], and the amount of current flowing from wiring OL to circuit MC[i,j] is I Y Furthermore, the amount of current flowing through each of the transistors M9 in the circuits MC[1,j] to MC[m,j] is I B When this is done, the amount of current I S [j] can be expressed as follows:

[0204]

number

[0205] As an example, the circuit ADR[j] has the function of outputting a voltage corresponding to the amount of current flowing from the wiring OL[j] to the circuit ADR[j], the function of performing an operation according to a predefined function system using the voltage, and the function of outputting the result of the operation of the function to the wiring ZL[j].

[0206] 17B, ​​a circuit BGC may be provided. The circuit BGC is electrically connected to the wirings BGL[1] to BGL[m]. For example, the circuit BGC has a function of inputting a desired constant voltage to each of the wirings BGL[1] to BGL[m]. That is, the circuit BGC functions as a circuit that supplies a constant voltage to the back gates of the transistors included in the circuits MC[1,1] to MC[m,n].

[0207] As described above, by using the circuit MC shown in FIG. 16A, it is possible to write a voltage corresponding to the first data to the circuit MC. In addition, the circuit MC generates a current I Y can be output to the wiring OL. Furthermore, by using the semiconductor device SDV1 in Fig. 17A or the semiconductor device SDV2 in Fig. 17B, it is possible to calculate the sum of products of a plurality of first data and a plurality of second data.

[0208] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0209] (Fourth embodiment) In this embodiment, an example of operation will be described in which part of the calculations of a program executed by the CPU 110 described in the above embodiment is executed by an accelerator described as the semiconductor device 100.

[0210] 18 is a diagram illustrating an example of the operation when part of the calculations of a program executed by a CPU is executed by an accelerator. The accelerator can select either the digital calculation unit 101 or the analog calculation unit 102 depending on the type of calculation.

[0211] The host program is executed by the CPU (host program execution; step S1).

[0212] When the CPU confirms an instruction to reserve a data area required for calculations using the accelerator in the memory circuit unit (memory reservation instruction; step S2), it reserves the data area in the memory circuit unit (memory reservation; step S3).

[0213] Next, the CPU transmits weight data, which is input data, from the main memory or an external storage device to the memory circuit unit (data transmission; step S4). The memory circuit unit receives the weight data and stores it in the area reserved in step S3 (data reception; step S5).

[0214] When the CPU confirms an instruction to start the kernel program (start kernel program; step S6), the accelerator starts executing the kernel program (start operation; step S7).

[0215] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (PG state transition; step S8). In this case, immediately before the accelerator finishes executing the kernel program, the CPU is switched from the PG state to a state performing calculations (PG state stop; step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the entire calculation processing system.

[0216] When the accelerator finishes executing the kernel program, the output data is stored in a storage unit that holds the calculation results in the accelerator (computation end; step S10).

[0217] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit the output data stored in the memory unit to the main memory or an external storage device (data transmission request; step S11), the output data is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission; step S12).

[0218] By repeating the above operations from step S1 to step S12, the power consumption and heat generation of the CPU and the accelerator can be suppressed, and part of the computations to be performed by the CPU can be performed by the accelerator. The semiconductor device of one embodiment of the present invention has a non-von Neumann architecture, and can perform computations with significantly less power consumption than a von Neumann architecture, which consumes more power as the processing speed increases.

[0219] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0220] (Embodiment 5) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0221] 19 shows an example of the configuration of the CPU 110. The CPU 110 has a CPU core 200, an L1 (level 1) cache memory device (L1 Cache) 202, an L2 cache memory device (L2 Cache) 203, a bus interface unit (Bus I / F) 205, power switches 210 to 212, and a level shifter (LS) 214. The CPU core 200 has a flip-flop 220.

[0222] The CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203 are interconnected by a bus interface unit 205.

[0223] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from the outside and signals such as the SLEEP1 signal issued by the CPU 110. The clock signal GCLK1 and the PG control signals are input to the CPU 110. The PG control signals control the power switches 210 to 212 and the flip-flop 220.

[0224] Power switches 210 and 211 control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line), respectively. A power switch 212 controls the supply of a voltage VDDH to a level shifter (LS) 214. A voltage VSSS is input to the CPU 110 and PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0225] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0226] Each of the L1 cache memory device 202, the L2 cache memory device 203, and the bus interface unit 205 has at least one power domain that can be power-gated. Each power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0227] The flip-flop 220 is used as a register. A backup circuit is provided in the flip-flop 220. The flip-flop 220 will be described below.

[0228] 20A shows an example of the circuit configuration of the flip-flop 220. The flip-flop 220 has a scan flip-flop 221 and a backup circuit 222.

[0229] The scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 221A.

[0230] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for a reset signal.

[0231] The signal SCE is a scan enable signal and is generated by the PMU 193. The PMU 193 generates signals BK and RC. The level shifter 214 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0232] The circuit configuration of the scan flip-flop 221 is not limited to that shown in Fig. 20. Flip-flops available in a standard circuit library can be applied.

[0233] The backup circuit 222 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0234] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 221. The node SN11 is a storage node of the backup circuit 222. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0235] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0236] The transistors M11 to M13 are OS transistors, similar to the transistors 61 to 63 included in the memory circuit 21. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0237] At least the transistors M11 and M12 are preferably OS transistors. The OS transistors have an extremely small off-state current, which prevents a voltage drop at the node SN11. Furthermore, the backup circuit 222 consumes almost no power to retain data, making it nonvolatile. Because data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and with low energy consumption.

[0238] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Fig. 20B, the backup circuit 222 can be stacked on a scan flip-flop 221 made up of a silicon CMOS circuit.

[0239] Since the backup circuit 222 has an extremely small number of elements compared to the scan flip-flop 221, stacking the backup circuit 222 does not require changing the circuit configuration and layout of the scan flip-flop 221. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be provided in the region where the scan flip-flop 221 is formed, even if the backup circuit 222 is incorporated, the area overhead of the flip-flop 220 can be reduced to zero. Therefore, providing the backup circuit 222 in the flip-flop 220 enables power gating of the CPU core 200. Because little energy is required for power gating, the CPU core 200 can be power gated with high efficiency.

[0240] By providing the backup circuit 222, a parasitic capacitance due to the transistor M11 is added to the node Q1, but since it is small compared to the parasitic capacitance due to the logic circuit connected to the node Q1, it does not affect the operation of the scan flip-flop 221. In other words, even if the backup circuit 222 is provided, the performance of the flip-flop 220 does not substantially deteriorate.

[0241] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state of the CPU core 200. The PMU 193 selects the low power consumption mode of the CPU core 200 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operating state to a clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0242] For example, when transitioning from a normal operating state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 210 and turns on the power switch 211 to input the voltage VDD1 to the CPU core 200. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 221. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0243] When the CPU core 200 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data of the scan flip-flop 221 to the backup circuit 222. When the CPU core 200 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 222 to the scan flip-flop 221.

[0244] The backup circuit 222 using OS transistors consumes small amounts of both dynamic and static power, making it highly suitable for normally-off computing. A CPU 110 including a CPU core 200 with a backup circuit 222 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has nonvolatile memory and can stop power supply when operation is not required. Even if the flip-flop 220 is installed, it is possible to minimize the degradation of CPU core 200 performance and the increase in dynamic power consumption.

[0245] The CPU core 200 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling the input of voltage. The CPU core 200 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 220 and the power switches 210 to 212.

[0246] The application of the flip-flop 220 is not limited to the CPU 110. In the CPU 110, the flip-flop 220 can be applied to a register provided in a power domain that is capable of power gating.

[0247] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0248] (Sixth embodiment) In this embodiment, a structural example of the semiconductor device described in the above embodiment and a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

[0249] <Configuration example of semiconductor device> 21 illustrates an example of the semiconductor device described in the above embodiment, which includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 22A illustrates a cross-sectional view of the transistor 500 in the channel length direction, Fig. 22B illustrates a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 22C illustrates a cross-sectional view of the transistor 300 in the channel width direction.

[0250] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of low off-state current and a low field-effect mobility even at high temperatures. By using the transistor 500 in the analog computing unit 102, the oxide semiconductor memory 103, the oxide semiconductor memory 104, or the like described in the above embodiment, a semiconductor device whose operation performance is not easily reduced even at high temperatures can be realized. In particular, by utilizing the low off-state current of the transistor 500 in the transistors in the oxide semiconductor memory 103 and the oxide semiconductor memory 104, a written potential can be held for a long time.

[0251] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example. Note that the capacitor 600 can be a capacitor included in the oxide semiconductor memory 103, the oxide semiconductor memory 104, or the like described in the above embodiment. Note that the capacitor 600 illustrated in FIG. 21 is not necessarily provided depending on the circuit configuration.

[0252] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Note that the transistor 300 can be applied to, for example, a transistor included in the digital computing unit 101 described in the above embodiment. Note that Figure 21 shows a configuration in which the gate of transistor 300 is electrically connected to one of the source or drain of transistor 500 through a pair of electrodes of the capacitor 600. However, depending on the configuration of the digital computing unit 101, etc., one of the source or drain of transistor 300 may be electrically connected to one of the source or drain of transistor 500 through a pair of electrodes of the capacitor 600, or one of the source or drain of transistor 300 may be electrically connected to the gate of transistor 500 through a pair of electrodes of the capacitor 600. Furthermore, each terminal of transistor 300 may not be electrically connected to each terminal of transistor 500 or each terminal of the capacitor 600.

[0253] With the above-described structure, an element layer including an OS can be formed on an element layer including Si, as shown in FIGS. 2A, 2B, 3A, and 3B.

[0254] The substrate 310 is preferably a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0255] 22C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0256] The transistor 300 may be either a p-channel type or an n-channel type.

[0257] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0258] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0259] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0260] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material containing at least one of titanium nitride, tantalum nitride, and the like as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material containing at least one of tungsten, aluminum, and the like as the conductor in a laminated layer, and tungsten is particularly preferable in terms of heat resistance.

[0261] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

[0262] The transistor 300 shown in FIG. 21 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method. For example, the transistor 300 may have a planar structure instead of the FIN structure shown in FIG. 22C. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 23. Details of the transistor 500 will be described later. In this specification and the like, a unipolar circuit refers to a circuit including transistors of only one polarity, either n-channel transistors or p-channel transistors.

[0263] 23, the transistor 300 is provided on a substrate 310A. However, in this case, the substrate 310A may be a semiconductor substrate similar to the substrate 310 of the semiconductor device in FIG. 21. When the substrate 310A in FIG. 23 is a semiconductor substrate similar to the substrate 310 of the semiconductor device in FIG. 21, the transistor 300 shown in FIG. 21 may be formed on the semiconductor substrate. The substrate 310A may be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Examples include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper.

[0264] With the above-described structure, an element layer including a second OS can be formed over an element layer including a first OS, as shown in FIGS. 2B, 3B, 5B, and 16B.

[0265] In the transistor 300 shown in FIG. 21, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0266] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0267] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0268] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0269] The insulator 324 is preferably a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0270] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0271] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0272] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0273] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0274] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material containing at least one of tungsten and molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material containing at least one of aluminum and copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0275] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 21 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0276] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against impurities including at least one of water and hydrogen, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having barrier properties against impurities including at least one of water and hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the opening of the insulator 350 having barrier properties against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0277] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0278] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0279] The insulator 360 is preferably an insulator having barrier properties against impurities including at least one of water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0280] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, similar to the insulator 324, it is preferable to use an insulator that has a barrier property against impurities containing at least one of water and hydrogen. Therefore, the insulators 362 and / or 364 can be made of a material that can be used for the insulator 324.

[0281] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0282] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364 and the conductor 366. It is preferable that any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 be made using a substance that has a barrier property against oxygen or hydrogen.

[0283] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0284] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0285] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0286] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0287] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0288] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 22A and 22B), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductors 328 and 330.

[0289] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0290] Above the insulator 516 is the transistor 500 .

[0291] As shown in FIGS. 22A and 22B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 571b on the oxide 571b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 22A and 22B , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulators 554, 550, 552, and 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, 552, 550, 554, and 580.

[0292] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0293] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0294] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0295] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0296] FIG. 24A shows an enlarged view of the vicinity of the channel formation region in FIG. 22A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in a region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 24A, the oxide 530b includes a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. The region 530bc at least partially overlaps with the conductor 560. In other words, the region 530bc is located in a region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0297] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0298] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0299] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or a high concentration of at least one impurity such as hydrogen, nitrogen, or a metal element, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0300] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0301] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0302] 24A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0303] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0304] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0305] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0306] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0307] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0308] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0309] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0310] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0311] CAAC-OS has a highly crystalline and dense structure, and contains impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0312] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0313] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0314] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the oxygen supplied to the source region or the drain region varies within the substrate plane, the characteristics of the semiconductor device having the transistor will vary.

[0315] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0316] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0317] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0318] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0319] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0320] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0321] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be prevented, maintaining n-type conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 500, thereby reducing variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0322] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0323] 22B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0324] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0325] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0326] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0327] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0328] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0329] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0330] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0331] 22A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0332] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0333] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0334] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0335] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, it is preferable to use aluminum oxide or magnesium oxide, which has the function of capturing and fixing hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0336] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0337] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0338] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may also be used as appropriate.

[0339] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0340] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0341] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0342] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0343] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0344] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0345] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0346] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0347] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0348] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0349] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 22B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0350] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0351] 22B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0352] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0353] Insulator 522 and insulator 524 function as gate insulators.

[0354] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0355] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 and the oxide 530 can be suppressed.

[0356] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0357] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0358] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0359] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0360] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0361] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0362] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0363] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0364] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0365] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0366] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0367] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0368] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0369] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0370] As shown in FIG. 22B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0371] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0372] 22A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 571, the insulator 544, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0373] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0374] To form the insulator 552 into a thin film as described above, it is preferable to form the film by the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma-enhanced ALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0375] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0376] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0377] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0378] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15.0 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0379] 22A and 22B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in Fig. 24B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0380] As shown in FIG. 24B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0381] When silicon oxide or silicon oxynitride is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator with a layered structure of the insulators 550a and 550b, a thermally stable layered structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0382] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0383] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0384] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0385] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed on the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 22A and 22B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Although the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 22A and 22B, it may also be a single-layer structure or a stacked structure of three or more layers.

[0386] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0387] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0388] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can be made of titanium or titanium nitride and the above-mentioned conductive material.

[0389] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0390] 22B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0391] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0392] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0393] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0394] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0395] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0396] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0397] For example, the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 22A and insulators 582 and 586 shown in FIG. 21, and the conductor 540a is provided inside the openings. For example, the conductor 540b is provided in a region overlapping with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Fig. 22A and insulators 582 and 586 shown in Fig. 21, and the conductor 540b is provided inside the openings. Note that the insulators 582 and 586 will be described later.

[0398] 22A, an insulator 541a may be provided as an insulator having barrier properties against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having barrier properties against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0399] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0400] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0401] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0402] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 22A, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0403] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0404] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0405] 21, conductors 610 and 612, which function as wiring and are in contact with the upper portions of conductors 540a and 540b, may be disposed. Conductor 610 and conductor 612 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may have a layered structure. Specifically, for example, the conductors may be a layered structure of titanium or titanium nitride and the above conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0406] The structure of the transistors included in the group of semiconductor devices of the present invention is not limited to the transistor 500 shown in Figures 21, 22A, 22B, and 23. The structure of the transistors included in the group of semiconductor devices of the present invention may be changed depending on the situation.

[0407] For example, the transistor 500 illustrated in FIGS. 21, 22A, 22B, and 23 may have the structure illustrated in FIG. 25. The transistor in FIG. 25 differs from the transistor 500 illustrated in FIGS. 21, 22A, 22B, and 23 in that it includes an oxide 543a and an oxide 543b. Note that in this specification and the like, the oxide 543a and the oxide 543b are collectively referred to as the oxide 543. The cross-sectional structure of the transistor in FIG. 25 in the channel width direction can be similar to that of the cross-section of the transistor 500 illustrated in FIG. 22B.

[0408] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. The oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0409] The oxide 543 preferably has a function of suppressing oxygen permeation. Placing the oxide 543, which has a function of suppressing oxygen permeation, between the conductor 542 functioning as a source or drain electrode and the oxide 530b is preferable because the electrical resistance between the conductor 542 and the oxide 530b can be reduced. Such a structure can improve the electrical characteristics, field-effect mobility, and reliability of the transistor 500 in some cases.

[0410] Alternatively, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 543 has a higher concentration of element M than oxide 530b. Alternatively, oxide 543 may be gallium oxide. Alternatively, oxide 543 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more or 1 nm or more, and is preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-mentioned lower and upper limits may be combined. Preferably, oxide 543 is crystalline. When oxide 543 is crystalline, oxygen release from oxide 530 can be effectively suppressed. For example, if the oxide 543 has a crystal structure such as a hexagonal crystal structure, the release of oxygen from the oxide 530 may be suppressed.

[0411] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0412] The insulator 582 is preferably made of a substance that has a barrier property against at least one of oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0413] The insulator 586 can be made of a material similar to that of the insulator 320. The use of a material with a relatively low dielectric constant for these insulators can reduce parasitic capacitance between wirings. For example, the insulator 586 can be made of a silicon oxide film or a silicon oxynitride film.

[0414] Next, a description will be given of a capacitor 600 and its peripheral wiring or plugs included in the semiconductor device shown in Fig. 21 and Fig. 23. Note that the capacitor 600, wiring, and / or plugs are provided above the transistor 500 shown in Fig. 21 and Fig. 23.

[0415] The capacitor 600 includes, for example, a conductor 610 , a conductor 620 , and an insulator 630 .

[0416] A conductor 610 is provided over one of the conductors 540a and 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of a pair of electrodes of the capacitor 600.

[0417] A conductor 612 is provided over the other of the conductor 540a and the conductor 540b and over the insulator 586. The conductor 612 functions as a plug, a wiring, a terminal, or the like that electrically connects the transistor 500 to a wiring or a circuit element above it. Specifically, for example, the conductor 612 can be the wiring WDL in the semiconductor device SDV1 described in Embodiment 3.

[0418] The conductor 612 and the conductor 610 may be formed at the same time.

[0419] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0420] 21, the conductor 612 and the conductor 610 are shown to have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0421] An insulator 630 is provided over the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitor 600.

[0422] The insulator 630 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like. The insulator 630 can be formed as a stacked layer or a single layer using any of the above-mentioned materials.

[0423] Furthermore, for example, the insulator 630 may have a laminated structure of a high dielectric strength material, such as silicon oxynitride, and a high dielectric constant (high-k) material. With this configuration, the capacitor 600 can ensure sufficient capacitance by having an insulator with a high dielectric constant (high-k), and the capacitor 600 can have improved dielectric strength by having an insulator with a high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 600.

[0424] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0425] Alternatively, the insulator 630 may be a single layer or a multilayer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). The insulator 630 may also be a compound containing hafnium and zirconium, such as an oxide containing zirconium and hafnium. As semiconductor devices become increasingly miniaturized and highly integrated, thinning of the gate insulator and dielectrics used in capacitors can cause problems such as leakage current in transistors and capacitors. Using a high-k material for the insulators that function as the gate insulator and dielectrics used in capacitors allows for a reduction in the gate potential during transistor operation and a secure capacitance for capacitors, while maintaining the physical film thickness.

[0426] Alternatively, a ferroelectric material may be used as the insulator 630. For example, a mixed crystal of hafnium oxide and zirconium oxide (also referred to as "HZO"), or a material in which element X (element X is silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide. Alternatively, a piezoelectric ceramic having a perovskite structure may be used as the insulator 630. For example, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0427] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 610 functions as one of a pair of electrodes of the capacitor 600. For example, the conductor 620 can be the wiring WWLB in the semiconductor device SDV1 described in Embodiment 3.

[0428] The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material containing at least one of tungsten and molybdenum, which have both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other structures such as a conductor, at least one of low-resistance metal materials such as Cu (copper) and Al (aluminum) can be used. For example, the conductor 620 can be made of a material that can be used for the conductor 610. The conductor 620 may have a laminated structure of two or more layers, rather than a single-layer structure.

[0429] An insulator 640 is provided over the conductor 620 and the insulator 630. For the insulator 640, for example, a film having a barrier property that prevents impurities such as hydrogen from diffusing into a region where the transistor 500 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.

[0430] An insulator 650 is provided over the insulator 640. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of, for example, a material that can be used for the insulator 324.

[0431] 21 and 23 is a planar type, the shape of the capacitive element is not limited to this. The capacitive element 600 may be, for example, a cylindrical type instead of a planar type.

[0432] 21, an insulator 411, an insulator 412, an insulator 413, and an insulator 414 are provided in this order above an insulator 650. A conductor 416 functioning as a plug or a wiring is provided in the insulators 411, 412, and 413. For example, the conductor 416 can be provided in a region overlapping with a conductor 660 described later.

[0433] Furthermore, openings are provided in the insulators 630, 640, and 650 in regions overlapping with the conductor 612, and the conductor 660 is provided to fill the openings. The conductor 660 functions as a plug or wiring electrically connected to the conductor 416 included in the above-described wiring layer.

[0434] The insulators 411 and 414 are preferably made of an insulator that has barrier properties against impurities including at least one of water and hydrogen, similar to the insulator 324. Therefore, the insulators 411 and 414 can be made of a material that can be used for the insulator 324, for example.

[0435] For the insulators 412 and 413, similar to the insulator 326, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings.

[0436] Furthermore, the conductor 612 and the conductor 416 can be formed using, for example, the same material as the conductor 328 and the conductor 330 .

[0437] By applying the structure described in this embodiment to a semiconductor device including a transistor having an oxide semiconductor, fluctuations in electrical characteristics of the transistor can be suppressed and reliability can be improved. Alternatively, miniaturization or high integration of a semiconductor device including a transistor having an oxide semiconductor can be achieved.

[0438] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0439] (Embodiment 7) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0440] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0441] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 26A. Fig. 26A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0442] As shown in FIG. 26A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous (excluding single crystal and polycrystal). "Crystal" includes single crystal and polycrystal.

[0443] The structure within the bold frame in Figure 26A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0444] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 26B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 26B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 26B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 26B is 500 nm.

[0445] As shown in Figure 26B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 26B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0446] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 26C. Figure 26C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 26C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0447] As shown in FIG. 26C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0448] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 26A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0449] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0450] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0451] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0452] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0453] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0454] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0455] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0456] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0457] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0458] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0459] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0460] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0461] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0462] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0463] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0464] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0465] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0466] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0467] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0468] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0469] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0470] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0471] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0472] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0473] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0474] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0475] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0476] When an oxide semiconductor contains at least one of silicon and carbon, which are elements of Group 14, defect levels are formed in the oxide semiconductor. Therefore, the concentration of at least one of silicon and carbon in the oxide semiconductor and the concentration of at least one of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0477] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0478] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0479] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0480] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0481] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0482] (Embodiment 8) This embodiment mode will describe an example of a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0483] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 27A.

[0484] 27A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. Note that on the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is an area for dicing.

[0485] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0486] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0487] By performing a dicing process, chips 4800a as shown in FIG. 27B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. Note that spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0488] 27A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0489] <Electronic components> FIG. 27C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 27C has chip 4800a in mold 4711. Note that, as shown in FIG. 27C, chip 4800a may have a configuration in which circuit section 4802 is stacked. FIG. 27C omits a portion to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. Mounting substrate 4704 is completed by combining a plurality of such electronic components and electrically connecting them on printed circuit board 4702.

[0490] 27D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0491] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, any of the semiconductor devices described in the above embodiments or a high bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0492] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0493] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0494] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0495] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0496] Furthermore, in SiP or MCM using silicon interposers, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on the interposer.

[0497] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0498] Electrodes 4733 may be provided on the bottom of package substrate 4732 in order to mount electronic component 4730 on another substrate. Fig. 27D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0499] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0500] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0501] (Embodiment 9) In this embodiment, an example of an electronic device including the semiconductor device described in the above embodiment will be described. Note that Fig. 28 illustrates how each electronic device includes an electronic component 4700 including the semiconductor device.

[0502] [mobile phone] 28 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0503] By applying the semiconductor device described in the above embodiment, the information terminal 5500 can execute applications using artificial intelligence. Examples of the applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs at least one biometric authentication such as a fingerprint or a voiceprint.

[0504] [Wearable devices] 28 illustrates a wristwatch-type information terminal 5900 as an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0505] The wearable terminal can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment, similar to the information terminal 5500 described above. Examples of applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, and a navigation system that selects and guides the user along the optimal route based on the input of a destination.

[0506] [Information terminal] 28 also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0507] The desktop information terminal 5300, like the information terminal 5500 described above, can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, the desktop information terminal 5300 can be used to develop new artificial intelligence.

[0508] In the above description, a smartphone, a desktop information terminal, and a wearable terminal are illustrated as examples of electronic devices in Fig. 28, but information terminals other than smartphones, desktop information terminals, and wearable terminals can also be applied. Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0509] [electric appliances] 28 also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0510] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the semiconductor device described in the above embodiment to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have at least one of a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, and a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800.

[0511] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0512] [Game consoles] 28 also shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0513] FIG. 28 further illustrates a home video game console 7500, which is an example of a video game console. The home video game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 28, the controller 7522 can include at least one of a display unit that displays game images, a touch panel that serves as an input interface other than buttons, a stick, a rotary knob, and a sliding knob. The shape of the controller 7522 is not limited to that shown in FIG. 28, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0514] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0515] A low-power consumption portable game console 5200 can be realized by applying the semiconductor device described in the above embodiment to the portable game console 5200. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0516] Furthermore, by applying the semiconductor device described in the above embodiment modes to the portable game machine 5200, the portable game machine 5200 can have artificial intelligence.

[0517] Normally, the progression of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the game's program, but by applying artificial intelligence to the portable game console 5200, it becomes possible to express things that are not limited to the game's program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of characters appearing in the game.

[0518] Furthermore, when playing a game requiring multiple players on the portable game console 5200, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0519] 28 illustrates a portable game machine as an example of a game machine, but the electronic device of an embodiment of the present invention is not limited to this. Examples of the electronic device of an embodiment of the present invention include a home-use stationary game machine, an arcade game machine installed in an entertainment facility (such as an arcade or amusement park), and a pitching machine for batting practice installed in a sports facility.

[0520] [Moving object] The semiconductor device described in the above embodiment mode can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0521] FIG. 28 shows an automobile 5700 as an example of a moving object.

[0522] An instrument panel capable of displaying at least one of a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, and air conditioning settings is provided around the driver's seat of the automobile 5700. A display device showing such information may also be provided around the driver's seat.

[0523] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0524] The semiconductor device described in the above embodiment can be applied as a component of artificial intelligence, and therefore, for example, the semiconductor device can be used in an automatic driving system for the automobile 5700. The semiconductor device can also be used in a system that provides road guidance, hazard prediction, and the like. The display device may be configured to display information such as road guidance and hazard prediction.

[0525] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A semiconductor device according to one embodiment of the present invention can be applied to these moving objects to provide them with a system using artificial intelligence.

[0526] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0527] 28 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that at least one of a strobe device, a viewfinder, etc. can be separately attached.

[0528] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment modes to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0529] Furthermore, the digital camera 6240 having artificial intelligence can be realized by applying the semiconductor device described in the above embodiment to the digital camera 6240. By using artificial intelligence, the digital camera 6240 can have a function of automatically recognizing a subject such as a face or an object, a function of adjusting focus according to the subject, a function of automatically firing a flash according to the environment, a function of adjusting the color of a captured image, and the like.

[0530] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0531] 28 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, and the like. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. A configuration may be adopted in which the image on the display unit 6303 is switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0532] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By utilizing artificial intelligence, the video camera 6300 can perform pattern recognition using artificial intelligence during encoding. This pattern recognition allows the calculation of differential data for people, animals, objects, etc. contained in consecutive captured image data, and then compresses the data.

[0533] [PC expansion device] The semiconductor device described in the above embodiment can be applied to an expansion device for a computer such as a PC (Personal Computer) or an information terminal.

[0534] Figure 29A shows an example of such an expansion device: a portable expansion device 6100 mounted on a chip capable of arithmetic processing and externally attached to a PC. The expansion device 6100 can perform arithmetic processing using the chip by connecting it to a PC via, for example, a Universal Serial Bus (USB). Note that while Figure 29A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0535] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, the board 6104 is equipped with a chip 6105 (such as the semiconductor device, electronic component 4700, or memory chip described in the above embodiment) and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0536] By using the expansion device 6100 with a PC or the like, the processing power of the PC can be increased. This allows a PC with insufficient processing power to perform calculations such as artificial intelligence and video processing.

[0537] [Broadcasting System] The semiconductor device described in the above embodiment can be applied to a broadcasting system.

[0538] Fig. 29B shows a schematic diagram of data transmission in a broadcasting system. Specifically, Fig. 29B shows the path that radio waves (broadcast signals) transmitted from a broadcasting station 5680 take to reach a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by an antenna 5650 is transmitted to the TV 5600 via the receiving device.

[0539] In FIG. 29B, antenna 5650 is illustrated as a UHF (Ultra High Frequency) antenna, but antenna 5650 can also be a BS·110° CS antenna, a CS antenna, or the like.

[0540] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. Each home can watch terrestrial broadcasting on TV 5600 by receiving radio waves 5675B with antenna 5650. Note that the broadcasting system is not limited to terrestrial broadcasting shown in Fig. 29B, and may also be satellite broadcasting using an artificial satellite, data broadcasting via optical fiber lines, or the like.

[0541] The above-described broadcasting system may be a broadcasting system utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. When broadcast data is transmitted from the broadcasting station 5680 to the TV 5600 in each home, the broadcast data is compressed by an encoder. When the antenna 5650 receives the broadcast data, the broadcast data is restored by a decoder in a receiving device included in the TV 5600. By utilizing artificial intelligence, for example, it is possible to recognize a display pattern included in a display image in motion compensation prediction, which is one of the compression methods used by the encoder. It is also possible to perform intra-frame prediction using artificial intelligence. Furthermore, for example, when low-resolution broadcast data is received and displayed on a high-resolution TV 5600, image interpolation processing such as upconversion can be performed when the decoder restores the broadcast data.

[0542] The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which involves an increasing amount of broadcast data.

[0543] Furthermore, as an application of artificial intelligence on the TV 5600 side, for example, a recording device with artificial intelligence may be provided in the TV 5600. With such a configuration, the recording device can be made to learn user preferences using artificial intelligence, thereby automatically recording programs that match the user's preferences.

[0544] [Authentication System] The semiconductor device described in the above embodiment can be applied to an authentication system.

[0545] FIG. 29C shows a palm print authentication device, which includes a housing 6431 , a display unit 6432 , a palm print reader 6433 , and wiring 6434 .

[0546] 29C shows how a palm print authentication device acquires a palm print of a hand 6435. The acquired palm print is subjected to pattern recognition processing using artificial intelligence, and it is possible to determine whether the palm print belongs to the individual. This makes it possible to build a system that performs authentication with high security. Furthermore, the authentication system according to one aspect of the present invention is not limited to a palm print authentication device, and may be a device that acquires biometric information such as fingerprints, veins, face, iris, voiceprint, genes, and physique to perform biometric authentication.

[0547] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0548] (Notes regarding the present specification) The above-described embodiment and each configuration in the embodiment will be described below with additional notes.

[0549] The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0550] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0551] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0552] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0553] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0554] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0555] Furthermore, the positional relationships of components shown in the drawings are relative. Therefore, when describing components with reference to the drawings, terms such as "above" and "below" indicating the positional relationships may be used for convenience. The positional relationships of components are not limited to the content described in this specification, and can be rephrased appropriately depending on the situation.

[0556] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0557] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0558] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0559] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0560] In this specification, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection in which an electrical signal can be transmitted between A and B when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between A and B. Note that "A and B are electrically connected" also includes a case in which A and B are directly connected. Here, "A and B are directly connected" means a connection in which an electrical signal can be transmitted between A and B via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0561] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0562] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0563] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0564] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." [Explanation of symbols]

[0565] A1: input data, A2: input data, C1: capacitance, C11: capacitance element, CK1: node, D1: node, GCLK1: clock signal, LBL_N: wiring, LBL_1: wiring, LBL_4: wiring, LBL_6: wiring, M1: transistor, M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, M7: transistor, M8: transistor, M9: transistor, M10: transistor, M11: transistor, M12: transistor, M13: transistor, MAC1: output data, MAC2: output Data, MC1: circuit, MC2: circuit, MCL1: layer, MCL2: layer, Q1: node, RWL_M: read word line, RWL_1: read word line, SCL1: scribe line, SCL2: scribe line, SDV1: semiconductor device, SDV2: semiconductor device, SLEEP1: signal, SN11: node, T1: time, T2: time, T6: time, T7: time, W1: data, W2: data, WBL_1: write bit line, WBL_N: write bit line, WWL_M: write word line, WWL_1: write word line, 10: semiconductor device, 10_n: semiconductor device , 10_1: semiconductor device, 11: layer, 12: layer, 20: memory circuit section, 20_N: memory circuit section, 20_1: memory circuit section, 20_4: memory circuit section, 20_6: memory circuit section, 21: memory circuit, 21_N: memory circuit, 21_P: memory circuit, 21A: memory circuit, 21B: memory circuit, 21C: memory circuit, 22: transistor, 23: semiconductor layer, 24: multiplication circuit, 25: addition circuit, 26: register, 30: arithmetic circuit, 30_N: arithmetic circuit, 30_1: arithmetic circuit, 30_4: arithmetic circuit, 30_6: arithmetic circuit, 40: switching circuit, 40_1: switching circuit, 40_4: switching circuit, 40_6: switching circuit, 50: drive circuit, 60: memory circuit, 61: transistor, 61_N: transistor, 61_P: transistor, 61A: transistor, 61B: transistor, 62: transistor, 62_N: transistor, 62_P: transistor, 62B: transistor, 63: transistor, 63_N: transistor, 63_P: transistor, 64: capacitance element, 64_N: capacitance element, 64_P: capacitance element, 64A: capacitance element, 64B: capacitance element, 71: controller, 71G: controller, 72: row decoder,73: Word line driver, 74: Column decoder, 75: Driver, 76: Precharge circuit, 81: Input / output buffer, 82: Arithmetic control circuit, 90A: Input layer, 90B: Hidden layer, 90C: Output layer, 91: Input processing, 92: Arithmetic processing, 93: Arithmetic processing, 94: Pooling arithmetic processing, 95: Arithmetic processing, 96: Pooling arithmetic processing, 97: Fully connected arithmetic processing, 100: Semiconductor device, 101: Digital arithmetic unit, 102: Analog arithmetic unit, 103: Oxide semiconductor memory, 104: Oxide semiconductor memory, 105: Oxide semiconductor arithmetic unit, 106: Oxide semiconductor memory, 1 07: silicon circuit, 110: CPU, 120: bus, 193: PMU, 200: CPU core, 202: cache memory device, 203: cache memory device, 205: bus interface unit, 210: power switch, 211: power switch, 212: power switch, 214: level shifter, 220: flip-flop, 221: scan flip-flop, 221A: clock buffer circuit, 222: backup circuit, 300: transistor, 310: substrate, 310A: substrate, 312: element isolation layer, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 411: insulator, 412: insulator, 413: insulator, 414: insulator, 416: conductor, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 514: insulator, 516: insulator body, 518: conductor, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530ba: region, 530bb: region, 530bc: region, 540: conductor, 540a: conductor, 540b: conductor, 541: insulator, 541a: insulator, 541b: insulator, 542: conductor, 542a: conductor, 542b: conductor, 543: oxide, 543a: oxide, 543b: oxide, 544: insulator, 546: conductor, 550: insulator, 550a: insulator, 550b: insulator, 552: insulator, 554: insulator, 560: conductor,560a: conductor, 560b: conductor, 571: insulator, 571a: insulator, 571b: insulator, 574: insulator, 576: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitance element, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 650: insulator, 660: conductor, 4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: semiconductor device, 4711: mold, 4712: land, 4713: electrode pad, 47 14: Wire, 4730: Electronic component, 4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit unit, 4803: Spacing, 4803a: Spacing, 5200: Portable game machine, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main body, 5302: Display, 5303: Keyboard, 5500: Information terminal ,5510: Housing, 5511: Display, 5600: TV, 5650: Antenna, 5670: Radio tower, 5675A: Radio waves, 5675B: Radio waves, 5680: Broadcasting station, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal, 5901: Housing, 5902: Display, 5903: Operation button, 5904: Operator, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Board, 6 105: Chip, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation button, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Housing, 6302: Housing, 6303: Display unit, 6304: Operation key, 6305: Lens, 6306: Connection unit, 6431: Housing, 6432: Display unit, 6433: Palm print reader, 6434: Wiring, 6435: Hand, 7500: Stationary game console, 7520: Main unit, 7522: Controller,

Claims

1. an analog computing unit and a memory circuit; the analog computing unit and the memory circuit each include a transistor having an oxide semiconductor in a channel formation region; the memory circuit has a function of supplying the weight data as analog data to the analog computing unit; the analog computing unit has a function of performing a product-sum operation using the weight data, At least one of the transistors included in the analog computing unit and the memory circuit and having an oxide semiconductor in a channel formation region, The amount of current flowing between the source and drain of the semiconductor device is the amount of current that flows when the transistor operates in the subthreshold region.

2. In claim 1, The semiconductor device, wherein the oxide semiconductor is indium oxide.

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