Floating-point conversion method, apparatus, chip, device, and medium

Abstract

To provide a method, apparatus, and program for reducing the precision of floating-point numbers by rounding a mantissa of a floating-point number to reduce computational and storage overhead.SOLUTION: A method includes: Step S201 of determining, for a floating-point number to be converted, exponent data and mantissa data of the floating-point number; Step S203 of determining an exponent value of the floating-point number; Step S204 of concatenating first padding data to the left of the mantissa data to determine first concatenated data; Step S205 of performing, based on the exponent value of the floating-point number, a first left-shift operation on the first concatenated data to determine first intermediate data; Step S206 of determining, based on the exponent value and the mantissa data, a carry amount of the floating-point number; Step S207 of performing, in response to the carry amount of the floating-point number indicating that a carry occurs during the floating-point rounding normalization, a carry operation on a first part of the first intermediate data; and Step S208 of determining a normalized floating-point number corresponding to the floating-point number.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to the field of computer technology, particularly to the field of data processing and chip technology, and specifically to methods, apparatus, chips, electronic devices, computer-readable storage media and computer program products for floating-point conversion. [Background technology]

[0002] Artificial intelligence is a field that studies how computers can imitate some human thought processes and intelligent behaviors (e.g., learning, reasoning, thinking, planning, etc.), and includes both hardware and software technologies. AI hardware technologies generally include sensors, AI-specific chips, cloud computing, distributed storage, and big data processing, while AI software technologies mainly include several major areas such as computer vision technology, speech recognition technology, natural language processing technology, machine learning / deep learning, big data processing technology, and knowledge graph technology.

[0003] In modern computing devices, floating-point numbers are used to represent large amounts of data and perform complex calculations. In some computing scenarios, it may be desirable to reduce the precision of a floating-point number (e.g., rounding the mantissa of a floating-point number to reduce the precision of the floating-point number). Therefore, rounding the mantissa may be selected to meet the requirements of subsequent processing, such as image processing or signal processing, to reduce computational and storage burdens. The methods described in this section are not necessarily methods previously conceived or adopted. Unless otherwise specified, any method described in this section should not be considered prior art solely for its inclusion in this section. Similarly, unless otherwise specified, the problems mentioned in this section should not be considered to be acknowledged in any prior art. Summary of the Invention

[0004] The present disclosure provides a method for floating-point conversion, an apparatus for floating-point conversion, a chip, an electronic device, a computer-readable storage medium, and a computer program product.

[0005] According to one aspect of the present disclosure, a method for floating-point conversion is provided, comprising: determining exponent data and mantissa data of a floating-point number to be converted; determining an exponent value of the floating-point number, which is a power value corresponding to the floating-point number, based on the exponent data and mantissa data, in response to the floating-point conversion being a rounded normalization of the floating-point number; concatenating first padding data, including a first predetermined number of 1s equal to or greater than the bit width of the mantissa data, to the left of the mantissa data in response to the exponent value of the floating-point number being smaller than a bit width of the mantissa data; determining first concatenated data; performing a first left-shift operation on the first concatenated data based on the exponent value of the floating-point number; determining first intermediate data; and determining a carry-up operation that occurs in the rounded normalization of the floating-point number based on the exponent value and mantissa data of the floating-point number. determining a carry amount of the floating-point number indicating whether an overflow will occur when a carry occurs in the rounding normalization of the floating-point; in response to the carry amount of the floating-point number indicating the occurrence of a carry in the rounding normalization of the floating-point, performing a carry operation on a retained portion corresponding to the first padding data in the first intermediate data and a first portion of the first intermediate data which is data of a retained bit of the mantissa data; determining second intermediate data and an overflow variable, wherein a bit width of the first portion of the first intermediate data is equal to a difference between the bit width of the mantissa data and one, and the overflow variable indicates whether an overflow will occur when a carry occurs in the rounding normalization of the floating-point; and determining a normalized floating-point number corresponding to the floating-point number based on the exponent value of the floating-point number, the second intermediate data, and the overflow variable.

[0006] According to one aspect of the present disclosure, there is provided an apparatus for floating-point conversion, the apparatus including: a pre-processing module configured to determine exponent data and mantissa data of a floating-point number for a floating-point number to be converted; a first data determination unit configured to determine an exponent value of the floating-point number, which is a power value corresponding to the floating-point number, based on the exponent data and the mantissa data; a first data concatenation unit configured to concatenate first padding data, including a first predetermined number of 1's equal to or greater than the bit width of the mantissa data, to the left of the mantissa data in response to the exponent value of the floating-point number being smaller than the bit width of the mantissa data, to determine first concatenated data; a first left-shift unit configured to perform a first left-shift operation on the first concatenated data based on the exponent value of the floating-point number, to determine first intermediate data; and a floating-point number determining unit configured to determine first intermediate data based on the exponent value and the mantissa data of the floating-point number, which indicates whether a carry-up will occur in rounding normalization of the floating-point number. and a floating-point normalization module including: a carry amount determination unit configured to determine a carry amount of a point number; a first carry unit configured to, in response to the carry amount of the floating-point number indicating the occurrence of a carry in the floating-point rounding normalization, perform a carry operation on a first portion of the first intermediate data, which is data of a retained bit of the mantissa data and a retained portion corresponding to first padding data in the first intermediate data, and determine second intermediate data and an overflow variable, wherein the bit width of the first portion of the first intermediate data is equal to the difference between the bit width of the mantissa data and 1, and the overflow variable indicates whether an overflow occurs when a carry occurs in the floating-point rounding normalization; and a first floating-point number determination unit configured to determine a normalized floating-point number corresponding to the floating-point number based on the exponent value of the floating-point number, the second intermediate data, and the overflow variable.

[0007] According to one aspect of the present disclosure, there is provided a chip including an apparatus for floating-point conversion as described above.

[0008] According to one aspect of the present disclosure, there is provided an electronic device including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method for floating-point conversion described above.

[0009] According to one aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon computer instructions for causing the computer to perform the method for floating-point conversion described above.

[0010] According to one aspect of the present disclosure, there is provided a computer program product including a computer program, wherein the computer program when executed by a processor is capable of implementing the method for floating-point conversion described above.

[0011] According to one or more embodiments of the present disclosure, a floating-point number with high mantissa precision in floating-point rounding normalization can be directly converted to a floating-point number with low mantissa precision without first converting it to an integer type number and then converting it to a floating-point number with low mantissa precision, and the mantissa of the floating-point number can determine whether a carry overflow occurs due to rounding up, thereby achieving accurate and efficient floating-point rounding normalization.

[0012] It should be understood that the material described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily apparent from the following specification. [Brief explanation of the drawings]

[0013] The drawings illustratively illustrate examples, constitute a part of the specification, and together with the written description serve to explain exemplary embodiments of the examples. The illustrated examples are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar, but not necessarily identical, elements.

[0014] [Figure 1] 1 is a schematic diagram of an example system in which various methods described herein may be implemented, according to an example embodiment of the present disclosure. [Figure 2] 1 is a flowchart illustrating a method for floating-point conversion, according to an exemplary embodiment of the present disclosure. [Figure 3A] FIG. 10 is a schematic diagram illustrating a process of performing a first left shift operation on first concatenated data according to an exemplary embodiment of the present disclosure. [Figure 3B] FIG. 10 is a schematic diagram illustrating a process of performing a first left shift operation on first concatenated data according to an exemplary embodiment of the present disclosure. [Figure 4A] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 4C] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 4D] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 5A] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 5B] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 5C] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 5D] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 5E] FIG. 10 is a schematic diagram illustrating a process of performing a carry operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure. [Figure 6A] FIG. 2 is a schematic diagram illustrating a process for determining mantissa data of a normalized floating-point number according to an exemplary embodiment of the present disclosure. [Figure 6B] FIG. 2 is a schematic diagram illustrating a process for determining mantissa data of a normalized floating-point number according to an exemplary embodiment of the present disclosure. [Figure 6C] FIG. 2 is a schematic diagram illustrating a process for determining mantissa data of a normalized floating-point number according to an exemplary embodiment of the present disclosure. [Figure 6D] FIG. 2 is a schematic diagram illustrating a process for determining mantissa data of a normalized floating-point number according to an exemplary embodiment of the present disclosure. [Figure 7A] 1 is a flowchart illustrating a method for floating-point conversion, according to an exemplary embodiment of the present disclosure. [Figure 7B] 1 is a flowchart illustrating a method for floating-point conversion, according to an exemplary embodiment of the present disclosure. [Figure 8A] FIG. 10 is a schematic diagram illustrating a process of performing a third left shift operation on the second concatenated data according to an exemplary embodiment of the present disclosure. [Figure 8B] FIG. 10 is a schematic diagram illustrating a process of performing a third left shift operation on the second concatenated data according to an exemplary embodiment of the present disclosure. [Figure 9] 1 is a structural schematic diagram illustrating an apparatus for floating-point conversion according to an exemplary embodiment of the present disclosure; [Figure 10] FIG. 1 is a block diagram illustrating an exemplary electronic device capable of implementing an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0023] The following describes exemplary embodiments of the present disclosure in conjunction with the drawings. For ease of understanding, various details of the embodiments of the present disclosure are included therein, but they should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, the following description omits descriptions of known functions and structures.

[0016] In this disclosure, unless otherwise specified, the use of terms such as "first," "second," etc. to describe various elements is not intended to limit the location, timing, or importance of these elements. Such terms are used only to distinguish one element from another. In some instances, a first element and a second element may refer to the same instance of the element, or in some cases, may refer to different instances based on the context.

[0017] The terms used in the description of various examples of the present disclosure are intended only to describe particular examples and are not intended to be limiting. Unless the context clearly indicates otherwise, and unless the number of elements is specifically limited, the element may be one or more. Furthermore, as used in this disclosure, the term "and / or" covers any and all possible combinations of the listed items.

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0019] 1 illustrates a schematic diagram of an exemplary system 100 in which various methods and apparatus described herein may be implemented, according to embodiments of the present disclosure. Referring to FIG. 1, the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 may be configured to run one or more applications.

[0020] In an embodiment of the present disclosure, the server 120 may run one or more services or software applications that enable methods for floating-point conversion to be performed.

[0021] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtualized and virtualized environments. In some embodiments, these services may be provided as web-based or cloud services, for example, provided to users of client devices 101, 102, 103, 104, 105, and / or 106 in a Software as a Service (SaaS) model.

[0022] In the configuration shown in FIG. 1 , server 120 may include one or more assemblies that implement the functionality performed by server 120. These assemblies may include software assemblies, hardware assemblies, or a combination thereof that are executable by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 may, in turn, utilize one or more client applications to interact with server 120 to access services provided by these assemblies. It should be understood that a variety of different system configurations are possible and may differ from system 100. Accordingly, FIG. 1 is intended to be illustrative of an example system for implementing various methods described herein and is not intended to be limiting.

[0023] Users may use client devices 101, 102, 103, 104, 105, and / or 106 to submit data processing tasks to be performed or data to be processed. The client devices may provide an interface through which a user of the client device interacts with the client device. The client devices may also output information to the user through the interface. Although only six client devices are shown in FIG. 1, one skilled in the art will understand that the present disclosure can support any number of client devices.

[0024] Client devices 101, 102, 103, 104, 105, and / or 106 may include various types of computing devices, such as portable handheld devices, general-purpose computers (e.g., personal computers or laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors and other sensing devices, etc. These computing devices may run various types and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (e.g., Google Chrome OS), and may include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, Android, etc. Portable handheld devices may include mobile phones, intelligent phones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (e.g., smart glasses) and other devices. Gaming systems may include various handheld gaming devices, Internet-enabled gaming devices, etc. The client device may run a variety of applications, such as Internet-related applications, communication applications (eg, email applications), and short message service (SMS) applications, and may use a variety of communication protocols.

[0025] Network 110 may be any type of network known to those skilled in the art that is capable of supporting data communications using any of a variety of available protocols (including, but not limited to, TCP / IP, SNA, IPX, etc.) By way of example, one or more networks 110 may be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0026] Server 120 may include one or more general-purpose computers, dedicated server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframes, server clusters, or any other suitable configuration and / or combination. Server 120 may also include one or more virtual machines running virtual operating systems or other computing architectures involving virtualization (e.g., one or more flexible pools of virtualized logical storage devices to maintain the server's virtual storage devices). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0027] The computing units in server 120 may run one or more operating systems, including any of the operating systems listed above and any commercial server operating system. Server 120 may also run any one of a variety of additional server and / or middle-tier applications, such as an HTTP server, an FTP server, a CGI server, a JAVA server, a database server, etc.

[0028] In some embodiments, server 120 may include one or more applications for analyzing and consolidating data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0029] In some embodiments, server 120 may be a server in a distributed system or a server incorporating blockchain. Server 120 may be a cloud server, or a smart cloud computing server or smart cloud host equipped with artificial intelligence technology. A cloud server is a host product in a cloud computing service system that solves the drawbacks of traditional physical hosts and virtual private server (VPS) services, such as high management difficulty and poor service scalability.

[0030] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data or other information. For example, one or more of databases 130 may be used to store information such as audio files or video files. Databases 130 may be located in a variety of locations. For example, a database used by server 120 may be local to server 120 or may be remote from server 120 and in communication with server 120 over a network or dedicated connection. Databases 130 may be of different types. In some embodiments, a database used by server 120 may be a relational database. One or more of these databases may store, update, and retrieve data from the databases in response to instructions.

[0031] In some embodiments, one or more of databases 130 may be used by an application to store data for the application. The databases used by the application may be different types of databases, such as key-value repositories, object repositories, general-purpose repositories backed by a file system, etc.

[0032] The system 100 of FIG. 1 can be configured and operated in a variety of ways to accommodate the various methods and apparatus described in accordance with this disclosure.

[0033] The prior art provides only a conversion circuit from a floating-point number to an integer-type numeric value, but does not provide a circuit that realizes floating-point rounding normalization that directly converts a floating-point number with a high mantissa precision into a floating-point number with a low mantissa precision.

[0034] Therefore, the present disclosure provides a method for floating-point conversion, which realizes a floating-point number with high mantissa precision in floating-point rounding normalization to be directly converted to a floating-point number with low mantissa precision without first converting it to an integer type number and then converting it to a floating-point number with low mantissa precision, and further, the mantissa of the floating-point number can determine whether a carry overflow occurs due to rounding up, thereby achieving accurate and efficient floating-point rounding normalization.

[0035] 2 is a flowchart illustrating a method 200 for floating-point conversion in accordance with an exemplary embodiment of the present disclosure. As shown in FIG. 2, the method 200 for floating-point conversion includes: Step S201 of determining exponent data and mantissa data of a floating-point number to be converted; step S202, determining whether the floating-point conversion is a floating-point rounding normalization, where if step S202 is "yes", proceeding to step S203; Step S203 of determining an exponent value of the floating-point number, which is a power value corresponding to the floating-point number, based on the exponent data and the mantissa data; a step S204 of concatenating first padding data including a first predetermined number of 1's, which is equal to or greater than the bit width of the mantissa data, to the left side of the mantissa data in response to the exponent value of the floating-point number being smaller than the bit width of the mantissa data, to determine first concatenated data; a step S205 of performing a first left shift operation on the first concatenated data based on the exponent value of the floating-point number to determine first intermediate data; Step S206: determining a carry amount of the floating-point number based on the exponent value and mantissa data of the floating-point number, and the carry amount of the floating-point number indicates whether a carry amount occurs in the rounding normalization of the floating-point number; step S207, in response to the carry amount of the floating-point number indicating the occurrence of a carry in the rounding normalization of the floating-point number, performing a carry operation on a first portion of the first intermediate data, and determining second intermediate data and an overflow variable, the first portion of the first intermediate data being data of a retained portion corresponding to first padding data in the first intermediate data and a retained bit of the mantissa data, the bit width of the first portion of the first intermediate data being equal to the difference between the bit width of the mantissa data and 1, and the overflow variable indicating whether an overflow will occur when the carry occurs in the rounding normalization of the floating-point number; and step S208 of determining a normalized floating-point number corresponding to the floating-point number based on the exponent value of the floating-point number, the second intermediate data, and the overflow variable.

[0036] In the embodiments described in the present disclosure, a floating-point number with high mantissa precision in floating-point rounding normalization does not need to be first converted into an integer type number and then converted into a floating-point number with low mantissa precision, but is directly converted into a floating-point number with low mantissa precision, and the mantissa of the floating-point number can determine whether a carry overflow occurs due to rounding up, thereby achieving accurate and efficient floating-point rounding normalization.

[0037] According to some embodiments, in step S201, exponent data and mantissa data of the floating-point number are determined based on the floating-point number standard and / or floating-point number type used by the floating-point number. For example, taking a single-precision floating-point number (32 bits) as an example, the floating-point number consists of three parts: 1 sign bit, 8 exponent bits, and 23 mantissa bits. Therefore, the exponent data and mantissa data of the floating-point number can be determined by extracting bits at specific bit positions of the floating-point number. For example, for the floating-point number "01000001001101100000000000000000", the exponent data from the second to ninth bits is "10000010", and the mantissa data from the tenth to 32nd bits is "01101100000000000000000".

[0038] According to some embodiments, floating-point rounding normalization is a floating-point number conversion, in which the mantissa of the floating-point number is regarded as an integer and undergoes integer type conversion and rounding, while the overall representation format of the floating-point number is not changed, and in which, when the mantissa is carried over, if an overflow occurs, the exponent part of the floating-point number is correspondingly adjusted, i.e., the exponent value corresponding to the exponent part of the floating-point number is modified by adding 1.

[0039] According to some embodiments, the rounding types of floating-point round normalization may include round up conversion, round down conversion, round towards zero conversion, and round to nearest even conversion.

[0040] According to some embodiments, in step S203, determining a carry amount and an exponent value of the floating-point number based on the exponent data and the mantissa data includes: determining an exponent value of the floating-point number based on the exponent data; and determining a carry amount of the floating-point number based on the exponent value and the mantissa data of the floating-point number.

[0041] According to some embodiments, determining the exponent value of the floating-point number based on the exponent data includes obtaining the exponent value of the floating-point number by subtracting the exponent bias from a numerical value corresponding to the exponent data. For example, for the floating-point number "01000001001101100000000000000000", the exponent data is "10000010", the corresponding decimal data is "130", and the bias 127 is subtracted therefrom to obtain the exponent value of 3.

[0042] According to some embodiments, determining a carry amount for the floating-point number based on an exponent value and mantissa data of the floating-point number includes: determining a reserve bit and a round bit corresponding to the mantissa data based on the exponent value and mantissa data of the floating-point number; and determining a carry amount for the floating-point number based on a round bit, a least significant bit of the reserve bit, and sign data corresponding to the mantissa data.

[0043] According to some embodiments, determining a carry amount for the floating-point number based on the round bit corresponding to the mantissa data, the least significant bit of the retained bits, and the sign data includes determining a carry amount for the floating-point number based on the round bit corresponding to the mantissa data, the least significant bit of the retained bits, the sign data, and a type of rounding conversion.

[0044] According to some embodiments, the method described herein further includes: determining sign data of the floating-point number and determining a carry amount for the floating-point number based on an exponent value and mantissa data of the floating-point number includes determining a carry amount for the floating-point number based on the mantissa data, the exponent value, the sign data of the floating-point number, and a type of floating-point rounding normalization, where the floating-point rounding normalization is round-up rounding mode conversion, round-down conversion, round-to-nearest-even conversion, or round-to-zero conversion.

[0045] For example, when converting to zero, no carry occurs.

[0046] For example, for a round up conversion, no rounding is performed for negative numbers, and for positive numbers, rounding is performed only if there is a non-zero value in the rounding bit of the mantissa data, i.e., a carry is performed.

[0047] For example, for a floor conversion, no rounding is done for positive numbers, and a rounding is performed for negative numbers if the discarded part is non-zero.

[0048] For example, in the case of rounding conversion to the nearest even number, if the data in the rounding bits is greater than 0.5 (the most significant bit of the rounding bits is 1 and there are non-zero bits after that), carry is performed; if the data in the rounding bits is equal to 0.5 (the most significant bit of the rounding bits is 1 and all subsequent bits are 0), the least significant bit of the retained bits of the mantissa data is examined, and if the least significant bit of the retained bits is odd, carry is performed; if the least significant bit of the retained bits is even, no carry is performed; and if the data in the rounding bits is less than 0.5 (the most significant bit of the rounding bits is 0), no carry is performed.

[0049] According to some embodiments, in step S204, in response to the exponent value of the floating-point number being smaller than the bit width of the mantissa data, first padding data is concatenated to the left side of the mantissa data to determine first concatenated data, where the least significant bit of the first predetermined number of 1s in the first padding data is 1 corresponding to the hidden leading bit of the mantissa data of the floating-point number, and for example, in the IEEE 754 standard, the floating-point value satisfies the following formula (1):

number

[0050] 3A-3B are schematic diagrams illustrating a process of performing a first shift-left operation on first concatenated data according to an exemplary embodiment of the present disclosure.

[0051] As shown in Figure 3A, a first predetermined number of 1's are concatenated to the left side of the mantissa data to form first concatenated data, where bits marked with "X" indicate corresponding bits of the mantissa data. As shown in Figure 3B, the first concatenated data is shifted left by the number of bits of the exponent value of the floating-point number, thereby removing some embedded 1's, to obtain first intermediate data.

[0052] According to some embodiments, the carry amount of the floating-point number is determined by determining the second intermediate part based on the first part of the first intermediate data by indicating whether a carry occurs in the rounding normalization of the floating-point number, wherein the first part of the first intermediate data is a retained part corresponding to the first padding data in the first intermediate data and data of the retained bits of the mantissa data. For example, as shown in FIG. 3B, the first part of the first intermediate data is a retained part of the first padding data and retained bits of the mantissa data retained in the first intermediate data after a first left shift operation (in the example shown in FIG. 3B, the first concatenated data is moved leftward by the number of bits of the exponent value of the floating-point number), i.e., the first part of the first intermediate data corresponds to (mantissa bit width - 1) bits to the left of the decimal point corresponding position.

[0053] In the embodiment described in the present disclosure, the concatenation and subsequent shift operations are performed only when the exponent value of the floating-point number is smaller than the bit width of the mantissa data, so that the number of bits of the first portion of the first intermediate data is the mantissa bit width minus 1, thereby reducing the number of bits of data required for subsequent processing. According to some embodiments, performing a carry operation on the first portion of the first intermediate data and determining the second intermediate data and overflow variable in response to the carry amount of the floating-point number indicating the occurrence of a carry in the floating-point rounding conversion includes performing an operation of adding 1 to a least significant bit of the first portion of the first intermediate data to determine the second intermediate data; setting the overflow variable in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data causing an overflow, to indicate that an overflow occurred when a carry occurred in the floating-point rounding normalization; and setting the overflow variable in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data not causing an overflow, to indicate that an overflow did not occur when a carry occurred in the floating-point rounding normalization.

[0054] According to some embodiments, in response to a carry amount of the floating-point number indicating the occurrence of a carry in the round normalization of the floating-point number, a carry operation is performed by adding 1 to the least significant bit of the first portion of the first intermediate data.

[0055] According to some embodiments, a first portion of the first intermediate data is cropped, the first portion of the first intermediate data is determined (e.g., the first portion of the first intermediate data is extracted and other portions of the first intermediate data are discarded), and the cropped first portion of the first intermediate data is rounded up, and second intermediate data and an overflow variable are determined.

[0056] 4A-4D are schematic diagrams illustrating a process of performing a carry-up operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure.

[0057] As shown in Figure 4A, as already shown in Figure 2 (e.g., step S205 in Figure 2) and Figure 3B, a first left shift operation is performed on the first concatenated data to determine first intermediate data, where the (mantissa bit width - 1) bits to the left of the decimal point corresponding position in the first intermediate data are the first part.

[0058] According to some embodiments, a crop is performed on the first portion of the first intermediate data to determine the first portion of the first intermediate data, for example, as shown in FIG. 4B, extracting the first portion in the first intermediate data and discarding other portions of the first intermediate data.

[0059] According to some embodiments, 1 is added to the least significant bit of the first portion of the first intermediate data, i.e., rounding up is performed on the least significant bit of the first portion of the first intermediate data, as shown in FIG. 4B.

[0060] According to some embodiments, as shown in FIG. 4C , when adding 1 to the first portion of the first intermediate data and no overflow occurs, the result of adding 1 to the least significant bit of the first portion of the first intermediate data becomes the second intermediate data, and an overflow variable is set to indicate that no overflow occurred when a carry occurs in floating-point rounding normalization.

[0061] According to some embodiments, as shown in FIG. 4D, when an overflow occurs by adding 1 to the first portion of the first intermediate data, all bits of the second intermediate data become 0, and an overflow variable is set to indicate that an overflow occurs when a carry occurs in floating-point rounding normalization.

[0062] According to some embodiments, a rounding operation is performed on a first portion of the first intermediate data to determine the rounded data and an overflow variable, and a truncation operation is performed on the first portion of the rounded data to determine the second intermediate data, wherein the first portion of the rounded data is a bit in the rounded data that corresponds to the first portion of the first intermediate data, i.e., (mantissa bit width - 1) bits in the rounded data from the least significant bit corresponding to the mantissa data (including the least significant bit corresponding to the mantissa data) to the left.

[0063] 5A-5E are schematic diagrams illustrating a process of performing a carry-up operation on a first portion of first intermediate data according to an exemplary embodiment of the present disclosure.

[0064] As shown in Figure 5A, as already shown in Figure 2 (for example, step S205 in Figure 2) and Figure 3B, a first left shift operation is performed on the first concatenated data to determine first intermediate data, where the (mantissa bit width - 1) bits to the left of the decimal point corresponding position in the first intermediate data are the first part.

[0065] According to some embodiments, as shown in FIG. 5B, when an overflow does not occur when adding 1 to the least significant bit of the first portion of the first intermediate data, the overflow variable is set to indicate that no overflow occurred when a carry occurs in floating-point rounding normalization, and the portion corresponding to the mantissa data in the carried data is data that has already taken into account the effects of the rounding carry (i.e., the bit indicated by the symbol "Y" in FIG. 5B indicates the portion corresponding to the mantissa data).

[0066] According to some embodiments, as shown in FIG. 5C, a first portion of the carried data is truncated to determine second intermediate data, where the second intermediate data is a bit in the carried data corresponding to the first portion of the first intermediate data, i.e., (mantissa bit width-1) bits in the carried data from the least significant bit corresponding to the mantissa data (including the least significant bit corresponding to the mantissa data) to the left.

[0067] According to some embodiments, as shown in FIG. 5D , when an overflow occurs by adding 1 to the least significant bit of the first portion of the first intermediate data, the overflow variable is set to indicate that an overflow occurs when a carry occurs in floating-point rounding normalization, and the bits to the left of the decimal point corresponding position in the carried data (i.e., the bit corresponding to the least significant bit of the mantissa data in the carried data and the bits to the left of that bit) are all 0.

[0068] According to some embodiments, as shown in Figure 5E, the first portion of the carried data in Figure 5D is truncated to determine second intermediate data, where the second intermediate data is bits in the carried data corresponding to the first portion of the first intermediate data, i.e., (mantissa bit width - 1) bits in the carried data from the least significant bit corresponding to the mantissa data (including the least significant bit corresponding to the mantissa data) to the left. According to another embodiment, to illustrate a case in which an overflow occurs when adding 1 to the least significant bit of the first portion of the first intermediate data in Figure 5D, all bits of the second intermediate data may be directly set to 0 without truncating as shown in Figure 5E.

[0069] According to some embodiments, in response to the carry amount of the floating-point number indicating the occurrence of a carry in the floating-point rounding conversion, performing a carry operation on the first portion of the first intermediate data and determining the second intermediate data and the overflow variable further includes: in response to the bits of the first portion of the first intermediate data being all 1, setting the overflow variable to indicate that an overflow occurred when a carry occurred in the floating-point rounding normalization, and setting the second intermediate data to all 0; and in response to the bits of the first portion of the first intermediate data not being all 1, setting the overflow variable to indicate that an overflow did not occur when a carry occurred in the floating-point rounding normalization, and performing an operation of adding 1 to the least significant bit of the first portion of the first intermediate data, and determining the second intermediate data.

[0070] According to some embodiments, when the bits of the first part of the first intermediate data are not all 1, the process of determining the second intermediate data by performing an operation of adding 1 to the least significant bit of the first part of the first intermediate data is similar to the description with reference to Figures 4A to 4D or Figures 5A to 5E above, that is, the first part may be first extracted from the first intermediate data and then an operation of adding 1 to the least significant bit of the first part may be performed, or the operation of adding 1 to the least significant bit of the first intermediate data may be first performed and then extracted, thereby determining the second intermediate data.

[0071] In some embodiments described herein, determining whether an overflow occurs when a carry occurs during floating-point rounding normalization is performed by determining whether all bits of the first portion of the first intermediate data are 1. According to some embodiments, determining a normalized floating-point number corresponding to the floating-point number based on the exponent value of the floating-point number, the second intermediate data, and the overflow variable includes performing a second left-shift operation on the second intermediate data based on the exponent value of the floating-point number to determine third intermediate data, concatenating one zero to the right of the third intermediate data to determine mantissa data of the normalized floating-point number, and determining the exponent data of the normalized floating-point number based on the exponent value of the floating-point number and the overflow variable.

[0072] 6A-6B are schematic diagrams illustrating a process 600 for determining mantissa data of a normalized floating-point number when the carry amount of the floating-point number indicates the occurrence of a carry in the round normalization of the floating-point number, according to an exemplary embodiment of the present disclosure.

[0073] According to some embodiments, as shown in Figures 6A to 6B, the corresponding bits of the first padding data are removed by shifting the second intermediate data to the left, for example, by shifting the second intermediate data to the left by (mantissa bit width - exponent value - 1) bits, where the bit indicated by the symbol "Y" indicates the corresponding bit of the mantissa data in the second intermediate data, for example, the bit corresponding to the mantissa data in the second intermediate data indicated by the symbol "Y" in Figures 4C and 5C.

[0074] According to some embodiments, one 0 is concatenated to the right side of the third intermediate data, and the bit width is expanded from (mantissa bit width - 1) bits to data of the mantissa bit width, i.e., it becomes the mantissa data of a normalized floating-point number.

[0075] In some embodiments, when the overflow variable indicates that an overflow occurs, the process of determining the third intermediate data by performing the second left shift operation on the second intermediate data as described above may be omitted, and all bits of the third intermediate data may be directly set to 0, and one 0 may be concatenated to the right of the third intermediate data to obtain the mantissa data of the normalized floating-point number, i.e., the mantissa bit width 0s.

[0076] According to some embodiments, determining exponent data of the normalized floating-point number based on the exponent value of the floating-point number and the overflow variable includes: setting the exponent data of the normalized floating-point number to indicate that the exponent value of the normalized floating-point number is the sum of the exponent value of the original floating-point number plus 1, in response to an overflow occurring when the overflow variable of the floating-point number indicates that a carry has occurred in the rounding normalization of the floating-point; and setting the exponent data of the normalized floating-point number to indicate that the exponent value of the normalized floating-point number is the exponent value of the original floating-point number, in response to an overflow not occurring when the overflow variable of the floating-point number indicates that a carry has occurred in the rounding normalization of the floating-point.

[0077] According to some embodiments, the exponent data of the normalized floating-point number may be set to the exponent value of the normalized floating-point number plus an exponent bias.

[0078] According to some embodiments, the method described in the present disclosure further includes, in response to the floating-point conversion being a rounded normalization of a floating-point, and in response to the carry amount of the floating-point number indicating that no carry occurred in the rounded normalization of the floating-point, performing a second left-shift operation on a first portion of the first intermediate data based on an exponent value of the floating-point number to determine fourth intermediate data, concatenating one zero to the right of the fourth intermediate data, determining mantissa data of the normalized floating-point number, and determining exponent data of the normalized floating-point number based on the exponent value of the floating-point number.

[0079] 6C-6D are schematic diagrams illustrating a process 600 for determining mantissa data of a normalized floating-point number when the carry amount of the floating-point number indicates that no carry occurred in the round normalization of the floating-point number, according to an exemplary embodiment of the present disclosure.

[0080] According to some embodiments, a first portion of the first intermediate data is cut out from the first intermediate data, for example, as shown in FIG. 4B, the first portion in the first intermediate data is extracted and other portions of the first intermediate data are discarded.

[0081] According to some embodiments, as shown in Figures 6C-6D, the first portion of the first intermediate data is shifted leftward to remove the corresponding bits of the first padding data, and third intermediate data is obtained, for example, the first portion of the first intermediate data is shifted leftward by (mantissa bit width-exponent value-1) bits, where the bits indicated by the symbol "X" indicate the corresponding bits of the mantissa data in the first portion.

[0082] According to some embodiments, one 0 is concatenated to the right side of the third intermediate data, and the data having a bit width of (mantissa bit width - 1) bits is extended to the bits of the mantissa bit width, i.e., the mantissa data of the normalized floating-point number.

[0083] According to some embodiments, determining exponent data of the normalized floating-point number based on the exponent value of the floating-point number includes setting the exponent data of the normalized floating-point number to indicate that the exponent value of the normalized floating-point number is the exponent value of the original floating-point number.

[0084] According to some embodiments, the exponent data of the normalized floating-point number may be set to the exponent value of the normalized floating-point number plus an exponent bias.

[0085] According to some embodiments, the method disclosed herein is performed in response to the floating-point conversion being a rounded normalization of a floating-point number, and further in response to the exponent value of the floating-point number being equal to or greater than the bit width of the mantissa data, by setting a normalized floating-point number corresponding to the floating-point number to the floating-point number to be converted.

[0086] According to some embodiments, the method disclosed herein further includes: in response to the floating-point conversion being a conversion from a floating-point to an integer type, determining a carry amount and an exponent value of the floating-point number based on the exponent data and the mantissa data; in response to the exponent value of the floating-point number being smaller than an output bit width of the floating-point to integer type conversion, concatenating second padding data to the left of the mantissa data to determine second concatenated data, the second padding data including a second predetermined number of 0s and one 1, where the second predetermined number is equal to the difference between the bit width of the integer type of the floating-point conversion minus 1; performing a third left-shift operation on the second concatenated data based on the exponent value of the floating-point number; determining fifth intermediate data; and determining a rounded integer type numeric value of the floating-point number based on the carry amount of the floating-point number and the fifth intermediate data.

[0087] 7A-7B are flowcharts illustrating a method 700 for floating-point conversion, according to an exemplary embodiment of the present disclosure. As shown in FIGS. 7A-7B, method 700 includes: Step S701 of determining exponent data and mantissa data of a floating-point number to be converted; step S702, determining whether the floating-point conversion is a floating-point rounding normalization, where if step S702 is "yes", proceed to step S703, and if step S702 is "no", proceed to step S709; Step S703: determining an exponent value of the floating-point number based on the exponent data and the mantissa data, where the exponent value of the floating-point number is a power value corresponding to the floating-point number; Step S704: in response to the exponent value of the floating-point number being smaller than the bit width of the mantissa data, concatenate first padding data to the left side of the mantissa data to determine first concatenated data, where the first padding data includes a first predetermined number of 1's, and the first predetermined number is equal to or greater than the bit width of the mantissa data; Step S705: performing a first left-shift operation on the first concatenated data based on the exponent value of the floating-point number to determine first intermediate data; Step S706: determining a carry amount of the floating-point number based on the exponent value and mantissa data of the floating-point number, where the carry amount of the floating-point number indicates whether a carry occurs in rounding normalization of the floating-point number; Step S707: in response to the carry amount of the floating-point number indicating the occurrence of a carry in the rounding normalization of the floating-point number, performing a carry operation on a first portion of the first intermediate data, and determining second intermediate data and an overflow variable, where the first portion of the first intermediate data is a retained portion corresponding to first padding data in the first intermediate data and data of retained bits of the mantissa data, the bit width of the first portion of the first intermediate data is equal to the difference between the bit width of the mantissa data and 1, and the overflow variable indicates whether an overflow will occur when the carry occurs in the rounding normalization of the floating-point number; a step S708 of determining a normalized floating-point number corresponding to the floating-point number based on the exponent value of the floating-point number, the second intermediate data, and the overflow variable; a step S709 of determining an exponent value of the floating-point number based on the exponent data and the mantissa data; Step S710: in response to the exponent value of the floating-point number being smaller than the output bit width of the floating-point to integer conversion, concatenate second padding data to the left side of the mantissa data to determine second concatenated data, where the second padding data includes a second predetermined number of 0s and one 1, and the second predetermined number is equal to the difference between the bit width of the integer type numeric value of the floating-point conversion and 1; Step S711 of performing a third left shift operation on the second concatenated data based on the exponent value of the floating-point number to determine fifth intermediate data; a step S712 of determining a carry amount of the floating-point number based on the exponent value and mantissa data of the floating-point number; and step S713 of determining an integer type numeric value after rounding the floating point number based on the carry amount of the floating point number and the fifth intermediate data.

[0088] According to some embodiments, steps S701-708 are the same as or similar to steps S201-208, respectively.

[0089] According to some embodiments, after determining the exponent data and mantissa data of a floating-point number (i.e., step S201 in FIG. 2 or step S701 in FIG. 7A), for special cases of floating-point numbers, corresponding processing can be performed, and no subsequent processing is required.

[0090] According to some embodiments, the floating-point conversion is a floating-point to integer conversion, the output type is an unsigned integer, and in response to the sign data of the floating-point number being converted being 1, the converted integer number is set to 0, which indicates that the floating-point number being converted is a negative number.

[0091] According to some embodiments, in response to the bits of the exponent data of the floating-point number to be converted being all 1's and the mantissa data of the floating-point number to be converted being not all 0's, the floating-point number to be converted is of a Not a Number (NaN) type, and in this case, if the floating-point conversion is a rounded normalization of a floating-point number, the normalized floating-point number can be set to a NaN output format; and in response to the floating-point conversion being a conversion from a floating-point number to an integer type, the converted integer type number can be set to 0.

[0092] According to some embodiments, in response to the exponent value of the floating-point number to be converted being greater than or equal to the output bit width, or the exponent value of the floating-point number to be converted being equal to (output bit width-1) and the floating-point number to be converted being a signed number, if the floating-point conversion is a rounded normalization of a floating-point number, a normalized floating-point number can be set to the floating-point number to be converted, and if the floating-point conversion is a conversion from a floating-point to an integer type, the converted integer type number can be set to the maximum or minimum value of the corresponding type based on the sign bit. According to some embodiments, when the floating-point number to be converted is of infinity type, if the floating-point number to be converted is an unsigned number, the converted integer type numeric value is set to the maximum unsigned value; if the floating-point number to be converted is a signed number and the code data is 1, the converted integer type numeric value is set to the minimum signed number value (i.e., the most significant bit is 1 and all other bits are 0); and if the floating-point number to be converted is a signed number and the code data is 0, the converted integer type numeric value is set to the maximum signed number value (i.e., the most significant bit is 0 and all other bits are 1).

[0093] According to some embodiments, when an overflow occurs during a floating-point conversion, if the floating-point conversion is a rounded normalization of a floating-point number, the normalized floating-point number can be set to the target floating-point number; if the floating-point conversion is a floating-point to integer conversion, the converted integer type value can be set to the corresponding floating-point type based on the sign bit. According to some embodiments, when an overflow occurs during a floating-point conversion, if the target floating-point number is an unsigned number, the converted integer type value can be set to the maximum unsigned value; if the target floating-point number is a signed number and the sign data is 1, the converted integer type value can be set to the minimum signed value (i.e., the most significant bit is 1 and all other bits are 0); if the target floating-point number is a signed number and the sign data is 0, the converted integer type value can be set to the maximum signed value (i.e., the most significant bit is 0 and all other bits are 1).

[0094] According to some embodiments, in response to all bits of the exponent data of the floating-point number to be converted being 0 and all bits of the conversion data being 0, the floating-point number to be converted corresponds to 0. According to some embodiments, when the floating-point number to be converted corresponds to 0, if the floating-point conversion is a conversion from floating-point to an integer type, all bits of the converted integer type number are set to 0. According to some embodiments, if the floating-point conversion is a floating-point rounding normalization, a normalized floating-point number corresponding to the floating-point number is set to the floating-point number to be converted.

[0095] According to some embodiments, if all bits of the exponent data of the floating-point number to be converted are 0, and all bits of the mantissa data of the floating-point number to be converted are not 0, or if the exponent value of the floating-point number to be converted is less than -1, an underflow determination is performed, and a conversion corresponding value is set based on the result of the underflow determination. According to some embodiments, if the above-mentioned underflow determination conditions are met, in the underflow determination, if the sign data of the floating-point number to be converted is 0 and the rounding type is not round-up, or if the sign data of the floating-point number to be converted is 1 and the rounding type is not round-down, it is determined that an underflow has occurred; otherwise, it is determined that an underflow has not occurred.

[0096] According to some embodiments, when determining whether an underflow has occurred, if the floating-point conversion is a floating-point rounding normalization and the sign data of the floating-point number to be converted is 1, the sign data of the normalized floating-point number is set to 1, and the exponent data and mantissa data of the normalized floating-point number are set to 0; if the floating-point conversion is a floating-point rounding normalization and the sign data of the floating-point number to be converted is 0, the sign data of the normalized floating-point number is set to 0, and the exponent data and mantissa data of the normalized floating-point number are set to 0; and if the floating-point conversion is a conversion from floating-point to integer type, all of the converted integer type values ​​are set to 0.

[0097] According to some embodiments, when it is determined that no underflow has occurred, the floating-point conversion is floating-point rounding normalization, and if the sign data of the floating-point number to be converted is 1, the sign data of the normalized floating-point number is set to 1, the exponent data of the normalized floating-point number is set so that the most significant bit is 0 and the other bits are all 1, and all bits of the mantissa data of the normalized floating-point number are set to 0; or, if the floating-point conversion is floating-point rounding normalization, and the sign data of the floating-point number to be converted is 0, the sign data of the normalized floating-point number is set to 0, the exponent data of the normalized floating-point number is set so that the most significant bit is 0 and the other bits are all 1, and all bits of the mantissa data of the normalized floating-point number are set to 0. In some embodiments, when determining that an underflow has not occurred, if the floating-point conversion is from floating-point to integer and the sign data of the floating-point number to be converted is 1, the sign data of the converted integer number is set to 1 and all other bits of the converted integer number are set to 1; if the floating-point conversion is from floating-point to integer and the sign data of the floating-point number to be converted is 0, the least significant bit of the converted integer number is set to 1 and all other bits of the converted integer number are set to 0.

[0098] According to some embodiments, when the exponent value of the floating-point number to be converted is (-1), it is determined whether a carry-up will occur in the floating-point conversion of the floating-point number to be converted. According to some embodiments, when the exponent value of the floating-point number to be converted is (-1) and it is determined that a carry-up will occur in the floating-point conversion of the floating-point number to be converted, the output of the floating-point conversion is set based on the sign data of the floating-point number to be converted, where if the sign bit of the floating-point number to be converted is 1, the normalized floating-point number or the converted integer-type numeric value is set to a value corresponding to (-1), and if the sign bit of the floating-point number to be converted is 0, the normalized floating-point number or the converted integer-type numeric value is set to a value corresponding to 1.

[0099] According to some embodiments, if the exponent value of the floating-point number to be converted is (-1) and it is determined that no carry-over occurred in the floating-point conversion of the floating-point number to be converted, for floating-point rounding normalization, the sign data of the normalized floating-point number is set to the same value as the sign data of the floating-point number to be converted, and both the exponent data and the mantissa data of the normalized floating-point number are set to 0. For floating-point to integer conversion, the converted integer-type numeric value is set to a value corresponding to 0, for example, all bits of the converted integer-type numeric value are set to 0. Figures 8A and 8B are schematic diagrams illustrating a process of performing a third left-shift operation on the second concatenated data according to an exemplary embodiment of the present disclosure.

[0100] As shown in Figure 8A, a second predetermined number of 0s and one 1 are concatenated to the left side of the mantissa data to form second concatenated data, where the bits marked with "X" indicate the corresponding bits of the mantissa data. Also, as shown in Figure 8B, the second concatenated data is shifted left by the number of bits of the exponent value of the floating-point number to determine the integer part after the shifting process, i.e., the integer part after the shifting process is determined based on the part between the position of the hidden leading 1 and the corresponding position of the decimal point.

[0101] According to some embodiments, the first predetermined quantity is equal to the bit width of the integer type of the floating-point conversion, and the first left shift operation and the third left shift operation are performed by the same shifter. In the embodiments described in the present disclosure, by using the same shifter in the first left shift operation and the third left shift operation, the same circuit resources can be shared among different rounding conversions, thereby saving circuit costs.

[0102] According to another aspect of the present disclosure, there is further provided an apparatus for testing a cache memory. Figure 9 shows a block diagram of an apparatus 900 for testing a cache memory, where the cache memory is used to cache data stored in a main memory device, according to an exemplary embodiment of the present disclosure.As shown in FIG. 9 , the apparatus 900 includes a pre-processing module 901 configured to determine exponent data and mantissa data of a floating-point number to be converted; a first data determining unit 9021 configured to determine an exponent value of the floating-point number based on the exponent data and the mantissa data, where the exponent value of the floating-point number is a power value corresponding to the floating-point number; and a first data determining unit 9021 configured to concatenate first padding data to the left side of the mantissa data in response to the exponent value of the floating-point number being smaller than the bit width of the mantissa data, and to generate a first a first data concatenation unit 9022 configured to determine concatenated data, where the first padding data includes a first predetermined number of 1's, the first predetermined number being equal to or greater than a bit width of the mantissa data; a first left shift unit 9023 configured to perform a first left shift operation on the first concatenated data based on an exponent value of the floating-point number to determine first intermediate data; and a carry amount determination unit 90 configured to determine a carry amount of the floating-point number based on the exponent value and the mantissa data of the floating-point number. 24, wherein the carry amount of the floating-point number indicates whether a carry occurs in round normalization of the floating-point number; and a first carry unit 9025 configured to perform a carry operation on a first portion of the first intermediate data in response to the carry amount of the floating-point number indicating the occurrence of a carry in round normalization of the floating-point number, and determine second intermediate data and an overflow variable, wherein the first portion of the first intermediate data includes a hold portion corresponding to first padding data in the first intermediate data; and a floating-point normalization module 902 including: data of retained bits of mantissa data, wherein the bit width of a first portion of the first intermediate data is equal to the difference between the bit width of the mantissa data and 1; an overflow variable indicating whether an overflow occurs when a carry occurs in floating-point rounding normalization; and a first floating-point number determination unit 9026 configured to determine a normalized floating-point number corresponding to the floating-point number based on an exponent value of the floating-point number, the second intermediate data, and the overflow variable.

[0103] According to some embodiments, the first carry unit 9025 includes an adding subunit configured to perform an operation of adding 1 to the least significant bit of the first portion of the first intermediate data to determine second intermediate data; and an overflow setting subunit configured to, in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data causing an overflow, set an overflow variable to indicate that an overflow has occurred when a carry occurs in floating-point rounding normalization, and to, in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data causing no overflow, set the overflow variable to indicate that an overflow has not occurred when a carry occurs in floating-point rounding normalization.

[0104] According to some embodiments, the first carry unit 9025 includes an overflow setting subunit configured to, in response to the bits of the first portion of the first intermediate data being all 1, set an overflow variable to indicate that an overflow has occurred when a carry occurs in floating-point rounding normalization, and to set the second intermediate data to all 0; and, in response to the bits of the first portion of the first intermediate data not being all 1, set the overflow variable to indicate that an overflow has not occurred when a carry occurs in floating-point rounding normalization, and to perform an operation of adding 1 to the least significant bit of the first portion of the first intermediate data to determine the second intermediate data.

[0105] According to some embodiments, the first floating-point number determination unit 9026 includes: a second left-shift subunit configured to perform a second left-shift operation on the second intermediate data to determine third intermediate data based on the exponent value of the floating-point number; a mantissa determination subunit configured to concatenate one zero to the right of the third intermediate data to determine mantissa data of the normalized floating-point number; and an exponent determination subunit configured to determine the exponent data of the normalized floating-point number based on the exponent value of the floating-point number and an overflow variable.

[0106] According to some embodiments, the floating-point normalization module 902 further includes an uncarry unit configured to, in response to the carry amount of the floating-point number indicating that no carry occurred in the rounded normalization of the floating-point, perform a second left-shift operation on the first portion of the first intermediate data based on the exponent value of the floating-point number to determine mantissa data of the normalized floating-point number, and also to determine exponent data of the normalized floating-point number based on the exponent value of the floating-point number.

[0107] According to some embodiments, the floating-point normalization module 902 further includes a second floating-point number determination unit configured to, in response to the exponent value of the floating-point number being greater than or equal to the bit width of the mantissa data, set a normalized floating-point number corresponding to the floating-point number to the floating-point number to be converted.

[0108] According to some embodiments, the pre-processing module 901 is further configured to determine sign data of the floating-point number, and the carry amount determination unit 9024 includes a carry amount determination subunit configured to determine a carry amount of the floating-point number based on the mantissa data, the exponent value, the sign data of the floating-point number, and a type of floating-point rounding normalization, where the floating-point rounding normalization is a round-up conversion, a round-down conversion, a round-to-nearest-even conversion, or a round-to-zero conversion.

[0109] According to some embodiments, the apparatus 900 further includes a floating-point to integer conversion module, the floating-point to integer conversion module including: a second data determination unit configured to determine a carry amount and an exponent value of the floating-point number based on the exponent data and the mantissa data; and a second data concatenation unit configured to concatenate second padding data to the left of the mantissa data and determine second concatenated data in response to the exponent value of the floating-point number being smaller than an output bit width of the floating-point to integer conversion. wherein the second padding data includes a second predetermined number of 0s and one 1, the second predetermined number being equal to the difference between the integer bit width of the floating-point conversion and 1; a third left-shift unit configured to perform a third left-shift operation on the second concatenated data based on an exponent value of the floating-point number to determine fifth intermediate data; and a second integer number determination unit configured to determine an integer number after rounding the floating-point number based on the carry amount of the floating-point number and the fifth intermediate data.

[0110] According to some embodiments, the first predetermined quantity is equal to the bit width of the integer type of the floating-point conversion, and the first left shift operation and the third left shift operation are performed by the same shifter.

[0111] According to an aspect of the present disclosure, there is further provided a chip including the apparatus 900 for floating-point conversion as described above.

[0112] According to one aspect of the present disclosure, there is further provided an electronic device including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method for floating-point conversion described above.

[0113] According to one aspect of the present disclosure, there is further provided a non-transitory computer-readable storage medium having stored thereon computer instructions for causing the computer to perform the method for floating-point conversion described above.

[0114] According to one aspect of the present disclosure, there is further provided a computer program product including a computer program, wherein said computer program when executed by a processor implements the above method for floating-point conversion.

[0115] As shown in FIG. 10 , a block diagram of an electronic device 1000 that can be used as a server or client of the present disclosure will be described below as an example of a hardware device applicable to various aspects of the present disclosure. The electronic device may represent various types of digital electronic computers, such as laptop computers, desktop computers, stage computers, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various types of mobile devices, such as personal digital processing devices, mobile phones, intelligent phones, wearable devices, and other similar computing devices. The components, their connections, and their functions shown herein are merely exemplary and do not limit the implementation of the present disclosure as described and / or claimed herein.

[0116] 10, the device 1000 includes a computing unit 1001 and can perform various appropriate operations and processes by means of a computer program stored in a read-only memory (ROM) 1002 or loaded from a storage unit 1008 into a random access memory (RAM) 1003. The RAM 1003 can further store various programs and data necessary for operating the device 1000. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0117] The components of device 1000 are connected to I / O interface 1005 and include input unit 1006, output unit 1007, storage unit 1008, and communication unit 1009. Input unit 1006 may be any type of device capable of inputting information into device 1000. Input unit 1006 can generate input numeric or character information and key signal input for user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, keyboard, touch screen, trackpad, trackball, joystick, microphone, and / or remote controller. Output unit 1007 may be any type of device capable of presenting information, and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 1008 may include, but is not limited to, a magnetic disk, an optical disk, etc. The communication unit 1009 enables the device 1000 to exchange information / data with other devices via a computer network, e.g., the Internet, and / or various telecommunications networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, e.g., a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0118] The computing unit 1001 may be a variety of general-purpose and / or special-purpose processing components having processing and computing capabilities. Some examples of the computing unit 1001 may include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that execute machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs each of the methods and processes described above, such as the method for floating-point conversion. For example, in some embodiments, the method for floating-point conversion may be embodied as a computer software program and tangibly contained in a machine-readable medium, such as the storage unit 1008. In some embodiments, some or all of the computer program may be loaded and / or installed into the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, it may perform one or more steps of the method for floating-point conversion described above. Alternatively, in another embodiment, the computation unit 1001 may be configured to perform the method for floating-point conversion in any other suitable manner (eg, by firmware).

[0119] Various embodiments of the systems and techniques described herein may be realized in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being embodied in one or more computer programs that may be executed and / or interpreted by a programmable system including at least one programmable processor, which may be a special purpose or general purpose programmable processor, and which may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device;

[0120] The program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable apparatus for implementing the method for floating-point conversion, so that when executed by the processor or controller, the program code performs the functions / operations specified in the flowcharts and / or block diagrams. The program code may be executed entirely on a machine, partially on a machine, as a separate software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0121] In the context of this disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the above. More specific examples of machine-readable storage media include an electrical connection with one or more leads, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0122] To provide for interaction with a user, the systems and techniques described herein may be implemented in a computer having a display device (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor) for displaying information to a user, and a keyboard and pointing device (e.g., a mouse or trackball) by which a user may provide input to the computer. Other types of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user may be received in any form (including audio input, voice input, and tactile input).

[0123] The systems and techniques described herein may be implemented in a computing system including backstage components (e.g., as a data server), middleware components (e.g., as an application server), front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with the system or technique implementation), or any combination of backstage components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

[0124] The computer system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The client-server relationship is created by running computer programs on the corresponding computers that have a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server combined with a blockchain.

[0125] It should be understood that the various forms of flow described above may be used, and steps may be rearranged, added, or deleted. For example, the steps described in this disclosure may be performed in parallel, sequentially, or in a different order, and the present disclosure is not limited thereto as long as the technical solution disclosed in this disclosure achieves the desired results.

[0126] Although embodiments or examples of the present disclosure have been described with reference to the drawings, it should be understood that the above-described methods, systems, and devices are merely exemplary embodiments or examples, and that the scope of the present invention is not limited by these embodiments or examples. Various elements of the embodiments or examples may be omitted or replaced by equivalent elements. Furthermore, each step may be performed in an order different from that described in this disclosure. Furthermore, various elements in the embodiments or examples may be combined in various ways. It is important to note that as technology evolves, many elements described herein may be replaced by equivalent elements that appear later in this disclosure.

Claims

1. 1. A method for floating-point conversion, comprising: determining exponent data and mantissa data of a floating-point number to be converted; In response to the floating-point conversion being a floating-point round normalization, determining an exponent value of the floating-point number, which is a power value corresponding to the floating-point number, based on the exponent data and the mantissa data; In response to the exponent value of the floating-point number being smaller than a bit width of the mantissa data, concatenating first padding data including a first predetermined number of 1's, which is equal to or greater than the bit width of the mantissa data, to a left side of the mantissa data to determine first concatenated data; performing a first left-shift operation on the first concatenated data based on an exponent value of the floating-point number to determine first intermediate data; determining a carry amount of the floating-point number, which indicates whether a carry will occur in the rounding normalization of the floating-point number, based on the exponent value of the floating-point number and the mantissa data; In response to a carry amount of the floating-point number indicating the occurrence of a carry in the rounding normalization of the floating-point number, a carry operation is performed on a retained portion of the first intermediate data corresponding to the first padding data and a first portion of the first intermediate data, which is data of a retained bit of the mantissa data; and second intermediate data and an overflow variable are determined, wherein a bit width of the first portion of the first intermediate data is equal to the difference obtained by subtracting 1 from the bit width of the mantissa data, and the overflow variable indicates whether an overflow occurs when a carry occurs in the rounding normalization of the floating-point number; and determining a normalized floating-point number corresponding to the floating-point number based on an exponent value of the floating-point number, the second intermediate data, and the overflow variable.

2. In response to a carry amount of the floating-point number indicating an occurrence of a carry in the floating-point rounding conversion, performing a carry operation on a first portion of the first intermediate data and determining second intermediate data and an overflow variable includes: performing an operation of adding 1 to the least significant bit of a first portion of the first intermediate data to determine the second intermediate data; 2. The method of claim 1, comprising: in response to performing an operation of adding 1 to a least significant bit of a first portion of the first intermediate data causing an overflow, setting the overflow variable to indicate that an overflow has occurred when a carry-up occurs in the floating-point rounding normalization; and in response to performing an operation of adding 1 to a least significant bit of the first portion of the first intermediate data causing no overflow, setting the overflow variable to indicate that an overflow has not occurred when a carry-up occurs in the floating-point rounding normalization.

3. In response to a carry amount of the floating-point number indicating an occurrence of a carry in the floating-point rounding conversion, performing a carry operation on a first portion of the first intermediate data and determining second intermediate data and an overflow variable includes: In response to the bits of the first portion of the first intermediate data being all 1, setting the overflow variable to indicate that an overflow occurs when a carry occurs in the floating-point rounding normalization, and setting the second intermediate data to all 0; 2. The method of claim 1, further comprising: in response to the bits of the first portion of the first intermediate data not being all 1, setting an overflow variable to indicate that an overflow did not occur when a carry occurs in the floating-point rounding normalization; and performing an operation of adding 1 to the least significant bit of the first portion of the first intermediate data to determine the second intermediate data.

4. determining a normalized floating-point number corresponding to the floating-point number based on an exponent value of the floating-point number, the second intermediate data, and the overflow variable, performing a second left-shift operation on the second intermediate data based on an exponent value of the floating-point number to determine third intermediate data; concatenating one zero to the right of the third intermediate data to determine mantissa data of the normalized floating-point number; determining exponent data of the normalized floating-point number based on the exponent value of the floating-point number and the overflow variable.

5. In response to the floating-point conversion being a floating-point round normalization, in response to the carry amount of the floating-point number indicating that no carry occurred in the round normalization of the floating-point number, performing a second left-shift operation on a first portion of the first intermediate data based on an exponent value of the floating-point number to determine fourth intermediate data; concatenate one zero to the right of the fourth intermediate data to determine mantissa data of the normalized floating-point number; The method of any one of claims 1 to 3, further comprising: determining exponent data of the normalized floating-point number based on an exponent value of the floating-point number.

6. In response to the floating-point conversion being a floating-point round normalization, 2. The method of claim 1, further comprising: in response to an exponent value of the floating-point number being equal to or greater than a bit width of the mantissa data, setting the normalized floating-point number corresponding to the floating-point number to the floating-point number to be converted.

7. determining sign data for the floating-point number; Determining a carry amount of the floating-point number based on the exponent value of the floating-point number and the mantissa data includes:

2. The method of claim 1, further comprising: determining a carry amount for the floating-point number based on the mantissa data, the exponent value, sign data of the floating-point number, and a type of rounding normalization for the floating-point number, wherein the rounding normalization for the floating-point number is a round-up conversion, a round-down conversion, a round-to-nearest-even conversion, or a round-to-zero conversion.

8. In response to the floating-point conversion being a floating-point to integer conversion, determining an exponent value of the floating-point number based on the exponent data and the mantissa data; In response to the exponent value of the floating-point number being smaller than an output bit width of the floating-point to integer conversion, concatenate second padding data including a second predetermined number of 0s and one 1, equal to the difference between the bit width of the integer type numeric value of the floating-point conversion and one, to the left of the mantissa data to determine second concatenated data; performing a third left-shift operation on the second concatenated data based on an exponent value of the floating-point number to determine fifth intermediate data; determining a carry amount for the floating-point number based on the exponent data and the mantissa data; 4. The method according to claim 1, further comprising: determining an integer-type numeric value after rounding the floating-point number based on the carry amount of the floating-point number and the fifth intermediate data.

9. 9. The method of claim 8, wherein the first predetermined quantity is equal to a bit width of an integer type of the floating-point conversion, and the first left shift operation and the third left shift operation are performed by the same shifter.

10. 1. An apparatus for floating-point conversion, comprising: a pre-processing module configured to, for a floating-point number to be converted, determine exponent data and mantissa data of said floating-point number; a first data determination unit configured to determine an exponent value of the floating-point number, the exponent value being a power value corresponding to the floating-point number, based on the exponent data and the mantissa data; a first data concatenation unit configured to, in response to an exponent value of the floating-point number being smaller than a bit width of the mantissa data, concatenate first padding data including a first predetermined number of 1's, the first predetermined number being equal to or greater than a bit width of the mantissa data, to a left side of the mantissa data to determine first concatenated data; a first left-shift unit configured to perform a first left-shift operation on the first concatenated data based on an exponent value of the floating-point number to determine first intermediate data; a carry amount determination unit configured to determine a carry amount of the floating-point number, which indicates whether a carry occurs in rounding normalization of the floating-point number, based on an exponent value of the floating-point number and the mantissa data; a first carry unit configured to, in response to a carry amount of the floating-point number indicating the occurrence of a carry in the rounding normalization of the floating-point number, perform a carry operation on a retained portion of the first intermediate data corresponding to the first padding data and a first portion of the first intermediate data, which is data of a retained bit of the mantissa data, and determine second intermediate data and an overflow variable, wherein a bit width of the first portion of the first intermediate data is equal to a difference obtained by subtracting 1 from the bit width of the mantissa data, and the overflow variable indicates whether an overflow will occur when a carry occurs in the rounding normalization of the floating-point number; and a floating-point normalization module comprising: an exponent value of the floating-point number; and a first floating-point number determination unit configured to determine a normalized floating-point number corresponding to the floating-point number based on the second intermediate data and the overflow variable.

11. The first carrying unit comprises:

11. The apparatus of claim 10, comprising: an adding subunit configured to perform an operation of adding 1 to a least significant bit of a first portion of the first intermediate data to determine the second intermediate data; and an overflow setting subunit configured to, in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data causing an overflow, set the overflow variable to indicate that an overflow has occurred when a carry-up occurs in the floating-point rounding normalization, and to, in response to performing the operation of adding 1 to the least significant bit of the first portion of the first intermediate data not causing an overflow, set the overflow variable to indicate that an overflow has not occurred when a carry-up occurs in the floating-point rounding normalization.

12. The first carrying unit comprises:

11. The apparatus of claim 10, further comprising: an overflow setting subunit configured to, in response to the bits of the first portion of the first intermediate data being all 1, set the overflow variable to indicate that an overflow has occurred when a carry-up occurs in the floating-point rounding normalization, and to set the second intermediate data to all 0; and an adding subunit configured to, in response to the bits of the first portion of the first intermediate data not being all 1, set the overflow variable to indicate that an overflow has not occurred when a carry-up occurs in the floating-point rounding normalization, and to perform an operation of adding 1 to a least significant bit of the first portion of the first intermediate data to determine the second intermediate data.

13. The first floating-point number determination unit: a second left-shift subunit configured to perform a second left-shift operation on the second intermediate data based on an exponent value of the floating-point number to determine third intermediate data; a mantissa determination subunit configured to concatenate one zero to the right of the third intermediate data to determine mantissa data of the normalized floating-point number; an exponent determination subunit configured to determine exponent data of the normalized floating-point number based on an exponent value of the floating-point number and the overflow variable.

14. The floating-point normalization module:

13. The apparatus of claim 10, further comprising: an uncarry unit configured to, in response to a carry amount of the floating-point number indicating that no carry occurred in the rounded normalization of the floating-point number, perform a second left-shift operation on a first portion of the first intermediate data based on an exponent value of the floating-point number to determine mantissa data of the normalized floating-point number, and to determine exponent data of the normalized floating-point number based on the exponent value of the floating-point number.

15. The floating-point normalization module:

11. The apparatus of claim 10, further comprising: a second floating-point number determination unit configured to set the normalized floating-point number corresponding to the floating-point number to the floating-point number to be converted in response to an exponent value of the floating-point number being equal to or greater than a bit width of the mantissa data.

16. the pre-processing module is further configured to determine sign data for the floating-point number; The carry amount determination unit 11. The apparatus of claim 10, further comprising a carry amount determination subunit configured to determine a carry amount of the floating-point number based on the mantissa data, the exponent value, the sign data of the floating-point number, and a type of rounding normalization of the floating-point number, the rounding normalization of the floating-point number being a round-up conversion, a round-down conversion, a round-to-nearest-even conversion, or a round-to-zero conversion.

17. The device comprises: a second data determination unit configured to determine a carry amount and an exponent value of the floating-point number based on the exponent data and the mantissa data; a second data concatenation unit configured to, in response to an exponent value of the floating-point number being smaller than an output bit width of the floating-point to integer type conversion, concatenate second padding data including a second predetermined number of 0s and one 1, equal to a difference between the bit width of the integer type of the floating-point conversion minus 1, to a left side of the mantissa data to determine second concatenated data; a third left-shift unit configured to perform a third left-shift operation on the second concatenated data based on an exponent value of the floating-point number to determine fifth intermediate data; and a second integer number determination unit configured to determine an integer number after rounding the floating-point number based on the carry amount of the floating-point number and the fifth intermediate data. The apparatus according to any one of claims 10 to 12, further comprising a floating-point to integer conversion module comprising:

18. 18. The apparatus of claim 17, wherein the first predetermined quantity is equal to a bit width of an integer type of the floating-point conversion, and the first left shift operation and the third left shift operation are performed by the same shifter.

19. A chip comprising an apparatus for floating-point conversion according to any one of claims 10 to 12.

20. An electronic device, at least one processor; a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions, when executed by the at least one processor, cause the at least one processor to perform the method according to any one of claims 1 to 3.

21. A non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 1 to 3.

22. A computer program product comprising a computer program which, when executed by a processor, performs the method of any one of claims 1 to 3.

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