Semiconductor device

Abstract

To provide a semiconductor device in which a wiring shape of a transistor and a connection part has a particular structure so that the transistor has excellent electric characteristics and the connection part has excellent electric characteristics and less conduction failure.SOLUTION: A semiconductor device includes a transistor 150 and a connection part 160. The transistor includes a gate electrode 104a, a first insulating film 108 formed on the gate electrode, an oxide semiconductor film 110 formed on the first insulating film and formed at a position overlapping the gate electrode, and a source electrode 112a and a drain electrode 112b electrically connected to the oxide semiconductor film. The connection part includes a first wire 104b formed on the same surface as the gate electrode, a second wire 112c formed on the same surface as the source electrode and the drain electrode, and a third wire 122b connecting between the first wire and the second wire. The distance between an upper end part and a lower end part is longer at an end part of the second wire than at an end part of the source electrode and the drain electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a transistor including an oxide semiconductor film. The present invention relates to a display device using the same. [Background technology]

[0002] A transistor (thin film transistor (TFT)) is formed using a semiconductor thin film formed on a substrate. The technology for constructing transistors is attracting attention. It is widely used in electronic devices such as image display devices (display devices). Silicon-based semiconductor materials are widely known as usable semiconductor thin films, but other materials and Oxide semiconductors have been attracting attention as a solution.

[0003] For example, indium (In), gallium (Ga) and nickel are used as the active layer of a transistor. Transistors using oxide semiconductors containing lead (Zn) have been disclosed (Patent Document 1 and (See Patent Document 2).

[0004] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, A driving circuit is formed by integrating transistors or connection wiring etc. at high density, and the driving circuit and the display device There is an increasing demand for display devices with an integrated driving circuit in which the display device and the driving circuit are provided on the same substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] In a semiconductor device including an oxide semiconductor film, a transistor and an electric field When wiring such as power lines or signal lines that are electrically connected are densely integrated, Defects may occur.

[0007] For example, when the spacing between wiring is high density or when the wiring has large unevenness, The connection is not functioning properly due to a break in the conductive film connecting the wires or a poor coating of the conductive film connecting the wires. When a semiconductor device having such a connection portion is applied to, for example, a display device, In this case, the abnormality in the connection portion causes a decrease in the yield of the display device.

[0008] In view of the above problems, one embodiment of the present invention provides a semiconductor device including a transistor and a connection portion. The wiring shape of the transistor and the connection portion is made to have a specific structure, and thus the electrical characteristics The present invention aims to provide a semiconductor device having a transistor with excellent characteristics and a connection portion with excellent electrical characteristics. This is one of the challenges.

[0009] Another embodiment of the present invention is a semiconductor device including an oxide semiconductor, which can provide good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device using an oxide semiconductor. One of the objectives of the present invention is to provide a highly reliable semiconductor device by suppressing fluctuations in the electrical characteristics of the device. Another object of one embodiment of the present invention is to provide a semiconductor device that is suitable for miniaturization. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. It shall be one.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor and a connection portion, The capacitor includes a gate electrode, a first insulating film formed on the gate electrode, and a second insulating film formed on the first insulating film. and an oxide semiconductor film formed at a position overlapping with the gate electrode, and an oxide semiconductor film electrically connected to the oxide semiconductor film. and a source electrode and a drain electrode which are electrically connected to each other, and the connection portion is on the same surface as the gate electrode. The first wiring formed on the surface and the source electrode and the drain electrode are formed on the same surface. a second wiring and a third wiring that connects the first wiring and the second wiring, The ends are characterized in that the distance between the upper end and the lower end is longer than the ends of the source electrode and the drain electrode. This is a semiconductor device characterized by the above.

[0012] The ends of the second wiring are spaced apart from the ends of the source electrode and the drain electrode by a distance between the upper end and the lower end. By making the second wiring longer, it is possible to reduce the step caused by the second wiring. By reducing the step caused by the above, the insulating film formed above the second wiring or This can improve the coverage of the conductive film, thereby providing a conductive film with excellent electrical properties. This results in a connection portion with reduced conduction defects.

[0013] The edges of the source electrode and the drain electrode of the transistor are connected to the edges of the second wiring. The distance between the top end and the bottom end is shorter than that of the transistor. For example, when the transistor is a channel-etched type transistor, the transistor can have favorable electrical characteristics. In the case of a transistor structure, when forming the source electrode and the drain electrode, the semiconductor layer The oxide semiconductor film may be damaged during the formation of the source and drain electrodes. However, by forming the source electrode and the drain electrode into the above-described structure, the oxide semiconductor film In addition, the damage to the source and drain electrodes can be minimized. By forming the end portion into the above-described structure, the oxide semiconductor film that functions as a channel region can be formed. This makes it possible to apply an electric field in a suitable manner.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor and a connection portion, The transistor includes a gate electrode, a first insulating film formed on the gate electrode, and a first insulating film. an oxide semiconductor film formed on the oxide semiconductor layer and overlapping with a gate electrode; a source electrode and a drain electrode electrically connected to the body film, and the connection portion is connected to a gate electrode. a first wiring formed on the same surface as the electrode; a first insulating film on the first wiring; A first opening is provided in the film, and a second opening is formed on the same surface as the source electrode and the drain electrode. a second wiring, a second insulating film on the second wiring, and a second opening provided in the second insulating film; The first wiring and the second wiring are connected to each other by a first opening and a second opening. and a third wiring, and an end of the second wiring is closer to the source electrode and the drain electrode than the end of the second wiring. The semiconductor device is characterized by a long distance between its top and bottom ends. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a transistor having excellent electrical characteristics and a connection having excellent electrical characteristics can be obtained. It is possible to provide a semiconductor device having the above structure. [Brief explanation of the drawings]

[0016] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 3] 1A and 1B are top views illustrating one embodiment of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 7] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 10] 1A and 1B are a cross-sectional view and a band diagram illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A and 1B are a block diagram and a circuit diagram illustrating one embodiment of a display device. [Figure 13] FIG. 2 is a diagram illustrating a display module. [Figure 14] FIG. 1 is a diagram illustrating an electronic device. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 18] FIG. 10 is a diagram illustrating a gray-tone mask. [Figure 19] FIG. 2 is a cross-sectional view illustrating a sample structure according to an embodiment of the present invention. [Figure 20] FIG. 1 is a diagram illustrating STEM results of an example. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and methods thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments and examples. In the embodiments and examples described below, the same parts or parts having similar functions In the case of parts, the same symbols or the same hatch patterns are used in common among different drawings, and the repetition The explanation of repetition will be omitted.

[0018] In each figure described in this specification, the size of each component, the thickness of the film, or the area is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0019] In addition, terms such as first, second, and third used in this specification are used interchangeably to avoid confusion of components. It is not intended to limit the number of items. The terms "second" or "third" can be used interchangeably to explain the present invention.

[0020] The functions of the "source" and "drain" are also different when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0021] In this specification, when an etching step is performed after a photolithography step, The mask formed in the photolithography process is removed.

[0022] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. do.

[0023] <Configuration example of semiconductor device> FIG. 1A is a top view of a semiconductor device of one embodiment of the present invention, and FIG. 1B is a top view of a semiconductor device of FIG. ) corresponds to a cross-sectional view of the cut surface between the dashed dotted line AB and the dashed dotted line CD. In FIG. 1(A), in order to avoid complication, only a part of the components of the semiconductor device (gate In the figure, insulating films that function as insulating films, etc. are omitted.

[0024] The semiconductor device shown in FIGS. 1A and 1B includes a transistor 150 and a connection portion 160. do.

[0025] The transistor 150 has a gate electrode 104a on the substrate 102 and a gate electrode 104b on the gate electrode 104a. a first insulating film 108 formed on the gate electrode 10; The oxide semiconductor film 110 is formed at a position overlapping with the oxide semiconductor film 4a. The transistor has a source electrode 112a and a drain electrode 112b which are electrically connected to each other.

[0026] In FIG. 1B, the first insulating film 108 is formed between the insulating film 106 and the insulating film 107. A two-layer laminated structure is shown as an example. However, the structure of the first insulating film 108 is not limited to this. For example, it may have a single layer structure or a laminated structure of three or more layers.

[0027] In addition, on the transistor 150, more specifically, the oxide semiconductor film 110 and the source electrode 112 A second insulating film 120 is formed on the drain electrode 112a and the drain electrode 112b. In the present embodiment, the second insulating film 120 is a laminated structure of three insulating films 114, 116, and 118. The structure of the second insulating film 120 is not limited to this, and may be, for example, a single layer structure. The laminated structure may be a laminated structure of two layers, or a laminated structure of four or more layers.

[0028] In addition, an opening 142a is formed in the second insulating film 120, reaching the drain electrode 112b. In addition, a pixel electrode is formed on the second insulating film 120 so as to cover the opening 142a. The conductive film 122a is formed on the transistor 150. It is connected to the drain electrode 112b.

[0029] The connection portion 160 is connected to the first wiring 104b on the substrate 102 and the first wiring 104b. the insulating film 108, the opening 142b provided in the first insulating film 108, and the first insulating film 10 8, a second wiring 112c on the second wiring 112c, a second insulating film 120 on the second wiring 112c, and a second insulating film The opening 140 provided in the veil 120, the opening 142b and the opening 140 are formed to cover the opening 142b. and functions as a third wiring that connects the first wiring 104b and the second wiring 112c. 1B, the opening over the first wiring 104b is Although the two-stage opening shape of the opening 140 and the opening 142b has been illustrated, the present invention is not limited to this. For example, in the process of forming the opening 142b, an opening that reaches the first wiring 104b is formed. It may be formed.

[0030] The first wiring 104b is formed in the same process as the gate electrode 104a of the transistor 150. In other words, the first wiring 104b is formed on the gate electrode 10 of the transistor 150. The second wiring 112c is formed on the same surface as the transistor 150. The second electrode 112a and the second electrode 112b are formed in the same process. The wiring 112c is connected to the source electrode 112a and the drain electrode 112b of the transistor 150. It is formed on the same surface as

[0031] Here, a part of the transistor 150 and the connection portion 160 of the semiconductor device shown in FIG. Enlarged views are shown in FIGS. 2(A) and 2(B). FIG. 2(A) shows the source voltage of the transistor 150. 2(A) shows an enlarged view of a portion of the electrode 112a and the drain electrode 112b, and FIG. 2(B) shows a portion of the connection portion 16 10 shows an enlarged view of a portion of the second wiring 112c of FIG.

[0032] As shown in FIG. 2A, the source electrode 112a and the drain electrode 112b of the transistor 150 The end of 12b has a lower end α1 and an upper end α2. Although the lower end α1 and the upper end α2 are shown only for the source electrode 112a, the drain electrode 112 b has a similar configuration.

[0033] As shown in FIG. 2B, the end of the second wiring 112c of the connection portion 160 is a lower end β 2B, the end of the second wiring 112c has a top end β1 and a top end β2. Although only one of the lower end β1 and upper end β2 is shown, the other end of the second wiring 112c is also However, the shape of the end of the second wiring 112c is the same as that of the structure shown in FIG. For example, only one end of the second wiring 112c may be The configuration may be the same.

[0034] As shown in FIGS. 2A and 2B, the source electrode 112a and the The distance between the ends of the drain electrode 112b and the connecting portion 160 is larger than the distance between the ends of the drain electrode 112b (the distance between α1 and α2). The distance between the ends of the second wiring 112c (the distance between β1 and β2) is longer.

[0035] The end of the second wiring 112c is spaced apart from the end of the source electrode 112a and the end of the drain electrode 112b. By increasing the distance between the upper end and the lower end, the step caused by the second wiring 112c can be reduced. By reducing the step caused by the second wiring 112c, The insulating films 114, 116, 118 and / or the third wiring 112c are formed above the second wiring 112c. The coverage of the conductive film 122b, which functions as a wiring, can be improved. The contact failure between the second wiring 112c and the conductive film 122b functioning as the third wiring is reduced. This can be done.

[0036] In addition, the ends of the source electrode 112a and the drain electrode 112b of the transistor 150 The distance between the upper end and the lower end of the second wiring 112c is shorter than that of the end of the second wiring 112c. By doing so, the transistor can have good electrical characteristics. As shown in FIG. 2(A), when the transistor 150 has a channel etch type transistor structure, In this case, when forming the source electrode 112a and the drain electrode 112b, the oxide semiconductor film 1 10 can take damage.

[0037] For example, the source electrode 112a, the drain electrode 112b, and the second wiring 112c During the formation, the source electrode 112a and the drain electrode 112b are formed by adjusting the etching conditions. The shape of each end of the first electrode 112b and the second wiring 112c can be adjusted. However, the shape of the end portions of the source electrode 112a and the drain electrode 112b is changed to the shape of the second wiring 112c. By making the end portion have a similar shape to that of the oxide semiconductor film 110, the etching time becomes longer. Therefore, a transistor having a damaged oxide semiconductor film 110 may be damaged. The transistor 150 may not have stable electrical characteristics. and the distance between the drain electrode 112b determines the channel length (L) of the transistor 150. Therefore, the shape of the end portions of the source electrode 112a and the drain electrode 112b can be adjusted. This may cause variations in the channel length (L) within the substrate surface.

[0038] However, in the semiconductor device of one embodiment of the present invention, The shape of the end of the electrode and the drain electrode is made different from the shape of the end of the wiring of the connection part. This allows for stable electrical characteristics of the transistor and good contact resistance at the connection points. This is an excellent effect that can be obtained by the semiconductor device of one embodiment of the present invention.

[0039] In the semiconductor device according to one embodiment of the present invention, the source electrode and the drain electrode of the transistor The formation of the contact electrodes and the formation of the wiring of the connection parts can be performed at the same time using the same mask. Therefore, it is possible to provide a semiconductor device with excellent productivity.

[0040] Here, a modified example of the connecting portion 160 shown in FIG. 2(B) will be explained using FIGS. 2(C) and 2(D). The explanation will be given below.

[0041] FIG. 2C shows a modified example of the connection part shown in FIG. 2B, in which the end of the second wiring 112c In addition, due to the difference in the shape of the end of the second wiring 112c, The insulating films 114, 116, and 118 also have different shapes.

[0042] The end of the connecting portion 160 shown in FIG. 2(C) is a middle end β4 between a lower end β3 and an upper end β5. In this way, the end of the second wiring 112c has a stepped shape with multiple angles. By forming a stepped shape with multiple angles in this way, This can further improve the coverage of the insulating films 114, 116, and 118 formed above. do.

[0043] In addition, at the end of the connection portion 160 shown in FIG. 2(C), the middle end portion β4 and the upper end portion β5 are In this way, by making the end portion have a curvature, This can further improve the coverage of the insulating films 114, 116, and 118 that are applied.

[0044] Next, FIG. 2D shows a modified example of the connection part shown in FIG. 2B, in which the second wiring 112c The shape of the end of the second wiring 112c is different. The shapes of the insulating films 114, 116, and 118 to be formed are also different.

[0045] The ends of the connecting portion 160 shown in FIG. 2(D) are a lower end β6 and an upper end β 11 Between them, the middle end β 7, β8, β9, β 10 For example, if the laminated structure of the second wiring 112c is as shown in FIG. As shown in FIG. 1D, the second wiring 112c_1, the second wiring 112c_2, the second wiring 11 By using a three-layer laminated structure of 2c_3, the lower end β6 and the upper end β 11 Between them, the middle end β7 , β8, β9, β 10 In this way, the second wiring 11 2c preferably has a laminated structure of at least two layers.

[0046] As shown in FIGS. 2A, 2B, 2C, and 2D, a semiconductor device of one embodiment of the present invention includes: At least the source electrode 112a and the drain electrode 112b of the transistor 150 The distance between the upper end and the lower end (the distance α1-α2) is smaller than the distance between the second wiring 1 of the connecting portion 160. The distance between the top and bottom of 12c (β1-β2 distance, β3-β5 distance, or β6-β 11 The longer the distance between the two points, the better.

[0047] However, as shown in FIGS. 2(A) to 2(D), the source electrode 112a and the drain electrode 11 2b and the second wiring 112c, the upper end is provided inside the lower end. It is necessary.

[0048] <Top surface shape of connection part (modified example)> Here, a modified example of the top surface shape of the connection part 160 shown in FIG. 1(A) will be explained with reference to FIG. Make it clear.

[0049] FIG. 3A shows a circuit in which the first wiring 104b and the second wiring 112c function as a third wiring. The connection is made via the conductive film 122b.

[0050] As shown in FIG. 3A, the top shapes of the tips of the first wiring 104b and the second wiring 112c are The shape may be a circle. Although not shown, the shape may be an ellipse or a polygon. The top surface shape may be a combination of curved and straight lines.

[0051] As shown in FIG. 3A, the top shapes of the tips of the first wiring 104b and the second wiring 112c are By making the shape circular, it is possible to reduce the amount of dust (also called particles) that may be generated during the manufacturing process of a semiconductor device. ) can be prevented from accumulating at the edge. Therefore, it functions as a third wiring. The second wiring 112c can cover the openings 140, 142b, and 142c well. This becomes:

[0052] In addition, in FIG. 1A and FIG. 3A, the first wiring 104b and the second wiring 11 2c are extended parallel to each other, as shown in FIG. 3(B). The first wiring 104b and the second wiring 112c may be arranged to face each other. As shown in FIG. 3C, the first wiring 104b and the second wiring 112c are arranged to face each other at right angles. As shown in FIGS. 3(A), (B), and (C), the first wiring 104 The upper surface shape and arrangement of the second wiring 112b and the second wiring 112c can be determined by the implementer as appropriate. The shape and arrangement may be as follows.

[0053] 3B and 3C, the region 14 is located above the second wiring 112c. 4a and region 144b.

[0054] The regions 144a and 144b shown in FIGS. 3B and 3C are portions of the end of the second wiring 112c. The distance between the upper end and the lower end of the part is the distance between the source electrode 112a and the drain electrode 112b of the transistor 150. This is a region where the distance between the upper end and the lower end of the second electrode 112b is longer than the distance between the upper end and the lower end of the second electrode 112b. When forming the wiring 112c, a gray-tone mask or the like is used in a photolithography process. The second wiring 112c is processed using the exposure mask. The shape of a part of the end of c is the structure shown in Figure 1(B) and Figures 2(B), (C), and (D). It is possible.

[0055] Note that the details of the semiconductor device of one embodiment of the present invention illustrated in FIGS. The details of the method for fabricating the body device are described below.

[0056] <Method for manufacturing semiconductor device> A method for manufacturing the semiconductor device of one embodiment of the present invention shown in FIGS. 1A and 1B will be described with reference to FIGS. This will be explained in detail below with reference to FIG.

[0057] First, a substrate 102 is prepared. The substrate 102 is made of aluminosilicate glass, aluminum, or the like. Glass materials such as minoborosilicate glass and barium borosilicate glass are used. Above, the substrate 102 is 8th generation (2160mm x 2460mm), 9th generation (2400 mm x 2800 mm, or 2450 mm x 3050 mm, 10th generation (2950 mm It is preferable to use mother glass such as a glass with a diameter of 3400 mm. When using mother glass for mass production, the temperature is high and the processing time is long, so the glass shrinks significantly. The heat treatment in the manufacturing process is preferably performed at 600° C. or less, more preferably at 450° C. or less, More preferably, the temperature is set to 350° C. or lower.

[0058] Next, a conductive film is formed on the substrate 102 and processed into a desired region to form a gate. Then, the substrate 102, the gate electrode 104a, and the first wiring 104b are formed. 104a, and a first insulating film including an insulating film 106 and an insulating film 107 on the first wiring 104b. A film 108 is formed (see FIG. 4(A)).

[0059] The process of forming the gate electrode 104a and the first wiring 104b is the same as the process of forming the first pattern. This is the processing process.

[0060] The gate electrode 104a and the first wiring 104b are made of aluminum, quartz, or the like. a metal element selected from the group consisting of chromium, copper, tantalum, titanium, molybdenum, and tungsten, or Using alloys containing the above metal elements or alloys combining the above metal elements In addition, the material used for the gate electrode 104a and the first wiring 104b can be The film may have a single layer structure or a laminated structure of two or more layers. For example, a titanium film may be formed on an aluminum film. Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride film Two-layer structure with tungsten film laminated on top, tantalum nitride film or tungsten nitride film Two-layer structure with tungsten film stacked, titanium film, and aluminum film stacked on the titanium film. There are also three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, a film of a selected element, an alloy film of a combination of multiple elements, or a nitride film may be used. The gate electrode 104a and the first wiring 104b may be made of a material such as a sputtered material. The film can be formed by using a coating method.

[0061] The insulating film 106 may be, for example, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film. A film such as a silicon film can be used, and it can be formed as a laminate or a single layer using a PE-CVD device. When the insulating film 106 has a laminated structure, a silicon nitride film with few defects is used as the first silicon nitride film. A silicon nitride film was used as the first silicon nitride film, and a second silicon nitride film was used as the second silicon nitride film. It is preferable to provide a silicon nitride film that emits less ammonia. Hydrogen and nitrogen contained in the oxide semiconductor film 110 are transferred or diffused into the oxide semiconductor film 110 to be formed later. This can prevent the

[0062] The insulating film 107 may be a silicon oxide film, a silicon oxynitride film, or the like. It is formed in a laminated or single layer using an E-CVD device.

[0063] The first insulating film 108 is made of, for example, a 400 nm thick insulating film. A silicon nitride film is formed, and then a silicon oxynitride film having a thickness of 50 nm is formed as an insulating film 107. A laminated structure in which the silicon nitride film and the silicon oxynitride film are formed can be used. It is preferable to form the silicon film continuously in a vacuum, since this prevents the inclusion of impurities. The first insulating film 108 at the position where it overlaps with the electrode 104a is a gate insulating film of the transistor 150. Silicon nitride oxide has a nitrogen content greater than the oxygen content. Silicon oxynitride is an insulating material, whereas silicon oxynitride is a material with a higher oxygen content than nitrogen content. This refers to insulating materials.

[0064] By using the above-described structure for the gate insulating film, the following effects can be obtained, for example: Silicon nitride film has a higher dielectric constant than silicon oxide film, and it can be used at the same static Because the film thickness required to obtain capacitance is large, it is not possible to physically thicken the gate insulating film. Therefore, the decrease in the dielectric strength voltage of the transistor 150 can be suppressed, and the dielectric strength voltage can be improved. As a result, electrostatic damage to the transistor 150 can be suppressed.

[0065] Next, an oxide semiconductor film is formed over the first insulating film 108, and the oxide semiconductor film is The oxide semiconductor film 110 is formed by processing the oxide semiconductor film 110 into a thin film region (see FIG. 4B).

[0066] Note that the step of forming the oxide semiconductor film 110 is a second patterning step.

[0067] The oxide semiconductor film 110 contains at least indium (In), zinc (Zn), and M. In-M containing (metals such as Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) It is preferable that the film contains a film represented by In-Zn oxide. Alternatively, it may contain both In and Zn. Furthermore, it is preferable to reduce variations in electrical characteristics of transistors using the oxide semiconductor. Therefore, it is preferable to include a stabilizer together with them.

[0068] The stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides include lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. do.

[0069] The oxide semiconductor constituting the oxide semiconductor film 110 is, for example, an In—Ga—Zn-based oxide. oxides, In-Al-Zn oxides, In-Sn-Zn oxides, In-Hf-Zn oxides In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides , In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, I n-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In -Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides It can be used.

[0070] Here, the In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than n may be included.

[0071] The oxide semiconductor film 110 is formed by a sputtering method, an MBE (Molecular Beam Epitaxy) method, or the like. Beam Epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomi (c) Layer Deposition) method, etc. can be used as appropriate. When the compound semiconductor film 110 is formed, a dense film is formed by using a sputtering method. , is preferable.

[0072] When the oxide semiconductor film 110 is formed, it is desirable to minimize the amount of the oxide semiconductor contained in the film. It is preferable to reduce the hydrogen concentration in the film. When forming a film using the ring method, not only is the film formation chamber evacuated to a high vacuum, but the sputtering gas The oxygen gas and argon gas used as sputtering gas have a dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less, and even more preferably By using a gas that has been highly purified to -120°C or lower, moisture and other substances are not absorbed into the oxide semiconductor film. This can prevent as many users as possible from being caught in the system.

[0073] In order to remove residual moisture in the film-forming chamber, an adsorption-type vacuum pump, e.g., It is preferable to use an opto-pump, an ion pump, or a titanium sublimation pump. Alternatively, a turbomolecular pump with a cold trap may be used. For example, hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), compounds containing carbon atoms, etc. Because of the high pumping capacity of the cryopump, the gas contained in the film formed in the film formation chamber evacuated using a cryopump can be This can reduce the concentration of impurities.

[0074] In addition, when the oxide semiconductor film 110 is formed by a sputtering method, In this case, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less. Preferably, the relative density is 95% or more and 100% or less. This allows the deposited film to be a dense film.

[0075] The oxide semiconductor film 110 was formed by keeping the substrate 102 at a high temperature. Forming a film is also effective in reducing the concentration of impurities that may be contained in the oxide semiconductor film. The temperature to which the substrate 102 is heated may be preferably 150° C. or higher and 450° C. or lower. Alternatively, the substrate temperature may be set to 200°C or higher and 350°C or lower.

[0076] Next, it is preferable to perform a first heat treatment. ℃ or less, preferably 300℃ to 500℃, in an inert gas atmosphere, an oxidizing gas atmosphere The first heat treatment may be carried out in an atmosphere containing 10 ppm or more of fluorine or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replace the oxygen that has been removed. The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine. The crystallinity of the oxide semiconductor used for the first insulating film 10 is increased, and the first insulating film 108 and the oxide semiconductor Impurities such as hydrogen and water can be removed from the oxide semiconductor film 110. A first heating step may be carried out before processing the 0 into islands.

[0077] Next, a source electrode 112a and a drain electrode 112b are formed on the first insulating film 108 and the oxide semiconductor film 110. Then, a conductive film 112 is formed to become a second electrode 112b and a second wiring 112c (see FIG. 4(C)). see).

[0078] The source electrode 112a, the drain electrode 112b, and the second wiring 112c can be formed by Possible materials for the conductive film 112 include aluminum, titanium, chromium, nickel, copper, and iron. Monolithic alloys consisting of tritium, zirconium, molybdenum, silver, tantalum, or tungsten The metal or alloy containing it as the main component can be used as a single layer structure or a laminated structure. In particular, aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten For example, titanium may be added to an aluminum film. Two-layer structure with titanium film laminated on tungsten film, two-layer structure with titanium film laminated on tungsten film, copper-magnesium Two-layer structure consisting of a copper film laminated on a sodium-aluminum alloy film, a titanium film, or a titanium nitride film Then, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and A three-layer structure in which a titanium film or titanium nitride film is formed on top of the above, a molybdenum film or a nitride film A molybdenum film and an aluminum film or a molybdenum nitride film are laminated on the molybdenum film or the molybdenum nitride film. A three-layer structure in which a copper film is laminated on top of a molybdenum film or molybdenum nitride film is formed on top of that. The transparent conductive material containing indium oxide, tin oxide or zinc oxide is used. The conductive film can be formed by, for example, a sputtering method.

[0079] Next, resist masks 148a, 148b, and 148c are formed in desired regions on the conductive film 112. (See FIG. 4(D)).

[0080] The resist masks 148a, 148b, and 148c are formed by applying a photosensitive resin to the conductive film 11. After forming the photoresist on the substrate, the photoresist is exposed using a gray-tone mask or a half-tone mask. Only the resist mask 148c in the region that will become the second wiring 112c is formed in a stepped shape. This can be done.

[0081] As a gray-tone mask or a half-tone mask, for example, the masks shown in FIGS. 3(B) and 3(C) are used. This can be applied to the areas located in areas 144a and 144b as shown in FIG.

[0082] Next, the conductive film 112 is etched from above the resist masks 148a, 148b, and 148c. After etching, the resist masks 148a, 148b, and 148c are removed. Thus, the source electrode 112a, the drain electrode 112b, and the second wiring 112c are formed. (See Figure 5(A)).

[0083] The source electrode 112a, the drain electrode 112b, and the second wiring 112c are formed. This step is the third patterning step.

[0084] In this way, the source electrode 112a, the drain electrode 112b, and the second wiring 112c The source electrode 112a, the drain electrode 112b, and the second wiring are formed in the same process. The end of 112c can be shaped differently.

[0085] In this embodiment, the conductive film 112 is etched by a dry etching method. is used.

[0086] When the conductive film 112 is etched, a part of the oxide semiconductor film 110 is removed, and a recess is formed. In some cases, the oxide semiconductor film 110 has the following characteristics.

[0087] In addition, a source electrode 112a and a drain electrode 112b are formed on the oxide semiconductor film 110. At this stage, transistor 150 is formed.

[0088] Next, the first insulating film 108, the oxide semiconductor film 110, the source electrode 112a, the drain electrode Insulating films 114 and 116 are formed on the electrode 112b and the second wiring 112c (FIG. 5(B) reference).

[0089] The insulating films 114 and 116 are made of a material having a structure similar to that of the oxide semiconductor used for the oxide semiconductor film 110. To improve the interface properties, inorganic insulating materials containing oxygen can be used. Examples of inorganic insulating materials include silicon oxide films and silicon oxynitride films. The insulating films 114 and 116 may be formed by using, for example, the PE-CVD method. This can be done.

[0090] The thickness of the insulating film 114 is 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the insulating film 116 can be set to 10 nm or less and preferably 30 nm or less. The thickness can be 30 nm or more and 500 nm or less, preferably 150 nm or more and 400 nm or less. Cut.

[0091] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating film In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single layer structure, the insulating film 116 may have a single layer structure, or the insulating film 116 may have a single layer structure. A laminated structure of three or more layers may also be used.

[0092] Next, desired regions of the insulating films 114 and 116 are processed to form openings 140 ( See Figure 5(C)).

[0093] The step of forming the opening 140 is the fourth patterning step.

[0094] The opening 140 is formed so as to expose at least the insulating film 107. In this embodiment, the opening 140 exposes a part of the surface of the insulating film 107 . The opening 140 can be formed by, for example, dry etching. However, the method for forming the opening 140 is not limited to this, and may be a wet etching method or Alternatively, the formation method may be a combination of dry etching and wet etching.

[0095] Next, an insulating film 118 is formed on the insulating film 116 and so as to cover the opening 140. By forming 118, a first insulating film including insulating films 114, 116, and 118 is formed on transistor 150. A second insulating film 120 is then formed (see FIG. 5(D)).

[0096] The insulating film 118 is resistant to external impurities such as water, alkali metals, alkaline earth metals, etc. is a film formed of a material that prevents diffusion of hydrogen into the oxide semiconductor film 110. include.

[0097] An example of the insulating film 118 is a silicon nitride film having a thickness of 150 nm or more and 400 nm or less. A silicon nitride oxide film or the like can be used. In this embodiment, the insulating film 118 A silicon nitride film having a thickness of 150 nm is used.

[0098] The silicon nitride film is formed at a high temperature to improve its ability to block impurities. For example, the substrate temperature is preferably 100° C. or higher and lower than the distortion point of the substrate, more preferably It is preferable to form the film by heating at a temperature of 300°C or more and 400°C or less. In this case, oxygen is released from the oxide semiconductor used as the oxide semiconductor film 110, and the carriers The temperature should be set so that this phenomenon does not occur. .

[0099] In FIG. 5D, although not shown, an insulating film is further formed above the insulating film 118. The insulating film may be formed by, for example, a PE-CVD method using organic silane gas. The silicon oxide film formed by the above method can be used. The organic silane gas can be ethyl silicate (TEOS : Chemical formula Si(OC2H5)4), tetramethylsilane (TMS: Chemical formula Si(CH3) 4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetra Siloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2) 3) and other silicon-containing compounds can be used. For example, organic silane gas and oxygen are used, and the substrate temperature is set to 200° C. or higher and 550° C. or lower, preferably PE-CV at 220°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower It can be formed by Method D.

[0100] The insulating film 118 is further formed on the insulating film 118 to form the transistor 150. Furthermore, the insulating film described above is made of an inorganic material. Therefore, compared with a planarization resin film using an organic material, the oxide semiconductor film 110 is formed by This is preferable because it contains few impurities that have an adverse effect.

[0101] Next, desired regions of the insulating films 114, 116, and 118 are processed to form openings 142a, 142b and 142c are formed (see FIG. 6(A)).

[0102] The process of forming the openings 142a, 142b, and 142c is the fifth patterning process. This becomes:

[0103] The opening 142a is formed so as to expose a part of the drain electrode 112b. The opening 142b is formed so as to expose a part of the first wiring 104b. The opening 142c is formed so as to expose a part of the second wiring 112c. The openings 142a, 142b, and 142c can be formed by, for example, dry etching. However, the openings 142a, 142b, and 142c can be formed by the following method. The etching method may be a wet etching method or a dry etching method and a wet etching method. A combination of these methods may also be used.

[0104] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film is processed into a desired region to form a conductive film 122a that functions as a pixel electrode, and At this stage, the connection portion 160 is formed. is formed (see FIG. 6(B)).

[0105] The step of forming the conductive films 122a and 122b is the sixth patterning step.

[0106] In addition, in the connection portion 160, the distance between the upper end and the lower end of the second wiring 110c is , on the ends of the source electrode 112a and the drain electrode 112b of the transistor 150. In other words, the shape of the end of the second wiring 110c is The taper angle is smaller than that of the source electrode 112a and the drain electrode 112b. The angle is the angle between the source electrode 112a, the drain electrode 112b, and the second wiring 112c. When observed from a direction perpendicular to the cross section, the source electrode 112a, the drain electrode 112b, and The angle of inclination between the bottom surface and the side surface of the second wiring 112c is also shown. The taper angle of the curved shape is such that the bottom surfaces of the source electrode, the drain electrode, and the second wiring are aligned. It represents the inclination angle formed by any point on a shape with curvature.

[0107] By making the second wiring 112c have the above-mentioned shape, it functions as a third wiring. This can improve the coverage of the conductive film 122b.

[0108] In addition, in the connection portion 160, the first wiring 104b and the second wiring 110c are connected to a third wiring The connection is made via the conductive film 122b which functions as a line.

[0109] The conductive films 122a and 122b can be formed using an oxide film containing indium. For example, indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium dioxide, indium oxide containing titanium dioxide, Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc Conductive materials with transparency, such as indium tin oxide and silicon oxide, are used. In addition, the conductive films 122a and 122b can be formed of can be formed by using, for example, a sputtering method.

[0110] Through the above steps, the transistor 150 and the connection portion 160 on the substrate 102 can be formed.

[0111] Note that in the semiconductor device of one embodiment of the present invention, the transistor 150 and the connection portion 160 are formed on the same substrate. It can be fabricated using six masks (six patterning steps). As a result, a semiconductor device with excellent productivity can be provided.

[0112] Next, a modified example of the semiconductor device of one embodiment of the present invention shown in FIGS. 1A and 1B will be described. The following explanation will be given using Figs. 5(A), (B), and (C). The same symbols are used for parts having the same functions, and their repetition is The explanation will be omitted.

[0113] <Configuration Example (Modification) of Semiconductor Device> 15A is a top view of a semiconductor device of one embodiment of the present invention, and FIG. 15B is a top view of a semiconductor device of FIG. 5(A) corresponds to a cross-sectional view of the cut surface between dashed dotted lines AB and CD. FIG. 15(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line EF in FIG. 15(A). In FIG. 15A, in order to avoid complication, the components of the semiconductor device are not shown. Some elements (such as an insulating film that functions as a gate insulating film) are omitted in the illustration.

[0114] The semiconductor device shown in FIGS. 15A, 15B, and 15C includes a transistor 450 and a connecting portion 4 60 and has.

[0115] The transistor 450 has a gate electrode 104a on the substrate 102 and a gate electrode 104b on the gate electrode 104a. a first insulating film 108 formed on the gate electrode 10; 4a and an oxide semiconductor film 410a formed in a position overlapping the oxide semiconductor film 410a. It has a source electrode 412a and a drain electrode 412b that are electrically connected to each other.

[0116] 15(B) and (C), the first insulating film 108 is insulated from the insulating film 106. The film 107 has a two-layer laminate structure.

[0117] In addition, on the transistor 450, more specifically, the oxide semiconductor film 410a and the source electrode 41 2a and the drain electrode 412b, a second insulating film 120 is formed on the gate electrode 412b. In (C), the second insulating film 120 is made of three insulating films 114, 116, and 118. 1 illustrates a stack of layers.

[0118] In addition, an opening 142a is formed in the second insulating film 120, reaching the drain electrode 412b. In addition, a pixel electrode is formed on the second insulating film 120 so as to cover the opening 142a. The conductive film 122a is formed on the transistor 450. It is connected to the drain electrode 412b.

[0119] The connection portion 460 is connected to the first wiring 104b on the substrate 102 and the first wiring 104b. the insulating film 108, the opening 142b provided in the first insulating film 108, and the first insulating film 10 8, an oxide semiconductor film 410b, a second wiring 412c on the oxide semiconductor film 410b, The second insulating film 120 on the second wiring 412c and the opening 1 provided in the second insulating film 120 40, and the first wiring 104b formed to cover the opening 142b and the opening 140. and a conductive film 122b that functions as a third wiring that connects the second wiring 412c.

[0120] The first wiring 104b is formed in the same process as the gate electrode 104a of the transistor 450. In other words, the first wiring 104b is formed on the gate electrode 10 of the transistor 450. The second wiring 412c is formed on the same surface as the transistor 450. The second electrode 412a and the second electrode 412b are formed in the same process. The wiring 412c is connected to the source electrode 412a and the drain electrode 412b of the transistor 450. It is formed on the same surface as

[0121] The semiconductor device shown in FIGS. 1(A) and 1(B) of the semiconductor device shown in FIGS. 15(A), 15(B), and 15(C) The structure different from the above includes an oxide semiconductor film 410a, an oxide semiconductor film 410b, a source electrode, and a The electrode 412a, the drain electrode 412b, and the second wiring 412c. The materials that can be used for the conductive films 410a and 410b include the materials shown in FIGS. The same material as that of the oxide semiconductor film 110 of the semiconductor device can be used. The source electrode 412a, the drain electrode 412b, and the second wiring 412c can be used. The material is the same as that of the source electrode 112a and the drain electrode 112b of the semiconductor device shown in FIGS. The material that can be used for the electrode 112b and the second wiring 112c can be used. .

[0122] In the semiconductor device shown in FIGS. 15A, 15B, and 15C, the oxide semiconductor film 410a , 410b, a source electrode 412a, a drain electrode 412b, and By forming the conductive film that becomes the second wiring 412c in the same process, the number of masks can be reduced and the manufacturing process can be simplified. This reduces manufacturing costs.

[0123] <Method for manufacturing semiconductor device (modification)> A method for manufacturing a semiconductor device according to one embodiment of the present invention, which is illustrated in FIGS. This will be explained below with reference to FIGS. 16 and 17.

[0124] First, a conductive film is formed on the substrate 102, and the conductive film is subjected to a first patterning process and an etching process. The gate electrode 104a and the first wiring 104b are then formed by a etching process. A first insulating film including insulating films 106 and 107 is formed on the gate electrode 104a and the first wiring 104b. An insulating film 108 is formed. The steps up to this point are the same as the steps shown in FIG.

[0125] Next, an oxide semiconductor film 410 and a conductive film 412 are formed over the insulating film 107 (FIG. 16(A) )reference).

[0126] Next, resist masks 448a and 448b are formed in desired regions on the conductive film 412 ( See Figure 16(B)).

[0127] The resist masks 448a and 448b are formed by forming a photosensitive resin over the conductive film 412. After that, the resist mask is exposed using a gray-tone mask or a half-tone mask. By using the gate electrodes 448a and 448b, the oxide semiconductor film serving as a channel formation region and the source The electrode and the drain electrode can be formed at the same time. The resist mask 448b in the region can be formed in a stepped shape. For the blocks 448a and 448b, negative or positive photosensitive resin can be used. However, it is preferable to use a positive photosensitive resin, as this allows for finer shapes to be obtained. do.

[0128] Here, a group capable of forming resist masks 448a and 448b using FIG. The gray-tone mask will now be explained. Figure 18 shows a schematic diagram of the top surface of the gray-tone mask. For example, the gray-tone mask shows a transistor portion 470 and a connection portion 472. The transistor section 470 includes a region 474, a region 475, a region 476, and and the connecting portion 472 has a region 474, a region 475, and a region 478. .

[0129] For example, the region 474 is a light blocking region, the region 475 is a light transmitting region, and the region 476 is a first The light transmittance is determined as follows: By setting the order of area 475 > area 476 > area 478 > area 474, as shown in FIG. 16(B), Resist masks 448a and 448b can be formed. The light irradiated to 48a and 448b is i-line (wavelength 365 nm) and / or g-line (wavelength 436 nm) and the like. Note that ArF excimer lasers have wavelengths shorter than the i-line. A KrF excimer laser or the like may also be used.

[0130] Next, the conductive film 412 and the oxide semiconductor film 41 are removed over the resist masks 448a and 448b. During the etching process, the resist mask 448a is etched back or The resist mask 448 is then shrunk and separated into resist masks 448c and 448d. At this stage, the oxide semiconductor film 448b is recessed or shrunk to form a resist mask 448e. The oxide semiconductor film 410 is separated into oxide semiconductor films 410a and 410b (see FIG. 16C). Then, the conductive film 412 is subjected to etching treatment. After etching, a resist mask is formed. By removing 448c, 448d, and 448e, the source electrode 412a and the drain electrode 4 Then, a second wiring 12b and a second wiring 412c are formed (see FIG. 16D).

[0131] The oxide semiconductor films 410a and 410b, the source electrode 412a, and the drain electrode 412 The step of forming the second wiring 412b and the second wiring 412c constitutes a second patterning step.

[0132] In this manner, the oxide semiconductor films 410a and 410b, the source electrode 412a, the drain electrode When forming the first wiring 412b and the second wiring 412c, a gray-tone mask or halftone mask is used. By forming the resist using a thin mask, it is possible to reduce the number of masks by one. become.

[0133] In addition, by changing the shapes of the resist masks 448a and 448b, the so The end of the source electrode 412a and the drain electrode 412b is different in shape from the end of the second wiring 412c. It can be a shape.

[0134] In this embodiment, the oxide semiconductor film 410 and the conductive film 412 are etched. For this purpose, a dry etching method is used.

[0135] Note that when the oxide semiconductor film 410 and the conductive film 412 are etched, the resist mask 4 Depending on the thickness or shape of the oxide semiconductor film 48a, a part of the oxide semiconductor film 410a may disappear, forming a recess. In some cases, the oxide semiconductor film 410a becomes a thin film.

[0136] At this stage, transistor 450 is formed.

[0137] Next, the first insulating film 108, the oxide semiconductor film 410a, the source electrode 412a, the drain electrode 412b, and the Insulating films 114 and 116 are formed on the electrode 412b and the second wiring 412c (FIG. 16( (See E).

[0138] Next, desired regions of the insulating films 114 and 116 are processed to form openings 140 ( See Figure 17(A).

[0139] The step of forming the opening 140 is the third patterning step.

[0140] Next, an insulating film 118 is formed on the insulating film 116 and so as to cover the opening 140. By forming 118, the first insulating film including insulating films 114, 116, and 118 is formed on the transistor 450. A second insulating film 120 is formed (see FIG. 17(B)).

[0141] Next, desired regions of the insulating films 114, 116, and 118 are processed to form openings 142a, 142b and 142c are formed (see FIG. 17(C)).

[0142] The process of forming the openings 142a, 142b, and 142c is the fourth patterning process. This becomes:

[0143] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film is processed into a desired region to form a conductive film 122a that functions as a pixel electrode, and At this stage, the connection portion 460 is formed. is formed (see FIG. 17(D)).

[0144] The step of forming the conductive films 122a and 122b is the fifth patterning step.

[0145] In addition, in the connection portion 460, the distance between the upper end and the lower end of the second wiring 410c is , on the ends of the source electrode 412a and the drain electrode 412b of the transistor 450. In other words, the shape of the end of the second wiring 410c is The taper angle is smaller than that of the source electrode 412a and the drain electrode 412b.

[0146] By making the shape of the second wiring 412c as described above, it is possible to make it function as a third wiring. This can improve the coverage of the conductive film 122b.

[0147] In addition, in the connection portion 460, the first wiring 104b and the second wiring 410c are connected to a third wiring The connection is made via the conductive film 122b which functions as a line.

[0148] Through the above steps, the transistor 450 and the connection portion 460 on the substrate 102 can be formed.

[0149] Note that in the semiconductor device of one embodiment of the present invention, the transistor 450 and the connection portion 460 are formed on the same substrate. It can be fabricated using five masks (five patterning steps). As a result, a semiconductor device with excellent productivity can be provided.

[0150] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0151] (Embodiment 2) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Note that the same reference numerals as those shown in Figs. 1 to 6 are used, and the same reference numerals are used in the same manner. The explanation will be omitted.

[0152] The semiconductor device illustrated in FIG. 7 includes the transistor 150 described in Embodiment 1 and a capacitor 170. This is an example of a configuration in which the above are connected.

[0153] The transistor 150 has a gate electrode 104a on the substrate 102 and a gate electrode 104b on the gate electrode 104a. a first insulating film 108 formed on the gate electrode 10; The oxide semiconductor film 110 is formed at a position overlapping with the oxide semiconductor film 4a. The transistor has a source electrode 112a and a drain electrode 112b which are electrically connected to each other.

[0154] In addition, on the transistor 150, more specifically, the oxide semiconductor film 110 and the source electrode 112 A second insulating film 120 is formed on the drain electrode 112a and the drain electrode 112b. In this example, the second insulating film 120 has a three-layer laminate structure of insulating films 114, 116, and 118. There are.

[0155] The second insulating film 120 is provided with an opening 142a that reaches the drain electrode 112b. In addition, a pixel electrode is formed on the second insulating film 120 so as to cover the opening 142a. The conductive film 122a functions as a transistor 15. 0 is connected to the drain electrode 112b.

[0156] The capacitor 170 is formed by the oxide semiconductor film 110a and a part of the end of the oxide semiconductor film 110a. The insulating films 114 and 116 are formed to overlap with the oxide semiconductor film 110. a conductive film 122a formed on the insulating film 118. is doing.

[0157] The capacitor element 170 has a structure in which a dielectric film is disposed between a pair of electrodes. The oxide semiconductor film 110a functions as a conductive film and serves as one of the electrodes. The conductive film 122a functions as an oxide semiconductor film. The oxide semiconductor film 110 is formed in the same process as the oxide semiconductor film 110, in other words, on the same surface as the oxide semiconductor film 110. The conductive film 122a functions as a pixel electrode and an electrode of a capacitor. The dielectric film of the capacitor 170 is the second insulating film of the transistor 150. An insulating film 118 is used to function as part of the film.

[0158] In this manner, the transistor 150 and the capacitor 170 can be fabricated at the same time. By connecting the capacitor 170 to the transistor 150, one embodiment of the present invention can be realized. The semiconductor device can be used in, for example, a pixel portion of a liquid crystal display device.

[0159] Although not shown in FIG. 7, the connection part 160 shown in FIG. The capacitor element 170 may be formed at the same time.

[0160] In addition, the capacitor 170 has a light-transmitting property. the oxide semiconductor film 110a serving as the second electrode, the conductive film 122a serving as the second electrode, and the conductive film 122b serving as the third electrode. The insulating film 118 functioning as a conductive film may be formed of a light-transmitting oxide semiconductor film, a conductive film, or a In this way, the capacitor element 170 is made of an insulating film. This allows the capacitor 170 to be formed over a large area.

[0161] Here, a manufacturing method of the semiconductor device shown in FIG. 7 will be described with reference to FIGS. 8 and 9. .

[0162] First, a substrate 102 is prepared. Next, a conductive film is formed on the substrate 102, and the conductive film is then applied to a desired area. The gate electrode 104a is formed by processing the substrate 102 and the gate electrode 104b. A first insulating film 108 including an insulating film 106 and an insulating film 107 is formed on the port electrode 104a. After that, the oxide semiconductor film 110 and the oxide semiconductor film 110a are formed on the first insulating film 108. (See FIG. 8(A)).

[0163] The step of forming the gate electrode 104a is the first patterning step. The process of forming the oxide semiconductor film 110 and the oxide semiconductor film 110a is the same as the second patterning process. This is the manufacturing process.

[0164] Next, a thin film was formed on the first insulating film 108, the oxide semiconductor film 110, and the oxide semiconductor film 110a. A conductive film is formed and processed into a desired region, thereby forming a source electrode 112a and a drain electrode 112b. The rain electrode 112b is formed (see FIG. 8(B)).

[0165] The process of forming the source electrode 112a and the drain electrode 112b is the same as that of the third pattern. This is the cleaning process.

[0166] In addition, a source electrode 112a and a drain electrode 112b are formed on the oxide semiconductor film 110. At this stage, transistor 150 is formed.

[0167] Next, the first insulating film 108, the oxide semiconductor film 110, the oxide semiconductor film 110a, the source Insulating films 114 and 116 are formed on the electrode 112a and the drain electrode 112b (FIG. 8( See C).

[0168] Next, desired regions of the insulating films 114 and 116 are processed to form openings 140a. (See Figure 8(D)).

[0169] The step of forming the opening 140a is the fourth patterning step. The step of forming 40a can be performed simultaneously with the formation of opening 140 shown in FIG. 5(C). do.

[0170] The opening 140a is formed so as to expose at least a part of the oxide semiconductor film 110a. In this embodiment, the opening 140a exposes the surface of the oxide semiconductor film 110a. The opening 140a is formed by, for example, dry etching. However, the method for forming the opening 140a is not limited to this. , wet etching, or a combination of dry and wet etching. A forming method in which the above-mentioned is performed may also be used.

[0171] Next, an insulating film 116 is formed on the oxide semiconductor film 110a so as to cover the opening 140a. The insulating film 118 is formed. The insulating film 118 forms a second insulating film on the transistor 150. A film 120 is formed (see FIG. 9(A)).

[0172] The insulating film 118 is resistant to external impurities such as water, alkali metals, alkaline earth metals, etc. is a film formed of a material that prevents diffusion of hydrogen into the oxide semiconductor film 110. Therefore, when hydrogen in the insulating film 118 diffuses into the oxide semiconductor film 110a, the oxide semiconductor In the conductive film 110a, hydrogen bonds with oxygen or hydrogen bonds with oxygen vacancies to form carriers. As a result, the oxide semiconductor film 110a becomes highly conductive and light-transmitting. The resulting conductive film has excellent properties.

[0173] In this embodiment, the insulating film 118 in contact with the oxide semiconductor film 110a The method of introducing hydrogen is not limited to the above. A mask is provided over the oxide semiconductor film 110 functioning as a channel of 50. For example, hydrogen may be introduced into the undoped region using an ion doping device or the like. Hydrogen can be introduced into the oxide semiconductor film 110a.

[0174] Next, desired regions of the insulating films 114, 116, and 118 are processed to form openings 142a. (See FIG. 9(B)).

[0175] The step of forming the opening 142a is the fifth patterning step.

[0176] The opening 142a is formed so as to expose a part of the drain electrode 112b. The opening 142a can be formed by, for example, dry etching. However, the method for forming the opening 142a is not limited to this, and may be a wet etching method. Alternatively, a combination of dry etching and wet etching may be used. stomach.

[0177] Next, a conductive film is formed on the insulating film 118 so as to cover the opening 142a, and the conductive film is By processing the conductive film 122a into a region, the conductive film 122a functions as a pixel electrode and an electrode of a capacitor element. At this stage, the capacitor element 170 is formed (see FIG. 9C).

[0178] The step of forming the conductive film 122a is the sixth patterning step.

[0179] Through the above steps, the transistor 150 and the capacitor 170 can be formed over the substrate 102 .

[0180] Note that in the semiconductor device of one embodiment of the present invention, the transistor 150 and the capacitor 170 are formed on the same substrate. It can be fabricated using six masks (six patterning steps) on a plate. As a result, it is possible to provide a semiconductor device with excellent productivity.

[0181] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0182] (Embodiment 3) In this embodiment, a transistor that can be used as a semiconductor device according to one embodiment of the present invention will be described. The structure of the transistor will be explained with reference to FIG.

[0183] The semiconductor device shown in FIG. 10A is a semiconductor device including transistor 1 included in the semiconductor device described above. The oxide semiconductor film 110 of FIG. 50 is formed by stacking an oxide semiconductor film 111a and an oxide film 111b. Therefore, the other configurations are the same as those of the transistor 150. The explanation can be taken into consideration.

[0184] Here, the oxide semiconductor film 111a and the oxide film 111b will be described in detail below.

[0185] The oxide semiconductor film 111a and the oxide film 111b have at least one common constituent element. It is preferable to use a metal oxide. Alternatively, the oxide semiconductor film 111a and the oxide film 111 The constituent elements of b may be the same, and the compositions of the two may be different.

[0186] The oxide semiconductor film 111a is an In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, In the case of In-M-Zn oxides (Sn, La, Ce or Hf), the The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M: Zn=1:1:1, In:M:Zn=5:5:6(1:1:1.2), In:M:Zn= The atomic ratio of the oxide semiconductor film 111a to be formed is preferably 3:1:2, for example. The error is the ratio of the number of atoms of the metal elements contained in the sputtering target. Includes a minus 20% fluctuation.

[0187] When the oxide semiconductor film 111a is an In-M-Zn oxide, excluding Zn and O, The atomic ratio of In and M in the above is preferably 25 atomic % or more of In and 75 atomic % or more of M. more preferably, In is 34 atomic % or more and M is 66 atomic % or more Less than ic%.

[0188] The oxide semiconductor film 111a has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the energy gap is 3 eV or more. By using a semiconductor, the off-state current of a transistor can be reduced.

[0189] The thickness of the oxide semiconductor film 111a is 3 nm to 200 nm, preferably 3 nm or more. The thickness is set to 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0190] The oxide film 111b is typically an In-Ga oxide, an In-Zn oxide, an In-Mn oxide, or an In-GaAs oxide. Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), In addition, the energy of the bottom of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 111a. The energy of the bottom of the conduction band of the oxide film 111b and the energy of the conduction band of the oxide semiconductor film 111a are The difference in energy from the lower end of the band is 0.05 eV or more, 0.07 eV or more, or 0.1 eV or more , or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0. That is, the electron affinity of the oxide film 111b and the electron affinity of the oxide semiconductor film 111a are The difference from the electron affinity is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 0.15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less is.

[0191] The oxide film 111b has the above-mentioned M in a higher atomic ratio than In, and thus has the following effects: (1) The energy gap of the oxide film 111b is increased. (2) (3) To reduce the electron affinity of the oxide film 111b. (4) To block impurities from the outside. ) The insulating property is higher than that of the oxide semiconductor film 111a. Since M is a metal element with a strong magnetic field, oxygen vacancies occur when M is present in a higher atomic ratio than In. It becomes difficult.

[0192] When the oxide film 111b is an In-M-Zn oxide, In and O are not included. The atomic ratio of M is preferably less than 50 atomic % In and 50 atomic % M. % or more, more preferably, In is less than 25 atomic % and M is 75 atomic % or more. The above.

[0193] The oxide semiconductor film 111a and the oxide film 111b are made of In-M-Zn oxide (M is In the case of Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf, the oxide semiconductor film 1 The ratio of the number of M atoms contained in the oxide film 111b is larger than that of the oxide film 111a. The amount of the atoms contained in the compound semiconductor film 111a is 1.5 times or more, preferably 2 times or more. More preferably, the atomic ratio is three times or more higher.

[0194] The oxide film 111b is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide When the conductor film 111a has an atomic ratio of In:M:Zn=x2:y2:z2, y1 / x1 is greater than y2 / x2, and preferably, y1 / x1 is 1.5 times or more greater than y2 / x2. More preferably, y1 / x1 is at least twice as large as y2 / x2, and even more preferably In this case, y1 / x1 is three times or more larger than y2 / x2. When y2 is equal to or larger than x2, a transistor using an oxide semiconductor has stable electrical conductivity. However, if y2 is three times or more of x2, the oxide semiconductor Since the field effect mobility of the transistor using It is preferable to have one.

[0195] When the oxide semiconductor film 111a and the oxide film 111b are an In-M-Zn oxide, In- Atomic ratio of metal elements in the sputtering target used to deposit M-Zn oxide films It is preferable that M>In and Zn≧M are satisfied. The atomic ratio of the metal elements is In:Ga:Zn=1:3:2, In:Ga:Zn=1: 3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1:3:5, In:Ga: Zn=1:3:6, In:Ga:Zn=1:3:7, In:Ga:Zn=1:3:8, I n:Ga:Zn=1:3:9, In:Ga:Zn=1:3:10, In:Ga:Zn=1 :6:4, In:Ga:Zn=1:6:5, In:Ga:Zn=1:6:6, In:Ga :Zn=1:6:7, In:Ga:Zn=1:6:8, In:Ga:Zn=1:6:9, The preferred ratio is In:Ga:Zn=1:6:10. The atoms of the metal element contained in the oxide semiconductor film 111a and the oxide film 111b formed by The numerical ratios are calculated by taking into account the number of atoms of the metal elements contained in the sputtering target as an error. This includes a variation of plus or minus 20% in the ratio.

[0196] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the carrier density and the impurity concentration of the oxide semiconductor film 111a are controlled. The purity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. must be appropriate. It is preferable that

[0197] The oxide film 111b is formed as a protective film when forming the insulating film 114 or the insulating film 116 to be formed later. The oxide film 111b also functions as a film for reducing damage to the oxide semiconductor film 111a. is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less.

[0198] The oxide semiconductor film 111a contains silicon or carbon, which is one of the Group 14 elements. As a result, oxygen vacancies increase in the oxide semiconductor film 111a, causing the oxide semiconductor film 111a to become n-type. , the concentration of silicon or carbon in the oxide semiconductor film 111a, or the concentration of the oxide film 111b, The concentrations of silicon and carbon near the interface with the oxide semiconductor film 111a (measured by secondary ion mass spectrometry) The concentration obtained by 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0199] In addition, in the oxide semiconductor film 111a, alkali metal ions obtained by secondary ion mass spectrometry were The concentration of alkaline earth metals or alkaline earth metals is 1×10 18atoms / cm 3 The following is preferred: Kuha 2 x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are When the oxide semiconductor is bonded to the SiO2, carriers may be generated, and the off-state current of the transistor may decrease. Therefore, the alkali metal or alkali metal in the oxide semiconductor film 111a may increase. It is preferable to reduce the concentration of alkaline earth metals.

[0200] When nitrogen is contained in the oxide semiconductor film 111a, electrons serving as carriers are generated. The carrier density increases, making it easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor film 111 tends to be normally on. In a, it is preferable that nitrogen is reduced as much as possible. For example, the secondary ion mass The nitrogen concentration obtained by the analytical method is 5 x 10 18 atoms / cm 3 It is preferable to I wish.

[0201] Note that the oxide semiconductor film 111a and the oxide film 111b are not simply stacked layers. <Continuous junction (here, specifically, a structure in which the energy of the bottom of the conduction band changes continuously between each film) ) is formed at the interface of each film. The layer structure is such that there are no impurities that would form defect levels like the center. Impurities are present between the stacked oxide semiconductor film 111a and the stacked oxide film 111b. When this happens, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. They combine and disappear.

[0202] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each film is laminated in succession using a sputtering device without being exposed to the atmosphere. Each chamber in the sputtering device is required for the oxide semiconductor film. In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gases, especially gases containing carbon or hydrogen, from flowing back into the .

[0203] Here, the band structure of the stacked layer structure included in the transistor 150 is shown in FIG. This will be explained using:

[0204] FIG. 10B schematically illustrates a part of the band structure of the transistor 150. Here, the case where silicon oxide films are provided as the insulating films 107 and 114 will be described. 10B is the silicon oxide used as the insulating film 107. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 111a. EcS2 denotes the energy of the bottom of the conduction band of the oxide film 111b, and E cI2 represents the energy of the bottom of the conduction band of the silicon oxide film used as the insulating film 114.

[0205] As shown in FIG. 10B, in the oxide semiconductor film 111a and the oxide film 111b, The energy at the bottom of the conduction band changes smoothly without any barrier. In other words, it changes continuously. This is because the oxide semiconductor film 111a and the oxide film 111b have a common oxygen is transferred between the oxide semiconductor film 111a and the oxide film 111b. This can be said to be because a mixed layer is formed by the

[0206] As shown in FIG. 10B, the oxide semiconductor film 111a serves as a well, and the channel region It can be seen that the oxide semiconductor film 111a is formed. The oxide film 111b has a continuously changing energy at the bottom of the conduction band, and therefore has an oxide semiconductor property. It can be said that the body film 111a and the oxide film 111b are continuously bonded to each other.

[0207] As shown in FIG. 10B, the oxide film 111b and the insulating film 114 are adjacent to each other. The reason is that the insulating film 114 is formed by impurities such as silicon or carbon, which are constituent elements of the insulating film 114, or by defects. Although a loop level may be formed, the oxide film 111b is provided, and thus the oxide semiconductor However, EcS1 and EcS2 When the energy difference between the oxide semiconductor film 111a and the oxide semiconductor film 111b is small, electrons in the oxide semiconductor film 111a exceed the energy difference. When electrons are captured in the trap level, the insulating film boundary A negative fixed charge is generated on the surface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 is preferably 0.1 eV or more. If the value is set to 0.15 eV or more, the fluctuation of the threshold voltage of the transistor is reduced and the transistor becomes stable. This is preferable because it results in excellent electrical properties.

[0208] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0209] (Fourth embodiment) In this embodiment, a transistor that can be used as a semiconductor device according to one embodiment of the present invention will be described. The structure of the transistor will be described with reference to FIG.

[0210] 11A to 11C are top views and diagrams of a transistor 151 included in a semiconductor device. 11A is a top view of the transistor 151, and FIG. 11B is a cross-sectional view of the transistor 151. FIG. 11(C) corresponds to a cross-sectional view of the cut surface between the dashed line AB in FIG. 11(A), and FIG. 11(D) corresponds to a cross-sectional view of the cut surface between the dashed line AB in FIG. 11(A) corresponds to the cross-sectional view of the cut surface between the dashed line CD. Therefore, some of the components are omitted in the illustration.

[0211] The transistor 151 shown in FIGS. 11B and 11C is a channel-etched transistor. The transistor is a gate electrode 104a provided on the substrate 102, and a gate electrode 104b is provided on the substrate 102. A first insulating film 108 including an insulating film 106 and an insulating film 107 formed on the bottom electrode 104a. and an oxide semiconductor film 110 overlapping the gate electrode 104a with the first insulating film 108 interposed therebetween. The source electrode 112a and the drain electrode 112b are in contact with the oxide semiconductor film 110. In addition, the first insulating film 108, the oxide semiconductor film 110, the source electrode 112a, and the drain electrode 112b are A second insulating film 120 including insulating films 114, 116, and 118 is formed on the first electrode 112b. and a gate electrode 122c formed on the insulating film 120. The gate electrode 122c is In the openings 142d and 142e provided in the first insulating film 108 and the second insulating film 120, Thus, it is connected to the gate electrode 104a.

[0212] Note that the first insulating film 108 functions as a first gate insulating film of the transistor 151. The second insulating film 120 functions as a second gate insulating film of the transistor 151. In addition, the conductive film 122a functions as a pixel electrode.

[0213] The transistor 151 described in this embodiment has a gate electrode 104a and a gate electrode 122. Between the first insulating film 108 and the second insulating film 120, the oxide semiconductor film 110 is formed. As shown in FIG. 11(A), the gate electrode 104a has a top view The first insulating film 108 overlaps with the side surface of the oxide semiconductor film 110 with the first insulating film 108 interposed therebetween.

[0214] The first insulating film 108 and the second insulating film 120 have a plurality of openings. 11(B), the drain electrode 112b has an opening 142a through which a part of the drain electrode 112b is exposed. 11C, the oxide semiconductor film 110 is That is, the oxide semiconductor film 110 has openings 142d and 142e sandwiching the openings. The opening 142a has openings 142d and 142e. The gate electrode 104a and the film 122a are connected to each other through the openings 142d and 142e. That is, in the channel width direction, the gate electrode 10 is connected to the gate electrode 122c. 4a and the gate electrode 122c are electrically connected to each other through the first insulating film 108 and the second insulating film 120. The gate electrode 142a is formed on the side surface of the opening 142d. The portion 122c faces the side surface of the oxide semiconductor film 110.

[0215] The gate electrode 104a and the gate electrode 122c are The gate electrode 122c is set to the same potential, and the side surface of the oxide semiconductor film 110 is connected to the gate electrode 122c. By facing each other, the gate electrode 104a and the gate electrode 104b are The electrode 122c is connected to the oxide semiconductor film 11 via the first insulating film 108 and the second insulating film 120. 0, the region in which carriers flow in the oxide semiconductor film 110 is surrounded by the first insulating film. The interface between the second insulating film 120 and the oxide semiconductor film 11 Since carriers flow not only at the interface with the oxide semiconductor film 110 but also in a wide range of the oxide semiconductor film 110, , the amount of carrier movement in the transistor 151 increases.

[0216] As a result, the on-current of the transistor 151 increases and the field effect mobility also increases. Typically, the field-effect mobility is 10 cm 2 / V·s or more, even 20cm 2 / V·s The field-effect mobility here is the mobility as a physical property value of the oxide semiconductor film. It is not an approximation of the current driving force in the saturation region of the transistor, but an index of the current driving force in the saturation region of the transistor. The field-effect mobility is 0.5 μm or more and 6.5 μm or less, preferably more than 1 μm and less than 6 μm, more preferably 1 μm more preferably, greater than 1 μm and less than 3.5 μm; By making the thickness greater than 1 μm and less than 2.5 μm, the increase in field effect mobility is significant. In addition, the channel length is small, between 0.5 μm and 6.5 μm, so the channel width It is also possible to make it smaller.

[0217] For this reason, a plurality of regions are provided to serve as connection portions between the gate electrode 104a and the gate electrode 122c. Even if this is the case, the area of ​​the transistor 151 can be reduced.

[0218] In addition, at the end portion of the oxide semiconductor film 110 that has been processed by etching or the like, The damage caused by this leads to the formation of defects, and the material is contaminated by the adhesion of impurities. In the transistor 151, only one of the gate electrode 104a and the gate electrode 122c is formed. In this case, even if the oxide semiconductor film 110 is intrinsic or substantially intrinsic, By applying stress, the end portion of the oxide semiconductor film 110 is activated and becomes an n-type (low resistance area).

[0219] The n-type end is provided between the source electrode 112a and the drain electrode 112b. As a result, the n-type region becomes a path for carriers, forming a parasitic channel. As a result, the drain current increases gradually at the threshold voltage, and the threshold voltage is However, as shown in Figure 11(C), , the gate electrode 104a and the gate electrode 122c are at the same potential, and The gate electrode 122c is in contact with the oxide semiconductor film 11 on the side surface of the second insulating film 120. By facing the side surface of the oxide semiconductor film 110, the electric field of the gate electrode 122c is As a result, the side surface of the oxide semiconductor film 110 or the side surface and its vicinity is affected. The occurrence of parasitic channels at the edge is suppressed. As a result, the drain This results in a transistor with excellent electrical characteristics, with a steep rise in on-current.

[0220] Furthermore, by having the gate electrode 104a and the gate electrode 122c, each of them can be externally Since the gate electrode 104a has a function of shielding the electric field from the substrate 102, the gate electrode 104a is Charges of charged particles or the like provided on the electrode 122c do not affect the oxide semiconductor film 110. As a result, stress tests (e.g., applying a negative potential to the gate electrode) Deterioration during the Bias-Temperature stress test is suppressed, and , the fluctuation of the on-current rising voltage at different drain voltages can be suppressed. .

[0221] The BT stress test is a type of accelerated test that detects the transitions that occur during long-term use. It is possible to evaluate the characteristic changes (i.e., aging) of the transistor in a short time. The amount of change in the threshold voltage of a transistor before and after stress testing is used to examine reliability. This is an important indicator. The smaller the amount of change in threshold voltage before and after the BT stress test, the better. Therefore, it can be said that this is a highly reliable transistor.

[0222] Note that the transistor 151 is manufactured as follows.

[0223] The openings 142d and 142e shown in FIGS. 11(B) and 11(C) are the same as the opening 142a. In other words, the gate electrode 122c can be formed at the same time as the opening 142a. is formed in the same process as the conductive film 122a having the function of a pixel electrode, that is, the conductive film 122a can be formed simultaneously.

[0224] The manufacturing steps other than the openings 142d and 142e and the gate electrode 122c are the same as those in the embodiment. The manufacturing method is similar to that of the transistor 150 of the first embodiment, and therefore, description thereof will be omitted here.

[0225] In this way, in a semiconductor device including a transistor having an oxide semiconductor film, A semiconductor device having excellent characteristics can be obtained. In a semiconductor device having a capacitor, a highly reliable semiconductor device can be obtained.

[0226] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. They can be used in appropriate combination.

[0227] (Embodiment 5) In this embodiment, an oxide semiconductor film applicable to the transistor 150 in Embodiment 1 is An example will be described.

[0228] <Crystallineness of oxide semiconductor film>

[0229] The structure of the oxide semiconductor film will be described below.

[0230] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0231] First, the CAAC-OS film will be described.

[0232] The CAAC-OS film is one of the oxide semiconductor films with multiple crystal parts. The crystal part is small enough to fit inside a cube with a side length of less than 100 nm. The crystals contained in the OS film are cubes with sides of less than 10 nm, 5 nm, or 3 nm. This also includes cases where the size fits inside.

[0233] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystals are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0234] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0235] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0236] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0237] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0238] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0239] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0240] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0241] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0242] Furthermore, the crystallinity of the CAAC-OS film may not be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface to be formed. When impurities are added to the AC-OS film, the crystallinity of the region where the impurities are added changes, and the Regions of differing crystallinity may be formed.

[0243] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0244] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0245] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0246] The CAAC-OS film is an oxide semiconductor film with a low density of defect states.

[0247] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0248] Next, a microcrystalline oxide semiconductor film will be described.

[0249] In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, the grain boundaries may not be clearly visible.

[0250] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. be.

[0251] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0252] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, C a laminated film having two or more of the AAC-OS films may be used.

[0253] <Formation method of CAAC-OS film> The CAAC-OS film is formed, for example, by a sputtering method using a target for sputtering an oxide semiconductor that is polycrystalline. When ions collide with the sputtering target, the crystal regions contained in the sputtering target split from the a-b plane, and are peeled off as flat plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a-b plane. In this case, the CAAC-OS film can be formed by the flat plate-shaped or pellet-shaped sputtering particles reaching the substrate while maintaining the crystalline state. The flat plate-shaped or pellet-shaped sputtering particles reach the substrate while maintaining the crystalline state, thereby forming the CAAC-OS film.

[0254] The flat plate-shaped or pellet-shaped sputtering particles have, for example, a circular equivalent diameter of the plane parallel to the a-b plane of 3 nm or more and 10 nm or less, and a thickness (length in the direction perpendicular to the a-b plane) of 0.7 nm or more and less than 1 nm. Note that the flat plate-shaped or pellet-shaped sputtering particles may have a plane parallel to the a-b plane that is a regular triangle or a regular hexagon. Here, the circular equivalent diameter of the plane refers to the diameter of a perfect circle equal to the area of the plane.

[0255]

[0256] In addition, in order to form the CAAC-OS film, it is preferable to apply the following conditions. By increasing the substrate temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the film is formed with the substrate temperature being from not less than 100°C to not more than 740°C, preferably from not less than 200°C to not more than 500°C. By increasing the substrate temperature during film formation, the flat plate-shaped or pellet-shaped​​ When the sputtered particles reach the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate. By being charged, the sputtering particles repel each other and adhere to the substrate. The ring particles do not overlap unevenly, resulting in the formation of a CAAC-OS film with a uniform thickness. It is possible.

[0257] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0258] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0259] Alternatively, the CAAC-OS film is formed by the following method.

[0260] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500°C or less, preferably 150°C to 450°C, and the oxygen ratio in the deposition gas is set to 30 The film is formed at a concentration of at least 100% by volume, preferably 100% by volume.

[0261] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be carried out at a pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0262] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0263] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by sputtering. Specifically, the substrate temperature is set to 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower. The temperature is set to 0°C or lower, and the oxygen ratio in the film-forming gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0264] Next, heat treatment is performed to form a second oxide semiconductor film from the first CAAC-OS film by solid-phase growth. The second CAAC-OS film was obtained by heating at a temperature of 350 The temperature is set to 740°C or higher, preferably 450°C or higher and 650°C or lower. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be carried out in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen deficiency can be reduced by heat treatment in a reactive atmosphere. It may be carried out under reduced pressure of 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0265] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. The CAAC-OS film can be suitably used as an oxide semiconductor film in an oxide stack. You can be there.

[0266] Next, for example, the substrate is not heated, so that the surface to be formed is kept at a low temperature (for example, less than 130°C). , oxide film at temperatures below 100°C, below 70°C, or room temperature (20°C to 25°C) A method for forming the above will be described.

[0267] When the surface to be formed is at a low temperature, the sputtered particles fall irregularly onto the surface. For example, because there is no migration, there is no area where other sputtered particles have already accumulated. That is, the oxide film obtained by deposition has a uniform thickness, for example. The oxide film obtained in this way may not only be uniform but also have a disordered crystal orientation. The sputter particles have crystalline portions (nanocrystals) to maintain the crystallinity to some extent.

[0268] In addition, for example, when the pressure during film formation is high, the flying sputtered particles may be mixed with other gases such as argon. The frequency of collisions with other particles (atoms, molecules, ions, radicals, etc.) increases. However, the crystal structure may be destroyed by collisions with other particles during flight (resputtering). For example, sputtered particles collide with other particles and form into flat or pellet-like shapes. The structure may not be maintained and may be fragmented (e.g., separated into individual atoms). At this time, atoms separated from the sputtered particles are deposited on the surface to be formed, forming an amorphous oxide. A nitride film may be formed.

[0269] Also, instead of a sputtering method using a target having a polycrystalline oxide as a starting point, In the case of a method of forming a film using a liquid, or by gasifying a solid such as a target, a film is formed. In the case of the method, the atoms fly in a separated state and deposit on the surface to be formed, so amorphous oxide In laser ablation, for example, the target Atoms, molecules, ions, radicals, clusters, etc. emitted from the As a result, an amorphous oxide film may be formed.

[0270] The oxide semiconductor film included in the resistor and the transistor of one embodiment of the present invention may be any of the above-described oxide semiconductor films. An oxide semiconductor film having a stacked structure may be used. In this case, the crystal state of each oxide semiconductor film may be different from that of the other oxide semiconductor films. A CAAC-OS film is preferably used as the oxide semiconductor film functioning as the panel. The oxide semiconductor film included in the resistor element has a higher resistance than the oxide semiconductor film included in the transistor. Since the impurity concentration is higher than that of silicon dioxide, the crystallinity may be reduced.

[0271] As described above, the structures, methods, etc. described in this embodiment may be different from the structures, methods, etc. described in other embodiments. They can be used in appropriate combinations.

[0272] (Embodiment 6) In this embodiment, an example in which a semiconductor device according to one embodiment of the present invention is applied to a display device will be described. The following description will be given with reference to the drawings. Note that the same reference numerals as those in the previous embodiment are used to designate the same parts or components. The parts having the above functions are denoted by the same reference numerals, and detailed explanations thereof will be omitted.

[0273] An example of a display device is shown in Fig. 12(A). The display device shown in Fig. 12(A) has a pixel section 20 0, a scanning line driving circuit 204, and a signal line driving circuit 206 are arranged parallel or approximately parallel to each other. m scanning lines 207, the potentials of which are controlled by a scanning line driving circuit 204, and The individual electrodes are arranged parallel or approximately parallel, and the potential is controlled by a signal line driving circuit 206. and n signal lines 209. Furthermore, the pixel section 200 has multiple The pixel array 301 has a number of pixels 301. The pixels 301 are arranged parallel or approximately parallel along the scanning line 207. The capacitance lines 215 are arranged along the signal line 209. The scanning line driving circuit 204 and the signal line driving circuit 205 may be arranged in rows or substantially parallel to each other. The circuit 206 may be collectively referred to as a drive circuit section.

[0274] Each scanning line 207 is connected to one of the pixels 202 arranged in m rows and n columns in the pixel section 200. The signal lines 209 are electrically connected to the n pixels 301 arranged in any one of the rows. is m pixels 301 arranged in m rows and n columns, and m pixels 301 arranged in any one of the columns. 1. Both m and n are integers equal to or greater than 1. is n pixels 301 arranged in any row among the pixels 301 arranged in m rows and n columns. 1. The capacitance lines 215 are arranged parallel to the signal lines 209. In the case where the pixels 301 are arranged in m rows and n columns, one of the pixels 301 is arranged in m rows and n columns. The pixel array 301 is electrically connected to m pixels 301 arranged in a column.

[0275] The semiconductor device described in Embodiment 1 includes a pixel 301 and a scan line driver circuit 2 shown in FIG. 04 and the signal line driver circuit 206. In particular, the scanning line driver circuit 204 The connection portion of the signal line driver circuit 206 has the connection portion 160 shown in the first embodiment. In addition, in the pixel 301, the transistor shown in Embodiment 2 is preferably used. It is preferable to apply a resistor 150 and a capacitance element 170.

[0276] 12B can be used for the pixel 301 of the display device shown in FIG. 1 shows an example of a circuit configuration.

[0277] The pixel 301 shown in FIG. 12B includes a liquid crystal element 322, a transistor 150, and a capacitor. It has a child 170.

[0278] The potential of one of the pair of electrodes of the liquid crystal element 322 is set appropriately according to the specifications of the pixel 301. The orientation state of the liquid crystal element 322 is set by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 322 included in each pixel 301. In addition, one of the pair of electrodes of the liquid crystal element 322 for each pixel 301 in each row may be applied. may be given different potentials.

[0279] The liquid crystal element 322 controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of the liquid crystal is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal element 322 is controlled by an electric field in a diagonal direction or an electric field in a diagonal direction. These include nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, discotic liquid crystals, Thermotropic liquid crystal, lyotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal polymer liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, main chain liquid crystals, side chain polymer liquid crystals, banana-shaped liquid crystals, etc. Examples include:

[0280] The display device having the liquid crystal element 322 can be driven in a variety of modes, including TN mode, STN mode, etc. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TB A (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electro Cally Controlled Birefringence mode, PDLC ( Polymer Dispersed Liquid Crystal (PNL) mode C (Polymer Network Liquid Crystal) mode, guest However, there are other liquid crystal elements and their driving methods, including but not limited to the above. A variety of materials can be used.

[0281] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent The liquid crystal element may be configured by the following. The liquid crystal that exhibits the blue phase has a response speed of 1 msec or less. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0282] In the configuration of the pixel 301 shown in FIG. 12B, the source electrode of the transistor 150 and One of the drain electrodes is electrically connected to the signal line 209, and the other is connected to one of the pair of liquid crystal elements 322. The gate electrode of the transistor 150 is electrically connected to the other electrode of the scan line The transistor 150 is electrically connected to the transistor 207. The transistor 150 can be turned on or off. This provides a function of controlling the writing of data signals.

[0283] In the configuration of the pixel 301 shown in FIG. 12B, one of the pair of electrodes of the capacitor 170 is , electrically connected to the capacitor line 215 to which a potential is supplied, and the other is electrically connected to the pair of liquid crystal elements 322 The potential value of the capacitance line 215 is determined by the specifications of the pixel 301. The capacitance element 170 serves as a storage capacitor for storing written data. It has the function of

[0284] For example, in a display device having the pixel 301 shown in FIG. 12B, the scanning line driver circuit 204 The pixels 301 in each row are selected in sequence, and the transistors 150 are turned on to transmit the data signal. Write the data.

[0285] The pixel 301 to which the data has been written is retained by turning off the transistor 150. By repeating this process for each row, an image can be displayed.

[0286] As described above, the structures, methods, etc. described in this embodiment may be different from the structures, methods, etc. described in other embodiments. They can be used in appropriate combinations.

[0287] (Embodiment 7) In this embodiment, a display module and an electronic device to which the semiconductor device of one embodiment of the present invention is applied will be described. The vessel will be described with reference to FIGS. 13 and 14.

[0288] The display module 8000 shown in FIG. 13 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and Display panel 8006, backlight 8007, frame 8009, printed circuit board 801 0, has battery 8011.

[0289] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0290] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0291] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0292] The backlight 8007 includes a light source 8008. 7 and a light diffusion plate may be used.

[0293] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0294] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0295] The display module 8000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. Additional ones may be provided.

[0296] 14(A) to 14(H) are diagrams showing electronic devices. These electronic devices are housed in a housing. Body 5000, display unit 5001, speaker 5003, LED lamp 5004, operation key 50 05 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 ( Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances , sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, 5008, a microphone 5009, etc. can.

[0297] FIG. 14(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 14(B) shows a portable terminal equipped with a recording medium. A portable image reproducing device (for example, a DVD reproducing device) is also included. The display unit 5002, the recording medium reading unit 5011, etc. It is a group-type display, and in addition to the above, it has a second display unit 5002, a support unit 5012 , earphones 5013, etc. FIG. 14(D) shows a portable gaming machine. In addition to the above, it may have a recording medium reading unit 5011, etc. It is a digital camera with a TV receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. It is a belt-type gaming machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 14(G) shows a television receiver, which, in addition to the above, has It can have a tuner, an image processor, etc. FIG. 14(H) shows a portable television receiver. In addition to the above, it has a charger 5017 capable of transmitting and receiving signals, etc. can be done.

[0298] The electronic devices shown in FIGS. 14A to 14H can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( It has a function to control processing by a program, a wireless communication function, and various controls using the wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, The function of receiving, reading out the program or data recorded on the recording medium and displaying it on the display Furthermore, in an electronic device having multiple display units, In this case, one display section is used mainly to display image information, and another display section is used mainly to display text information. or a function to display images that take parallax into account on multiple displays to create a three-dimensional effect. Furthermore, in electronic devices having an image receiving unit, The camera has the functions to take still images, record videos, and automatically or manually correct captured images. function to correct the image, to save the captured image to a recording medium (external or built-in to the camera), 14A to 14C, and the like. The functions that the electronic device shown in 4(H) can have are not limited to these, and various functions can be It can have.

[0299] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done. [Example]

[0300] In this example, Sample 1 was fabricated as a semiconductor device according to one embodiment of the present invention. In addition, Sample 2 was fabricated as a semiconductor device for comparison, and the cross section of Sample 2 was First, Sample 1 and Sample 2 will be described below.

[0301] FIG. 19(A) shows a cross-sectional view of Sample 1, and FIG. 19(B) shows a cross-sectional view of Sample 2.

[0302] (Sample 1) The semiconductor device shown in FIG. 19A includes a transistor 550 and a connection portion 560.

[0303] The transistor 550 includes a gate electrode 504a on the substrate 502 and a gate electrode 504b on the gate electrode 504a. a first insulating film 508 formed on the first insulating film 508 and a gate electrode 50 The oxide semiconductor film 510 is formed in a position overlapping with the oxide semiconductor film 4a. The transistor has a source electrode 512a and a drain electrode 512b which are electrically connected to each other.

[0304] The first insulating film 508 was formed from the insulating film 506 and the insulating film 507 .

[0305] In addition, the transistor 550, more specifically, the oxide semiconductor film 510 and the source electrode 512 A second insulating film 520 was formed on the first insulating film 512a and the drain electrode 512b. The insulating film 514, 516, and 518 were laminated into a three-layer structure.

[0306] In addition, an opening 542a reaching the drain electrode 512b is formed in the second insulating film 520. In addition, a conductive film serving as a pixel electrode was formed on the second insulating film 520 so as to cover the opening 542a. The conductive film 522a is a drain electrode of the transistor 550. It is connected to 512b.

[0307] The connection portion 560 is connected to the first wiring 504b on the substrate 502 and the first wiring 504b. the insulating film 508, the opening 542b provided in the first insulating film 508, and the first insulating film 50 8, a second wiring 512c on the second wiring 512c, a second insulating film 520 on the second wiring 512c, and a second insulating film The opening 540 provided in the insulating film 520, the opening 542b and the opening 540 are formed to cover the opening 542b. and functions as a third wiring that connects the first wiring 504b and the second wiring 512c. and a conductive film 522b.

[0308] The first wiring 504b is formed in the same process as the gate electrode 504a of the transistor 550. The second wiring 512c is connected to the source electrode 512a of the transistor 550 and It was formed in the same process as the drain electrode 512b.

[0309] (Sample 2) The semiconductor device shown in FIG. 19B includes a transistor 550 and a connection portion 570.

[0310] The transistor 550 has the same structure as the transistor 550 of Sample 1.

[0311] The connection portion 570 is connected to the first wiring 504b on the substrate 502 and the first wiring 504b. the insulating film 508, the opening 542b provided in the first insulating film 508, and the first insulating film 50 8, a second wiring 512d on the second wiring 512d, a second insulating film 520 on the second wiring 512d, and a second insulating film The opening 540 provided in the insulating film 520, the opening 542b and the opening 540 are formed to cover the opening 542b. and functions as a third wiring that connects the first wiring 504b and the second wiring 512d. and a conductive film 522b.

[0312] The semiconductor device (sample 1) shown in FIG. 19(A) and the semiconductor device (sample 2) shown in FIG. 19(B) ) are the methods for forming the second wiring 512c and the second wiring 512d, and the cross-sectional shapes thereof. The methods for preparing Sample 1 and Sample 2 are explained below. The method for fabricating material 2 is the same as that for fabricating material 2 except for the second wiring 512c and the second wiring 512d. Therefore, the common manufacturing method will be explained in the same manner, and the repeated explanation will be omitted.

[0313] (Method for preparing sample 1) First, a substrate 502 was prepared. A glass substrate was used as the substrate 502. A conductive film that would become a gate electrode 504a and a first wiring 504b was formed on the substrate 502. As the conductive film, a tungsten film (W) was formed to a thickness of 200 nm by sputtering. After that, a first patterning step and an etching step are performed to form the gate electrode 504a and the first The wiring 504b was formed.

[0314] Next, an insulating film 506 is formed on the substrate 502, the gate electrode 504a, and the first wiring 504b. 507 was formed. As the insulating film 506, a silicon nitride film having a thickness of 400 nm was formed. The insulating film 507 is a silicon oxynitride film (SiON(1)) having a thickness of 50 nm. The silicon nitride film was made up of a first silicon nitride film (SiN(1)), a second silicon nitride film (SiN(2)), and a A three-layer structure consisting of a silicon film (SiN(2)), a silicon nitride film (SiN(3)), and a third silicon nitride film (SiN(4)). The first silicon nitride film (SiN(1)) was formed using silane at a flow rate of 200 sccm. The raw material gases were nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 100 sccm. The pressure in the reaction chamber was controlled to 100 Pa. A 12MHz high frequency power supply is used to supply 2000W of power, resulting in a thickness of 50nm. The second silicon nitride film (SiN(2)) was formed as follows: of silane, 2000 sccm of nitrogen, and 2000 sccm of ammonia gas. It is supplied as a raw material gas to the reaction chamber of the plasma CVD device, and the pressure in the reaction chamber is controlled to 100 Pa. The thickness was 30 mm. The third silicon nitride film (SiN(3)) was formed at a flow rate of 2 Plasma CV was performed using silane at a flow rate of 0.00 sccm and nitrogen at a flow rate of 5000 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency was generated. A power of 2000 W was supplied using a frequency power supply, and the film was formed to a thickness of 50 nm. The first silicon nitride film (SiN(1)) and the second silicon nitride film (SiN(2)) The substrate temperature during the formation of the third silicon nitride film (SiN(3)) was 350°C.

[0315] The silicon oxynitride film (SiON(1)) used as the insulating film 507 was Plasma CV using silane at a flow rate of 3000 sccm and nitrous oxide at a flow rate of 3000 sccm as source gases. The pressure in the reaction chamber was controlled to 40 Pa, and a high frequency of 27.12 MHz was generated. A silicon oxynitride film (SiON(1)) was formed by supplying 100 W of power using a microwave power supply. The substrate temperature during the formation of the silicon oxynitride film (SiON(1)) was 350°C. Ta.

[0316] Next, an oxide semiconductor is formed at a position overlapping the gate electrode 504a via insulating films 506 and 507. Here, a 35-nm-thick oxide semiconductor film was formed on the insulating film 507. The oxide semiconductor film 510 was formed by a second patterning method. The shape was processed by an etching process.

[0317] The oxide semiconductor film was prepared by using a sputtering target of In:Ga:Zn=1:1:1 (atomic ratio) The target was oxygen at a flow rate of 100 sccm and argon at a flow rate of 100 sccm. is supplied as a sputtering gas into the reaction chamber of the sputtering device, and the pressure in the reaction chamber is The oxide semiconductor film was formed by controlling the pressure to 0.6 Pa and supplying AC power of 2.5 kW. The substrate temperature during the formation was set to 170°C.

[0318] Next, the source electrode 512a and the drain electrode 512b in contact with the oxide semiconductor film 510 are A second wiring 512c was formed on the insulating film 507. 12a, a drain electrode 512b, and a second wiring 512c are formed by a third patterning process. The shape was processed by the third patterning process and the etching process. The source electrode 512a and the drain electrode 512b are formed by using a resist mask shown in FIG. A resist mask having the same shape as the second wiring 512c was used. As the resist mask, a resist mask having the same shape as the resist mask 148c shown in FIG. 4(D) is used. The resist mask for the region of the second wiring 512c was a gray-tone mask. A mask was used.

[0319] The source electrode 512a, the drain electrode 512b, and the second wiring 512c are made of a 5 mm thick metal. A 400 nm thick aluminum film (Al) is formed on a 0 nm thick tungsten film (W), A titanium film (Ti) with a thickness of 200 nm was formed on the aluminum film (Al). For the titanium (Ti) film, the aluminum (Al) film, and the titanium (W) film, The film was formed by sputtering.

[0320] Next, the substrate is moved into a depressurized reaction chamber, heated at 350°C, and then placed in the reaction chamber. A high-frequency power of 150 W was supplied to the upper electrode using a 27.12 MHz high-frequency power supply. The oxide semiconductor film 510 was exposed to oxygen plasma generated in a dinitrogen oxide atmosphere.

[0321] Next, the oxide semiconductor film 510, the source electrode 512a, the drain electrode 512b, and the second Insulating films 514 and 516 were formed to cover the wiring 512c. As the insulating film 516, a second oxide insulating film was formed.

[0322] First, after the oxygen plasma treatment, the first oxide insulating film is continuously formed without being exposed to the atmosphere. A 50-nm-thick oxynitride film was formed as the first oxide insulating film. A silicon film (SiON(2)) is formed, and a 400 nm thick oxide insulating film is formed. A silicon oxynitride film (SiON(3)) was formed. The silicon oxide film (SiON(2)) and the silicon oxynitride film (SiON(3)) are Since the film is formed using a variety of deposition gases, the interface may not be clearly visible.

[0323] The first oxide insulating film was formed using silane at a flow rate of 20 sccm and monoxide at a flow rate of 3000 sccm. Dinitrogen was used as the source gas, the pressure in the reaction chamber was 200 Pa, the substrate temperature was 350°C, and the power was 100 W. The film was formed by the plasma CVD method in which high frequency power of 1000 kJ / cm was supplied to parallel plate electrodes.

[0324] The second oxide insulating film was formed using silane at a flow rate of 160 sccm and monocarboxylic acid at a flow rate of 4000 sccm. Nitrogen dioxide was used as the source gas, the pressure in the reaction chamber was 200 Pa, the substrate temperature was 220°C, and The film was formed by plasma CVD in which 0 W of high frequency power was supplied to parallel plate electrodes. This results in the oxygen content exceeding the stoichiometric value, and some of the oxygen is removed by heating. A silicon oxynitride film that desorbs can be formed.

[0325] Next, heat treatment is performed to remove water, nitrogen, and hydrogen from the first oxide insulating film and the second oxide insulating film. and the like are desorbed, and part of the oxygen contained in the second oxide insulating film is The material was then supplied to the furnace 10. Here, heat treatment was carried out at 350°C for 1 hour in a nitrogen and oxygen atmosphere. Ta.

[0326] Next, openings 540 were formed in desired regions of the insulating films 514 and 516. The formation of the film was carried out by processing the shape through the fourth patterning step and the etching step. The opening 540 was formed by dry etching.

[0327] Next, an insulating film 518 was formed on the insulating film 516 so as to cover the opening 540. A nitride insulating film having a thickness of 100 nm was formed as 518. The nitride insulating film was formed by a flow rate of 50 silane at a flow rate of 5000 sccm, nitrogen at a flow rate of 5000 sccm, and ammonia at a flow rate of 100 sccm. The gas was used as the source gas, the pressure in the reaction chamber was 100 Pa, the substrate temperature was 350°C, and the power was 1000 W. The film was formed by the plasma CVD method in which high frequency power of 1000 kJ / cm was supplied to parallel plate electrodes.

[0328] Next, an opening 542a reaching the drain electrode 512b is formed in the insulating films 514, 516, and 518. , an opening 542b is formed in the insulating films 506 and 507, the opening 542b reaching the first wiring 504b, and the insulating film 514, An opening 542c reaching the second wiring 512c was simultaneously formed in 516 and 518. The openings 542a, 542b, and 542c are formed by a fifth patterning step and etching. The shape was processed by a molding process. For this purpose, a dry etching method was used.

[0329] Next, a conductive film 522a was formed over the insulating film 518 to cover the opening 542a. A conductive film serving as a third wiring is formed on the insulating film 518 so as to cover the openings 542b and 542c. The conductive films 522a and 522b were formed using the sixth patterning. The shape was processed by a grinding and etching process.

[0330] The conductive films 522a and 522b are formed by sputtering. Indium oxide-tin oxide compound containing silicon oxide (ITO-SiO2, hereafter referred to as ITSO The composition of the target used for the conductive film was In2O3:Sn The ratio of O2:SiO2 was 85:10:5 [wt %]. The formation method used was wet etching.

[0331] Through the above steps, Sample 1 according to one embodiment of the present invention was fabricated.

[0332] (Method for preparing sample 2) The method for preparing Sample 2 differs from the method for preparing Sample 1 only in the following points.

[0333] After forming the oxide semiconductor film 510, a source electrode 512 in contact with the oxide semiconductor film 510 is formed. A second wiring 512d was formed on the insulating film 507. The source electrode 512a, the drain electrode 512b, and the second wiring 512d were formed. The shape was processed by the third patterning step and the etching step. A normal mask was used for the source electrode 512a, the drain electrode 512b, and the second wiring 512d.

[0334] Comparative sample 2 was prepared by the above steps.

[0335] 20(A) and (B) show the cross-sectional observation results of Sample 1 and Sample 2.

[0336] In this embodiment, the connection portion 560 and the connection portion 57 shown in FIGS. 20(A) and 20(B) The cross-sectional observation results shown in Figures 20(A) and 20(B) are for S TEM(Scanning Transmission Electron Micro The results are those observed by the scopy method. The C in the figure represents the carbon (C) coating used during STEM observation, and the Pt in the figure represents S This shows the platinum (Pt) coating used during TEM observation.

[0337] From the results of FIG. 20(A), it is clear that the tungsten film ( The taper angle of the cross-sectional shape of the aluminum film (Al) and titanium film (Ti) is small. In this embodiment, the taper angle is the angle at which the sample is cut when viewed from the cross section (perpendicular to the surface of the substrate). When observed from the direction of the SiON (1) surface, the aluminum film (Al) and indicates the angle formed by the side of the titanium film (Ti). It can be seen that the silicon film (Ti) has receded. The cross-sectional shape of the second wiring 512c is shown in FIG. 20( ), the film formed above the second wiring 512c, In A), the coverage of SiON(2), SiON(3), SiN(4), and ITSO is It can be confirmed that it is good.

[0338] On the other hand, from the result of FIG. 20(B), it is found that the tungsten used as the second wiring 512d of Sample 2 The taper angles of the cross-sectional shapes of the tungsten (W), aluminum (Al), and titanium (Ti) films are It can be seen that the cross-sectional shape of the second wiring 512d is as shown in FIG. By forming the second wiring 512d in this shape, the film formed above the second wiring 512d, The coating of SiON(2), SiON(3), SiN(4), and ITSO is poor, especially S For iN(4) and ITSO, the coating is on an inverse tapered region.

[0339] The structure shown in this embodiment can be used in appropriate combination with other embodiment modes. [Explanation of symbols]

[0340] 102 Circuit Board 104a gate electrode 104b Wiring 106 insulating film 107 Insulating film 108 insulating film 110 Oxide semiconductor film 110a Oxide semiconductor film 110c wiring 111a Oxide semiconductor film 111b Oxide film 112 Conductive film 112_2 Wiring 112_3 Wiring 112a Source electrode 112b Drain electrode 112c wiring 112c_1 wiring 114 insulating film 116 Insulating film 118 insulating film 120 insulating film 122a Conductive film 122b Conductive film 122c Gate electrode 140 Aperture 140a aperture 142a aperture 142b aperture 142c aperture 142d aperture 142e aperture 144a area 144b area 148a Resist mask 148b Resist mask 148c Resist mask 150 transistors 151 transistors 160 Connection 170 Capacitive element 200 pixel unit 202 pixels 204 Scanning line driving circuit 206 Signal line driver circuit 207 scan lines 209 Signal Line 215 Capacitance Line 301 pixels 322 Liquid crystal element 410 Oxide semiconductor film 410a Oxide semiconductor film 410b Oxide semiconductor film 410c wiring 412 Conductive film 412a Source electrode 412b Drain electrode 412c wiring 448a Resist mask 448b Resist mask 448c Resist mask 448d Resist Mask 448e Resist mask 450 transistors 470 Transistor section 472 Connection 474 area 475 area 476 area 478 area 460 Connection 502 board 504a Gate electrode 504b wiring 506 Insulating film 507 Insulating film 508 insulating film 510 Oxide semiconductor film 512a Source electrode 512b Drain electrode 512c wiring 512d wiring 514 Insulating film 516 Insulating film 518 Insulating film 520 insulating film 522a Conductive film 522b Conductive film 540 Aperture 542a aperture 542b aperture 542c aperture 550 transistors 560 Connection 570 Connection 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A semiconductor device including a transistor, a pixel electrode electrically connected to a source or a drain of the transistor, a first wiring, a second wiring, and a third wiring, a first conductive layer, a second conductive layer, a first insulating layer, an oxide semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a second insulating layer, a sixth conductive layer, and a seventh conductive layer; the first conductive layer functions as a gate electrode of the transistor, the second conductive layer has a function as the first wiring, the first insulating layer has a region disposed above the first conductive layer and a region disposed above the second conductive layer, and functions as a gate insulating layer of the transistor; the oxide semiconductor layer has a region disposed above the first insulating layer and functions as a channel formation region of the transistor; the third conductive layer has a region disposed above the oxide semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor; the fourth conductive layer has a region disposed above the oxide semiconductor layer and functions as the other of the source electrode and the drain electrode of the transistor; the fifth conductive layer has a region disposed above the first insulating layer and functions as the second wiring; the second insulating layer has a region disposed above the third conductive layer, a region disposed above the fourth conductive layer, and a region disposed above the fifth conductive layer; the sixth conductive layer has a region disposed above the second insulating layer, is connected to the fourth conductive layer through a first opening provided in the second insulating layer, and functions as the pixel electrode; the seventh conductive layer has a region disposed above the second insulating layer, is connected to the second conductive layer at a second opening provided in the second insulating layer and a third opening provided in the first insulating layer and overlapping with the second opening, and is connected to the fifth conductive layer at a fourth opening provided in the second insulating layer, and has a function as the third wiring; In a plan view, an end portion of the fifth conductive layer has a first region and a second region, the first region overlaps with the seventh conductive layer in a plan view; the second region does not overlap the seventh conductive layer in a plan view; In a plan view, the first region is disposed around the fourth opening, A semiconductor device, wherein the distance between the upper end and the lower end of the fifth conductive layer in the first region is longer than the distance between the upper end and the lower end of the fifth conductive layer in the second region, longer than the distance between the upper end and the lower end of the third conductive layer, and longer than the distance between the upper end and the lower end of the fourth conductive layer.

2. In claim 1, the sixth conductive layer and the seventh conductive layer include a light-transmitting conductive material.

Images