Audio processing device, audio output system, audio processing method, and audio processing program

Abstract

To provide an audio processing device, audio output system, audio processing method, and audio processing program that enable improved reproducibility of audio data even when using a PWM port with insufficient resolution relative to the bit depth of the audio data.SOLUTION: The audio processing device outputs two PWM signals on the basis of audio data via a first port and a second port that output PWM signals corresponding to input data. The audio processing device obtains expanded data by dividing a value obtained by multiplying the audio data of a predetermined bit depth by the number of clocks within the PWM period of the first and second ports by 2 raised to the predetermined bit depth. The audio processing device then outputs the integer part of the expanded data to the first port and outputs the amplified fractional part of the expanded data to the second port.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an audio processing device, an audio output system, an audio processing method, and an audio processing program that generate a PWM (Pulse Width Modulation) signal based on audio data. [Background technology]

[0002] Conventionally, there has been known an audio output system that amplifies a PWM signal based on audio data and outputs the amplified signal from a speaker (see, for example, Patent Document 1). The audio output system described in Patent Document 1 is configured such that a microcomputer converts audio data into a PWM signal, and a drive circuit controls the driving of the speaker based on the PWM signal output from the microcomputer. Such audio output systems are also installed in home appliances, etc., and are configured such that audio data is converted into a PWM signal by one PWM port (PWM output device), and audio based on the PWM signal is reproduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-171462 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the conventional method of setting and outputting audio data to one PWM port per PWM cycle, the resolution of the PWM port determines the quality of audio reproduction. In other words, if a microcontroller or other device has a PWM port with a resolution lower than the number of bits of audio data, conversion errors will occur during conversion to PWM signals, degrading audio quality. For example, to reproduce 16-bit audio data, a PWM port with a 10-bit resolution is insufficient, and a PWM port with a higher resolution is required.

[0005] The present invention has been made to solve the above-mentioned problems, and aims to provide an audio processing device, an audio output system, an audio processing method, and an audio processing program that enable improved reproducibility of audio data even when using a PWM port whose resolution is insufficient for the number of bits of the audio data. [Means for solving the problem]

[0006] An audio processing device according to one embodiment of the present invention is an audio processing device that outputs a PWM signal based on audio data via a first port and a second port that output a PWM signal according to input data, and has an arithmetic processing unit that obtains extended data by multiplying audio data with a predetermined number of bits by the number of clocks in the PWM period of the first port and the second port and dividing the result by 2 to the power of the number of bits, outputs the integer portion of the extended data to the first port, and amplifies the decimal portion of the extended data and outputs it to the second port.

[0007] An audio output system according to one embodiment of the present invention includes the above-described audio processing device, a synthesis processor that synthesizes a PWM signal output from the first port with a PWM signal that is an attenuated output from the second port, and a speaker unit that amplifies the PWM signal synthesized by the synthesis processor and outputs audio.

[0008] An audio processing method according to one embodiment of the present invention is an audio processing method in which one or more processors output a PWM signal based on audio data via a first port and a second port that output a PWM signal according to input data, and the method obtains extended data by multiplying audio data C of a predetermined number of bits by the number of clocks in the PWM period of the first port and the second port and dividing the result by 2 to the power of the number of bits, and outputs the integer portion of the extended data to the first port, while amplifying the decimal portion of the extended data and outputting it to the second port.

[0009] An audio processing program according to one embodiment of the present invention causes a computer that outputs a PWM signal based on audio data to a first port and a second port that output a PWM signal according to input data to function as an extension processing means that obtains extended data by multiplying audio data with a predetermined number of bits by the number of clocks in the PWM period of the first port and the second port and dividing the result by 2 to the power of the number of bits, and an extraction processing means that outputs the integer portion of the extended data to the first port and amplifies the decimal portion of the extended data and outputs it to the second port. [Effects of the Invention]

[0010] The present invention outputs audio data and the integer portion of extended data based on the number of clocks in a PWM cycle to a first port, and amplifies and outputs the fractional portion of the extended data to a second port. Then, by combining the PWM signal output from the first port with the attenuated PWM signal output from the second port, the integer and fractional portions of the extended data can be reflected in the combined PWM signal. Therefore, audio quality can be improved even if the first and second ports do not have a resolution corresponding to the number of bits of the audio data. In other words, even if a PWM port with insufficient resolution for the number of bits of the audio data is used, the reproducibility of the audio data can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a configuration diagram illustrating an example of an audio output system according to an embodiment of the present invention. [Figure 2] 2 is an explanatory diagram showing an example of the functional configuration of a processing unit in FIG. 1 and an example of the configuration of related devices. FIG. [Figure 3] 2 is an explanatory diagram illustrating the reproducibility of audio data by the audio output system of FIG. 1. FIG. [Figure 4] 2 is a table showing an example of a simulation result in the audio output system of FIG. 1. [Figure 5] 10 is a table showing another example of the simulation results in the audio output system of FIG. [Figure 6]6 is a graph showing time variations in the output value of the sound source data, the PWM output of the first port, and the synthesized output by the synthesis processor in FIG. 5. [Figure 7] 6 is a graph showing the change over time of a conversion value related to the first port and a conversion value related to a combined output of a combining processor, with the audio data in FIG. 5 used as a reference. [Figure 8] 1 is a flowchart illustrating an example of the flow of operations of an audio output method including an audio processing method according to the present embodiment. [Figure 9] FIG. 1 is an explanatory diagram schematically illustrating the reproducibility of audio data by a conventional audio output system having only one PWM port. DETAILED DESCRIPTION OF THE INVENTION

[0012] Embodiment 1 to 9, configuration examples and operation examples of a voice processing device 10 and a voice output system 100 according to an embodiment of the present invention will be described. In each figure, some reference numerals are omitted as appropriate to avoid complication.

[0013] 1, the audio output system 100 includes an audio processing device 10, a storage device 20, a synthesis processor 40, and a speaker unit 80. The audio output system 100 is configured such that the audio processing device 10 drives a speaker 70 via the synthesis processor 40 and an amplifier 60, and reproduces audio from the speaker 70.

[0014] 1 shows an example in which audio data C is stored in the storage device 20. The audio data C is composed of, for example, PCM data obtained by converting an analog audio signal using PCM (Pulse Code Modulation). The audio data C is data with a predetermined number of bits (hereinafter also referred to as "predetermined number of bits"). The storage device 20 is composed of RAM (Random Access Memory), ROM (Read Only Memory), flash memory, eMMC (embedded Multi Media Card), SSD (Solid State Drive), HDD (Hard Disk Drive), or the like.

[0015] The audio processing device 10 outputs a PWM signal based on audio data C via a first port (first output device) 13a and a second port (second output device) 13b. The audio processing device 10 illustrated in Fig. 1 includes a storage unit 11, an arithmetic processing unit 12, the first port 13a, and the second port 13b.

[0016] The storage unit 11 stores various information, including the operation programs of the arithmetic processing unit 12, such as the audio processing program 11p. The storage unit 11 includes RAM, ROM, flash memory, eMMC, or SSD. The first port 13a and the second port 13b generate and output PWM signals according to input data. More specifically, the first port 13a and the second port 13b output pulse signals with duty cycles based on data set in an internal counter for each PWM period. The first port 13a may be a PWM port having a resolution according to the integer part of the extended data, and the second port 13b may be a PWM port having a resolution according to the decimal part of the extended data. In this embodiment, the first port 13a and the second port 13b are PWM ports with the same resolution.

[0017] The arithmetic processing unit 12 obtains extended data by multiplying the audio data C of a predetermined number of bits by the number of periodic clocks and dividing the result by 2 raised to the power of the predetermined number of bits. The arithmetic processing unit 12 outputs the integer part of the extended data to the first port 13a and amplifies the decimal part of the extended data and outputs it to the second port 13b. The number of periodic clocks refers to the number of clocks within a PWM period (the number of clocks per PWM period), and the PWM period here refers to the PWM period of the first port 13a and the second port 13b (see FIG. 3). The number of clocks refers to the number of times the internal circuit of the audio processing device 10 (e.g., a microcomputer) is synchronized within a unit time using a clock. In other words, the number of periodic clocks refers to the number of clocks the audio processing device 10 (e.g., a microcomputer) ticks within a PWM period.

[0018] The arithmetic processing unit 12 obtains extended data for each PWM period, extracts its integer portion and outputs it to the first port 13a, and amplifies its decimal portion and outputs it to the second port 13b. The arithmetic processing unit 12 is configured with one or more processors. That is, the arithmetic processing unit 12 can be configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an MPU (Micro-Processing Unit), or the like. The audio processing device 10 in this embodiment is configured with a so-called microcomputer.

[0019] The synthesis processor 40 synthesizes the PWM signal output from the first port 13a and the PWM signal obtained by attenuating the output from the second port 13b, and outputs the synthesized signal. The speaker unit 80 amplifies the PWM signal synthesized by the synthesis processor 40 and outputs audio. More specifically, the speaker unit 80 includes an amplifier 60 and a speaker 70, and reproduces audio from the speaker 70 using the PWM signal amplified by the amplifier 60. The speaker 70 is controlled by two PWM signals output from the audio processing device 10 and outputs audio. The speaker 70 is configured using a piezoelectric speaker, a dynamic speaker, or the like. Note that a piezoelectric speaker includes a piezo element (piezoelectric element) that deforms when a voltage is applied to it, and outputs audio using air vibrations caused by the deformation of the piezo element.

[0020] 1 is an assumed periphery of an electronic board. In other words, the audio processing device 10, storage device 20, synthesis processor 40, and amplifier 60 may be mounted on the same board. However, this is not limited to such an assumption. For example, the speaker 70 may be mounted on the same board as the above components, or only the audio processing device 10, storage device 20, and synthesis processor 40 may be mounted on the same board. When a speaker unit 80 in which the amplifier 60 and speaker 70 are integrated is used, the speaker unit 80 may be located inside or outside the board.

[0021] Next, referring to FIG. 2, an example of the functional configuration of the arithmetic processing unit 12 and an example of the configuration of the combining processor 40 will be described. The combining processor 40 illustrated in FIG. 2 has a first conductor W1 connected to the first port 13a and a second conductor W2 connected to the second port 13b. The combining processor 40 has a first resistor R1 provided in the first conductor W1 and a second resistor R2 and a third resistor R3 provided in the second conductor W2. The end of the second conductor W2 opposite the second port 13b is grounded (connected to GND). In the second conductor W2, a third conductor W3 is connected between the second resistor R2 on the second port 13b side and the third resistor R3 on the GND side. The third conductor W3 is connected to the end of the first conductor W1 opposite the first port 13a, and a fourth conductor W4 connected to the amplifier 60 extends from this connection point. The connection point between the first conductor portion W1, the third conductor portion W3, and the fourth conductor portion W4 functions as a mixer.

[0022] The combining processor 40 has a function of attenuating the PWM signal output from the second port 13b, and the attenuation rate is determined by the resistance values ​​of the first resistor R1 and the second resistor R2. Hereinafter, the attenuation rate of the PWM signal from the second port 13b will also be referred to as the "attenuation rate by the combining processor 40." In the configuration of FIG. 2, the attenuation rate by the combining processor 40 is R1 / R2 (more specifically, "(R1 / R3) / (R2 / R3)"). That is, in the combining processor 40, the second resistor R2 has a larger resistance value than the first resistor R1.

[0023] The calculation processing unit 12 has an extension processing means 12a and an extraction processing means 12b. The extension processing means 12a obtains extension data by dividing the value obtained by multiplying audio data C of a predetermined number of bits by the number of periodic clocks by 2 to the power of the predetermined number of bits. That is, the extension data can be obtained by multiplying the audio data C by the value obtained by dividing the number of periodic clocks by 2 to the power of the predetermined number of bits, as shown in the following equation (1). The calculation of dividing by 2 to the power of the predetermined number of bits is synonymous with the process of shifting the decimal point of the value obtained by multiplying audio data C by the number of periodic clocks to the left by a predetermined number of bits.

[0024]

number

[0025] The extraction processing means 12b outputs the integer portion of the extended data to the first port 13a and amplifies the decimal portion of the extended data and outputs it to the second port 13b. The amplification factor (second port pre-amplification factor) used by the extraction processing means 12b to amplify the decimal portion is the reciprocal of the attenuation factor of the combining processor 40. That is, in the configuration of FIG. 2, the second port pre-amplification factor is R2 / R1 (R2>R1). The second port pre-amplification factor is set to be equal to or less than the number of periodic clocks. It is recommended that the second port pre-amplification factor be set to the maximum value within the range that does not exceed the number of periodic clocks. In the configuration of FIG. 2, the second port pre-amplification factor depends on the combination of the first resistor R1 and the second resistor R2.

[0026] The arithmetic processing unit 12 can be configured by a calculation device such as a CPU, GPU, or MPU, and software (including an audio processing program 11p) that cooperates with the calculation device to realize the various functions described above or below. The audio processing program 11p causes a computer that outputs PWM signals based on audio data C to the first port 13a and the second port 13b to function as the extension processing means 12a and the extraction processing means 12b. The storage unit 11 corresponds to a computer-readable recording medium on which the audio processing program 11p is recorded. However, some of the various functions in the arithmetic processing unit 12 may be realized by hardware.

[0027] Here, an overview of the effects obtained by the audio processing device 10 and the audio output system 100 will be described with reference to Fig. 3 and Fig. 9. Fig. 3 is an explanatory diagram that schematically shows the reproducibility of audio data by the audio output system 100. Fig. 9 is an explanatory diagram that schematically shows the reproducibility of audio data by a conventional audio output system that has only one PWM port. Figs. 3 and 9 illustrate waveforms that show the voltage values ​​of the audio data and bar graphs that show the voltage values ​​according to the ON pulse width of the PWM signal.

[0028] If audio data is converted directly into pulses using one PWM port, a large conversion error E occurs with the audio data shown by the solid line, as shown in Figure 9. In contrast, in the case of audio output system 100, a PWM signal corresponding to the decimal part of the extended data is added to a PWM signal corresponding to the integer part of the extended data, so the conversion error is suppressed, as shown in gray in Figure 3. Note that Figures 3 and 9 simply show an example where the number of periodic clocks is 8.

[0029] Next, an example of actual simulation results will be described with reference to Table 1 and Figure 4. The timer clock frequency, PWM frequency, number of periodic clocks, and second port pre-amplification factor of the audio processing device 10 were set as shown in Table 1 below. Audio data C was assumed to be 16-bit PCM data. The PWM frequency is a positive integer multiple of the sampling frequency. In Figure 4, each value has been rounded appropriately.

[0030] [Table 1]

[0031] The first column of the table in Figure 4 shows the audio data for each PWM cycle, and the values ​​in parentheses (normalized values) are the original data normalized to a value between 0 and 1. The audio data for each PWM cycle is multiplied by "1000", which is the number of clock cycles, and then multiplied by "2 to the power of a specified number of bits". 16 " Dividing by " gives us the extended data, which contains the integer part (integer part) and the fractional part (fractional part).

[0032] The first port 13a is set to a value of the integer part, which determines the duty ratio (set value / number of cycle clocks) of the PWM signal output from the first port 13a. On the other hand, the second port 13b is set to a value obtained by multiplying the decimal part by an amplification factor of "800," which determines the duty ratio (set value / number of cycle clocks) of the PWM signal output from the second port 13b.

[0033] The synthesis processor 40 applies attenuation processing to the PWM signal output from the second port 13b at an attenuation rate of 1 / 800, and then synthesizes the attenuated PWM signal with the PWM signal output from the first port 13a (see "Synthesized Output" in Figure 4). As can be seen from Figure 4, there is a relative magnitude error between the normalized value of the audio data and the output value of the PWM signal from the first port 13a. In contrast, the synthesized output by the synthesis processor 40 includes the decimal portion of the extended data, so the error between the normalized value of the audio data is extremely small.

[0034] The converted values ​​shown in the table of Fig. 4 are indexes calculated from the following formula (2) to more clearly show the error reduction achieved by the audio output system 100. The converted value has the characteristic that the smaller the deviation between the audio data and the output value, the smaller the difference between the converted value and -16.0 (the closer it is to -16.0). The difference between the converted value related to the first port 13a and the converted value related to the combined output also indicates that the accuracy of the PWM signal finally output by the audio output system 100 is good.

[0035]

number

[0036] Next, in order to make it clear at a glance that the audio output system 100 improves the reproducibility of audio data, the settings were changed as shown in Table 2, and a simulation similar to that described above was performed. The results are shown in Figures 5 to 7. The table in Figure 5 has the same structure as the table in Figure 4, so duplicated explanations will be omitted or simplified.

[0037] [Table 2]

[0038] The audio data for each PWM cycle is multiplied by the number of cycle clocks, "62", and the result is multiplied by 2 to the power of the specified number of bits, "2 16", extended data including an integer part (integer part) and a decimal part (fractional part) is obtained. The value of the integer part is set in the first port 13a, and this determines the duty ratio (set value / number of periodic clocks) of the PWM signal output from the first port 13a. Meanwhile, the value obtained by multiplying the decimal part by the amplification factor "62" is set in the second port 13b, and this determines the duty ratio (set value / number of periodic clocks) of the PWM signal output from the second port 13b.

[0039] The synthesis processor 40 performs attenuation processing with an attenuation rate of 1 / 62 on the PWM signal output from the second port 13b, and synthesizes the attenuated PWM signal with the PWM signal output from the first port 13a (see "Synthesized Output" in Figure 5). As can be seen from Figure 5, there is a relative magnitude error between the normalized value of the audio data and the output value of the PWM signal from the first port 13a. In contrast, the synthesized output by the synthesis processor 40 includes the decimal part of the extended data, so the error between the normalized value of the audio data is extremely small.

[0040] FIG. 6 is a graph showing the time changes of the output value of the sound source data (corresponding to (a) in FIG. 5), the PWM output of the first port 13a (corresponding to (b) in FIG. 5), and the composite output (corresponding to (c) in FIG. 5). In FIG. 6, there is a large discrepancy between the PWM output of the first port 13a and the output value of the sound source data, but the composite output and the output value of the sound source data are almost the same. FIG. 7 is a graph showing the time changes of the converted value related to the first port 13a (corresponding to (A) in FIG. 5) and the converted value related to the composite output (corresponding to (B) in FIG. 5), with the sound data (−16.0) as the reference. It can be seen from FIG. 7 that the difference between the converted value related to the first port 13a and −16.0 is narrowed in the converted value related to the composite output. In other words, by using the sound processing device 10 and the sound output system 100, the reproducibility of sound data can be improved, and sound quality can be improved.

[0041] Next, an audio processing method and an audio output method according to this embodiment will be described with reference to the flowchart of Fig. 8. It is assumed that the storage unit 11 of the audio processing device 10 stores information on the number of bits of audio data and the number of periodic clocks as appropriate.

[0042] [Sound Processing Device] The arithmetic processing unit 12 obtains extended data for each PWM cycle based on the audio data C and the number of periodic clocks. That is, as shown in equation (1), the arithmetic processing unit 12 obtains extended data for each PWM cycle by multiplying the audio data C by a value obtained by dividing the number of periodic clocks by the power of 2 to the predetermined number of bits (step S101). Next, the arithmetic processing unit 12 outputs the integer part of the extended data to the first port 13a (step S102). Furthermore, the arithmetic processing unit 12 amplifies the decimal part of the extended data and outputs it to the second port 13b (step S103). The arithmetic processing unit 12 repeatedly executes the series of processes from steps S101 to S103 for each PWM cycle.

[0043] [Two PWM ports] The first port 13a generates and outputs a PWM signal based on the integer part of the extended data (step S104), and the second port 13b generates and outputs a PWM signal based on the decimal part of the amplified extended data (step S105).

[0044] [Synthesis Processor] The synthesis processor 40 attenuates the PWM signal output from the second port 13b (step S106), synthesizes the attenuated PWM signal with the PWM signal output from the first port 13a, and outputs the synthesized signal (step S107).

[0045] [Speaker unit] The speaker unit 80 amplifies the PWM signal synthesized by the synthesis processor 40 using the amplifier 60 (step S108), and outputs sound based on the amplified PWM signal from the speaker 70 (step S109).

[0046] The above operations have been described in the order of the step numbers in Figure 8, but the order of processing is not limited to this. For example, the processing of step S102 and the processing of step S103 may be performed in parallel, or their order may be reversed. Note that the order of steps S104 and S105 is for convenience's sake. Furthermore, the processing of step S106 and the processing of step S107 are performed almost simultaneously.

[0047] As described above, the audio processing device 10 of this embodiment is configured to output the integer portion of the extended data based on the audio data C and the number of periodic clocks to the first port 13a, and to amplify and output the decimal portion of the extended data to the second port 13b. Therefore, by combining the PWM signal output from the first port 13a with the attenuated PWM signal output from the second port 13b, the integer and decimal portions of the extended data can be reflected in the combined PWM signal. Therefore, audio quality can be improved even if the first port 13a and the second port 13b do not have resolution corresponding to the number of bits of the audio data. Therefore, even if a PWM port with insufficient resolution for the number of bits of the audio data C is used, the reproducibility of the audio data C can be improved, and audio quality can be improved.

[0048] The above-described embodiments are merely examples of the audio processing device, audio output system, audio processing method, and audio processing program, and the technical scope of the present invention is not limited to these embodiments. For example, audio data may be stored in the storage unit 11. In this case, the audio output system 100 does not need to include the storage device 20. While FIGS. 4 and 5 illustrate 16-bit audio data, the audio data to be processed may be data with a bit count greater than 16 bits, such as 24-bit data, or data with a bit count less than 16 bits. While FIG. 2 illustrates an example in which the attenuation process by the synthesis processor 40 is implemented using three resistors, this is not limiting. The synthesis processor 40 may be configured to include three capacitors, and the attenuation process may be implemented by the capacitance difference between the three capacitors. The audio output system 100 may include a low-pass filter before or after the synthesis processor 40. [Explanation of symbols]

[0049] 10 Audio processing device, 11 Memory unit, 11p Audio processing program, 12 Arithmetic processing unit, 12a Expansion processing means, 12b Extraction processing means, 13a First port, 13b Second port, 20 Storage device, 40 Synthesis processor, 60 Amplifier, 70 Speaker, 80 Speaker unit, 100 Audio output system, R1 First resistor, R2 Second resistor, R3 Third resistor.

Claims

1. 1. An audio processing device that outputs a PWM signal based on audio data via a first port and a second port that output a PWM signal according to input data, An audio processing device having an arithmetic processing unit that obtains extended data by multiplying the audio data of a predetermined number of bits by the number of clocks in a PWM period of the first port and the second port and dividing the result by 2 to the power of the number of bits, and outputs the integer portion of the extended data to the first port and amplifies the decimal portion of the extended data and outputs it to the second port.

2. The audio processing device according to claim 1; a synthesis processor that synthesizes a PWM signal output from the first port and a PWM signal obtained by attenuating the output from the second port; a speaker unit that amplifies the PWM signal synthesized by the synthesis processor and outputs sound.

3. An audio processing method for outputting a PWM signal based on audio data via a first port and a second port that output a PWM signal according to input data by one or more processors, comprising: obtaining extension data by multiplying the audio data of a predetermined number of bits by the number of clocks in a PWM period of the first port and the second port and dividing the result by 2 raised to the power of the number of bits; An audio processing method comprising: outputting an integer portion of the extended data to the first port; and amplifying and outputting a fractional portion of the extended data to the second port.

4. a computer that outputs a PWM signal based on audio data to a first port and a second port that output PWM signals according to input data; an extension processing means for obtaining extension data by multiplying the audio data of a predetermined number of bits by the number of clocks in a PWM period of the first port and the second port and dividing the result by 2 raised to the power of the number of bits; and an audio processing program for causing the program to function as an extraction processing means that outputs the integer portion of the extended data to the first port and amplifies the decimal portion of the extended data and outputs it to the second port.

Images