Semiconductor device

Abstract

To provide a semiconductor device that suppresses a decrease in EM resistance while suppressing the increase in implementation area.SOLUTION: In a semiconductor device, a first wiring group extends in a first particular direction from an element region to a circuit region, adjacent to the element region, where a circuit used to generate a second power source is disposed, so as to be connected to an element included in the circuit and a third wiring group includes an internal power source supply branch line that electrically connects the first wring group provided in the circuit region and an internal power source supply main line by extending from the circuit region to the internal power source supply main line in a second particular direction that is different from the first particular direction. At least a part of the internal power source supply branch line overlaps with a part of the first wiring group and the element when the internal power source supply branch line is viewed from a first metal layer to a second metal layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device including a power supply circuit. [Background technology]

[0002] As the speed of DRAM (Dynamic Random Access Memory) used in semiconductor devices increases, current consumption has increased. Therefore, attempts have been made to reduce current consumption by using internal voltage step-down circuits, while attempts have also been made to reduce parasitic capacitance by thinning the AL (Aluminum) wiring layer in response to process speed increases. However, both of these methods exponentially degrade the EM (Electro Magnetic) resistance of the AL wiring layer.

[0003] As a result of the increase in the current supply of the internal step-down circuit, coupled with the decline in the EM reliability of the wiring layer and the need for high-temperature operation, the line width of the power supply branch lines connecting to the internal step-down circuit, which previously was limited to the width of the transistors constituting the driver, must now be exponentially increased, which can increase the mounting area of ​​the semiconductor device.

[0004] Patent Document 1 proposes a method of achieving both EM resistance, high speed, and high integration by using a material with high EM resistance for the power supply branch lines of logic gates. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 3-16135 Summary of the Invention [Problem to be solved by the invention]

[0006] However, if wiring with high EM resistance is used for the wiring of the transistors that make up the driver of a step-down power supply circuit, the electrical resistance will be about 500 times that of AL wiring, resulting in a large voltage drop in the step-down voltage - for example, a supply of 50 mA will result in a drop of 25 V, making it impractical.As such, conventional technology leaves room for improvement in terms of suppressing the decrease in EM resistance while suppressing an increase in the mounting area of ​​a semiconductor device.

[0007] In view of the above circumstances, the present disclosure has an object to provide a semiconductor device that suppresses a decrease in EM resistance while suppressing an increase in mounting area. [Means for solving the problem]

[0008] In order to solve the above problems, a semiconductor device according to the present disclosure is a semiconductor device including a power supply circuit that converts a voltage of a first power supply supplied from an external source into a voltage of a second power supply that is lower than the voltage of the first power supply and drives an internal circuit, using a plurality of transistors, and includes: a first metal layer provided above an element region including a plurality of the transistors; first contacts that connect the first metal layer to the plurality of transistors; a second metal layer provided above the first metal layer; second contacts that connect the second metal layer to the first metal layer; a first wiring group included in the first metal layer that commonly connects first terminals included in the plurality of transistors via the first contacts; a second wiring group included in the first metal layer that commonly connects second terminals different from the first terminals included in the plurality of transistors via the first contacts; the first wiring group extends in a first specific direction from the element region to a circuit region in which a circuit used to generate the second power supply is disposed adjacent to the element region, thereby being connected to elements included in the circuit; the third wiring group includes internal power supply branch lines that extend from the circuit region to the internal power supply trunk in a second specific direction different from the first specific direction, thereby electrically connecting the first wiring group provided in the circuit region to the internal power supply trunk; and at least a portion of the internal power supply branch line overlaps with the first wiring group and a portion of the element when the internal power supply branch line is viewed from the first metal layer toward the second metal layer. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic configuration diagram of a semiconductor device 100 including a power supply circuit 200 according to an embodiment of the present disclosure. [Figure 2]FIG. 2 is a schematic diagram of a power supply circuit 200. [Figure 3] FIG. 3 is a diagram showing the configuration of the semiconductor device 100. [Figure 4] FIG. 4 is a diagram showing the configuration of the semiconductor device 100. [Figure 5] FIG. 5 is a configuration diagram of a semiconductor device 100A according to a modified example. [Figure 6] FIG. 6 is a configuration diagram of a semiconductor device 100A according to a modified example. [Figure 7] FIG. 7 is a configuration diagram of a semiconductor device 100B according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0011] (Embodiment) FIG. 1 is a schematic diagram of a semiconductor device 100 including a power supply circuit 200 according to an embodiment of the present disclosure. The semiconductor device 100 may be considered a high-speed DRAM. In the high-speed DRAM, the power supply circuit 200 may step down the voltage of an external power supply, for example, from 1.5 V to 1.2 V, in order to reduce current consumption. The power supply circuit 200 may be considered a circuit that converts a first power supply voltage supplied from outside the semiconductor device 100 or from outside the power supply circuit 200 into a second power supply voltage that is lower than the first power supply voltage and drives an internal circuit 300. The internal circuit 300 may include a semiconductor memory circuit.

[0012] The voltage of the first power supply may be interpreted as the voltage of the external power supply (VDD), and the voltage of the second power supply may be interpreted as the voltage of the internal power supply (VPERI). The external power supply (VDD) may be supplied to the power supply circuit 200 via a VDD trunk line, and the power supply circuit 200 that supplies the internal power supply (VPERI) may be connected to a VPERI trunk line that is provided in a ring shape.

[0013] 2 is a schematic diagram of a power supply circuit 200. The power supply circuit 200 may include a plurality of transistors TR that constitute drivers. The power supply circuit 200 may be connected to an external power supply (VDD) via a VDD branch line and a VDD main line. The power supply circuit 200 may be connected to a VPERI branch line and a VPERI main line that supply an internal power supply (VPERI) to the internal circuit 300.

[0014] 3 and 4 are configuration diagrams of the semiconductor device 100. Fig. 3 shows the semiconductor device 100 in plan view, and Fig. 4 shows the structure of each layer included in the semiconductor device 100.

[0015] The semiconductor device 100 may include a first metal layer M1, a first contact C1, a second metal layer M2, a second contact C2, a first wiring group, a second wiring group, a third metal layer M3, and a third wiring group W3.

[0016] (First metal layer M1) The first metal layer M1 may be interpreted as a layer provided above the element region EA including the plurality of transistors TR, and as a layer provided below the second metal layer M2.

[0017] (Second metal layer M2) The second metal layer M2 may be interpreted as a layer provided on top of the first metal layer M1, or as a layer provided below the third metal layer M3, i.e., the second metal layer M2 may be interpreted as a layer provided between the first metal layer M1 and the third metal layer M3.

[0018] (Third metal layer M3) The third metal layer M3 may be interpreted as a layer provided on top of the second metal layer M2.

[0019] (First contact C1) The first contacts C1 may be interpreted as conductive contacts that connect the first metal layer M1 to the plurality of transistors TR, and more specifically, as contact contacts.

[0020] (Second contact C2) The second contact C2 may be interpreted as a conductive contact that connects the second metal layer M2 to the first metal layer M1, and more specifically, as a via.

[0021] (1st wiring group W1) The first wiring group W1 may be interpreted as a wiring group included in the first metal layer M1 that commonly connects the first terminals of the multiple transistors TR via the first contacts C1. Specifically, the first wiring group W1 may be interpreted as multiple VPERI branch lines included in the first metal layer M1. The VPERI branch line may be interpreted as a branch line for supplying the internal power supply voltage generated by the driver to the internal circuit. The first terminal may be interpreted as the source terminal or drain terminal of the transistor TR. Note that, typically, the side of the diffusion layer of a driver transistor that is connected to the VPERI branch line is called the drain terminal, and the side that is connected to the external power supply VDD is called the source terminal. Therefore, the first terminal may be interpreted as the drain terminal of the transistor TR.

[0022] The first wiring group W1 may extend in a first specific direction D1 from the element region EA to a circuit region CA where a circuit used to generate a second power supply is disposed adjacent to the element region EA, and may be connected to the elements included in the circuit. The first specific direction D1 may be interpreted as the gate length direction of the transistor TR. Specifically, the first specific direction D1 is the gate length direction of the gate electrode of the transistor TR.

[0023] (Second wiring group W2) The second wiring group W2 may be interpreted as a wiring group included in the first metal layer M1 that commonly connects second terminals, which are different from the first terminals of the multiple transistors TR, via the first contacts C1. Specifically, the second wiring group W2 may be interpreted as multiple VDD branch lines included in the first metal layer M1. The VDD branch lines may be interpreted as branch lines for supplying the voltage of an external power supply to each transistor TR in the driver. The second terminals may be interpreted as source terminals of the transistors TR.

[0024] (3rd wiring group W3) The third wiring group W3 may be interpreted as a wiring group included in the second metal layer M2 that commonly connects the first wiring group W1 via the second contacts C2. The third wiring group W3 may include an internal power supply branch line IW and an external power supply branch line OW.

[0025] (Internal power supply branch line IW) The internal power supply branch line IW may be interpreted as a branch line that electrically connects the first wiring group W1 provided in the circuit area CA to the internal power supply trunk line IWM by extending in a second specific direction D2 different from the first specific direction D1 from the circuit area CA to the internal power supply trunk line IWM.

[0026] The second specific direction D2 may be interpreted as a direction orthogonal to the first specific direction D1. Specifically, the second specific direction D2 may be interpreted as a direction orthogonal to the first specific direction D1 in a plane in which the semiconductor device 100 is viewed in plan. The orthogonal direction may include a direction perpendicular to the first specific direction D1. The second specific direction D2 may be interpreted as a gate width direction or a width direction of a diffusion layer of the transistor TR. Specifically, the second specific direction D2 may be interpreted as a direction orthogonal to an imaginary line passing through the source and drain of the transistor TR.

[0027] At least a portion of the internal power supply branch line IW may cover the first wiring group W1 and a portion of the elements when the internal power supply branch line IW is viewed from the first metal layer M1 toward the second metal layer M2. At least a portion of the internal power supply branch line IW may overlap the first wiring group W1 and a portion of the elements within the circuit area CA.

[0028] (External power supply branch line OW) The external power supply branch line OW may be interpreted as a branch line that extends from the element area EA to the external power supply main line OWM in the second specific direction D2, thereby electrically connecting the second wiring group W2 provided in the element area EA to the external power supply main line OWM.

[0029] When the internal power supply branch line IW is viewed from the first metal layer M1 toward the second metal layer M2, at least a portion of the external power supply branch line OW may cover a portion of the first wiring group W1 and the second wiring group W2. In other words, at least a portion of the external power supply branch line OW may overlap a portion of the first wiring group W1 and the second wiring group W2 in the element area EA.

[0030] The elements in the circuit area CA may be interpreted as phase compensation capacitances that utilize capacitances included in the semiconductor memory circuit.

[0031] The semiconductor device 100 includes a capacitive element having a MIM (Metal-Insulator-Metal) structure, and the capacitive element may be provided on top of the second metal layer M2.

[0032] In this manner, in the semiconductor device 100, a VPERI branch line (M2) extending perpendicularly to the VPERI branch line (M1) drawn out of the driver is connected. A phase compensation capacitor using a DRAM capacitance element (layer below M1) may be arranged below the portion where the VPERI branch line (M2) overlaps with the wiring length of the drawn-out VPERI branch line (M1). Alternatively, if the internally generated voltage trunk line of the third metal layer M3 is not routed in the gate length direction of the driver, a phase compensation element using an MIM element (layer above M2) may be arranged. A logic circuit (layer below M1) that does not require high speed, a phase compensation capacitor using a DRAM capacitance element (layer below M1), or the like may be arranged below the VPERI branch line (M2) between the VPERI branch line (M1) and the VPERI trunk line (M3). This improves EM resistance without increasing the mounting area of ​​the semiconductor device 100.

[0033] 5 and 6 are configuration diagrams of a semiconductor device 100A according to a modification. The semiconductor device 100A may include a third metal layer internal power supply branch line IW3 provided in the third metal layer M3.

[0034] The internal power supply branch lines IW included in the third wiring group W3 may include a first branch line IW1 and a second branch line IW2.

[0035] The first branch line IW1 may be interpreted as a branch line included in the second metal layer M2 that extends from the third metal layer internal power supply branch line IW3 to the circuit area CA in the second specific direction D2.

[0036] The second branch line IW2 may be interpreted as a branch line included in the second metal layer M2, which extends in the second specific direction D2 from the third metal layer internal power supply branch line IW3 to the internal power supply main line IWM.

[0037] Elements may be provided on a layer above or below the first branch line IW1 and the second branch line IW2.

[0038] In this way, in semiconductor device 100A, the VPERI branch line (M2) extending in a direction perpendicular to the VPERI branch line (M1) drawn out to the outside of the driver is connected. The VPERI branch line (M2) is then connected while bypassing the logic circuit used up to the second metal layer M2. In other words, the VPERI branch line (M2) is placed on the VPERI branch line of the third metal layer M3 and then connected to the VPERI trunk line.

[0039] A phase compensation capacitance using a DRAM capacitance element (layer below M1) may be placed between the VPERI branch line (M1) and the VPERI branch line (M3). Alternatively, a logic circuit (layer below M1) that does not require high speed, a phase compensation capacitance using a DRAM capacitance element (layer below M1), or the like may be placed below the VPERI branch line (M2) between the VPERI branch line and the trunk line in the third metal layer M3. A phase compensation capacitance using a DRAM capacitance element (layer below M1) may also be placed below the VPERI branch line (M3). This allows for a high-speed logic circuit that uses up to M2 near the step-down circuit, while improving EM resistance while suppressing an increase in the wiring area of ​​the second metal layer M2.

[0040] Figure 7 is a schematic diagram of a semiconductor device 100B according to a comparative example. In internal step-down circuits, the area of ​​greatest concern for EM resistance is the power supply wiring connected to the driver transistor TR. VPERI, used by each internal step-down circuit within the chip, is routed as a ring-shaped trunk line within the chip, and the internal step-down circuits outputting VPERI are distributed. External power supplies are also connected from power pads to each internal step-down circuit via trunk lines. Efficient layout of each internal step-down circuit within the chip requires flexibility in circuit layout. Since trunk lines for ground voltage VSS and internally generated voltages, in addition to VDD and VPERI, often run directly above the internal step-down circuits, it is common for the internal step-down circuits to extend the VDD and VPERI branch lines of M2 from the driver and connect them to the trunk lines. Signal wiring to M1 can be used below the M2 branch line to place the internal step-down circuit itself and logic circuits that do not require high-speed operation. Furthermore, the internal step-down circuit connects a phase compensation capacitor using a DRAM memory capacitor element or an MIM element. 7 has a configuration in which the second wiring group W2 is drawn out to the outside of the element area EA and the first wiring group W1 is extended beyond the second wiring group W2. The circuit area CA is shared with the first wiring group W1, but is not shared with at least one of the external power supply branch line OW and the internal power supply branch line IW, and therefore the mounting area of ​​the semiconductor device 100B increases by the amount of the circuit area CA.

[0041] (Actions and Effects) In the semiconductor device 100, 100A of the present disclosure, at least a portion of the internal power supply branch line IW overlaps with the first wiring group W1 and a portion of the elements on the circuit area CA when viewed from the first metal layer M1 toward the second metal layer M2. By overlapping (covering) the internal power supply branch line IW with the first wiring group W1 and a portion of the elements on the circuit area CA in this manner, a DRAM memory capacitor element can be placed in this portion of the circuit area CA as a phase compensation capacitor, for example. Furthermore, a DRAM memory capacitor element or a logic circuit that does not require high speed and is comprised of up to M1 can be placed in other areas. This allows the semiconductor device 100, 100A to have a reduced mounting area while improving its EM resistance.

[0042] In addition, the following supplementary notes are provided in relation to the above description.

[0043] (Appendix 1) 1. A semiconductor device comprising a power supply circuit that converts a first power supply voltage supplied from an external source into a second power supply voltage that is lower than the first power supply voltage and drives an internal circuit, using a plurality of transistors, a first metal layer provided above an element region including a plurality of the transistors; first contacts connecting the first metal layer to a plurality of the transistors; a second metal layer provided on top of the first metal layer; a second contact connecting the second metal layer to the first metal layer; a first wiring group included in the first metal layer, which commonly connects first terminals of the plurality of transistors via the first contacts; a second wiring group included in the first metal layer, which commonly connects second terminals different from the first terminals of the plurality of transistors via the first contacts; a third wiring group included in the second metal layer, which commonly connects the first wiring group via the second contact; a third metal layer provided on top of the second metal layer; an external power supply trunk line included in the third metal layer, which supplies the first power supply to a plurality of the transistors; an internal power supply trunk line included in the third metal layer, which supplies the second power supply to the internal circuit; Equipped with the first wiring group extends in a first specific direction from the element region to a circuit region adjacent to the element region, in which a circuit used to generate the second power supply is disposed, and is connected to an element included in the circuit; the third wiring group includes an internal power supply branch line that extends from the circuit area to the internal power supply trunk line in a second specific direction different from the first specific direction, thereby electrically connecting the first wiring group provided in the circuit area to the internal power supply trunk line, a semiconductor device in which at least a portion of the internal power supply branch line overlaps with the first wiring group and a portion of the element when the internal power supply branch line is viewed from the first metal layer toward the second metal layer;

[0044] (Appendix 2) the third wiring group includes an external power supply branch line that extends from the element region to the external power supply main line in the second specific direction, thereby electrically connecting the second wiring group provided in the element region to the external power supply main line; 2. The semiconductor device according to claim 1, wherein at least a portion of the external power supply branch line overlaps with a portion of the first wiring group and the second wiring group when the internal power supply branch line is viewed from the first metal layer toward the second metal layer.

[0045] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the internal circuit includes a semiconductor memory circuit.

[0046] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the element is a phase compensation capacitance that utilizes a capacitance included in a semiconductor memory circuit.

[0047] (Appendix 5) 5. The semiconductor device according to claim 1, wherein the first specific direction is a gate length direction of the plurality of transistors.

[0048] (Appendix 6) The capacitor element has a metal-insulator-metal (MIM) structure. 6. The semiconductor device according to claim 1, wherein the capacitive element is provided on an upper portion of the second metal layer.

[0049] (Appendix 7) a third metal layer internal power supply branch line provided in the third metal layer; The internal power supply branch lines included in the third wiring group are a first branch line included in the second metal layer, extending from the third metal layer internal power supply branch line to the circuit region in the second specific direction; a second branch line included in the second metal layer, extending from the third metal layer internal power supply branch line to the internal power supply main line in the second specific direction; 7. The semiconductor device according to any one of claims 1 to 6, comprising:

[0050] (Appendix 8) 8. The semiconductor device according to claim 7, wherein the element is provided in an upper layer or a lower layer of the first branch line and the second branch line. [Explanation of symbols]

[0051] 100 Semiconductor device 100A Semiconductor Device 100B Semiconductor device 200 Power circuit 300 Internal circuit

Claims

1. 1. A semiconductor device comprising a power supply circuit that converts a first power supply voltage supplied from an external source into a second power supply voltage that is lower than the first power supply voltage and drives an internal circuit, using a plurality of transistors, a first metal layer provided above an element region including a plurality of the transistors; first contacts connecting the first metal layer to a plurality of the transistors; a second metal layer provided on top of the first metal layer; a second contact connecting the second metal layer to the first metal layer; a first wiring group included in the first metal layer, which commonly connects first terminals of the plurality of transistors via the first contacts; a second wiring group included in the first metal layer, which commonly connects second terminals different from the first terminals of the plurality of transistors via the first contacts; a third wiring group included in the second metal layer, which commonly connects the first wiring group via the second contact; a third metal layer provided on top of the second metal layer; an external power supply trunk line included in the third metal layer, which supplies the first power supply to a plurality of the transistors; an internal power supply trunk line included in the third metal layer, which supplies the second power supply to the internal circuit; Equipped with the first wiring group extends in a first specific direction from the element region to a circuit region adjacent to the element region, in which a circuit used to generate the second power supply is disposed, and is connected to an element included in the circuit; the third wiring group includes an internal power supply branch line that extends from the circuit area to the internal power supply trunk line in a second specific direction different from the first specific direction, thereby electrically connecting the first wiring group provided in the circuit area to the internal power supply trunk line, At least a portion of the internal power supply branch line overlaps with the first wiring group and a portion of the element when the internal power supply branch line is viewed from the first metal layer toward the second metal layer.

2. the third wiring group includes an external power supply branch line that extends from the element region to the external power supply main line in the second specific direction, thereby electrically connecting the second wiring group provided in the element region to the external power supply main line; 2. The semiconductor device according to claim 1, wherein at least a portion of the external power supply branch line overlaps with a portion of the first wiring group and a portion of the second wiring group when the internal power supply branch line is viewed from the first metal layer toward the second metal layer.

3. 2. The semiconductor device according to claim 1, wherein said internal circuitry includes a semiconductor memory circuit.

4. 2. The semiconductor device according to claim 1, wherein said element is a phase compensation capacitance utilizing a capacitance included in a semiconductor memory circuit.

5. The semiconductor device according to claim 1 , wherein the first specific direction is a gate length direction of a plurality of the transistors.

6. A capacitance element having a MIM (Metal-Insulator-Metal) structure is provided, 2. The semiconductor device according to claim 1, wherein said capacitive element is provided above said second metal layer.

7. a third metal layer internal power supply branch line provided in the third metal layer; The internal power supply branch lines included in the third wiring group are a first branch line included in the second metal layer, extending from the third metal layer internal power supply branch line to the circuit region in the second specific direction; a second branch line included in the second metal layer, extending from the third metal layer internal power supply branch line to the internal power supply main line in the second specific direction; The semiconductor device according to claim 1 , comprising:

8. The semiconductor device according to claim 7 , wherein the element is provided in a layer above or below the first branch line and the second branch line.

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