Semiconductor device

Abstract

To protect a diode wiring connected to a temperature-sensing diode from noise and improve the strength beneath the diode wiring.SOLUTION: A semiconductor device comprises a semiconductor substrate. The semiconductor substrate comprises: a temperature-sensing diode provided above an upper surface of the semiconductor substrate; a diode wiring provided above the upper surface of the semiconductor substrate and connected to the temperature-sensing diode; a metal layer provided at least partly between the diode wiring and the upper surface of the semiconductor substrate; a first interlayer insulating film provided between the metal layer and the upper surface of the semiconductor substrate; and a second interlayer insulating film provided between the diode wiring and the metal layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices have been known in which the thermal element can be arranged electrically isolated from the semiconductor substrate without being restricted by the diffusion structure of the semiconductor layer below the thermal element (see, for example, Patent Document 1). Also known is a semiconductor device that includes a temperature sensor unit with stable temperature detection accuracy while suppressing an increase in chip area (see, for example, Patent Document 2). [Prior art document] [Patent documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-26279 [Patent Document 2] Patent No. 6872933 Summary of the Invention [Problem to be solved by the invention]

[0003] To protect a diode wiring connected to a temperature sensing diode from noise and to improve the strength below the diode wiring. [Means for solving the problem]

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate. In the semiconductor device, the semiconductor substrate may have a temperature sensing diode provided above an upper surface of the semiconductor substrate. In any of the semiconductor devices, the semiconductor substrate may have diode wiring provided above the upper surface of the semiconductor substrate and connected to the temperature sensing diode. In the semiconductor device, the semiconductor substrate may have a metal layer provided at least partially between the diode wiring and the upper surface of the semiconductor substrate. In the semiconductor device, the semiconductor substrate may have a first interlayer insulating film provided between the metal layer and the upper surface of the semiconductor substrate. In the semiconductor device, the semiconductor substrate may have a second interlayer insulating film provided between the diode wiring and the metal layer.

[0005] In any of the above semiconductor devices, the metal layer may also be provided in at least a portion between the temperature sensing diode and the upper surface of the semiconductor substrate.

[0006] In any of the above semiconductor devices, the metal layer may contain a metal harder than aluminum.

[0007] In any of the above semiconductor devices, the metal layer may contain at least one of tungsten, titanium, and tantalum.

[0008] The semiconductor device may further include a top electrode provided above the top surface of the semiconductor substrate and in contact with a partial region of the top surface of the semiconductor substrate. In the semiconductor device, the top electrode may be connected to the metal layer.

[0009] In any of the above semiconductor devices, the upper surface electrode may not overlap the diode wiring when viewed from above.

[0010] In any of the above semiconductor devices, the metal layer may contain a metal harder than the upper electrode.

[0011] In any of the above semiconductor devices, the metal layer may be in contact with the upper surface of the semiconductor substrate in a region that does not overlap with the diode wiring and the temperature sensing diode.

[0012] In any of the above semiconductor devices, a side surface of the second interlayer insulating film may be in contact with the upper electrode.

[0013] In any of the above semiconductor devices, the top electrode may include a first portion and a second portion that sandwich the diode wiring when viewed from above. In any of the above semiconductor devices, the metal layer may be provided from the first portion, passing under the diode wiring, to the second portion.

[0014] In any of the above semiconductor devices, the semiconductor substrate may further include a trench portion extending from an upper surface of the semiconductor substrate to an interior thereof, the trench portion having a conductive portion provided therein. In any of the above semiconductor devices, the semiconductor substrate may further include a well region extending from the upper surface of the semiconductor substrate to a depth deeper than a lower end of the trench portion. In any of the above semiconductor devices, the diode wiring may overlap the well region in a top view. In any of the above semiconductor devices, the first interlayer insulating film may be provided with a contact hole electrically connecting the metal layer and the well region.

[0015] In any one of the above semiconductor devices, the semiconductor substrate may further include an active portion in which a semiconductor element is provided, and the well region may be sandwiched between the active portions in a top view.

[0016] In any of the semiconductor devices described above, in a cross section perpendicular to the extension direction of the diode wiring, the width of the second interlayer insulating film in a direction parallel to the upper surface of the semiconductor substrate may be smaller than the width of the well region.

[0017] In any of the above semiconductor devices, two of the contact holes may be provided in the first interlayer insulating film. In any of the above semiconductor devices, the semiconductor substrate may further include a gate runner provided above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the gate runner may be provided between the two contact holes in a top view.

[0018] Any of the above semiconductor devices may further include an upper electrode provided above the upper surface of the semiconductor substrate and in contact with a partial region of the upper surface of the semiconductor substrate. Any of the above semiconductor devices may further include solder, at least a portion of which is provided above the upper electrode. In any of the above semiconductor devices, the solder may be provided up to an end position in the extension direction of the diode wiring. In any of the above semiconductor devices, the metal layer may be provided below the diode wiring at the end position in the extension direction.

[0019] Any of the above semiconductor devices may further include a protective film disposed above the semiconductor substrate and arranged to sandwich an active portion of the semiconductor substrate in a top view, and the metal layer may be disposed below an end of the protective film that overlaps with the diode wiring in a top view of the semiconductor device.

[0020] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0021] [Figure 1A] 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 1B] 10 is a diagram showing the arrangement of a temperature sensing diode 66, a diode wiring 60, and a metal layer 80 as viewed from above. [Figure 2] 2 is a diagram showing an example of the semiconductor device 100 in the AA' cross section of FIG. 1B. [Figure 3] FIG. 2 is a diagram showing a cross section of the semiconductor device 200 according to the comparative example taken along the line AA'. [Figure 4] 1C is a diagram showing an example of the semiconductor device 100 in the cross section BB' of FIG. 1B. [Figure 5] 1C is a diagram showing an example of the semiconductor device 100 in the CC' cross section of FIG. 1B. [Figure 6] FIG. 2 is a diagram showing an example of a top view of the semiconductor device 100. [Figure 7] 7 is a diagram showing an example of the semiconductor device 100 in the cross section taken along the line DD' in FIG. [Figure 8] FIG. 10 is a top view illustrating an example of a semiconductor device 300 according to another embodiment of the present invention. [Figure 9] 9 is a diagram showing an example of the semiconductor device 300 in the cross section taken along the line DD' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0023] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0024] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0025] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0026] Fig. 1A is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1A shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1A shows only some of the components of the semiconductor device 100, and some components are omitted.

[0027] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a compound semiconductor such as silicon or SiC. The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 facing each other in a top view. FIG. 1A shows one pair of edges 102-1 and 102-2 facing each other. In FIG. 1A, the direction parallel to the edges 102-1 and 102-2 is the Y-axis direction, and the direction perpendicular to the edges 102-1 and 102-2 is the X-axis direction.

[0028] An active portion 120 is provided on the semiconductor substrate 10. In this example, the semiconductor substrate 10 is provided with an active portion 120-1 and an active portion 120-2. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state.

[0029] A semiconductor element is provided in the active section 120. The semiconductor element may be a transistor element such as an IGBT, a diode element such as an FWD, or both.

[0030] The semiconductor device 100 includes an upper electrode 52 provided above the upper surface of the semiconductor substrate 10. The upper electrode 52 is provided above the active portion 120. The upper electrode 52 may be provided above each active portion 120. The semiconductor device 100 of this example includes an upper electrode 52-1 and an upper electrode 52-2. The upper electrode 52-1 is provided above the active portion 120-1, and the upper electrode 52-2 is provided above the active portion 120-2. In this specification, the upper electrode 52-1 may be referred to as a first portion, and the upper electrode 52-2 may be referred to as a second portion. The upper electrode 52 is, for example, an Al-Si alloy.

[0031] The top electrode 52-1 and the top electrode 52-2 may be electrically connected to each other by at least one of a metal layer, solder, or lead frame, which will be described later. The top electrode 52 may be the electrode with the largest area in a top view among the electrodes provided above the top surface of the semiconductor substrate 10. The top electrode 52 may be electrically connected to the emitter region or source region of the transistor section, or may be electrically connected to the anode region of the diode section. The active section 120 may be a region that overlaps with the top electrode 52 in a top view.

[0032] A P-type well region is provided in the semiconductor substrate 10. The well region is a P-type region with a higher concentration than the base region of the transistor section or the anode region of the diode section. The base region is a P-type region that is provided opposite the gate electrode and in which a channel is formed in the portion facing the gate electrode when a predetermined gate voltage is applied to the gate electrode. The semiconductor substrate 10 has a first well region 111 and a second well region 112. The first well region 111 and the second well region 112 are provided to sandwich an active section 120 in a top view. The first well region 111 and the second well region 112 are provided to sandwich the active section 120 in a predetermined direction (the X-axis direction in FIG. 1A). "Two well regions sandwich the active section 120" means that any line connecting the two well regions passes through the active section 120 in a top view. In this example, the first well region 111 and the second well region 112 are both rectangular in shape. In FIG. 1A, the first well region 111 and the second well region 112 are hatched.

[0033] The first well region 111 may be provided near the edge 102-1. That is, the distance between the first well region 111 and the edge 102-1 is smaller than the distance between the first well region 111 and the edge 102-2. The second well region 112 may be provided near the edge 102-2. That is, the distance between the second well region 112 and the edge 102-2 is smaller than the distance between the second well region 112 and the edge 102-1.

[0034] In this example, the first well region 111 is provided between the active portion 120 and the edge 102-1 in the X-axis direction. The active portion 120 is not provided between the first well region 111 and the edge 102-1. In other words, the first well region 111 is provided between the end of the active portion 120 in the X-axis direction and the edge 102-1.

[0035] In this example, the second well region 112 is provided between the active portion 120 and the edge 102-2 in the X-axis direction. The active portion 120 is not provided between the second well region 112 and the edge 102-2. In other words, the second well region 112 is provided between the end of the active portion 120 in the X-axis direction and the edge 102-2.

[0036] The first well region 111 and the second well region 112 may be provided in a range in the Y-axis direction that includes a center position Xc between the end sides 102-1 and 102-2. The first well region 111 may be sandwiched between the active portions 120 in the Y-axis direction. The second well region 112 may be sandwiched between the active portions 120 in the Y-axis direction. The second well region 112 may be provided in a wider range in the Y-axis direction than the first well region 111.

[0037] The semiconductor substrate 10 may have a peripheral well region 113 surrounding the active portion 120 in a top view. The peripheral well region 113 may be parallel to each edge of the semiconductor substrate 10. In FIG. 1A, the peripheral well region 113 contacts each edge of the semiconductor substrate 10, but the peripheral well region 113 may be spaced apart from each edge. In this example, the peripheral well region 113 is an annular region surrounding the active portion 120 in a top view. The width of the peripheral well region 113 may be constant in a direction perpendicular to each edge. In FIG. 1A, the peripheral well region 113 is also hatched. However, hatching of portions of each well region that overlap with the gate pad 50, the current detection pad 72, the anode pad 74, and the cathode pad 76 is omitted.

[0038] In this example, the first well region 111 and the second well region 112 protrude further toward the center of the active portion 120 than the peripheral well region 113. In another example, at least one of the first well region 111 and the second well region 112 may be provided between the peripheral well region 113 and the edge 102 of the semiconductor substrate 10. In this case, the first well region 111 and the second well region 112 protrude from the peripheral well region 113 toward the edge 102.

[0039] The semiconductor substrate 10 may have divided well regions 114 that divide the active portion 120 in a top view. The active portion 120 may be divided into active portion 120-1 and active portion 120-2 by well regions including the divided well regions 114. The divided well regions 114 are sandwiched between the active portions 120 in a top view. The divided well regions 114 have a longitudinal direction in a predetermined well longitudinal direction. The divided well regions 114 extend in the well longitudinal direction and cross the active portion 120. The well longitudinal direction of the divided well regions 114 is the X-axis direction. In FIG. 1A, the divided well regions 114 are also hatched.

[0040] The divided well region 114 may be provided between the first well region 111 and the second well region 112. One longitudinal end of the divided well region 114 may be connected to the first well region 111, and the other longitudinal end may be connected to the second well region 112. The divided well region 114 may be provided in a region overlapping with the center of the active portion 120.

[0041] The divided well region 114 may have a wide portion 115 whose width in a direction perpendicular to the longitudinal direction of the well (in this example, the Y-axis direction) in a top view is wider than other portions. The wide portion 115 is also provided between the first well region 111 and the second well region 112. The wide portion 115 may be provided in a region overlapping with the center of the active portion 120. The wide portion 115 may be provided in a region including the center of the divided well region 114 in the longitudinal direction of the well.

[0042] The semiconductor substrate 10 of this example has control electrodes such as a gate pad 50, a current detection pad 72, an anode pad 74, and a cathode pad 76. The gate pad 50 is provided above the first well region 111. The current detection pad 72, the anode pad 74, and the cathode pad 76 are provided above the second well region 112.

[0043] A predetermined gate voltage is applied to the gate pad 50. The gate voltage applied to the gate pad 50 is supplied to the transistor section of the active section 120 by a gate runner 48 or the like, which will be described later.

[0044] The semiconductor substrate 10 has a gate runner 48 provided above the upper surface of the semiconductor substrate 10. In FIG. 1A, the gate runner 48 is indicated by a dashed line. In this example, the gate runner 48 is a wiring formed of polysilicon doped with impurities. The gate runner 48 may also be formed of a conductive material such as metal. The gate runner 48 supplies a gate voltage applied to a gate pad 50 to a transistor portion provided in the active portion 120.

[0045] The gate runners 48 may be provided above each well region. A portion of the gate runners 48 may be provided along the peripheral well region 113 so as to surround the active portion 120. Other gate runners 48 may be provided along the first well region 111 and the second well region 112, between each control electrode and the active portion 120. Other gate runners 48 may be provided above the divided well regions 114 and may overlap with the temperature sensing diode 66 and diode wiring 60, which will be described later. In other words, the gate runners 48 in this example may divide the active portion 120 in a top view.

[0046] The current detection pad 72 is connected to a current detection unit (not shown) and detects the current flowing through the current detection unit.

[0047] 1B is a diagram showing the arrangement of the temperature sensing diode 66, the diode wiring 60, and the metal layer 80 when viewed from above. In FIG. 1B, the hatching of the well region is omitted, and the temperature sensing diode 66 and the metal layer 80 are hatched.

[0048] The semiconductor substrate 10 has a temperature sensing diode 66 provided above the top surface of the semiconductor substrate 10. The temperature sensing diode 66 detects the temperature of the semiconductor substrate 10. As an example, the temperature sensing diode 66 is a PN junction diode having an anode region and a cathode region formed of a semiconductor material such as polysilicon.

[0049] The semiconductor substrate 10 has a diode wiring 60. The diode wiring 60 is provided above the upper surface of the semiconductor substrate 10 and is connected to a temperature sensing diode 66. The diode wiring 60 has an anode wiring 60-1 and a cathode wiring 60-2. The diode wiring 60 may be formed of a semiconductor material such as polysilicon, or may be formed of a metal.

[0050] The anode pad 74 is connected to the anode region of the temperature sensing diode 66 via the anode wiring 60-1 of the diode wiring 60. The cathode pad 76 is connected to the cathode region of the temperature sensing diode 66 via the cathode wiring 60-2 of the diode wiring 60. As an example, the temperature of the semiconductor substrate 10 is measured by measuring the forward voltage of the temperature sensing diode 66 using the anode pad 74 and the cathode pad 76. In this example, the diode wiring 60, the temperature sensing diode 66, and the gate runner 48 overlap with the divided well region 114 in a top view.

[0051] The top electrode 52 and each control electrode are electrodes containing a metal such as aluminum. An interlayer insulating film is provided between the top electrode 52 and each control electrode and the semiconductor substrate 10. The top electrode 52 and the semiconductor substrate 10 are connected via contact holes provided in the interlayer insulating film. The interlayer insulating film and contact holes are omitted in FIG. 1B.

[0052] In the top view, the top electrode 52 of this example does not overlap with the diode wiring 60. In the top view, the top electrode 52 of this example does not overlap with the temperature sensing diode 66 either. In the top view, the diode wiring 60 and the temperature sensing diode 66 of this example are sandwiched between the first portion 52-1 and the second portion 52-2. In the top view, the diode wiring 60 and the temperature sensing diode 66 of this example are sandwiched between the active portion 120-1 and the active portion 120-2.

[0053] The semiconductor substrate 10 has a metal layer 80. The metal layer 80 is provided at least partially between the diode wiring 60 and the upper surface of the semiconductor substrate 10 (see FIG. 2). FIG. 1B shows only the metal layer 80 provided near the diode wiring 60. However, the metal layer 80 may be provided in an area other than the area overlapping with the diode wiring 60 in top view. For example, the metal layer 80 is also provided in the active section 120.

[0054] The semiconductor substrate 10 may include an edge termination structure between the peripheral well region 113 and the edge 102 of the semiconductor substrate 10. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may include, for example, a guard ring annularly arranged around the active region 120, a field plate, a resurf, or a combination of these structures. In this specification, the edge termination structure is omitted.

[0055] 2 is a diagram showing an example of the semiconductor device 100 in the A-A' cross section of FIG. 1B. The A-A' cross section is a YZ cross section perpendicular to the extension direction (X-axis direction) of the diode wiring 60. In this cross section, the semiconductor device 100 includes a semiconductor substrate 10, solder 35, plating 36, an interlayer insulating film 38, a gate runner 48, an upper electrode 52, the diode wiring 60, a metal layer 80, a lead frame 90, and a wiring protective film 92. In this cross section, the lower surface of the semiconductor substrate 10 is omitted.

[0056] A trench portion 40 is provided in the semiconductor substrate 10. The trench portion 40 is provided inward from the top surface 21 of the semiconductor substrate 10. The trench portion 40 may be a gate trench. The trench portion 40 has an insulating film 42 and a conductive portion 44 therein. The conductive portion 44 may be electrically connected to a gate pad 50 via a gate runner 48. In FIG. 2, the conductive portion 44 is hatched. The insulating film 42 insulates the semiconductor substrate 10 from the conductive portion. However, the trench portion 40 may be a dummy trench. In that case, the conductive portion 44 may be electrically connected to a top electrode 52.

[0057] In this cross section, a P+ type split well region 114 is provided inside the semiconductor substrate 10. The split well region 114 is provided from the upper surface 21 of the semiconductor substrate 10 to a depth deeper than the lower end of the trench portion 40. The end of the trench portion 40 in the extension direction (in this example, the Y-axis direction) may be located inside the split well region 114. In this cross section, an N- type drift region 18 is provided below the trench portion 40 and the split well region 114. In addition, in FIG. 2, the trench portion 40 extending into the split well region 114 is not shown in order to show the size of the split well region 114, but the split well region 114 and the conductive portion 44 are electrically insulated from each other by an insulating film 42.

[0058] The semiconductor substrate 10 has a first interlayer insulating film 38-1 provided on the upper surface 21. The first interlayer insulating film 38-1 is provided between the metal layer 80 and the upper surface 21 of the semiconductor substrate 10. The first interlayer insulating film 38-1 may be in contact with the upper surface 21. The first interlayer insulating film 38-1 insulates the metal layer 80 and the upper surface electrode 52 from the semiconductor substrate 10. In this example, the first interlayer insulating film 38-1 also insulates the metal layer 80 from the gate runner 48. An interlayer insulating film 38 is provided between the gate runner 48 and the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be an insulating film different from the first interlayer insulating film 38-1.

[0059] The semiconductor substrate 10 has a metal layer 80 provided above the upper surface 21. The metal layer 80 is provided at least partially between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10. The metal layer 80 may be provided over the entire area between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10 at a position where the metal layer 80 overlaps with the diode wiring 60 in the depth direction. In this example, the metal layer 80 is provided not only below the diode wiring 60 but also in the active section 120. The metal layer 80 may also be provided below the plating 36.

[0060] The semiconductor substrate 10 has a second interlayer insulating film 38-2 provided above the upper surface 21. The second interlayer insulating film 38-2 is provided between the diode wiring 60 and the metal layer 80, and insulates the diode wiring 60 from the metal layer 80. The first interlayer insulating film 38-1 and the second interlayer insulating film 38-2 are films including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and another insulating film.

[0061] The diode wiring 60 is provided above the second interlayer insulating film 38-2. As described above, the diode wiring 60 has an anode wiring 60-1 and a cathode wiring 60-2. In this example, the diode wiring 60 is covered with a wiring protective film 92. The wiring protective film 92 is, for example, polyimide.

[0062] An upper surface electrode 52 is provided above the metal layer 80. The upper surface electrode 52 is connected to the metal layer 80. The upper surface electrode 52 and the metal layer 80 may be stacked. As described above, the upper surface electrode 52 has a first portion 52-1 and a second portion 52-2. When viewed from above, the first portion 52-1 and the second portion 52-2 are arranged with the diode wiring 60 sandwiched between them.

[0063] Plating 36 is provided above the upper electrode 52. The upper electrode 52 is connected to a lead frame 90, which is a wiring member, via plating 36. One example of plating 36 is Ni plating. Providing plating 36 improves the wettability of the upper electrode 52 and solder 35, which is a joining member, and enhances the joining strength of the lead frame 90. Plating 36 may be provided over the entire upper surface of the upper electrode 52, or over most of the upper surface of the upper electrode 52 (e.g., more than half of the area of ​​the upper surface).

[0064] The solder 35 is provided above the plating 36. In this example, the solder 35 is provided between the lead frame 90 and the plating 36. In FIG. 2, the solder 35 is also provided above the wire protective film 92. In this example, the solder 35 is provided between the lead frame 90 and the wire protective film 92. However, the solder 35 does not have to be provided above the wire protective film 92.

[0065] The lead frame 90 is provided above the solder 35. The upper surface electrode 52 is connected to an external circuit via the lead frame 90.

[0066] At least a portion of the solder 35 may be provided at the same height as the wire protective film 92. The wire protective film 92 is provided at a position lower in the height direction (Z-axis direction) than the lead frame 90. In this example, the wire protective film 92 is provided below the lead frame 90.

[0067] In this example, there is a point where the solder 35, plating 36, and wiring protective film 92 meet. This point is referred to as triple point G1. When triple point G1 is present, repeated application of stress due to heat can cause stress concentration at triple point G1, which can lead to cracks extending from the triple point toward the top surface 21 of the semiconductor substrate 10. In this example, metal layer 80 can suppress the propagation of the cracks.

[0068] 3 is a diagram showing an A-A' cross section of a semiconductor device 200 according to a comparative example. In the semiconductor device 200, a metal layer 80 is not provided between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10. Accordingly, a second interlayer insulating film 38-2 is not provided either. The other configurations are the same as those of the semiconductor device 100.

[0069] In the semiconductor device 200, no metal layer 80 is provided between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10, and only a first interlayer insulating film 38-1 with low strength and a polysilicon gate runner 48 are provided. Therefore, if a crack from the above-mentioned triple point G1 propagates between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10, the propagation of the crack may not be fully suppressed. As a result, for example, a problem may occur in which the crack propagates through the first interlayer insulating film 38-1, causing electrical continuity between the diode wiring 60 and the gate runner 48.

[0070] On the other hand, in the semiconductor device 100 according to the embodiment, the metal layer 80 provided between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10 can improve the strength below the diode wiring 60. This can suppress the progression of cracks below the diode wiring 60. Furthermore, the metal layer 80 provided between the diode wiring 60 and the upper surface 21 of the semiconductor substrate 10 can protect the diode wiring 60 from noise from the semiconductor substrate 10. The second interlayer insulating film 38-2 also improves the strength below the diode wiring 60, and can protect the diode wiring 60 from noise.

[0071] The metal layer 80 may be made of a conductive material. This increases the effectiveness of noise suppression. Furthermore, from the perspective of improving strength, it is preferable that the metal layer 80 has a high hardness. As an example, the metal layer 80 contains a metal that is harder than aluminum. The metal layer 80 and the top electrode 52 may be made of different materials. The metal layer 80 may contain a metal that is harder than the top electrode 52. The metal layer 80 may contain at least one of tungsten, titanium, and tantalum. This can further improve the strength below the diode wiring 60.

[0072] 2, the side surface of the second interlayer insulating film 38-2 may be in contact with the top electrode 52. In this example, one side surface of the second interlayer insulating film 38-2 is in contact with the first portion 52-1, and the other side surface is in contact with the second portion 52-2. In other words, the second interlayer insulating film 38-2 is sandwiched between the top electrodes 52 in a direction (Y-axis direction) perpendicular to the extension direction (X-axis direction) of the diode wiring 60 in a plane parallel to the top surface 21.

[0073] In this example, the metal layer 80 is provided from the first portion 52-1 to the second portion 52-2, passing under the diode wiring 60. This allows the entire surface under the diode wiring 60 to be covered, so that the semiconductor device 100 can more reliably achieve improved strength and noise countermeasure effects.

[0074] In this example, the diode wiring 60 overlaps the split well region 114 in the depth direction. In this example, the first interlayer insulating film 38-1 has a contact hole 45 that electrically connects the metal layer 80 and the split well region 114. The top electrode 52 is electrically connected to the split well region 114 through the contact hole 45. This makes the potential of the split well region 114 equal to the potential of the top electrode 52, thereby protecting the diode wiring 60 and the gate runner 48 provided above the split well region 114 from noise from the semiconductor substrate 10.

[0075] A connection portion 46 may be provided below the contact hole 45. The connection portion 46 may be formed of the same material as the gate runner 48. In other words, the connection portion 46 may be a wiring formed of polysilicon to which an impurity is added. By providing the connection portion 46, it becomes easier to electrically connect the divided well region 114 and the upper electrode 52.

[0076] The first interlayer insulating film 38-1 of this example is provided with two contact holes 45. The gate runner 48 of this example is provided between the two contact holes 45 in top view.

[0077] In this example, the divided well regions 114 are sandwiched between the active portions 120 in the Y-axis direction. That is, the divided well regions 114 cross the active portions 120. The ends of the active portions 120 in the Y-axis direction in FIG. 2 may coincide with the ends of the divided well regions 114.

[0078] In the A-A' cross section, width T1 of second interlayer insulating film 38-2 in a direction parallel to upper surface 21 of semiconductor substrate 10 may be smaller than width T2 of divided well region 114. In the A-A' cross section, second interlayer insulating film 38-2 may entirely overlap divided well region 114.

[0079] 4 is a diagram showing an example of the semiconductor device 100 at the B-B' cross section of FIG. 1B. The B-B' cross section is a YZ cross section perpendicular to the extension direction (X-axis direction) of the diode wiring 60. Descriptions of the same configuration as that at the A-A' cross section shown in FIG. 2 will be omitted as appropriate.

[0080] The cross section is a cross section across the temperature sensing diode 66. The temperature sensing diode 66 is provided above the upper surface 21 of the semiconductor substrate 10. The position of the temperature sensing diode 66 in the Z-axis direction may be the same as the position of the diode wiring 60. In this example, the temperature sensing diode 66 is covered with a wiring protective film 92. In this example, the temperature sensing diode 66 overlaps with the gate runner 48 in the Z-axis direction.

[0081] The metal layer 80 in this example is also provided at least partially between the temperature sensing diode 66 and the upper surface 21 of the semiconductor substrate 10. The arrangement of the first interlayer insulating film 38-1 and the second interlayer insulating film 38-2 is the same as in FIG. 2. The second interlayer insulating film 38-2 in this example insulates the metal layer 80 from the temperature sensing diode 66. This improves the strength below the temperature sensing diode 66, as in the case of the diode wiring 60. It also protects the temperature sensing diode 66 from noise. The metal layer 80 may be provided over the entire area between the temperature sensing diode 66 and the upper surface 21 of the semiconductor substrate 10, at a position where it overlaps with the temperature sensing diode 66 in the depth direction. The metal layer 80 provided below the temperature sensing diode 66 may also be continuous with the metal layer 80 provided in the active section 120.

[0082] 5 is a diagram showing an example of the semiconductor device 100 in the CC' cross section of FIG. 1B. The CC' cross section is an XZ cross section that crosses the active portion 120. In this cross section, an IGBT is provided on the semiconductor substrate 10. However, the semiconductor substrate 10 may also be provided with a MOSFET or a diode.

[0083] In the CC' cross section, the semiconductor device 100 has a semiconductor substrate 10, a first interlayer insulating film 38-1, a metal layer 80, an upper electrode 52, and a lower electrode 24. The first interlayer insulating film 38-1 is provided on the upper surface 21 of the semiconductor substrate 10. The first interlayer insulating film 38-1 may be the same as the first interlayer insulating film 38-1 described with reference to FIG. 2 and the like. That is, the first interlayer insulating film 38-1 may be provided from below the diode wiring 60 to the active portion 120.

[0084] The top electrode 52 is provided above the first interlayer insulating film 38-1. In the CC' cross section, a second portion 52-2 of the top electrode 52 is provided. The top electrode 52 contacts a partial region of the top surface 21 of the semiconductor substrate 10 through a contact hole 54 formed in the first interlayer insulating film 38-1. The top electrode 52 may be considered to be in contact with the top surface 21 even when it contacts the top surface 21 of the semiconductor substrate 10 via a metal layer 80. A tungsten plug or the like for contact may be provided between the top surface 21 of the semiconductor substrate 10 and the top electrode 52. The top electrode 52 may be considered to be in contact with the top surface 21 even when it contacts the top surface 21 of the semiconductor substrate 10 via a tungsten plug.

[0085] A metal layer 80 is provided between the first interlayer insulating film 38-1 and the upper surface electrode 52. In this example, the metal layer 80 is electrically connected to the upper surface electrode 52 in the CC' cross section.

[0086] The metal layer 80 may be in contact with the upper surface 21 of the semiconductor substrate 10 in a region that does not overlap with the diode wiring 60 and the temperature sensing diode 66. In this example, the metal layer 80 is in contact with the upper surface 21 of the semiconductor substrate 10 via the contact hole 54 in the first interlayer insulating film 38-1 in the CC' cross section. The metal layer 80 may be in contact with multiple mesa portions 70. The metal layer 80 may be provided above multiple trench portions.

[0087] The metal layer 80 may function as a barrier metal in the active section 120. By providing the metal layer 80 in the active section 120, it is possible to prevent resin ions from a protective film, etc., provided above the upper electrode 52 from penetrating into the semiconductor substrate 10. The metal layer 80 may be provided from below the diode wiring 60 to the active section 120. The metal layer 80 may have the same composition as the metal layer 80 below the diode wiring 60. This allows for simplification of the manufacturing process. The metal layer 80 may have the same film thickness as the metal layer 80 below the diode wiring 60. This improves in-plane uniformity.

[0088] The lower electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The upper electrode 52 and the lower electrode 24 are made of a metal material such as aluminum.

[0089] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 may be a region of the semiconductor substrate 10 that remains without being implanted with dopants.

[0090] An N+ type emitter region 12 is provided on the upper surface 21 of the semiconductor substrate 10. In this example, the emitter region 12 is in contact with the metal layer 80 at the upper surface 21. A P- type base region 14 is provided between the emitter region 12 and the drift region 18 in the depth direction. An N+ type accumulation region 16 may be provided between the base region 14 and the drift region 18. In another cross section of the active portion 120, a P+ type contact region may be provided on the upper surface 21 of the semiconductor substrate 10.

[0091] One or more trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. The trenches 40 may be gate trenches. Each trench extends from the top surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, the contact region, and the accumulation region 16 is provided, each trench also extends through these doped regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed. The region sandwiched between the trenches within the semiconductor substrate 10 is referred to as a mesa portion 70.

[0092] The trench portion 40 has a trench provided on the upper surface 21 of the semiconductor substrate 10, an insulating film 42, and a conductive portion 44. The insulating film 42 is provided to cover the inner wall of the trench. The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the trench. The conductive portion 44 is provided inside the trench, further inside than the insulating film 42. In other words, the insulating film 42 insulates the conductive portion 44 from the semiconductor substrate 10. The conductive portion 44 is formed of a conductive material such as polysilicon.

[0093] The conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The conductive portion 44 is electrically connected to the gate runner 48. When a predetermined gate voltage is applied to the conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the trench portion 40.

[0094] The dummy trench portion 30 may have the same structure as the trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the upper surface electrode 52 in another cross section. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the conductive portion 44.

[0095] In this example, the trench portion 40 and the dummy trench portion 30 are covered by a first interlayer insulating film 38-1 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the trench portion 40 may be curved and convex downward (curved in cross section). The ends of the trench portion 40 and the dummy trench portion 30 in the Y-axis direction may be covered by a divided well region 114 (see FIGS. 2 and 4). However, the gate provided in the semiconductor substrate 10 is not limited to a trench type. A planar type gate may also be provided in the semiconductor substrate 10.

[0096] An N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the bottom end of the base region 14 from reaching the P+ type collector region 22.

[0097] A P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0098] Fig. 6 is a diagram showing an example of a top view of the semiconductor device 100. In Fig. 6, the positions of the solder 35, the lead frame 90, and the protective film 94 are shown.

[0099] A protective film 94 is provided above the upper surface 21 of the semiconductor substrate 10. The protective film 94 is arranged to sandwich the active portion 120 of the semiconductor substrate 10 in a top view. The protective film 94 may surround the active portion 120 in a top view. The dark hatching in FIG. 6 represents the protective film 94. The protective film 94 separates the gate pad 50, the current detection pad 72, the anode pad 74, and the cathode pad 76 from the active portion 120 in a top view. The protective film 94 may also separate a portion of the upper surface electrode 52 that faces each control electrode in the Y-axis direction. One example of the protective film 94 is polyimide.

[0100] In the active portion 120, solder 35 is provided above the upper surface electrode 52. The area where the solder 35 is provided in top view is defined by the protective film 94. In this example, the solder 35 is formed over the entire area of ​​the active portion 120 surrounded by the protective film 94. In FIG. 6, the area where the solder 35 is formed is indicated by light hatching.

[0101] The end of the solder 35 in the extension direction (X-axis direction) of the diode wiring 60 is defined as the end position Xe. In other words, the solder 35 is provided up to the end position Xe in the extension direction. In this example, the end position Xe coincides with the end of the protective film 94 that sandwiches the active portion 120. However, the end position Xe does not have to coincide with the end of the protective film 94 that surrounds the active portion 120. The end position Xe may be located inside the semiconductor substrate 10 relative to the end of the protective film 94. Furthermore, if the end position Xe varies depending on the position in the direction perpendicular to the extension direction of the diode wiring 60 (Y-axis direction), the end of the solder 35 at the position where the triple point G1 (see FIG. 2) is formed may be defined as the end position Xe. In other words, the triple point G1 is formed from the temperature sensing diode 66 side of the diode wiring 60 to the end position Xe. The lead frame 90 is provided above the solder 35.

[0102] 7 is a diagram showing an example of the semiconductor device 100 in the DD' cross section of FIG. 6. The DD' cross section is an XZ cross section that crosses the protective film 94 from the diode wiring 60. In this example, the solder 35 is also provided above the wiring protective film 92. However, the solder 35 does not have to be provided above the wiring protective film 92.

[0103] In this example, a metal layer 80 is provided below the diode wiring 60 at the end position Xe in the extension direction (X-axis direction). Among the triple junctions described above, stress is particularly likely to occur at the boundary portion where the solder 35 is no longer formed. Therefore, cracks are likely to occur at the triple junction at the end position Xe. By providing the metal layer 80 below the end position Xe, the strength of the portion below the diode wiring 60 near the position where cracks are likely to occur can be increased. When the diode wiring 60 and the end position Xe do not overlap in the depth direction, the metal layer 80 may be provided below the diode wiring 60 at a position where the end position Xe is extended to a position where it overlaps with the diode wiring 60 in the Y-axis direction.

[0104] The metal layer 80 may be provided outward (toward the negative side of the X-axis) from the end position Xe of the solder 35. The metal layer 80 may be formed to extend for at least 10 μm from the end position Xe in the extension direction of the diode wiring 60. The distance may be 20 μm or 100 μm. The metal layer 80 may be provided continuously from the temperature sensing diode 66 side of the diode wiring 60 to the end position Xe.

[0105] In top view, a metal layer 80 may be provided below the end of the protective film 94 that overlaps with the diode wiring 60. In this example, the end of the protective film 94 coincides with the end position Xe of the solder 35. Since the end position Xe of the solder 35 is often determined by the end of the protective film 94, providing the metal layer 80 below the end of the protective film 94 can increase the strength of the lower part of the diode wiring 60 in the vicinity of a position where cracks are likely to occur.

[0106] The metal layer 80 may be provided outward (toward the negative X-axis side) from the end of the protective film 94. The metal layer 80 may be formed from the end of the protective film 94 as the center and extend for at least 10 μm in the extension direction of the diode wiring 60. The distance may be 20 μm or 100 μm. The metal layer 80 may be provided continuously from the temperature sensing diode 66 side of the diode wiring 60 to the end of the protective film 94. The metal layer 80 may be provided below the ends of all of the protective films 94 that sandwich the active section 120.

[0107] 8 is a top view showing an example of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 of this example differs from the semiconductor device 100 shown in FIG. 1B in that the metal layer 80 is not formed below the temperature sensing diode 66. Other parts are the same as those of the semiconductor device 100. The metal layer 80 of this example may also be provided up to the active section 120.

[0108] 9 is a diagram showing an example of the semiconductor device 300 in the DD' cross section of Fig. 8. The DD' cross section is a YZ cross section perpendicular to the extension direction (X-axis direction) of the diode wiring 60. The DD' cross section is a cross section crossing the temperature sensing diode 66.

[0109] As described above, in the semiconductor device 300, the metal layer 80 is not formed below the temperature sensing diode 66. A first interlayer insulating film 38-1 and a gate runner 48 are formed below the temperature sensing diode 66 in this example. The other structures are the same as those of the semiconductor device 100 shown in FIG. 4. As described above, cracks are likely to occur at the triple junction at the end position Xe. In this example, the end position Xe of the solder 35 in the extension direction (X-axis direction) of the diode wiring 60 does not overlap with the temperature sensing diode 66. Therefore, the possibility of cracks progressing below the temperature sensing diode 66 is relatively low. Therefore, the metal layer 80 does not need to be provided below the temperature sensing diode 66.

[0110] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0111] 10 semiconductor substrate, 12 emitter region, 14 base region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 lower electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 35 solder, 36 plating, 38 interlayer insulating film, 40 trench portion, 42 insulating film, 44 conductive portion, 45 contact hole, 46 connection portion, 48 gate runner, 50 gate pad, 52 upper Surface electrode, 54 contact hole, 60 diode wiring, 66 temperature sensing diode, 70 mesa portion, 72 current detection pad, 74 anode pad, 76 cathode pad, 80 metal layer, 90 lead frame, 92 wiring protection film, 94 protection film, 100 semiconductor device, 102 edge, 111 first well region, 112 second well region, 113 peripheral well region, 114 divided well region, 115 wide portion, 120 active portion, 200 semiconductor device, 300 semiconductor device

Claims

1. A semiconductor device including a semiconductor substrate, The semiconductor substrate is a temperature sensing diode provided above the upper surface of the semiconductor substrate; a diode wiring provided above the upper surface of the semiconductor substrate and connected to the temperature sensing diode; a metal layer provided at least partially between the diode wiring and the upper surface of the semiconductor substrate; a first interlayer insulating film provided between the metal layer and an upper surface of the semiconductor substrate; a second interlayer insulating film provided between the diode wiring and the metal layer; A semiconductor device having:

2. The metal layer is also provided at least partially between the temperature sensing diode and the upper surface of the semiconductor substrate. The semiconductor device according to claim 1 .

3. The metal layer includes a metal harder than aluminum. The semiconductor device according to claim 1 .

4. The metal layer includes at least one of tungsten, titanium, and tantalum. The semiconductor device according to claim 3 .

5. an upper surface electrode provided above the upper surface of the semiconductor substrate and in contact with a partial region of the upper surface of the semiconductor substrate; The top electrode is connected to the metal layer. The semiconductor device according to claim 1 .

6. The upper surface electrode does not overlap the diode wiring when viewed from above. The semiconductor device according to claim 5 .

7. The metal layer includes a metal harder than the upper electrode. The semiconductor device according to claim 6.

8. The metal layer is in contact with the upper surface of the semiconductor substrate in a region that does not overlap the diode wiring and the temperature sensing diode. The semiconductor device according to claim 6.

9. The side surface of the second interlayer insulating film is in contact with the upper electrode. The semiconductor device according to claim 6.

10. the upper surface electrode includes a first portion and a second portion sandwiching the diode wiring in a top view, The metal layer is provided from the first portion, passing under the diode wiring, to the second portion. The semiconductor device according to claim 6.

11. The semiconductor substrate is a trench portion provided from the upper surface of the semiconductor substrate to the interior thereof, the trench portion having a conductive portion provided therein; a well region provided from the upper surface of the semiconductor substrate to a depth greater than the bottom end of the trench portion; and the diode wiring overlaps the well region in a top view, The first interlayer insulating film is provided with a contact hole that electrically connects the metal layer and the well region. The semiconductor device according to claim 6.

12. the semiconductor substrate further has an active portion in which a semiconductor element is provided, The well region is sandwiched between the active portions when viewed from above. The semiconductor device according to claim 11.

13. In a cross section perpendicular to the extending direction of the diode wiring, the width of the second interlayer insulating film in a direction parallel to the upper surface of the semiconductor substrate is smaller than the width of the well region. The semiconductor device according to claim 11.

14. two contact holes are provided in the first interlayer insulating film; the semiconductor substrate further comprises a gate runner disposed above an upper surface of the semiconductor substrate; The gate runner is provided between the two contact holes in a top view. The semiconductor device according to claim 11.

15. an upper surface electrode provided above the upper surface of the semiconductor substrate and in contact with a partial region of the upper surface of the semiconductor substrate; At least a portion of the solder is provided above the upper surface electrode. Further provided with In the extension direction of the diode wiring, the solder is provided up to an end position, The metal layer is provided below the diode wiring at the end position in the extension direction. The semiconductor device according to claim 1 .

16. a protective film provided above the semiconductor substrate and arranged to sandwich an active portion of the semiconductor substrate in a top view; When viewed from above, the metal layer is provided below the end of the protective film that overlaps with the diode wiring. The semiconductor device according to claim 1 .

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