Light detection device and electronic appliance

Abstract

To provide a light detection device in which the decrease in image quality is suppressed.SOLUTION: A light detection device includes a first semiconductor layer including a plurality of photoelectric conversion regions and charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions, a first wiring layer having one surface in contact with the first semiconductor layer, a second semiconductor layer having a transistor of a readout circuit electrically connected to the charge accumulation region provided therein and being in contact with the other surface of the first wiring layer, a second wiring layer having one surface in contact with the second semiconductor layer, a third semiconductor layer having a transistor provided therein and being in contact with the other surface of the second wiring layer, a signal line electrically connecting the charge accumulation region and the readout circuit, and a connection conductor extending along a depth direction and having a first end part existing closer to the third semiconductor layer present in the second wiring layer. The numbers of signal lines and connection conductors are respectively more than one. The connection conductors are disposed evenly for the respective signal lines.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and an electronic device, and in particular to a photodetector and an electronic device having a stacked structure. [Background technology]

[0002] To reduce the circuit scale and area per semiconductor substrate, image sensors have been developed that stack a light-receiving substrate and multiple circuit substrates. In such image sensors, electrode pads for bonding and electrical continuity and dummy pads for improving bonding strength are placed at the interface between the substrates. Multiple substrates are connected to the electrode pads through vias, which can act as a path for hydrogen absorbed in the circuit substrate to move to the light-receiving substrate, resulting in a decrease in image quality near the electrode pads. Uneven hydrogen supply within the pixel region can cause differences in the dark current of the charge storage region within the pixel region.

[0003] Patent Document 1 proposes a method of connecting dummy pads for improving bonding strength to parts of the wiring layers of each substrate with vias in order to prevent the amount of hydrogen supplied from the bonding interface from becoming uneven. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-145427 Summary of the Invention [Problem to be solved by the invention]

[0005] The present technology aims to provide a photodetector and electronic device in which degradation of image quality is suppressed. [Means for solving the problem]

[0006] a third semiconductor layer having a transistor and contacting the other surface of the second wiring layer; a signal line electrically connecting the charge accumulation region and the readout circuit; and a connection conductor extending in a depth direction and having a first end located within the second wiring layer and closer to the third semiconductor layer, wherein the signal line and the connection conductor are provided in a plurality of signal lines and a plurality of connection conductors, and the connection conductors are provided in a plurality of signal lines and are evenly arranged with respect to each of the plurality of signal lines.

[0007] A photodetector according to another aspect of the present technology includes a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions, a first wiring layer having one surface in contact with the first semiconductor layer, a second semiconductor layer provided with transistors of a readout circuit electrically connected to the charge accumulation regions and in contact with the other surface of the first wiring layer, the second wiring layer having one surface in contact with the second semiconductor layer, a third semiconductor layer provided with transistors and in contact with the other surface of the second wiring layer, and a third semiconductor layer having a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions. a signal line electrically connecting to a readout circuit; a connection conductor extending in the depth direction and having a first end located in the second wiring layer near the third semiconductor layer; and a wiring set including at least one of horizontal wires spaced apart along the row direction and horizontal wires spaced apart along the column direction at the same depth position, wherein a plurality of the signal lines and a plurality of the connection conductors are provided, and the horizontal wires included in the wiring set are evenly arranged with respect to each of the plurality of signal lines, and the connection conductor is connected to the wiring set.

[0008] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a chip layout diagram showing an example of a configuration of a photodetector according to a first embodiment of the present technology. [Figure 2] 1 is a block diagram showing an example of the configuration of a photodetector according to a first embodiment of the present technology; [Figure 3] 1 is an equivalent circuit diagram of a pixel of a photodetector according to a first embodiment of the present technology. [Figure 4] 1 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first embodiment of the present technology. [Figure 5] 3 is an explanatory diagram showing the positional relationship in plan view of signal lines and connecting conductors included in the photodetector according to the first embodiment of the present technology; FIG. [Figure 6] 3 is an explanatory diagram showing the positional relationship in plan view of signal lines and connecting conductors included in the photodetector according to the first embodiment of the present technology; FIG. [Figure 7] 3 is an explanatory diagram showing the positional relationship in plan view of signal lines and connecting conductors included in the photodetector according to the first embodiment of the present technology; FIG. [Figure 8] 1 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first modified example of the first embodiment of the present technology. [Figure 9] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second modification of the first embodiment of the present technology. FIG. [Figure 10] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a third modification of the first embodiment of the present technology. FIG. [Figure 11] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second embodiment of the present technology. FIG. [Figure 12] 10 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a second embodiment of the present technology. FIG. [Figure 13] 10 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a second embodiment of the present technology. FIG. [Figure 14] 10 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a second embodiment of the present technology. FIG. [Figure 15] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a first modified example of the second embodiment of the present technology. FIG. [Figure 16] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a second modification of the second embodiment of the present technology. FIG. [Figure 17] 13 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a third modification of the second embodiment of the present technology. FIG. [Figure 18] 13 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a third modification of the second embodiment of the present technology. FIG. [Figure 19] 13 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a third modification of the second embodiment of the present technology. FIG. [Figure 20] 13 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a third modification of the second embodiment of the present technology. FIG. [Figure 21] 10 is a longitudinal cross-sectional view showing a cross-sectional configuration of a pixel included in a photodetector according to a fourth modified example of the second embodiment of the present technology. FIG. [Figure 22] 13 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a fourth modified example of the second embodiment of the present technology. FIG. [Figure 23] 13 is an explanatory diagram showing the positional relationship in plan view of signal lines, connecting conductors, and wiring sets included in a photodetector according to a fourth modified example of the second embodiment of the present technology. FIG. [Figure 24] FIG. 1 is a block diagram illustrating an example of a schematic configuration of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0011] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0012] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] Furthermore, semiconductors have conductivity types such as n-type, p-type, and i-type. In the following description, a semiconductor region described as n-type corresponds to a semiconductor region of a first conductivity type, and a semiconductor region described as p-type corresponds to a semiconductor region of a second conductivity type. However, the present technology is not limited to this, and a semiconductor region described as p-type may correspond to a semiconductor region of the first conductivity type, and a semiconductor region described as n-type may correspond to a semiconductor region of the second conductivity type. It is sufficient that the first conductivity type and the second conductivity type are different from each other.

[0015] The explanation will be given in the following order. 1. First embodiment 2. Second embodiment 2. Third embodiment Application examples for electronic devices

[0016] [First embodiment] In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0017] <Overall configuration of the photodetector> First, the overall configuration of the photodetector 1 will be described. As shown in Fig. 1, the photodetector 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in plan. That is, the photodetector 1 is mounted on the semiconductor chip 2. As shown in Fig. 24, the photodetector 1 takes in image light (incident light 106) from an object via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the signal as a pixel signal.

[0018] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes a square pixel region 2A located in the center of a two-dimensional plane including an X direction and a Y direction that intersect with each other, and a peripheral region 2B located outside the pixel region 2A so as to surround the pixel region 2A.

[0019] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 24. In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other on the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction, depth direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0020] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0021] <Logic circuit> 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured with a CMOS (Complenentary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0022] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0023] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to the pixels. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0024] The horizontal drive circuit 6 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0025] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signals. Examples of signal processing that can be used include buffering, black level adjustment, column variation correction, and various types of digital signal processing.

[0026] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0027] <pixel> 3 is an equivalent circuit diagram showing an example of the configuration of pixel 3. Pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by this photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by this photoelectric conversion element PD to the charge accumulation region FD. Pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0028] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0029] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor driving line among the pixel driving lines 10 (see FIG. 2).

[0030] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0031] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, such as an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are configured as MOSFETs having, for example, a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. These transistors may also be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride film (Si3N4 film) or a stacked film of a silicon nitride film, a silicon oxide film, or the like.

[0032] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0033] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0034] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0035] <<Specific configuration of the photodetector>> Next, a specific configuration of the photodetector 1 will be described with reference to Figures 4 and 5. Note that illustrations of barrier metal layers, gate insulating films of transistors, and the like may be omitted.

[0036] <Layer structure of photodetector> The photodetector 1 (semiconductor chip 2) has a layered structure in which a first substrate A, a second substrate B, and a third substrate C are layered in that order along the depth direction. The first substrate A is a light-receiving substrate having a photoelectric conversion region 21, a charge accumulation region 22, and a transfer transistor TR (not shown), and has a layered structure in which a first semiconductor layer 20 and a wiring layer 30A are layered along the depth direction. The second substrate B is a circuit board on which, for example, a readout circuit 15 is configured, and has a layered structure in which a wiring layer 30B, a second semiconductor layer 40, and a wiring layer 50B are layered along the depth direction in that order. The third substrate C is a circuit board on which, for example, a logic circuit 13 or other circuit is configured, and has a layered structure in which a wiring layer 50C and a third semiconductor layer 60 are layered along the depth direction. The circuit configured on the third substrate C may be a circuit other than the logic circuit 13, such as a memory circuit. The first substrate A and the second substrate B are stacked so that the element forming surfaces of the semiconductor layers face each other (face to face). Transistors included in circuits configured in the substrate C, such as the logic circuit 13, are configured in the third semiconductor layer 60. Wiring included in circuits configured in the substrate C, such as the logic circuit 13, is mainly routed within the wiring layer 50C.

[0037] Between the first semiconductor layer 20 and the second semiconductor layer 40, the wiring layer 30A and the wiring layer 30B are bonded to each other. The boundary between the wiring layer 30A and the wiring layer 30B is called a boundary J1. The wiring layer 30A and the wiring layer 30B may be collectively referred to as the first wiring layer 30. The wiring layer 30A may be called the first layer, and the wiring layer 30B may be called the second layer. Between the second semiconductor layer 40 and the third semiconductor layer 60, the wiring layer 50B and the wiring layer 50C are bonded to each other. The boundary between the wiring layer 50B and the wiring layer 50C is called a boundary J2. The wiring layer 50B and the wiring layer 50C may be collectively referred to as the second wiring layer 50. The wiring layer 50B may be called the third layer, and the wiring layer 50C may be called the fourth layer.

[0038] <First semiconductor layer> The first semiconductor layer 20 is made of a semiconductor substrate. The first semiconductor layer 20 is made of, for example, a single-crystal silicon (Si) substrate, although not limited thereto. One surface of the first semiconductor layer 20 is a first surface S1, and the other surface is a second surface S2. The first surface S1 is sometimes referred to as a light incident surface or a back surface, and the second surface S2 is sometimes referred to as an element formation surface or a main surface. As shown in FIG. 1, a portion of the first semiconductor layer 20 corresponding to the pixel region 2A is provided with a plurality of cell regions 20a arranged in a matrix along the row and column directions in a plan view. The first semiconductor layer 20 is provided with a cell region 20a for each pixel 3. As shown in FIG. 4, the first semiconductor layer 20 is provided with, for example, an island-shaped cell region 20a partitioned by an isolation region 20b for each pixel 3.

[0039] The photoelectric conversion element PD, transfer transistor TR, and charge accumulation region FD shown in FIG. 3 are configured in the first semiconductor layer 20. More specifically, the photoelectric conversion element PD, transfer transistor TR, and charge accumulation region FD shown in FIG. 3 are configured in each cell region 20a in the first semiconductor layer 20. Note that the transfer transistor TR is not shown in FIG. 4. The cell region 20a includes, for example, a photoelectric conversion region 21 which is an n-type semiconductor region, and a charge accumulation region 22 which is an n+-type semiconductor region. The photoelectric conversion element PD is configured in a region including the photoelectric conversion region 21 in the cell region 20a. The charge accumulation region FD is configured as the charge accumulation region 22 in the cell region 20a.

[0040] The isolation region 20b is provided with an isolation structure that separates the cell regions 20a from each other. For example, the isolation region 20b is provided with a trench isolation structure in which a known isolation material is buried in a trench provided in the depth direction.

[0041] <Second semiconductor layer> The second semiconductor layer 40 is made of a semiconductor substrate. The second semiconductor layer 40 is made of, for example, a single-crystal silicon (Si) substrate, although not limited thereto. One surface of the second semiconductor layer 40 is a third surface S3, and the other surface is a fourth surface S4. The third surface S3 is sometimes called the element formation surface or main surface, and the fourth surface S4 is sometimes called the back surface. In this embodiment, the third surface S3 faces the second surface S2 of the first semiconductor layer 20. Various transistors (sometimes collectively referred to as pixel transistors) included in the readout circuit 15 shown in FIG. 3 are configured in the second semiconductor layer 40. The pixel transistors are, for example, provided in a portion of the second semiconductor layer 40 corresponding to the pixel region 2A, although not limited thereto. The pixel transistors are provided in a position in the second semiconductor layer 40 closer to the third surface S3 (element formation surface) in the depth direction. Therefore, gate electrodes of the pixel transistors are provided in the first wiring layer 30.

[0042] The photodetector 1 has a plurality of through conductors TSVs provided so as to penetrate the second semiconductor layer 40. The through conductors TSVs and the second semiconductor layer 40 are insulated from each other by an insulating film.

[0043] <Third semiconductor layer> The third semiconductor layer 60 shown in FIG. 4 is made of a semiconductor substrate. The third semiconductor layer 60 is made of, for example, a single-crystal silicon (Si) substrate, although not limited thereto. One surface of the third semiconductor layer 60 is a fifth surface S5 (element formation surface or main surface), and the other surface is a back surface. In this embodiment, the fifth surface S5 faces the fourth surface S4 of the second semiconductor layer 40. Various transistors included in the logic circuit 13 shown in FIG. 2 are configured in the third semiconductor layer 60.

[0044] <1st wiring layer> The first wiring layer 30 is a multi-layer wiring layer provided in the depth direction from the second surface S2 of the first semiconductor layer 20 to the third surface S3 of the second semiconductor layer 40. The first wiring layer 30 is formed by bonding together a wiring layer 30A stacked on the first semiconductor layer 20 and a wiring layer 30B stacked on the third surface S3 of the second semiconductor layer 40. The first wiring layer 30 includes, but is not limited to, a plurality of insulating films 31, wirings 32, pairs of connection pads 33 and 34, and vias 35. The insulating film 31 is made of a known insulating material. The wirings 32, the pair of connection pads 33 and 34, and the vias 35 are made of known conductive materials.

[0045] Materials constituting the insulating film 31 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride (SiON), and the like. The insulating film 31 may have a layered structure in which a plurality of insulating films are stacked. The wiring 32 is a horizontal wiring that extends mainly in the horizontal direction (the direction perpendicular to the depth direction). A plurality of layers of the wiring 32 are provided in the depth direction via the insulating film 31. Materials constituting the wiring 32 include, but are not limited to, metal materials such as copper (Cu) and aluminum (Al), and semiconductor materials (polysilicon) that have been made conductive by ion implantation of impurities.

[0046] The connection pads 33, 34 are bonded to each other along the depth direction at the boundary J1. Bonding the connection pads 33, 34 electrically connects the wiring 32 or via 35 provided in the wiring layer 30A to the wiring 32 or via 35 provided in the wiring layer 30B. The connection pad 33 is provided in the wiring layer 30A, and its surface closer to the second semiconductor layer 40 is connected to the connection pad 34 at the boundary J1. The connection pad 34 is provided in the wiring layer 30B, and its surface closer to the first semiconductor layer 20 is connected to the connection pad 33 at the boundary J1. Materials constituting the connection pads 33, 34 include, but are not limited to, metal materials such as copper (Cu) and aluminum (Al). The via 35 is a vertical wiring that extends mainly along the depth direction. The via 35 connects, for example, between the wirings 32, between the wiring 32 and the semiconductor layer, between the wiring 32 and the connection pads 33, 34, etc. The material for forming the via 35 is not limited to, but may be, for example, a metal material such as copper (Cu), aluminum (Al), or tungsten (W).

[0047] <Second wiring layer> The second wiring layer 50 is a multi-layer wiring layer provided in the depth direction from the fourth surface S4 of the second semiconductor layer 40 to the fifth surface S5 of the third semiconductor layer 60. The second wiring layer 50 is formed by bonding together a wiring layer 50B stacked on the fourth surface S4 of the second semiconductor layer 40 and a wiring layer 50C stacked on the third semiconductor layer 60. The second wiring layer 50 includes, but is not limited to, a plurality of insulating films 51, wirings 52, pairs of connection pads 53 and 54, and vias 55. The insulating film 51 is made of a known insulating material. The wirings 52, the pair of connection pads 53 and 54, and the vias 55 are made of known conductive materials.

[0048] Materials constituting the insulating film 51 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride (SiON), and the like. The insulating film 51 may have a layered structure in which a plurality of insulating films are stacked. The wiring 52 is a horizontal wiring that extends mainly in the horizontal direction (direction perpendicular to the depth direction). The wiring 52 is provided in multiple layers in the depth direction with the insulating film 51 interposed therebetween. Materials constituting the wiring 52 include, but are not limited to, metal materials such as copper (Cu) and aluminum (Al), and semiconductor materials (polysilicon) that have been made conductive by ion implantation of impurities.

[0049] The connection pads 53 and 54 are bonded to each other along the depth direction at the boundary J2. Bonding the connection pads 53 and 54 electrically connects the wiring 52 or via 55 provided in the wiring layer 50B to the wiring 52 or via 55 provided in the wiring layer 50C. The connection pad 53 is provided in the wiring layer 50B, and its surface closer to the third semiconductor layer 60 is connected to the connection pad 54 at the boundary J2. The connection pad 54 is provided in the wiring layer 50C, and its surface closer to the second semiconductor layer 40 is connected to the connection pad 53 at the boundary J2. The connection pads 53 and 54 may be made of, but are not limited to, metal materials such as copper (Cu) and aluminum (Al). The via 55 is a vertical wiring that extends mainly along the depth direction. The via 55 connects, for example, between the wirings 52, between the wiring 52 and the semiconductor layer, or between the wiring 52 and the connection pads 53 and 54. The material for forming the via 55 is not limited to, but may be, for example, a metal material such as copper (Cu), aluminum (Al), or tungsten (W).

[0050] A large number of wires 52 are provided in the second wiring layer 50. Of the wiring layer 50B and the wiring layer 50C of the second wiring layer 50, a large number of wires 52 are provided in the wiring layer 50C in particular. The wiring layer 50C contains wiring for the logic circuit 13, and therefore the number of wires provided in the wiring layer 50C is greater than in the other wiring layers (the first wiring layer and the wiring layer 50B). Because the number of wires provided in the wiring layer 50C is large, the amount of hydrogen elements or hydrogen ions (hereinafter simply referred to as hydrogen) contained in the wiring layer 50C is greater than in the other wiring layers (the first wiring layer and the wiring layer 50B).

[0051] <Signal line> The photodetector 1 has a plurality of signal lines 70 shown in FIGS. 3 and 4 in the pixel region 2A. As shown in the equivalent circuit diagram of FIG. 3, the signal line 70 is a wiring that electrically connects the charge accumulation region FD and the readout circuit 15. More specifically, the signal line 70 is a wiring that electrically connects the charge accumulation region FD and the gate electrode of the amplification transistor AMP. The signal line 70 is routed within the photodetector 1, for example, as shown in FIG. 4. More specifically, the signal line 70 is routed along the depth direction so as to electrically connect the charge accumulation region 22 provided in the first semiconductor layer 20 as the charge accumulation region FD to the pixel transistor provided in the second semiconductor layer 40 as the readout circuit 15. In this embodiment, the signal line 70 is provided across the wiring layer 30A and the wiring layer 30B. The signal line 70 includes a wiring 32, a pair of connection pads 33 and 34, a via 35, and the like provided in the wiring layer 30A and the wiring layer 30B. The readout circuit 15 to which the signal line 70 is connected is provided along the surface (third surface S3) of the second semiconductor layer 40 facing the first semiconductor layer 20, and therefore the signal line 70 does not include a through conductor TSV. As shown in FIG. 5, the signal lines 70 are arranged side by side along the row and column directions in a plan view. More specifically, the signal lines 70 are arranged side by side at regular intervals along the row and column directions in a plan view. Note that FIG. 5 also shows the vias 35 and connection pads 33 and 34 that the signal line 70 has.

[0052] <Connecting conductor> The photodetector 1 has a plurality of connection conductors 80 shown in FIGS. 4 and 5 in the pixel region 2A. The connection conductors 80 function as paths through which hydrogen contained inside the photodetector 1 can move. The connection conductors 80 are electrically floating and are not used to transmit electrical signals. The connection conductors 80 extend in the depth direction. In this embodiment, the connection conductors 80 are provided from the first wiring layer 30 to the second wiring layer 50. More specifically, the connection conductors 80 are provided from the wiring layer 30A to the wiring layer 50C. The connection conductors 80 include through conductors TSV that penetrate the second semiconductor layer. The connection conductors 80 are provided from the first wiring layer 30 to the second wiring layer 50 via the through conductors TSV. More specifically, the connection conductor 80 includes a wiring 32, a pair of connection pads 33, 34, a via 35, etc. provided in the first wiring layer 30, a through conductor TSV, and a wiring 52, a pair of connection pads 53, 54, and a via 55, etc. provided in the second wiring layer 50.

[0053] Of the two ends of the connection conductor 80 in the depth direction, the one located closer to the third semiconductor layer 60 is referred to as the first end 80a, and the one located closer to the first semiconductor layer 20 is referred to as the second end 80b. The first end 80a is located in the second wiring layer 50. More specifically, the first end 80a is located in the wiring layer 50C. The second end 80b is located in the first wiring layer 30. More specifically, the second end 80b is located in the wiring layer 30A. The second end 80b is located between both ends of the signal line 70 in the depth direction. The connection conductor 80 is a conductor that connects the second wiring layer 50 and the first wiring layer 30. More specifically, the connection conductor 80 is a connection conductor that connects the wiring layer 50C and the wiring layer 30A.

[0054] Hydrogen contained in the wiring layer 50C is absorbed into the connection conductor 80, for example, from the first end 80a. The hydrogen absorbed into the connection conductor 80 can move within the connection conductor 80, and at least a portion of the absorbed hydrogen can move within the connection conductor 80 along the depth direction and reach the second end 80b. Furthermore, the hydrogen absorbed into the connection conductor 80 can exit the connection conductor 80. At least a portion of the hydrogen that migrates from the portion of the connection conductor 80 located within the wiring layer 30A, including the second end 80b, to the surrounding wiring layer 30A moves through the insulating film 31, the wiring 32, the via 35, and other parts of the wiring layer 30A, and is absorbed into the signal line 70. The signal line 70 is connected to the charge accumulation region 22, which is most susceptible to hydrogen. At least a portion of the hydrogen absorbed into the signal line 70 is supplied to the charge accumulation region 22.

[0055] FIG. 5 shows the positional relationship between the signal lines 70 and the connection conductors 80 in a plan view. Note that FIG. 5 illustrates the connection conductors 80 as through conductors TSVs that the connection conductors 80 have. The connection conductors 80 are arranged around the signal lines 70 in a plan view and are positioned so as not to overlap the signal lines 70. More specifically, the connection conductors 80 are evenly spaced relative to each of the multiple signal lines 70. More specifically, the same number of connection conductors 80 are provided for each of the signal lines 70, with a first distance d between them. In the example shown in FIG. 5, four connection conductors 80 are provided for each of the signal lines 70, with a first distance d between them. Note that the first distance d may be the distance to the connection conductor 80 closest to a signal line 70. Also, in the example shown in FIG. 5, the connection conductors 80 are arranged side by side in the row and column directions at the same intervals as the signal lines 70. By arranging the connection conductors 80 evenly for each of the plurality of signal lines 70, it is possible to prevent the difference in the amount of hydrogen supplied between one signal line 70 and another signal line 70 from becoming too large.

[0056] <<Major Effects of the First Embodiment>> Below, we will explain the main effects of the first embodiment, but first we will provide an overview. If there is a large imbalance in the amount of hydrogen supplied within the surface of the pixel region 2A (FIG. 1), shading may occur in the generated image.

[0057] In contrast, the photodetector 1 according to the first embodiment of the present technology includes signal lines 70 that electrically connect the charge accumulation region 22 and the readout circuit 15, and connecting conductors 80 that extend in the depth direction and have first ends 80a located in the second wiring layer 50 and closer to the third semiconductor layer 60, and the connecting conductors 80 are evenly arranged with respect to each of the multiple signal lines 70. Therefore, hydrogen contained in a relatively large amount in the second wiring layer 50 can be supplied to the periphery of the signal lines 70 via the connecting conductors 80. Furthermore, since such connecting conductors 80 are evenly arranged with respect to each of the multiple signal lines 70, it is possible to prevent the difference in the amount of hydrogen absorbed into one signal line 70 from becoming too large between one signal line 70 and another signal line 70.

[0058] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the connection conductor 80 is located at a position that does not overlap with the signal line 70 in a plan view. Furthermore, the connection conductor 80 is in an electrically floating state. Therefore, the connection conductor 80, which serves as a path for hydrogen, can be provided without being restricted by the routing of wiring in the circuit of the photodetector 1.

[0059] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, at least one of the signal line 70 and the connecting conductor 80 includes a through conductor TSV that penetrates the second semiconductor layer 40, and the second end 80b of the connecting conductor 80, which is located closer to the first semiconductor layer 20, is located between both ends of the signal line 70 in the depth direction. Since a portion of the connecting conductor 80 is adjacent to the signal line 70 in the depth direction, hydrogen can move laterally from the connecting conductor 80 toward the signal line 70. This allows hydrogen to be efficiently supplied to the signal line 70.

[0060] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the connection conductor 80 includes a through conductor TSV that penetrates the second semiconductor layer 40, and a second end 80b of the connection conductor 80 is located in the first wiring layer 30 that is in contact with the first semiconductor layer 20. More specifically, the second end 80b is located in the wiring layer 30A that is closest to the first semiconductor layer 20. Because the connection conductor 80 has a through via TSV, the path of hydrogen is not blocked by the second semiconductor layer 40. Furthermore, since the charge accumulation region 22 is the region of the photodetector 1 that is most susceptible to the effects of hydrogen, extending the connection conductor 80 close to the charge accumulation region 22 allows hydrogen to be efficiently supplied to the charge accumulation region 22.

[0061] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the first end 80a of the connecting conductor 80 is located in the wiring layer 50C. Since the connecting conductor 80 extends into the wiring layer 50C, which has a larger number of wires than the other wiring layers, hydrogen can be efficiently taken into the connecting conductor 80.

[0062] Furthermore, according to the photodetector 1 according to the first embodiment of the present technology, the same number of connecting conductors 80 are provided at the first distance d between each of the signal lines 70. By providing the same number of connecting conductors 80 at the same distance from each of the signal lines 70, hydrogen can be supplied evenly toward the connecting conductors 80.

[0063] Each of the connection pads 33 and 34 may be integral with a via 35 provided on the opposite side of the boundary J1. Each of the connection pads 53 and 54 may be integral with a via 55 provided on the opposite side of the boundary J2.

[0064] According to the photodetector 1 of the first embodiment described above, the first end 80a is located within the wiring layer 50C, but the present technology is not limited to this. The first end 80a may be located within the wiring layer 50B without reaching the wiring layer 50C. The wiring layer 50B is joined to the wiring layer 50C, which contains a large amount of hydrogen, and therefore can absorb hydrogen from the wiring layer 50C, which contains a large amount of hydrogen, and can supply the absorbed hydrogen to the connection conductor 80.

[0065] Furthermore, in the photodetector 1 according to the first embodiment described above, four connecting conductors 80 are provided between each of the signal lines 70 and the other signal lines 70, with the first distance d between them. However, the number of connecting conductors 80 provided between each of the signal lines 70 and the other signal lines 70 is not limited to four. For example, as shown in FIG. 6 , two connecting conductors 80 may be provided between each of the signal lines 70 and the other signal lines 70, with the first distance d between them. In the example shown in FIG. 6 , the connecting conductors 80 are arranged in rows and columns at intervals twice the intervals between the signal lines 70. Furthermore, for example, as shown in FIG. 7 , one connecting conductor 80 may be provided between each of the signal lines 70 and the other signal lines 70, with the first distance d between them. In the example shown in FIG. 7 , one connecting conductor 80 is provided between four signal lines 70 arranged in two rows and two columns.

[0066] <<Modification of the First Embodiment>> A modification of the first embodiment will be described below.

[0067] <Variation 1> 8, in the photodetector 1 according to the first modification of the first embodiment, the second end 80b does not reach the wiring layer 30A but is located within the wiring layer 30B. Although the distance from the charge accumulation region 22 to the second end 80b is greater in this modification than in the first embodiment, the second end 80b is located closer to the first semiconductor layer 20 than to the second semiconductor layer 40, which is advantageous for supplying hydrogen. Even if the second end 80b is located within the wiring layer 30B, the connection conductor 80 has a through-via TSV that penetrates the second semiconductor layer 40, so the path of hydrogen is not blocked by the second semiconductor layer 40.

[0068] The photodetector 1 according to the first modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0069] <Variation 2> In the photodetector 1 according to the second modification of the first embodiment, as shown in FIG. 9 , the element formation surface (second surface S2) of the first semiconductor layer 20 and the back surface (fourth surface S4) of the second semiconductor layer 40 are stacked face to back. In this modification, the wiring layer stacked on the fourth surface S4 of the second substrate B is referred to as the wiring layer 30B, and the wiring layer stacked on the third surface S3 is referred to as the wiring layer 50B. The first wiring layer 30 is formed by bonding together the wiring layer 30A stacked on the first semiconductor layer 20 and the wiring layer 30B stacked on the fourth surface S4 of the second semiconductor layer 40. The second wiring layer 50 is formed by bonding together the wiring layer 50B stacked on the third surface S3 of the second semiconductor layer 40 and the wiring layer 50C stacked on the third semiconductor layer 60.

[0070] In this modification, the pixel transistors of the readout circuit 15 provided in the second semiconductor layer 40 are located on the third semiconductor layer 60 side. Therefore, the signal line 70 includes a through conductor TSV that penetrates the second semiconductor layer 40 and extends into the second wiring layer 50. More specifically, the signal line 70 extends from the charge accumulation region 22 through the second semiconductor layer 40 to the wiring layer 50B of the second wiring layer 50. The connection conductor 80 includes a through conductor TSV that penetrates the second semiconductor layer 40 and extends into the first wiring layer 30. More specifically, the second end of the connection conductor 80 is located in the first wiring layer 30. Note that in this modification, the end of the signal line 70 closest to the third semiconductor layer 60 may be interpreted as the portion of the signal line 70 closest to the third semiconductor layer 60.

[0071] The photodetector 1 according to the second modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0072] According to the photodetector 1 of the second modification of the first embodiment described above, the second end 80b is located in the first wiring layer 30, but the present technology is not limited to this. The second end 80b may be located in the second wiring layer 50. More specifically, the second end 80b does not need to have a through conductor TSV that penetrates the second semiconductor layer 40, and does not need to reach the inside of the first wiring layer 30.

[0073] <Variation 3> In the photodetector 1 according to the third modification of the first embodiment, one readout circuit 15 is shared by a plurality of photoelectric conversion elements PD, as shown in Fig. 10. In this modification, as in the first embodiment, the connecting conductors 80 are evenly arranged with respect to each of the plurality of signal lines 70. The relationship between the connecting conductors 80 and the signal lines 70 is the same as that described in the first embodiment, and therefore a detailed description thereof will be omitted in this modification.

[0074] The photodetector 1 according to the third modification of the first embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0075] [Second embodiment] 11 and 12, a photodetector 1 according to a second embodiment of the present technology will be described. The description of this embodiment will focus on differences from the first embodiment. The photodetector 1 according to this embodiment has a wiring set 90 electrically connected to a connecting conductor 80.

[0076] <Wiring assembly> As shown in FIG. 12 , the wiring set 90 includes horizontal wirings 90a and horizontal wirings 90b. The horizontal wirings 90a are arranged at intervals along the row direction in a plan view. More specifically, the horizontal wirings 90a are arranged at equal intervals along the row direction. All of the horizontal wirings 90a are arranged at the same position in the depth direction. The horizontal wirings 90b are arranged at intervals along the column direction in a plan view. More specifically, the horizontal wirings 90b are arranged at equal intervals along the column direction. All of the horizontal wirings 90b are arranged at the same position in the depth direction. The horizontal wirings 90a and 90b included in the wiring set 90 are evenly arranged with respect to each of the multiple signal lines 70. Furthermore, the horizontal wirings 90a and 90b are all arranged at the same position in the depth direction. The horizontal wirings 90a and 90b are connected to each other at their intersecting positions, and the wiring set 90 has a lattice pattern. The wiring set 90 is provided at a position overlapping the pixel region 2A in a plan view. The wiring set 90 is arranged to partition the periphery of the signal line 70 in a plan view. Each of the multiple signal lines 70 is surrounded by horizontal wirings 90a and 90b. As shown in FIG. 11 , the connection conductor 80 is connected to the wiring set 90, and at least a portion of the hydrogen in the connection conductor 80 can move into the wiring set 90. Hydrogen is supplied to the periphery of the signal line 70 from both the connection conductor 80 and the wiring set 90.

[0077] The wiring set 90 is provided in the first wiring layer 30. More specifically, the wiring set 90 is provided in the wiring layer 30A, and is located closer to the first semiconductor layer 20 in the depth direction than the connection pads 33 and 34. Furthermore, the connection conductor 80 and the wiring set 90 are in an electrically floating state and are not used for transmitting electrical signals.

[0078] As in the first embodiment, the connecting conductors 80 are arranged evenly relative to the plurality of signal lines 70. The positional relationship between the signal lines 70 and the connecting conductors 80 may be as shown in Fig. 12. Note that the positional relationship between the signal lines 70 and the connecting conductors 80 shown in Fig. 12 is the same as the positional relationship between the signal lines 70 and the connecting conductors 80 shown in Fig. 5 of the first embodiment.

[0079] <<Major Effects of the Second Embodiment>> The main effects of the second embodiment will be described below. The photodetector 1 according to the second embodiment also provides the same effects as the photodetector 1 according to the first embodiment described above.

[0080] Furthermore, the photodetector 1 according to the second embodiment described above includes a wiring set 90 including at least one of horizontal wirings 90a spaced apart along the row direction and horizontal wirings 90b spaced apart along the column direction at the same depth position, and the horizontal wirings 90a, 90b included in the wiring set 90 are evenly arranged relative to each of the multiple signal lines 70, and the connecting conductor 80 is connected to the wiring set 90. Since the horizontal wirings 90a, 90b included in the wiring set 90 are evenly arranged relative to each of the multiple signal lines 70, it is possible to prevent the difference in the amount of hydrogen absorbed into one signal line 70 from becoming too large between one signal line 70 and another signal line 70.

[0081] Furthermore, in the photodetector 1 according to the second embodiment, hydrogen is transferred through the connecting conductor 80 toward the first semiconductor layer 20 in the depth direction, and through the wiring set 90 in a direction perpendicular to the depth direction. Therefore, the wiring set 90 can be used to assist the transfer of hydrogen, allowing hydrogen to be efficiently supplied to the charge accumulation region 22. More specifically, the wiring set 90 can be used to assist the lateral transfer of hydrogen, allowing hydrogen to be efficiently supplied to the charge accumulation region 22. Furthermore, experimental results have shown that the transfer rate of hydrogen is faster in metal wiring than in silicon. Therefore, providing the wiring set 90 can assist the transfer of hydrogen, allowing hydrogen to be efficiently supplied to the charge accumulation region 22.

[0082] Furthermore, in the photodetector 1 according to the second embodiment, the wiring set 90 has a lattice shape including both horizontal wirings 90a spaced apart along the row direction and horizontal wirings 90b spaced apart along the column direction, and each of the signal lines 70 is surrounded by the horizontal wirings 90a and 90b. Therefore, by using the lattice-shaped wiring set 90, hydrogen can be supplied to all four sides of the signal line 70, and hydrogen can be efficiently supplied to the charge accumulation region 22.

[0083] Furthermore, in the photodetector 1 according to the second embodiment described above, the wiring set 90 is provided in the first wiring layer 30 that is in contact with the first semiconductor layer 20. By providing the wiring set 90 in the first wiring layer 30 close to the charge accumulation region 22, hydrogen can be efficiently supplied to the charge accumulation region 22.

[0084] In the photodetector 1 according to the second embodiment, the wiring set 90 includes both the horizontal wirings 90a spaced apart along the row direction and the horizontal wirings 90b spaced apart along the column direction. However, the present technology is not limited to this. The wiring set 90 may include only one of the horizontal wirings 90a and 90b. Even when the wiring set 90 includes only one of the horizontal wirings 90a and 90b, hydrogen can be transported through the wiring set 90 in a direction perpendicular to the depth direction.

[0085] Furthermore, the positional relationship between the signal line 70 and the connecting conductor 80 is not limited to the positional relationship shown in Fig. 12 and may be the positional relationship shown in Fig. 13 or the positional relationship shown in Fig. 14. The positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 13 is similar to the positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 6 of the first embodiment. The positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 14 is similar to the positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 7 of the first embodiment.

[0086] <Modification of the Second Embodiment> A modification of the second embodiment will be described below.

[0087] <Variation 1> 15, in the photodetector 1 according to the first modification of the second embodiment, the wiring set 90 is provided at the same position in the depth direction as the connection pads 33 and 34. In this way, the position in the depth direction at which the wiring set 90 is provided may be any position as long as it is within the first wiring layer 30, and is not limited to the second embodiment described above.

[0088] The photodetector 1 according to the first modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0089] <Variation 2> In the photodetector 1 according to the second modification of the second embodiment, as shown in FIG. 16, a plurality of wiring sets 90 are provided in the first wiring layer 30 along the depth direction.

[0090] The photodetector 1 according to the second modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0091] <Variation 3> 17 and 18, in the photodetector 1 according to the third modification of the second embodiment, the horizontal wires 90a and 90b included in the wiring set 90 may be interrupted midway. Because hydrogen can move within silicon and insulating films, even if the horizontal wires 90a and 90b are interrupted midway, hydrogen can be supplied to the periphery of the signal line 70.

[0092] The photodetector 1 according to the third modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0093] The positional relationship between the signal line 70 and the connecting conductor 80 is not limited to the positional relationship shown in Fig. 18 and may be the positional relationship shown in Fig. 19 or the positional relationship shown in Fig. 20. The positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 19 is similar to the positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 6 of the first embodiment. The positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 20 is similar to the positional relationship between the signal line 70 and the connecting conductor 80 shown in Fig. 7 of the first embodiment.

[0094] In addition, in this embodiment, both the horizontal wiring 90a and the horizontal wiring 90b are interrupted midway, but the present technology is not limited to this. The horizontal wiring 90a and the horizontal wiring 90b may be interrupted in at least one direction.

[0095] In addition, in this embodiment, the wiring set 90 includes both the horizontal wiring 90a and the horizontal wiring 90b, but it may include only one of them.

[0096] <Variation 4> 21 and 22, in the photodetector 1 according to the fourth modification of the second embodiment, the connection conductors 80 are not evenly arranged with respect to each of the signal lines 70. The multiple connection conductors 80 are arranged in a ring shape so as to surround the center of the wiring set 90 in a plan view.

[0097] FIG. 21 shows a longitudinal cross-sectional view including the pixel region 2A and the peripheral region 2B. FIG. 22 shows only a partial region of the wiring set 90, including the outermost end E. More specifically, the outermost end E of the wiring set 90 shown in FIG. 22 is a region including a corner of the wiring set 90. In FIGS. 21 and 22, the central portion of the wiring set 90 is omitted. The central portion of the wiring set 90 is located in a region overlapping with the central portion of the pixel region 2A shown in FIG. 2. As shown in FIG. 22, multiple connection conductors 80 are arranged in a ring shape, for example, in a single row, surrounding the central portion of the wiring set 90. The connection conductor 80 surrounds the central portion of the wiring set 90 and is connected to the outermost end E of the wiring set 90. More specifically, the connection conductor 80 is connected only to the horizontal wires 90a that are arranged outermost in the row direction among the multiple horizontal wires 90a. There are two horizontal wirings 90a arranged on the outermost side (only one is shown in FIG. 22), and these two horizontal wirings 90a are referred to as horizontal wirings 91a to distinguish them from the other horizontal wirings 90a. When there is no need to distinguish between the horizontal wirings 91a and 90a, they are simply referred to as horizontal wirings 90a. Furthermore, the connection conductor 80 is connected to only the horizontal wiring 90b arranged on the outermost side in the column direction among the multiple horizontal wirings 90b. There are two horizontal wirings 90b arranged on the outermost side (only one is shown in FIG. 22), and these two horizontal wirings 90b are simply referred to as horizontal wirings 91b to distinguish them from the other horizontal wirings 90b. When there is no need to distinguish between the horizontal wirings 91b and 90b, they are simply referred to as horizontal wirings 90b. In this way, the outermost peripheral end E includes the horizontal wirings 91a and 91b.

[0098] 22, the connecting conductors 80 are arranged next to the horizontal wirings 91a and 91b at the same intervals as the signal lines 70. As shown in FIG. 21, the connecting conductors 80 are provided in the wiring set 90 at positions closer to the peripheral region 2B.

[0099] The photodetector 1 according to the fourth modification of the second embodiment also provides the same effects as the photodetector 1 according to the second embodiment described above.

[0100] Furthermore, in the photodetector 1 according to the fourth modification of the second embodiment, the connecting conductors 80 are arranged in a ring shape so as to surround the center of the wiring set 90 in a plan view, and hydrogen is supplied to the region where the connecting conductors 80 are not provided using the wiring set 90. Therefore, even if it is difficult to provide the connecting conductors 80 uniformly over the entire surface of the pixel region 2A, it is possible to prevent the difference in the amount of hydrogen supplied between one signal line 70 and another signal line 70 from becoming too large. For example, if the second substrate B is a substrate on which the logic circuit 13 is configured, the connecting conductors 80 can be arranged so as not to interfere with the logic circuit 13.

[0101] Furthermore, in the photodetector 1 according to the fourth modification of the second embodiment, the connecting conductor 80 is connected to the outermost peripheral end E of the wiring set 90. Therefore, the connecting conductor 80 can be arranged so as to avoid interference with the second substrate B.

[0102] When the wiring set 90 includes only one of the horizontal wiring 90a and the horizontal wiring 90b, the outermost end E may include an end of one of the horizontal wiring 90a and the horizontal wiring 90b. For example, when the wiring set 90 includes only the horizontal wiring 90a of the horizontal wiring 90a and the horizontal wiring 90b, the outermost end E includes the horizontal wiring 91a and an end of the horizontal wiring 90a other than the horizontal wiring 91a.

[0103] Furthermore, although the connecting conductors 80 are arranged next to the horizontal wirings 91a and 91b at the same intervals as the signal lines 70, the present technology is not limited to this. As shown in Fig. 23, the connecting conductors 80 may be arranged next to the horizontal wirings 91a and 91b at intervals that are twice the intervals between the signal lines 70. Furthermore, the connecting conductors 80 may be arranged at any intervals other than the above.

[0104] [Third embodiment] <1. Application examples to electronic devices> Next, an electronic device 100 according to a third embodiment of the present technology shown in Fig. 24 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector 1 as the solid-state imaging device 101.

[0105] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed based on the drive signals (timing signals) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0106] With this configuration, the electronic device 100 can prevent a large imbalance in the amount of hydrogen supplied within the plane of the pixel region 2A in the solid-state imaging device 101, thereby improving the image quality of the video signal.

[0107] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0108] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 according to any one of the first embodiment to the second embodiment and the modified versions of those embodiments, or a photodetector 1 according to a combination of at least two of the first embodiment to the second embodiment and the modified versions of those embodiments.

[0109] [Other embodiments] As described above, the present technology has been described by the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0110] For example, the technical concepts explained in the first to third embodiments can be combined with each other, and various combinations according to the technical concepts can be made.

[0111] Furthermore, this technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light reflected back from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until the reflected light is received. The structure of the pixel 3 described above can be adopted as the structure of this distance measurement sensor.

[0112] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, impurities, and the like.

[0113] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0114] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0115] The present technology may be configured as follows. (1) a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, The connection conductors are evenly arranged with respect to each of the plurality of signal lines. Light detection device. (2) The connection conductor is located at a position where it does not overlap the signal line in a plan view. The photodetector according to (1). (3) the connecting conductor is in an electrically floating state; The photodetector according to (1) or (2). (4) at least one of the signal line and the connection conductor includes a through conductor that penetrates the second semiconductor layer; a second end portion of the connecting conductor located closer to the first semiconductor layer is located between both end portions of the signal line along the depth direction; A photodetector according to any one of (1) to (3). (5) the connecting conductor includes the through conductor that penetrates the second semiconductor layer, the second end of the connecting conductor is located in the first wiring layer; (4) The photodetector according to (4). (6) the first wiring layer has a first layer located closer to the first semiconductor layer and a second layer located closer to the second semiconductor layer along the depth direction, the second end of the connecting conductor is located within the first layer; the connection conductor includes a pair of connection pads joined to each other along the depth direction at the boundary between the first layer and the second layer; (5) The photodetector according to (5). (7) the second wiring layer has a third layer located closer to the second semiconductor layer and a fourth layer located closer to the third semiconductor layer along the depth direction, the first end of the connecting conductor is located in the fourth layer; the connection conductor includes a pair of connection pads joined to each other along the depth direction at the boundary between the third layer and the fourth layer; A photodetector according to any one of (1) to (6). (8) the connecting conductors are provided in equal numbers for each of the signal lines and spaced a first distance apart from one another; A photodetector according to any one of (1) to (7). (9) One, two, or four of the connection conductors are provided between one of the signal lines and another of the signal lines, spaced apart by the first distance. (8) The photodetector according to (8). (10) a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; a wiring set including at least one of horizontal wirings arranged at intervals along the row direction and horizontal wirings arranged at intervals along the column direction at the same depth position; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, the horizontal wirings included in the wiring set are evenly arranged with respect to each of the plurality of signal lines, The connecting conductor is connected to the wiring set. Light detection device. (11) The connection conductors are evenly arranged with respect to each of the plurality of signal lines. The photodetector according to (10). (12) The horizontal wiring is interrupted in at least one of the row direction and the column direction. The photodetector according to (11). (13) The plurality of connection conductors are arranged in a ring shape so as to surround a central portion of the wiring set in a plan view. The photodetector according to (10). (14) The connecting conductor is connected to the outermost end of the wiring set. The photodetector according to (13). (15) the wiring set has a lattice shape including both the horizontal wirings arranged at intervals along the row direction and the horizontal wirings arranged at intervals along the column direction, Each of the plurality of signal lines is surrounded by the horizontal wiring. The photodetector according to any one of (10) to (14). (16) The wiring set is provided in the first wiring layer. The photodetector according to any one of (10) to (15). (17) The wiring set is provided in a plurality of sets along the depth direction. The photodetector according to (16). (18) The connecting conductor and the wiring set are in an electrically floating state. The photodetector according to any one of (10) to (17). (19) a light detection device; and an optical system that forms an image of image light from a subject on the light detection device, The photodetector device a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, The connection conductors are evenly arranged with respect to each of the plurality of signal lines. electronic equipment.

[0116] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0117] 1. Photodetector 13 Logic Circuits 15 Readout circuit 20 First semiconductor layer 21 Photoelectric conversion area 22,FD charge storage region 30 1st wiring layer 30A,30B,50B,50C wiring layer 32,52 Wiring 33,34,53,54 connection pads Connection Pad 40 Second semiconductor layer 50 2nd wiring layer 60 Third semiconductor layer 70 Signal Line 80 Connecting conductor 80a 1st end 80b 2nd end 90 Wiring set 90a, 90b, 91a, 91b Horizontal wiring 100 Electronic equipment 102 Optical system d First distance E Outermost edge Charge storage area J1,J2 boundary TSV through conductor

Claims

1. a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, The connection conductors are evenly arranged with respect to each of the plurality of signal lines. Light detection device.

2. The connection conductor is located at a position where it does not overlap the signal line in a plan view. The photodetector device according to claim 1 .

3. the connecting conductor is in an electrically floating state; The photodetector device according to claim 1 .

4. at least one of the signal line and the connection conductor includes a through conductor that penetrates the second semiconductor layer; a second end portion of the connecting conductor located closer to the first semiconductor layer and located between both end portions of the signal line along the depth direction; The photodetector device according to claim 1 .

5. the connecting conductor includes the through conductor that penetrates the second semiconductor layer, the second end of the connecting conductor is located in the first wiring layer; 5. The photodetector according to claim 4.

6. the first wiring layer has a first layer located closer to the first semiconductor layer and a second layer located closer to the second semiconductor layer along the depth direction; the second end of the connecting conductor is located within the first layer; the connection conductor includes a pair of connection pads joined to each other along a depth direction at a boundary between the first layer and the second layer; 6. The photodetector according to claim 5.

7. the second wiring layer has a third layer located closer to the second semiconductor layer and a fourth layer located closer to the third semiconductor layer along the depth direction, the first end of the connecting conductor is located in the fourth layer; the connection conductor includes a pair of connection pads joined to each other along a depth direction at a boundary between the third layer and the fourth layer; The photodetector device according to claim 1 .

8. the connecting conductors are provided in equal numbers for one of the signal lines and the other of the signal lines, and are spaced a first distance apart; The photodetector device according to claim 1 .

9. One, two, or four of the connection conductors are provided between one of the signal lines and another of the signal lines, the connection conductors being spaced apart by the first distance. The photodetector device according to claim 8 .

10. a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; a wiring set including at least one of horizontal wirings arranged at intervals along the row direction and horizontal wirings arranged at intervals along the column direction at the same depth position; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, the horizontal wirings included in the wiring set are evenly arranged with respect to each of the plurality of signal lines, The connecting conductor is connected to the wiring set. Light detection device.

11. The connection conductors are evenly arranged with respect to each of the plurality of signal lines. The optical detection device according to claim 10.

12. The horizontal wiring is interrupted in at least one of the row direction and the column direction. The optical detection device according to claim 11 .

13. The plurality of connection conductors are arranged in a ring shape so as to surround a central portion of the wiring set in a plan view. The optical detection device according to claim 10.

14. The connecting conductor is connected to the outermost end of the wiring set.

14. The optical detection device according to claim 13.

15. the wiring set has a lattice shape including both the horizontal wirings arranged at intervals along the row direction and the horizontal wirings arranged at intervals along the column direction, Each of the plurality of signal lines is surrounded by the horizontal wiring. The optical detection device according to claim 10.

16. The wiring set is provided in the first wiring layer. The optical detection device according to claim 10.

17. The wiring set is provided in a plurality of sets along the depth direction.

17. The optical detection device of claim 16.

18. The connecting conductor and the wiring set are in an electrically floating state. The optical detection device according to claim 10.

19. a light detection device; and an optical system that forms an image of image light from a subject on the light detection device, The photodetector device a first semiconductor layer provided with a plurality of photoelectric conversion regions and a plurality of charge accumulation regions capable of accumulating signal charges generated in the photoelectric conversion regions; a first wiring layer having one surface in contact with the first semiconductor layer; a second semiconductor layer provided with a transistor of a readout circuit electrically connected to the charge accumulation region and in contact with the other surface of the first wiring layer; a second wiring layer having one surface in contact with the second semiconductor layer; a third semiconductor layer provided with a transistor and in contact with the other surface of the second wiring layer; a signal line electrically connecting the charge storage region and the readout circuit; a connection conductor extending in a depth direction and having a first end located in the second wiring layer and positioned closer to the third semiconductor layer; Equipped with a plurality of the signal lines and a plurality of the connection conductors are provided, The connection conductors are evenly arranged with respect to each of the plurality of signal lines. electronic equipment.

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