Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing increase of a chip area.SOLUTION: A semiconductor device comprises: an inter-layer insulation film; and a plurality of resistance films arranged onto the inter-layer insulation film. Each of the plurality of resistance films is extended to a first direction along an upper surface of the plurality of resistance films in a plan view. The plurality of resistance films is along the upper surface of the plurality of resistance films in the plan view, and is arranged with an interval to a second direction orthogonal to a first direction. The plurality of resistance films is divided into a first group; a second group; and a third group. The first group is positioned between the second group and the third group to a second direction. Each second width modulation amount of the plurality of second resistance films belongs to the second group and each third width modulation amount of the plurality of third resistance films belong to the third group are larger than each first width modulation amount of the plurality of first resistance films belonged to the first group.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The semiconductor device described in Japanese Patent Laid-Open No. 2011-155192 (Patent Document 1) includes an interlayer insulating film and a plurality of resistive films. The resistive films are disposed on the interlayer insulating film. Each of the resistive films extends along a first direction. The resistive films are arranged at intervals along a second direction perpendicular to the first direction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-155192 Summary of the Invention [Problem to be solved by the invention]

[0004] The width of each of the multiple resistive films is designed to be uniform. However, it is difficult to make the width of each of the multiple resistive films uniform, and if some of the multiple resistive films have widths that do not fall within a predetermined range and are used in a circuit, the accuracy of the circuit will decrease. Therefore, it is necessary to increase the number of multiple resistive films and use resistive films with widths that do not fall within the predetermined range as dummy resistive films that are not used in the circuit, which increases the chip area. Other issues and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device disclosed herein includes an interlayer insulating film and a plurality of resistive films disposed on the interlayer insulating film. Each of the resistive films extends in a first direction along the upper surface of the interlayer insulating film in a plan view. The resistive films are arranged at intervals along the upper surface of the interlayer insulating film in a second direction perpendicular to the first direction in a plan view. The resistive films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. The second width variation of each of the second resistive films belonging to the second group and the third width variation of each of the third resistive films belonging to the third group are greater than the first width variation of each of the first resistive films belonging to the first group. The first width variation is the difference between a reference width and the width of each of the first resistive films. The second width variation is the difference between the reference width and the width of each of the second resistive films. The third width variation is the difference between the reference width and the width of each of the third resistive films. The reference width is the width of one of the plurality of resistive films located at the center in the second direction. The plurality of first resistive films are electrically connected to a first circuit group. At least some of the plurality of second resistive films and / or at least some of the plurality of third resistive films are electrically connected to a second circuit group different from the first circuit group. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to suppress an increase in chip area. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the semiconductor device DEV1. [Figure 2] FIG. 2 is a planar layout diagram of a plurality of resistive films RF in the semiconductor device DEV1. [Figure 3] FIG. 2 is a schematic block diagram of a semiconductor device DEV1. [Figure 4] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 5] FIG. 10 is a cross-sectional view illustrating a first wiring forming step S1. [Figure 6] FIG. 10 is a cross-sectional view illustrating a first interlayer insulating film forming step S2. [Figure 7]FIG. 10 is a cross-sectional view illustrating a first via hole forming step S3. [Figure 8] FIG. 10 is a cross-sectional view illustrating a first via plug forming step S4. [Figure 9] FIG. 10 is a cross-sectional view illustrating a resistive film forming step S5. [Figure 10] FIG. 10 is a cross-sectional view illustrating a second interlayer insulating film forming step S6. [Figure 11] FIG. 10 is a cross-sectional view illustrating a second via hole forming step S7. [Figure 12] FIG. 10 is a cross-sectional view illustrating a second via plug forming step S8. [Figure 13] FIG. 10 is a cross-sectional view illustrating a second wiring forming step S9. [Figure 14] FIG. 10 is a planar layout diagram of a resistive film RF in the semiconductor device DEV2. [Figure 15] FIG. 10 is a planar layout diagram of a resistive film RF in the semiconductor device DEV3. [Figure 16] FIG. 10 is a planar layout diagram of a resistive film RF in the semiconductor device DEV4. [Figure 17] FIG. 10 is a planar layout diagram of a resistive film RF in the semiconductor device DEV5. [Figure 18] FIG. 10 is a planar layout diagram of a resistive film RF in a modified example of the semiconductor device DEV5. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) A semiconductor device according to the first embodiment will be described below. The semiconductor device according to the first embodiment is referred to as semiconductor device DEV1.

[0010] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0011] FIG. 1 is a cross-sectional view of a semiconductor device DEV1. FIG. 2 is a planar layout diagram of a resistive film RF in the semiconductor device DEV1. As shown in FIGS. 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB and a plurality of interlayer insulating films ILD. The semiconductor substrate SUB is made of, for example, single crystal silicon (Si). The plurality of interlayer insulating films ILD are arranged on the semiconductor substrate SUB. Each of the plurality of interlayer insulating films ILD is made of, for example, silicon oxide (SiO2). One of the plurality of interlayer insulating films ILD is referred to as an interlayer insulating film ILD1.

[0012] The semiconductor device DEV1 has wiring WL1 and wiring WL2. The wiring WL1 and wiring WL2 are arranged on an interlayer insulating film ILD1. The wiring WL1 and wiring WL2 are formed of, for example, aluminum (Al) or an aluminum alloy. A barrier metal BM1 is arranged between the wiring WL1 and the interlayer insulating film ILD1 and between the wiring WL2 and the interlayer insulating film ILD1. A barrier metal BM2 is arranged on the wiring WL1 and on the wiring WL2. The barrier metal BM1 and the barrier metal BM2 are each made of, for example, a stacked film of a titanium nitride (TiN) film and a titanium (Ti) film.

[0013] Another one of the multiple interlayer insulating films ILD is an interlayer insulating film ILD2. The interlayer insulating film ILD2 is disposed on the interlayer insulating film ILD1 so as to cover the wiring WL1 and the wiring WL2. Via holes VH1 and VH2 are formed in the interlayer insulating film ILD2. The via holes VH1 and VH2 penetrate the interlayer insulating film ILD2 in the thickness direction. At the bottom of the via holes VH1 and VH2, a portion of the wiring WL1 and a portion of the wiring WL2 are exposed, respectively.

[0014] The semiconductor device DEV1 has a via plug VP1 and a via plug VP2. The via plug VP1 and the via plug VP2 are buried in a via hole VH1 and a via hole VH2, respectively. The via plug VP1 and the via plug VP2 are formed of, for example, tungsten (W). The lower end of the via plug VP1 is electrically connected to a wiring WL1. The lower end of the via plug VP2 is electrically connected to a wiring WL2.

[0015] The semiconductor device DEV1 has a plurality of resistive films RF. The resistive films RF are disposed on an interlayer insulating film ILD2. The resistive films RF are formed of a conductive material. The resistive films RF are preferably formed of a material containing at least one selected from the group consisting of silicon chromium (SiCr), silicon chromium doped with carbon (C), nickel chromium (NiCr), titanium nitride, and tantalum nitride (TaN). However, the resistive films RF may be formed of other conductive materials (e.g., polycrystalline silicon).

[0016] The resistive film RF is electrically connected to the upper ends of the via plugs VP1 and VP2. As a result, the resistive film RF is electrically connected to the wirings WL1 and WL2. The semiconductor device DEV1 may have a plurality of insulating films IF. The insulating film IF is disposed on the resistive film RF. As will be described later, the insulating film IF is a mask (hard mask) for patterning the resistive film RF. The insulating film IF is formed of, for example, silicon oxide or silicon oxynitride (SiON).

[0017] Another one of the plurality of interlayer insulating films ILD is an interlayer insulating film ILD3. The interlayer insulating film ILD3 is disposed on the interlayer insulating film ILD2 so as to cover the plurality of resistive films RF and the plurality of insulating films IF.

[0018] Via holes VH3 and VH4 are formed in the interlayer insulating films ILD2 and ILD3. The via holes VH3 and VH4 penetrate the interlayer insulating films ILD2 and ILD3 in the thickness direction. Part of the wiring WL1 and part of the wiring WL2 are exposed at the bottom of the via holes VH3 and VH4, respectively.

[0019] The semiconductor device DEV1 has a via plug VP3 and a via plug VP4. The via plug VP3 and the via plug VP4 are embedded in the via holes VH3 and VH4, respectively. The via plugs VP3 and VP4 are made of, for example, tungsten. The lower end of the via plug VP3 is electrically connected to the wiring WL1, and the lower end of the via plug VP4 is electrically connected to the wiring WL2.

[0020] The semiconductor device DEV1 has wiring WL3 and wiring WL4. The wiring WL3 and wiring WL4 are arranged on an interlayer insulating film ILD3. The wiring WL3 and wiring WL4 are formed of, for example, aluminum or an aluminum alloy. A barrier metal BM3 is arranged between the wiring WL3 and the interlayer insulating film ILD3 and between the wiring WL4 and the interlayer insulating film ILD3. A barrier metal BM4 is arranged on the wiring WL3 and wiring WL4. The barrier metal BM3 and barrier metal BM4 are made of, for example, a stacked film of a titanium nitride film and a titanium film. The wiring WL3 and wiring WL4 are electrically connected to the upper ends of the via plugs VP3 and VP4, respectively. As a result, the wiring WL3 is electrically connected to the wiring WL1, and the wiring WL4 is electrically connected to the wiring WL2.

[0021] Another one of the multiple interlayer insulating films ILD is an interlayer insulating film ILD4. The interlayer insulating film ILD4 is disposed on the interlayer insulating film ILD3 so as to cover the wiring WL3 and the wiring WL4. Although not shown, other wirings and other interlayer insulating films may be sequentially stacked on the interlayer insulating film ILD4.

[0022] Each of the multiple resistive films RF extends in a first direction D1 along the upper surface of the interlayer insulating film ILD2 in a plan view. The multiple resistive films RF are arranged at intervals in a second direction D2 along the upper surface of the interlayer insulating film ILD2. The second direction D2 is a direction perpendicular to the first direction D1.

[0023] The resistive films RF are divided into a first group, a second group, and a third group. The resistive films RF belonging to the first group are referred to as resistive films RF1, the resistive films RF belonging to the second group are referred to as resistive films RF2, and the resistive films RF belonging to the third group are referred to as resistive films RF3. The second group is located on one side of the first group in the second direction D2 (on the left side in the example of FIG. 2). That is, the first group is located between the second group and the third group in the second direction D2. The third group is located on the other side of the first group in the second direction D2 (on the right side in the example of FIG. 2). The number of the resistive films RF1 is greater than the number of the resistive films RF2 and the number of the resistive films RF3. The lengths of the resistive films RF are, for example, equal to each other. Here, the length of the resistive film RF refers to the length of the resistive film RF in the first direction D1. Note that even if the lengths of the resistive films RF differ from each other due to manufacturing variations, this also applies when the lengths of the resistive films RF are equal to each other.

[0024] The width variation amount (second width variation amount) of each of the multiple resistive films RF2 and the width variation amount (third width variation amount) of each of the multiple resistive films RF3 are larger than the width variation amount (first width variation amount) of each of the multiple resistive films RF1. The first width variation amount is the difference between the width of each of the multiple resistive films RF1 and the reference width. The second width variation amount is the difference between the width of each of the multiple resistive films RF2 and the reference width. The third width variation amount is the difference between the width of each of the multiple resistive films RF3 and the reference width. The reference width is the width of the resistive film RF located at the center in the second direction D2. Note that when the number of multiple resistive films RF is an even number, the reference width is set to the width of either of the two central resistive films RF in the second direction D2. The first width variation amount of each of the multiple resistive films RF1 is, for example, within 0.5 percent of the reference width. The second width variation amount of each of the multiple resistive films RF2 and the third width variation amount of each of the multiple resistive films RF3 are, for example, more than 0.5 percent of the reference width. 2, the width of each of the resistive films RF2 and the width of each of the resistive films RF3 are smaller than the width of each of the resistive films RF1. Here, the width of the resistive film RF refers to the width of the resistive film RF in the second direction D2.

[0025] 3 is a schematic block diagram of the semiconductor device DEV1. As shown in FIG. 3, the semiconductor device DEV1 has a plurality of circuits CIR1 and a plurality of circuits CIR2. The plurality of circuits CIR1 constitute a first circuit group. The plurality of circuits CIR2 constitute a second circuit group. The plurality of resistive films RF1 are electrically connected to the first circuit group. The plurality of resistive films RF2 and the plurality of resistive films RF3 are electrically connected to the second circuit group. The second circuit group is different from the first circuit group. Alternatively, the plurality of resistive films RF2 may be electrically connected to the second circuit group, and the plurality of resistive films RF3 may be electrically connected to a third circuit group different from the first and second circuit groups.

[0026] Each of the plurality of circuits CIR1 is preferably at least one of an analog-digital converter circuit, a digital-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplifier circuit. Each of the plurality of circuits CIR2 is preferably at least one of a circuit for performing calibration and a circuit for generating a voltage from a power supply voltage. In other words, the second circuit group is preferably a circuit group requiring a lower precision of electrical resistance values ​​than the first circuit group.

[0027] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0028] Fig. 4 is a manufacturing process diagram of the semiconductor device DEV1. As shown in Fig. 4, the manufacturing method of the semiconductor device DEV1 includes a first wiring forming step S1, a first interlayer insulating film forming step S2, a first via hole forming step S3, a first via plug forming step S4, a resistance film forming step S5, a second interlayer insulating film forming step S6, a second via hole forming step S7, a second via plug forming step S8, a second wiring forming step S9, and a third interlayer insulating film forming step S10.

[0029] Before the first wiring formation step S1 is performed, the interlayer insulating film ILD1 and the structures below it are formed. These structures may be formed by conventionally known methods, and therefore, a description thereof will be omitted here.

[0030] 5 is a cross-sectional view illustrating the first wiring formation step S1. As shown in FIG. 5, in the first wiring formation step S1, wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed on an interlayer insulating film ILD1. In the first wiring formation step S1, first, constituent materials of the barrier metal BM1, wiring WL1 (wiring WL2), and barrier metal BM2 are sequentially deposited by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the barrier metal BM2. The resist pattern is formed by exposing and developing a photoresist.

[0031] Third, using the resist pattern as a mask, the constituent materials of the formed barrier metal BM1, wiring WL1 (wiring WL2), and barrier metal BM2 are etched. As a result, the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed. After the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed, the resist pattern is removed.

[0032] 6 is a cross-sectional view illustrating the first interlayer insulating film forming step S2. In the first interlayer insulating film forming step S2, as shown in FIG. 6, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wiring WL1, the wiring WL2, the barrier metal BM1, and the barrier metal BM2. In the first interlayer insulating film forming step S2, first, a constituent material of the interlayer insulating film ILD2 is deposited on the interlayer insulating film ILD1 by, for example, a CVD (Chemical Vapor Deposition) method so as to cover the wiring WL1, the wiring WL2, the barrier metal BM1, and the barrier metal BM2. Second, the upper surface of the deposited constituent material of the interlayer insulating film ILD2 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. In this manner, the interlayer insulating film ILD2 is formed.

[0033] FIG. 7 is a cross-sectional view illustrating the first via hole forming step S3. In the first via hole forming step S3, as shown in FIG. 7, via holes VH1 and VH2 are formed in the interlayer insulating film ILD2. In the first via hole forming step S3, first, a resist pattern is formed on the interlayer insulating film ILD2. The resist pattern is formed by exposing and developing a photoresist. Second, the interlayer insulating film ILD2 is etched using the resist pattern as a mask. In this way, the via holes VH1 and VH2 are formed. After the via holes VH1 and VH2 are formed, the resist pattern is removed.

[0034] 8 is a cross-sectional view illustrating the first via plug forming step S4. In the first via plug forming step S4, as shown in FIG. 8, via plugs VP1 and VP2 are formed in the via holes VH1 and VH2. In the first via plug forming step S4, first, the via holes VH1 and VH2 are filled with the constituent material of the via plug VP1 (via plug VP2) by, for example, a CVD method. Second, the constituent material of the via plug VP1 (via plug VP2) that protrudes from the via holes VH1 and VH2 is removed by, for example, a CMP method. In this way, the via plugs VP1 and VP2 are formed.

[0035] 9 is a cross-sectional view illustrating the resistive film forming step S5. As shown in FIG. 9, in the resistive film forming step S5, a resistive film RF and an insulating film IF are formed on the interlayer insulating film ILD2. In the resistive film forming step S5, first, a constituent material of the resistive film RF is formed on the interlayer insulating film ILD2 by, for example, sputtering. Second, a constituent material of the insulating film IF is formed on the formed constituent material of the resistive film RF. Third, a resist pattern is formed on the formed constituent material of the insulating film IF. The resist pattern is formed by exposing and developing a photoresist.

[0036] Fourth, the constituent material of the formed insulating film IF is etched using the resist pattern as a mask. In this way, the insulating film IF is formed. After the insulating film IF is formed, the resist pattern is removed. Fifth, the constituent material of the formed resistive film RF is etched using the insulating film IF as a mask (hard mask). In this way, the resistive film RF is formed. Note that the insulating film IF is not removed after the resistive film RF is formed.

[0037] 10 is a cross-sectional view illustrating the second interlayer insulating film forming step S6. In the second interlayer insulating film forming step S6, as shown in FIG. 10, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the resistive film RF. In the second interlayer insulating film forming step S6, first, a constituent material of the interlayer insulating film ILD3 is deposited on the interlayer insulating film ILD2 by, for example, a CVD method so as to cover the resistive film RF. Second, the upper surface of the constituent material of the deposited interlayer insulating film ILD3 is planarized by, for example, a CMP method. In this manner, the interlayer insulating film ILD3 is formed.

[0038] 11 is a cross-sectional view illustrating the second via hole forming step S7. In the second via hole forming step S7, via holes VH3 and VH4 are formed in the interlayer insulating films ILD2 and ILD3, as shown in FIG.

[0039] In the second via hole forming step S7, first, a resist pattern is formed on the interlayer insulating film ILD3. The resist pattern is formed by exposing and developing a photoresist. Second, the interlayer insulating film ILD2 and the interlayer insulating film ILD3 are etched using the resist pattern as a mask. In this way, the via holes VH3 and VH4 are formed. After the via holes VH3 and VH4 are formed, the resist pattern is removed.

[0040] 12 is a cross-sectional view illustrating the second via plug forming step S8. In the second via plug forming step S8, via plugs VP3 and VP4 are formed in the via holes VH3 and VH4, as shown in FIG.

[0041] In the second via plug formation process S8, first, the via holes VH3 and VH4 are filled with the constituent material of the via plug VP3 (via plug VP4) by, for example, a CVD method. Second, the constituent material of the via plug VP3 (via plug VP4) that protrudes from the via holes VH3 and VH4 is removed by, for example, a CMP method. In this way, the via plugs VP3 and VP4 are formed.

[0042] 13 is a cross-sectional view illustrating the second wiring formation step S9. As shown in FIG. 13, in the second wiring formation step S9, wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed on the interlayer insulating film ILD3. In the second wiring formation step S9, first, constituent materials of the barrier metal BM3, wiring WL3 (wiring WL4), and barrier metal BM4 are sequentially deposited by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the barrier metal BM4. The resist pattern is formed by exposing and developing a photoresist.

[0043] Third, using the resist pattern as a mask, the constituent materials of the formed barrier metal BM3, wiring WL3 (wiring WL4), and barrier metal BM4 are etched. As a result, the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed. Note that the resist pattern is removed after the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed.

[0044] In the third interlayer insulating film forming step S10, an interlayer insulating film ILD4 is formed on the interlayer insulating film ILD3 so as to cover the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4. In the third interlayer insulating film forming step S10, first, a constituent material of the interlayer insulating film ILD4 is deposited on the interlayer insulating film ILD3 by, for example, a CVD method so as to cover the wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4. Second, the upper surface of the deposited constituent material of the interlayer insulating film ILD4 is planarized by, for example, a CMP method. In this manner, the semiconductor device DEV1 having the structure shown in FIG. 1 is formed. After the third interlayer insulating film forming step S10 is performed, other wirings, other interlayer insulating films, etc. are sequentially stacked on the interlayer insulating film ILD4. These structures may be formed by conventionally known methods, and therefore, description thereof will be omitted here.

[0045] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0046] In the semiconductor device DEV1, even if the width of each of the multiple resistive films RF is designed to be constant, due to the microloading effect that occurs when etching is performed in the resistive film formation process S5, the width of each of the multiple resistive films RF2 and the width of each of the multiple resistive films RF3 may end up being smaller than the designed width.

[0047] If the multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to a first circuit group that requires high resistance value accuracy, the accuracy of the circuits included in the first circuit group will decrease. On the other hand, there is a case where the multiple resistive films RF2 and multiple resistive films RF3 are used as dummy resistive films that are not electrically connected to the circuits, and multiple other resistive films are formed that are electrically connected to the second circuit group. In this case, although the decrease in accuracy of the circuits included in the first circuit group can be suppressed, the chip area will increase because another resistive film electrically connected to the second circuit group is additionally formed.

[0048] In the semiconductor device DEV1, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group. This prevents a decrease in the accuracy of the circuits included in the first circuit group while suppressing an increase in chip area. This embodiment is not limited to the case where multiple resistive films RF are electrically connected to the first circuit group and the second circuit group. Multiple resistive films RF may be electrically connected to three or more circuit groups. For example, multiple resistive films RF1 may be electrically connected to the first circuit group, multiple resistive films RF2 may be electrically connected to the second circuit group, and multiple resistive films RF3 may be electrically connected to the third circuit group. In this case, multiple resistive films RF can be used in more circuits while suppressing an increase in chip size.

[0049] (Second embodiment) A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV2. Here, differences from semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0050] The semiconductor device DEV2 includes a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV2, the resistive films RF1 are electrically connected to a first circuit group, and the resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0051] 14 is a planar layout diagram of the resistive films RF in the semiconductor device DEV2. As shown in FIG. 14, in the semiconductor device DEV2, the width of each of the plurality of resistive films RF2 and the width of each of the plurality of resistive films RF3 are larger than the width of each of the plurality of resistive films RF1. In this respect, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0052] In the semiconductor device DEV2, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group, so that, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in accuracy of the circuits included in the first circuit group.

[0053] (Third embodiment) A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as semiconductor device DEV3. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0054] The semiconductor device DEV3 includes a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV3, the resistive films RF1 are electrically connected to a first circuit group, and the resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV1.

[0055] 15 is a planar layout diagram of the resistive film RF in the semiconductor device DEV3. As shown in FIG. 15, in the semiconductor device DEV3, the width of each of the multiple resistive films RF2 decreases toward one side in the second direction D2 (the left side in the example of FIG. 15). That is, the width of each of the multiple resistive films RF2 decreases as the distance from the first group (the multiple resistive films RF1) increases in the second direction D2. Also, in the semiconductor device DEV3, the difference in width between two adjacent resistive films RF2 increases toward one side in the second direction D2. That is, the difference in width between two adjacent resistive films RF2 increases as the distance from the first group increases in the second direction D2. Similarly, the width of each of the multiple resistive films RF3 decreases toward the other side in the second direction D2 (the right side in the example of FIG. 15), and the difference in width between two adjacent resistive films RF3 increases toward the other side in the second direction D2. That is, the width of each of the plurality of resistive films RF3 decreases as the distance from the first group increases in the second direction D2, and the difference in width between two adjacent ones of the plurality of resistive films RF3 increases as the distance from the first group increases. From another perspective, the width of each of the plurality of resistive films RF2 changes exponentially as the distance from the first group increases in the second direction D2, and the width of each of the plurality of resistive films RF3 changes exponentially as the distance from the first group increases in the second direction D2.

[0056] In the semiconductor device DEV3, the second circuit group includes an image processing circuit, and the resistive films RF2 and RF3 are electrically connected to the image processing circuit. In the image processing circuit, the resistive films RF2 and RF3 having varying widths as described above can be suitably used.

[0057] In the semiconductor device DEV3, multiple resistive films RF1 are electrically connected to the first circuit group, and multiple resistive films RF2 and multiple resistive films RF3 are electrically connected to the second circuit group, so that, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in accuracy of the circuits included in the first circuit group.

[0058] (Fourth embodiment) A semiconductor device according to a fourth embodiment will be described. The semiconductor device according to the fourth embodiment will be referred to as semiconductor device DEV4. Here, differences from semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0059] The semiconductor device DEV4 includes a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV4, the plurality of resistive films RF1 are electrically connected to the first circuit group. In these respects, the configuration of the semiconductor device DEV4 is common to the configuration of the semiconductor device DEV1.

[0060] 16 is a planar layout diagram of the resistive films RF in the semiconductor device DEV4. As shown in FIG. 16, in the semiconductor device DEV4, some of the resistive films RF2 form a fourth group, and the remaining resistive films RF2 form a fifth group. The resistive films RF2 belonging to the fourth group are referred to as resistive films RF2a. The resistive films RF2 belonging to the fifth group are referred to as resistive films RF2b. The resistive film RF2b is located on one side (the left side in the example of FIG. 16) of the resistive films RF2a in the second direction D2. That is, the resistive films RF2a are located between the resistive films RF1 and RF2b in the second direction D2. The width of the resistive film RF2b is greater than the width of each of the resistive films RF2a.

[0061] Furthermore, in the semiconductor device DEV4, some of the multiple resistive films RF3 form a sixth group, and the remaining multiple resistive films RF3 form a seventh group. The multiple resistive films RF3 belonging to the sixth group are referred to as multiple resistive films RF3a. The resistive films RF3 belonging to the seventh group are referred to as resistive films RF3b. The resistive film RF3b is located on the other side of the multiple resistive films RF3a in the second direction D2 (to the right in the example of FIG. 16). That is, the multiple resistive films RF3a are located between the multiple resistive films RF1 and resistive film RF3b in the second direction D2. The width of the resistive film RF3b is greater than the width of each of the multiple resistive films RF3a.

[0062] In the semiconductor device DEV4, the plurality of resistive films RF2a and the plurality of resistive films RF3a are electrically connected to the second circuit group. However, the resistive films RF2b and RF3b are not electrically connected to the second circuit group or other circuits. That is, in the semiconductor device DEV4, some of the plurality of resistive films RF2 and some of the plurality of resistive films RF3 are electrically connected to the second circuit group, but the remaining portions of the plurality of resistive films RF2 and the remaining portions of the plurality of resistive films RF3 are dummy resistive films. In these respects, the configuration of the semiconductor device DEV4 differs from the configuration of the semiconductor device DEV1.

[0063] In the above example, the number of resistive films RF2 belonging to the fifth group and the number of resistive films RF3 belonging to the seventh group were one, but the number of resistive films RF2 belonging to the fifth group and the number of resistive films RF3 belonging to the seventh group may be multiple.

[0064] In the semiconductor device DEV4, the plurality of resistive films RF1 are electrically connected to the first circuit group, and a portion of the plurality of resistive films RF2 and a portion of the plurality of resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group. Furthermore, in the semiconductor device DEV4, the remaining portions of the plurality of resistive films RF2 and the remaining portions of the plurality of resistive films RF3, which have increased widths, are not electrically connected to the second circuit group, so it is possible to suppress a decrease in the accuracy of the circuits included in the second circuit group.

[0065] (Fifth embodiment) A semiconductor device according to a fifth embodiment will be described. The semiconductor device according to the fifth embodiment is designated as semiconductor device DEV5. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0066] The semiconductor device DEV5 includes a semiconductor substrate SUB, interlayer insulating films ILD1, ILD2, ILD3, and ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistive films RF1, RF2, and RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV5, the resistive films RF1 are electrically connected to a first circuit group, and the resistive films RF2 and RF3 are electrically connected to a second circuit group. In these respects, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0067] 17 is a planar layout diagram of the resistive film RF in the semiconductor device DEV5. As shown in FIG. 17, in the semiconductor device DEV5, the length of each of the plurality of resistive films RF2 is shorter than the length of each of the plurality of resistive films RF1. In this respect, the configuration of the semiconductor device DEV5 differs from the configuration of the semiconductor device DEV1.

[0068] In the semiconductor device DEV5, the plurality of resistive films RF1 are electrically connected to the first circuit group, and the plurality of resistive films RF2 and RF3 are electrically connected to the second circuit group, so that, similar to the semiconductor device DEV1, it is possible to suppress a decrease in the accuracy of the circuits included in the first circuit group while suppressing an increase in the chip area. Furthermore, in the semiconductor device DEV5, the length of each of the plurality of resistive films RF2 can be adjusted according to the type of circuit to which it is connected, improving the degree of freedom in layout.

[0069] <Modification> In the above example, the resistance value of each of the plurality of resistive films RF2 is adjusted by adjusting the length of each of the plurality of resistive films RF2. FIG. 18 is a planar layout diagram of the resistive film RF in a modified example of the semiconductor device DEV5. As shown in FIG. 18, the resistance value of each of the plurality of resistive films RF2 may be adjusted by adjusting the distance between the via plug VP1 and the via plug VP2. More specifically, the distance in the first direction D1 between the via plug VP1 and the via plug VP2 electrically connected to the resistive film RF2 may be shorter than the distance in the first direction D1 between the via plug VP1 and the via plug VP2 electrically connected to the resistive film RF1.

[0070] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0071] BM1, BM2, BM3, BM4 barrier metal, CIR1, CIR2 circuit, D1 first direction, D2 second direction, DEV1, DEV2, DEV3, DEV4, DEV5 semiconductor device, IF insulating film, ILD interlayer insulating film, ILD1, ILD2, ILD3, ILD4 interlayer insulating film, RF, RF1, RF2, RF2a, RF2b, RF3, RF3a, RF3b resistive film, S1 first wiring formation step, S2 first interlayer insulating film formation step, S3 first via hole formation step, S4 first via plug formation step, S5 resistive film formation step, S6 second interlayer insulating film formation step, S7 second via hole formation step, S8 second via plug formation step, S9 second wiring formation step, S10 third interlayer insulating film formation step, VH1, VH2, VH3, VH4 via holes, VP1, VP2, VP3, VP4 Via plug, WL1, WL2, WL3, WL4 wiring, SUB semiconductor substrate.

Claims

1. an interlayer insulating film; a plurality of resistive films disposed on the interlayer insulating film; each of the plurality of resistive films extends in a first direction along an upper surface of the interlayer insulating film in a plan view; the plurality of resistive films are arranged along an upper surface of the interlayer insulating film in a plan view and spaced apart from one another in a second direction perpendicular to the first direction, The plurality of resistive films are divided into a first group, a second group, and a third group, the first group is located between the second group and the third group in the second direction, a second width variation amount of each of the plurality of second resistive films belonging to the second group and a third width variation amount of each of the plurality of third resistive films belonging to the third group are larger than a first width variation amount of each of the plurality of first resistive films belonging to the first group; the first width variation amount is a difference between a reference width and each width of the plurality of first resistive films, the second width variation amount is a difference between the reference width and each width of the plurality of second resistive films, the third width variation amount is a difference between the reference width and each width of the plurality of third resistive films, the reference width is a width of one of the plurality of resistive films located at the center in the second direction, the plurality of first resistive films are electrically connected to a first circuit group; at least a portion of the plurality of second resistive films and / or at least a portion of the plurality of third resistive films are electrically connected to a second circuit group different from the first circuit group; the first circuit group includes at least one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplifier circuit; The semiconductor device, wherein the second circuit group includes at least one of a circuit for performing calibration and a circuit for generating a voltage from a power supply voltage.

2. The semiconductor device according to claim 1 , wherein the plurality of second resistive films and the plurality of third resistive films are electrically connected to the second circuit group.

3. The semiconductor device according to claim 2 , wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are smaller than the reference width.

4. 4. The semiconductor device according to claim 3, wherein a length of each of the plurality of second resistive films in the first direction is shorter than a length of each of the plurality of first resistive films.

5. The semiconductor device according to claim 2 , wherein the width of each of the plurality of second resistive films and the width of each of the plurality of third resistive films are greater than the reference width.

6. the width of each of the plurality of second resistive films decreases as the distance from the first group in the second direction increases, a difference between the widths of two adjacent ones of the plurality of second resistive films increases as the distance from the first group in the second direction increases, the width of each of the plurality of third resistive films decreases as the distance from the first group in the second direction increases, 3 . The semiconductor device according to claim 2 , wherein the difference in width between two adjacent ones of said plurality of third resistive films increases as the distance from said first group in said second direction increases.

7. a part of the second resistive films and a part of the third resistive films are electrically connected to the second circuit group; The semiconductor device according to claim 1 , wherein the remaining portions of the plurality of second resistive films and the remaining portions of the plurality of third resistive films are dummy resistive films.

8. 2. The semiconductor device according to claim 1, wherein each of the plurality of resistive films is formed of a material including at least one selected from the group consisting of silicon chromium, silicon chromium doped with carbon, nickel chromium, titanium nitride, and tantalum nitride.

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