Thin Film Resistor (TFR) Device Structure for High-Performance Radio Frequency (RF) Filter Design

Abstract

The integrated circuit (IC, 450) includes a substrate (402) and a thin film resistor (TFR, 460) device structure. The TFR device structure includes a first portion (462) of a first metallization layer (M1) on the substrate and a second portion (470) of the first metallization layer. Also, the TFR device structure includes a first portion (464) of a dielectric layer on the first portion (462) of the first metallization layer and a second portion (472) of the dielectric layer on the second portion (470) of the first metallization layer. The TFR device structure further includes a first portion (466) of a second metallization layer (M2) on the first portion (464) of the dielectric layer and a second portion (474) of the second metallization layer on the second portion (472) of the dielectric layer. Also, the TFR device structure includes a first portion (469) of a third metallization layer (M3) that couples the first portion (466) of the second metallization layer to the second portion (474) of the second metallization layer.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to U.S. Patent Application No. 17 / 830,196, entitled "THIN FILM RESISTOR (TFR) DEVICE STRUCTURE FOR HIGH PERFORMANCE RADIO FREQUENCY (RF) FILTER DESIGN," filed on June 1, 2022, the disclosure of which is hereby incorporated by reference in its entirety.

[0002] Aspects of the present disclosure relate to semiconductor devices and integrated passive devices, and more particularly, to thin film resistor (TFR) device structures for high performance radio frequency (RF) filter design.

Background Art

[0003] Wireless communication devices incorporate radio frequency (RF) modules that facilitate the communications and functions desired by users. As wireless systems become more prevalent and include more functions, chip manufacturing has become more complex. Fifth generation (5G) / sixth generation (6G) new radio (NR) wireless communication devices incorporate the latest generation of electronic dies that house many functions and devices in smaller modules with smaller interconnects. As the density of these modules increases, resistors are important for combining and / or distributing RF power.

[0004] Design challenges for mobile radio frequency (RF) chips, such as mobile RF transceivers, include analog / RF performance considerations, including mismatches, noise, and other performance considerations. The design of these mobile RF transceivers involves the use of passive devices, such as resistors, to perform filtering and coupling. These resistors are incorporated into high-power system-on-chip devices, such as application processors and graphics processors.

[0005] In practice, the passive devices of mobile RF transceivers can involve high-performance resistor components. For example, analog integrated circuits use various types of passive devices, such as resistors. The use of resistors can enable high-performance power combiners / dividers filters that synthesize / distribute RF power using resistor components. Unfortunately, conventional resistor components cannot achieve the required isolation due to parasitic capacitive coupling between the electrodes of the resistor components. A thin-film resistor (TFR) device structure is desired to provide the isolation required to enable 5G / 6G front-end applications. SUMMARY OF THE INVENTION

[0006] An integrated circuit (IC) includes a substrate and a thin-film resistor (TFR) device structure. The TFR device structure includes a first portion of a first metallization layer and a second portion of the first metallization layer on the substrate. The TFR device structure also includes a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer. The TFR device structure further includes a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer. The TFR device structure also includes a first portion of a third metallization layer that couples the first portion of the second metallization layer to the second portion of the second metallization layer.

[0007] A method for manufacturing a thin film resistor (TFR) device structure is described. The method includes forming a first portion of a first metallization layer and a second portion of the first metallization layer on a substrate. The method also includes forming a first portion of a dielectric layer on the first portion of the first metallization layer and forming a second portion of the dielectric layer on the second portion of the first metallization layer. The method further includes forming a first portion of a second metallization layer on the first portion of the dielectric layer and forming a second portion of the second metallization layer on the second portion of the dielectric layer. The method also includes forming a first portion of a third metallization layer to couple the first portion of the second metallization layer to the second portion of the second metallization layer.

[0008] Above, the features and technical advantages of the present disclosure have been outlined rather broadly so that a better understanding of the subsequent detailed description can be obtained. Additional features and advantages of the present disclosure will be described below. Those skilled in the art will understand that the present disclosure can be readily utilized as a basis for modifying or designing other structures for achieving the same purpose as the present disclosure. Those skilled in the art will also recognize that such equivalent configurations do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered characteristic of the present disclosure will be better understood with reference to the following description in conjunction with the accompanying drawings, in which both the construction and method of operation, together with further objects and advantages, will be more particularly described. However, it is to be clearly understood that each of the drawings is provided for the purpose of illustration and description only and is not intended to limit the scope of the present disclosure.

[0009] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0011] In connection with the accompanying drawings, the "Embodiments for Carrying Out the Invention" described below are intended as descriptions of various configurations and are not intended to represent the only configuration capable of practicing the concepts described herein. The "Embodiments for Carrying Out the Invention" include specific details aimed at providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] The use of the term "and / or" as described in this specification is intended to represent an "inclusive OR", and the use of the term "or" is intended to represent an "exclusive OR". The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration", and should not necessarily be construed as being preferred or advantageous over other exemplary configurations. The term "coupled" used throughout this specification means "connected directly or indirectly through an electrical, mechanical, or other intervening connection (e.g., a switch)", and is not necessarily limited to a physical connection. Additionally, the connection can be made such that the objects are permanently connected or releasably connected. The connection can be through a switch. The term "proximate" used throughout this specification means "adjacent, very close, neighboring, or near". The term "on" used throughout this specification means "directly on" in some configurations and "indirectly on" in other configurations.

[0013] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) are migrating to deep submicron process nodes due to cost and power consumption issues. The design of mobile RF transceivers is becoming more complex due to additional circuit functions to support communication enhancements such as fifth generation (5G) new radio (NR) / sixth generation (6G) communication systems. Further design challenges related to mobile RF transceivers include the use of passive devices, which directly impact analog RF performance considerations, including incompatibilities, noise, and other performance considerations.

[0014] Passive devices in a mobile radio frequency (RF) transceiver can include high-performance resistor, capacitor, and inductor components. For example, an analog integrated circuit uses various types of passive devices such as integrated capacitors, integrated inductors, and resistor components. Integrated capacitors can include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures. An inductor is an example of an electrical device used to temporarily store energy in a magnetic field within a wire coil according to an inductance value. A resistor is a passive two-terminal electrical component that implements electrical resistance as a circuit element and can be used to reduce the flow of current, adjust signal levels, divide voltages, bias active elements, and terminate transmission lines. For example, the design of a mobile RF transceiver includes the use of an RF filter having resistors, inductors, and capacitors to meet bandwidth specifications.

[0015] A 5G / 6G radio frequency front-end (RFFE) module can include a combiner / divider filter and / or a directional coupler that includes resistor components, MIM capacitors, and inductors. These 5G / 6G RF front-end applications specify resistor components that synthesize / distribute RF power to enable the high-performance power of the combiner / divider filter. Unfortunately, thin-film resistors (TFRs) available using current integrated passive device (IPD) foundry processes cannot achieve the required isolation due to the parasitic capacitive coupling of the electrodes of the TFRs. Without the option to change the foundry's IPD process flow, it is impossible to implement and realize TFR devices for power combiner / divider filters. Therefore, a TFR device structure with design techniques / optimizations to solve these problems is desired.

[0016] Various aspects of the present disclosure provide a TFR device structure for an RF filter. A process flow for manufacturing a TFR device structure for an RF filter may include a front-end-of-line (FEOL) process, a middle-of-line (MOL) process, and a back-end-of-line (BEOL) process. It should be understood that the term "layer" includes a film and is not construed to indicate a vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to the substrate of a diced wafer or the substrate of an undiced wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0017] As described, a back-end-of-line (BEOL) interconnect layer may refer to a conductive interconnect layer (e.g., a first interconnect layer (M1) or metal 1 M1, metal 2 (M2), metal 3 (M3), metal 4 (M4), etc.) for electrically coupling to front-end-of-line (FEOL) active devices of an integrated circuit. The various BEOL interconnect layers are formed in corresponding BEOL interconnect layers where the underlying BEOL interconnect layer uses a thinner metal layer compared to the upper BEOL interconnect layer. The BEOL interconnect layer may be electrically coupled to a middle-of-line (MOL) interconnect layer. For example, M1 may be connected to an oxide diffusion (OD) layer of the integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of the integrated circuit. A BEOL first via (V2) may connect M2 to M3 or other layers of the BEOL interconnect layer.

[0018] Aspects of the present disclosure relate to thin film resistor (TFR) device structures for implementing RF filters such as power combiners / divider filters or directional couplers. In some aspects of the present disclosure, the TFR device structure includes a split first metallization layer (e.g., M1). The TFR device structure also includes a dielectric layer portion on the split portions of the M1 metallization layer. In some aspects of the present disclosure, the TFR device structure includes a split M2 metallization layer on each portion of the dielectric layer. In some aspects of the present disclosure, the M1 and M2 metallization layers are split to provide the required separation defined by the TFR device structure. This configuration of the TFR device structure can correspond to the required radio frequency (RF) response and can also meet the design target specifications of the power combiner / divider filter.

[0019] FIG. 1 is a schematic diagram of a radio frequency front end (RFFE) module 100 that uses a filter 104 (e.g., an RF filter implemented with a TFR device structure). The RFFE module 100 includes a power amplifier 102, a filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies a signal (s) to a certain power level for transmission. The filter 104 filters the input / output signal according to various different parameters including frequency, insertion loss, rejection, or other similar parameters. Additionally, the RF switch module 106 can select a particular portion of the input signal for passing to the rest of the RFFE module 100.

[0020] The radio frequency front end (RFFE) module 100 also includes a tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B), a second diplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuit 112 (e.g., the first tuner circuit 112A and the second tuner circuit 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuit 112 can perform impedance matching (e.g., voltage standing wave ratio (VSWR) optimization) for the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuit 112A and the second tuner circuit 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides this information to a modem 130 (e.g., a mobile station modem (MSM)). The modem 130 provides a digital signal to an application processor (AP) 110.

[0021] As shown in FIG. 1, the second diplexer 190 is between the tuner component of the tuner circuit 112 and the capacitor 116, inductor 118, and antenna 114. From the radio frequency front end (RFFE) module 100 to the chipset including the wireless transceiver 120, modem 130, and application processor 110, the second diplexer 190 may be disposed between the antenna 114 and the tuner circuit 112 to provide high system performance. Also, the second diplexer 190 performs frequency domain multiplexing for both high-band and low-band frequencies. After the second diplexer 190 performs its frequency multiplexing function on the input signal, the output of the second diplexer 190 is supplied to an optional inductor / capacitor (LC) network including the capacitor 116 and inductor 118. The LC network may provide additional impedance matching components for the antenna 114 as needed. Next, a signal having a specific frequency is transmitted or received by the antenna 114. Although a single capacitor and inductor are shown, multiple components are also contemplated.

[0022] FIG. 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 and a radio frequency front end (RFFE) module 170 for a chipset 210. The Wi-Fi module 150 includes a first diplexer 162 that communicatively couples an antenna 164 to a WLAN module 152. A first RF switch 160 communicatively couples the first diplexer 162 to the WLAN module 152. The RFFE module 170 includes a second diplexer 190 that communicatively couples an antenna 192 to a wireless transceiver (WTR) 120 via a filter 172 (e.g., an RF filter implemented with a TFR device structure). A second RF switch 180 communicatively couples the second diplexer 190 to the filter 172.

[0023] The WLAN module 152 of the WTR120 and the Wi-Fi module 150 is coupled to a modem (mobile station modem (MSM), e.g., a baseband modem) 130 that is powered by a power supply 202 via a power management integrated circuit (PMIC) 140. The chipset 210 also includes capacitors 144 and 148 and an inductor (s) 146 to provide signal integrity. Each of the PMIC 140, the modem 130, the WTR120, and the WLAN module 152 includes capacitors (e.g., 142, 132, 122, and 154) and operates according to a clock 204. Additionally, the inductor 146 couples the modem 130 to the PMIC 140. The shape and arrangement of the various inductor components and capacitor components in the RFIC) chip 200 can reduce electromagnetic coupling between the components. The design of the RFFE module 170 includes a filter 172, which can be an RF filter implemented with a TFR device structure as shown, for example, in FIG. 3, according to aspects of the present disclosure.

[0024] FIG. 3 is a block diagram showing a cross-sectional view of a radio frequency front end (RFFE) module 300 including a semiconductor die and an integrated passive device (IPD) filter die, according to aspects of the present disclosure. In this example, the RFFE module 300 includes a semiconductor die 350 and an IPD filter die 320 supported by a substrate 310. The semiconductor die 350 can be an active die having a semiconductor substrate 360 (e.g., an active silicon substrate) coupled to package balls 302 via a back end of line (BEOL) layer 370. The BEOL layer 370 includes a plurality of BEOL metallization layers (M1, M2, M3,..., Mn) on the semiconductor substrate 360 (e.g., a diced silicon wafer). The redistribution layer 312 is coupled to the package balls 302.

[0025] The IPD filter die 320 includes a substrate 330 (e.g., a passive substrate) coupled to the package ball 302 via a back-end-of-line (BEOL) layer 340. The redistribution layer 312 is coupled to the IPD filter die 320 via the package ball 302. In some aspects of the present disclosure, the substrate 330 is composed of glass, and the IPD filter die 320 is a glass-substrate integrated passive device (GIPD) filter die. The IPD filter die 320 may implement a fifth-generation (5G) new radio (NR) / sixth-generation (6G) power combiner / divider filter or a directional coupler.

[0026] The RFFE module 300 may include a power combiner / divider filter including resistor components, MIM capacitors, and inductors. The RFFE module 300 may specify resistor components for combining / distributing RF power to enable a high-performance power combiner / divider filter. Unfortunately, thin-film resistors (TFRs) obtained from current IPD foundry processes cannot achieve the required isolation due to parasitic capacitive coupling between the electrodes of the TFR device. Without the option to change the foundry IPD process flow, it is impossible to implement and realize a TFR device to meet the specifications of the power combiner / divider filter. In some aspects of the present disclosure, the IPD filter die 320 includes a TFR device structure for an RF filter, as further shown in FIGS. 4A and 4B.

[0027] Figures 4A and 4B are block diagrams showing a radio frequency integrated circuit (RFIC) chip including a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) device for a radio frequency (RF) filter according to aspects of the present disclosure. Figure 4A shows an RFIC chip 400 including a substrate 402 having an oxide layer 404 (e.g., tetraethyl orthosilicate (TEOS) oxide) on the surface of the substrate 402. In some aspects of the present disclosure, the RFIC chip 400 includes a metal-insulator-metal (MIM) capacitor 410 and a thin film resistor (TFR) device structure 420 on the oxide layer 404.

[0028] In some aspects of the present disclosure, the TFR device structure 420 includes a split first metallization layer (e.g., M1) including a first portion 422 and a second portion 424 of the M1 metallization layer on the surface of the oxide layer 404. Also, the TFR device structure 420 includes a dielectric layer 426 on the first portion 422 and the second portion 424 of the M1 metallization layer. Also, the TFR device structure 420 further includes an M2 metallization layer 428 on the dielectric layer 426. The M2 metallization layer 428 may be composed of a TFR layer such as titanium nitride (TiN), tantalum nitride (TaN), nickel chromium (NiCr), or other similar conductive materials for resistors. Further, a first portion 430 and a second portion 432 of a third metallization layer (e.g., M3 metallization layer) are coupled to the M2 metallization layer 428 via a via V2, completing the formation of the TFR device structure 420.

[0029] In this example, the MIM capacitor 410 includes a first plate 412 composed of an M1 metallization layer on the surface of the oxide layer 404. The MIM capacitor 410 also includes an MIM insulator layer 414 on the first plate 412 of the MIM capacitor 410. Further, the second plate 416 of the MIM capacitor 410 is composed of an M2 metallization layer on the MIM insulator layer 414. Further, the first portion 418 and the second portion 419 of the M3 metallization layer are coupled to the second plate 416 and the first plate 412 via a via V2 in the first interlayer dielectric (ILD) layer 408, and the formation of the MIM capacitor 410 is completed. A passivation layer 406 is provided on portions of the M3 metallization layer (e.g., 418, 419, 430, and 432) and on the first ILD layer 408.

[0030] FIG. 4B shows an RFIC chip 450 including a substrate 402 having an oxide layer 404 (e.g., tetraethyl orthosilicate (TEOS) oxide) on the surface of the substrate 402. In some aspects of the present disclosure, the RFIC chip 450 includes an MIM capacitor 410 and a TFR device structure 460 on the oxide layer 404. In some aspects of the present disclosure, the TFR device structure 460 includes a split M1 metallization layer including a first portion 462 and a second portion 470 of the M1 metallization layer on the surface of the oxide layer 404. The TFR device structure 460 includes a first portion 464 of a dielectric layer on the first portion 462 of the M1 metallization layer and a second portion 472 of the dielectric layer on the second portion 470 of the M1 metallization layer.

[0031] In some aspects of the present disclosure, the TFR device structure 460 includes a split M2 metallization layer. In these aspects of the present disclosure, the TFR device structure 460 includes a first portion 464 of a dielectric layer over a first portion 462 of the M1 metallization layer and a second portion 472 of the dielectric layer over a second portion 470 of the M1 metallization layer. The TFR device structure 460 further includes a first portion 466 of the M2 metallization layer over the first portion 464 of the dielectric layer and a second portion 474 of the M2 metallization layer over the second portion 472 of the dielectric layer. The M2 metallization layer may be composed of a TFR layer such as titanium nitride (TiN), tantalum nitride (TaN), nickel chromium (NiCr), or other similar conductive materials for resistors. In these aspects of the present disclosure, a second portion 469 of the M3 metallization layer couples the first portion 466 of the M2 metallization layer to the second portion 474 of the M2 metallization layer. Further, a first portion 468 and a third portion 476 of the M3 metallization layer are coupled to the first portion 466 and the second portion 474 of the M2 metallization layer via vias V2. A passivation layer 406 is also provided over portions of the M3 metallization layer (e.g., 418, 419, 468, 469, and 476) and over the first ILD layer 408 to complete the formation of the TFR device structure 460.

[0032] Figures 5A-5D are schematic diagrams of a power combiner / divider filter having a thin film resistor (TFR) device structure according to aspects of the present disclosure. Figure 5A shows a schematic diagram of a power combiner / divider filter 500 having a metal-insulator-metal (MIM) capacitor 510, a thin film resistor (TFR) device structure 550, and an inductor 580. Figure 5B shows a perspective view and an exploded view 570 of a first TFR device structure 560 according to aspects of the present disclosure. As shown in the exploded view 570, the first TFR device structure 560 includes a dielectric layer (e.g., silicon nitride (SiN)), an M2 metallization layer, and an M3 metallization layer that joins a first portion and a second portion of the M1 metallization layer including via V2.

[0033] FIG. 5C shows a cross-sectional view 590 of a first TFR device structure 560 that includes a first port (e.g., port 1) and a second port (e.g., port 2). The cross-sectional view 590 of the first TFR device structure 560 further shows a divided lower electrode (M1) that extends below the divided upper electrode (M2). FIG. 5D shows a top view of the first TFR device structure 560. In this configuration, the aspect ratio (AR) between the length and width of a unit cell of the first TFR device structure 560 (e.g., the M1 metallization layer portion) is about 1.5. Further, the space between portions of the M1 metallization layer is about one fifteenth (1 / 15) of the length. This configuration is available through a low-cost and high-degree integrated passive device (IPD) process and implements a high-performance power combiner (PC) with the required separation that cannot be achieved with conventional TFR designs. This first TFR device structure 560 can correspond to the required radio frequency (RF) response and can also meet the design target specifications of a power combiner filter. The formation of the TFR device structure is shown in FIGS. 6A-6J.

[0034] FIGS. 6A-6J are diagrams showing a process 600 for manufacturing a radio frequency integrated circuit (RFIC) chip that includes a metal-insulator-metal (MIM) capacitor, a thin film resistor (TFR) device structure, and an inductor, according to aspects of the present disclosure. FIGS. 6A-6J may use reference numbers similar to those of the RFIC chip 450 shown in FIG. 4B. FIG. 6A shows step 1 of process 600 in which a high resistivity silicon (HRS) substrate 402 is prepared for manufacturing. The substrate 402 may be composed of silicon (Si), HRS, glass, gallium arsenide (GaAs), alumina, silicon carbide (SiC), or other similar substrate materials.

[0035] FIG. 6B is a diagram showing step 2 of process 600 in which oxide layer 404 is deposited on the surface of substrate 402. Oxide layer 404 may be composed of tetraethyl orthosilicate (TEOS) oxide material or other similar oxide materials. The M1 metallization material may be composed of alumina (Al), low-concentration copper-doped aluminum (AlCu), or other similar conductive materials.

[0036] FIG. 6C is a diagram showing step 3 of process 600 in which M1 metallization layer 602 is deposited on oxide layer 404 on the surface of substrate 402. M1 metallization layer 602 may be deposited on oxide layer 404 using a physical vapor deposition (PVD) process.

[0037] FIG. 6D is a diagram showing step 4 of process 600 in which dielectric layer 604 is deposited on the surface of M1 metallization layer 602. In this example, dielectric layer 604 is composed of silicon nitride (SiN) and is deposited on the surface of M1 metallization layer 602 using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0038] FIG. 6E is a diagram showing step 5 of process 600 in which M2 metallization layer 606 is deposited on the surface of dielectric layer 604. In this example, the deposition of M2 metallization layer 606 on the surface of dielectric layer 604 is performed using a physical vapor deposition (PVD) process. In some aspects of the present disclosure, M2 metallization layer 606 provides, for example, the second plate of MIM capacitor 410 and the TFR layer of TFR device structure 460 as shown in FIG. 4B.

[0039] FIG. 6F shows step 6 of process 600 in which the dielectric layer 604 and the M2 metallization layer 606 are subjected to a patterning and etching process to expose a portion of the M1 metallization layer 602. By applying a patterning and etching process to the dielectric layer 604 and the M2 metallization layer 606, the MIM insulator layer 414 and the second plate 416 of the MIM capacitor 410 are formed. Further, by applying a patterning and etching process to the dielectric layer 604 and the M2 metallization layer 606, a first portion 466 of the M2 metallization layer 606 is formed on a first portion 464 of the dielectric layer 604, and a second portion 474 of the M2 metallization layer 606 is formed on a second portion 472 of the dielectric layer 604. In some aspects of the present disclosure, the first portion 464 and the second portion 474 of the M2 metallization layer 606 are split to provide the required separation defined by the TFR device structure 460, as shown, for example, in FIG. 4B.

[0040] FIG. 6G shows step 7 of process 600 in which the M1 metallization layer 602 is subjected to a patterning and etching process to expose a portion of the oxide layer 404. By applying a patterning and etching process to the M1 metallization layer 602, the first plate 412 of the MIM capacitor 410 is formed. Further, by applying a patterning and etching process to the M1 metallization layer 602, a first portion 462 and a second portion 470 of the M1 metallization layer 602 are formed. By applying a patterning and etching process to the M1 metallization layer 602, a third portion 482 of the M1 metallization layer 602 is formed to enable the formation of the inductor 480. In some aspects of the present disclosure, the first portion 462 and the second portion 470 of the M1 metallization layer 602 are split to provide the required separation defined by the TFR device structure 460, as shown, for example, in FIG. 4B.

[0041] FIG. 6H shows step 8 of process 600 in which the first interlayer dielectric (ILD) layer 408 is deposited. The deposition of the first ILD layer 408 may be performed by using tetraethyl orthosilicate (TEOS) deposition of silicon oxide to form the first ILD layer 408. Alternatively, the first ILD layer 408 is fabricated by using polyimide (PI) to form the first ILD layer. Thereafter, a via opening process is performed to expose a portion of the second plate 416 and the first plate 412 of the MIM capacitor 410. Further, the via opening process is performed to expose a portion of the first portion 466 and the second portion 474 of the M2 metallization layer 606 and a portion of the third portion 482 of the M1 metallization layer 602 through the via opening 610.

[0042] FIG. 6I shows step 9 of process 600 in which a physical vapor deposition (PVD) sputtering and patterning process is performed to form portions of the M3 metallization layer and via V2, according to an aspect of the present disclosure. The sputtering and patterning process forms the first portion 418 and the second portion 419 of the M3 metallization layer, and these portions are coupled to the second plate 416 and the first plate 412 through the via V2 in the first ILD layer 408 to complete the formation of the MIM capacitor 410. Further, the sputtering and patterning process forms the second portion 469 of the M3 metallization layer, and this second portion 469 couples the first portion 466 of the M2 metallization layer to the second portion 474. The first portion 468 and the third portion 476 of the M3 metallization layer are formed and coupled to the first portion 466 and the second portion 474 of the M2 metallization layer through the via V2 to complete the formation of the TFR device structure 460. Further, various portions (e.g., 484, 486, 488, and 492) of the M3 metallization layer for the inductor 480 and the pad 490 are formed. The M1 metallization material may be composed of alumina (Al), low-concentration copper-doped aluminum (AlCu), or other similar conductive materials.

[0043] FIG. 6J shows step 10 of process 600 in which the plasma enhanced chemical vapor deposition (PECVD) and via opening process of the passivation layer 406 are performed on the M3 metallization layer. To expose certain portions of the M3 metallization layer (e.g., 418, 419, 468, 476, 484, 486, 488, and 492), a portion of the passivation layer 406 (e.g., silicon nitride (SiNx), silicon oxide (SiOx), etc.) is etched. The manufacturing process of an RFIC chip including MIM capacitors, TFR device structures, and inductors is shown, for example, in FIG. 7.

[0044] FIG. 7 is a process flow diagram showing a method for manufacturing a thin film resistor (TFR) device structure according to an aspect of the present disclosure. Method 700 begins at block 702, where a first portion and a second portion of a first metallization layer are formed on a substrate. For example, FIG. 6G shows the M1 metallization layer 602 that has been subjected to a patterning and etching process to expose a portion of the oxide layer 404. By applying a patterning and etching process to the M1 metallization layer 602, a first portion 462 and a second portion 470 of the M1 metallization layer 602 are formed.

[0045] At block 704, a first portion of a dielectric layer is formed on the first portion of the first metallization layer, and a second portion of the dielectric layer is formed on the second portion of the first metallization layer on the substrate. As shown in FIG. 6F, the dielectric layer 604 is subjected to a patterning and etching process to expose a portion of the M1 metallization layer 602. By applying a patterning and etching process to the dielectric layer 604, a first portion 464 of the dielectric layer 604 and a second portion 472 of the dielectric layer 604 are formed on the second portion 470 of the M1 metallization layer 602.

[0046] Referring back to FIG. 7, in block 706, a first portion of the second metallization layer is formed over a first portion of the dielectric layer, and a second portion of the second metallization layer is formed over a second portion of the dielectric layer. For example, as shown in FIG. 6F, the M2 metallization layer 606 is subjected to a patterning and etching process to expose a portion of the M1 metallization layer 602. By applying a patterning and etching process to the M2 metallization layer 606, a first portion 466 of the M2 metallization layer 606 is formed over a first portion 464 of the dielectric layer 604, and a second portion 474 of the M2 metallization layer 606 is formed over a second portion 472 of the dielectric layer 604. In some aspects of the present disclosure, the first portion 466 and the second portion 474 of the M2 metallization layer are split to provide a required separation defined by, for example, the TFR device structure 460 as shown in FIG. 4B.

[0047] In block 708, a first portion of a third metallization layer is formed to couple the first portion of the second metallization layer to the second portion of the second metallization layer. For example, as shown in FIG. 6I, a portion of the M3 metallization layer and via V2 according to aspects of the present disclosure are formed by a PVD sputtering and patterning process. By the sputtering and patterning process, a second portion 469 of the M3 metallization layer is formed, and this second portion 469 couples the first portion 466 of the M2 metallization layer 606 to the second portion 474. Further, as shown in FIG. 4B, a first portion 468 and a third portion 476 of the M3 metallization layer are formed and coupled to the first portion 466 and the second portion 474 of the M2 metallization layer via via V2 to complete the formation of the TFR device structure 460.

[0048] Aspects of the present disclosure relate to thin film resistor (TFR) device structures for implementing RF filters such as power combiners / dividers filters and directional couplers. In some aspects of the present disclosure, the TFR device structure includes a split first metallization layer (e.g., M1). The TFR device structure also includes a dielectric layer portion on the split portions of the M1 metallization layer. In some aspects of the present disclosure, the TFR device structure includes a split M2 metallization layer on each portion of the dielectric layer. In some aspects of the present disclosure, the M1 and M2 metallization layers are split to provide the required separation defined by the TFR device structure. This configuration of the TFR device structure can correspond to the required radio frequency (RF) response and can also meet the design target specifications of the power combiner / divider filter.

[0049] According to a further aspect of the present disclosure, an integrated circuit (IC) includes a thin film resistor (TFR) device structure. In one configuration, the IC has means for coupling a first portion of a second metallization layer to a second portion of the second metallization layer, the first portion of the second metallization layer extending across a first portion and a second portion of the first metallization layer. In one configuration, the coupling means may be a second portion 469 of an M3 metallization layer that couples a first portion 466 of an M2 metallization layer to a second portion 474 of the M2 metallization layer, as shown in FIG. 4B. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions enumerated by the aforementioned means.

[0050] FIG. 8 is a block diagram showing an exemplary wireless communication system 800 in which an aspect of the present disclosure can be advantageously employed. For illustrative purposes, FIG. 8 shows three remote units 820, 830, and 850 and two base stations 840. It will be recognized that a wireless communication system may have more remote units and base stations than shown. Remote units 820, 830, and 850 include integrated circuit (IC) devices 825A, 825C, and 825B that include the disclosed TFR device structures. It will also be recognized that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed TFR device structures. FIG. 8 shows forward link signals 880 from base station 840 to remote units 820, 830, and 850, and reverse link signals 890 from remote units 820, 830, and 850 to base station 840.

[0051] In FIG. 8, remote unit 820 is shown as a cellular phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a stationary remote unit within a wireless local loop system. For example, a remote unit may be a cellular phone, a handheld personal communication systems (PCS) unit, a portable data unit such as a personal digital assistant, a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a stationary data unit such as a meter reading device, or other device that stores or retrieves data or computer instructions, or a combination thereof. FIG. 8 shows remote units according to aspects of the present disclosure, but the present disclosure is not limited to these exemplary units. Aspects of the present disclosure can be suitably employed in many devices that include the disclosed TFR device structures.

[0052] FIG. 9 is a block diagram showing a design workstation used for circuit design, layout design, and logic design of semiconductor components such as the TFR device structure disclosed above. Design workstation 900 includes a hard disk 901 that contains operating system software, support files, and design software such as Cadence or OrCAD. Design workstation 900 also includes a display 902 for facilitating the design of circuit 910 or radio frequency (RF) components 912 such as cross-type capacitors. A storage medium 904 is provided for tangibly storing the design of circuit 910 or RF component 912 (e.g., the TFR device structure). The design of circuit 910 or RF component 912 can be stored on storage medium 904 in a file format such as GDSII or GERBER. Storage medium 904 can be a compact disc read-only memory (CD-ROM), digital versatile disc (DVD), hard disk, flash memory, or other suitable device. Further, design workstation 900 includes a drive device 903 for receiving input from or writing output to storage medium 904.

[0053] The data recorded on storage medium 904 can define logical circuit configurations, pattern data for photolithography masks, or mask pattern data for serial drawing tools such as electron beam lithography. The data can further include logic verification data such as timing diagrams and net circuits associated with logic simulations. By providing the data on storage medium 904, the design of circuit 910 or radio frequency (RF) component 912 is facilitated by reducing the number of processes for designing semiconductor wafers.

[0054] In the following numbered clauses, implementation examples will be described. 1. a substrate, and A thin film resistor (TFR) device structure, and an integrated circuit (IC) comprising, wherein the TFR device structure a first portion of a first metallization layer on a substrate and a second portion of the first metallization layer, and a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer, and a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer, and a first portion of a third metallization layer connecting the first portion of the second metallization layer to the second portion of the second metallization layer, and the IC comprising. 2. a first interlayer dielectric (ILD) layer on the surface of the substrate and on the first and second portions of the second metallization layer, and a first plurality of vias extending through the first ILD layer to the first portion of the second metallization layer, and a second plurality of vias extending through the first ILD layer to the second portion of the second metallization layer, and a second portion of a third metallization layer on the first ILD layer, the second portion being connected to the first portion of the second metallization layer via the first plurality of vias, and a third portion of a third metallization layer on the first ILD layer, the third portion being connected to the second portion of the second metallization layer via the second plurality of vias, and the IC of clause 1 further comprising. 3. a first plate composed of a first metallization layer on the surface of the substrate, and a MIM insulator layer on the first plate, and a second plate on the MIM insulator layer, a metal-insulator-metal (MIM) capacitor the IC of clause 1 or 2 further comprising. 4. On the surface of the substrate and a first interlayer dielectric (ILD) layer on the first plate and the second plate of the MIM capacitor, A first plurality of vias extending through the first ILD layer to the second plate of the MIM capacitor, A second plurality of vias extending through the first ILD layer to the first plate of the MIM capacitor, A second portion of the third metallization layer on the first ILD layer, which is coupled to the second plate of the MIM capacitor via the first plurality of vias, A third portion of the third metallization layer on the first ILD layer, which is coupled to the first plate of the MIM capacitor via the second plurality of vias, The IC according to clause 3, further comprising 5. A third portion of the first metallization layer on the surface of the substrate, A first interlayer dielectric (ILD) layer on the surface of the substrate and on the third portion of the first metallization layer, A plurality of vias extending through the first ILD layer to the third portion of the first metallization layer, A second portion of the third metallization layer on the first ILD layer, which is coupled to the third portion of the first metallization layer via the plurality of vias, An inductor comprising The IC according to any one of clauses 1 to 4, further comprising 6. The IC according to any one of clauses 1 to 5, further comprising a direct oxide layer on the surface of the substrate. 7. The IC according to any one of clauses 1 to 6, wherein the substrate comprises a high resistivity silicon (HRS) substrate. 8. The IC according to any one of clauses 1 to 7, wherein the IC is incorporated into an integrated passive device (IPD). 9. The IC according to clause 8, wherein the IPD is incorporated into a radio frequency (RF) filter. 10. The IC according to clause 9, wherein the RF filter is incorporated into a radio frequency front end (RFFE) module. 11. A method for manufacturing a thin film resistor (TFR) device structure, comprising: forming a first portion of a first metallization layer and a second portion of the first metallization layer on a substrate; forming a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer; forming a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer; forming a first portion of a third metallization layer to couple the first portion of the second metallization layer to the second portion of the second metallization layer; The method includes. 12. depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and on the first and second portions of the second metallization layer; forming a first plurality of vias that penetrate the first ILD layer and extend to the first portion of the second metallization layer; forming a second plurality of vias that penetrate the first ILD layer and extend to the second portion of the second metallization layer; forming a second portion of a third metallization layer on the first ILD layer and coupled to the first portion of the second metallization layer through the first plurality of vias; forming a third portion of a third metallization layer on the first ILD layer and coupled to the second portion of the second metallization layer through the second plurality of vias; The method of clause 11 further includes. 13. forming a first plate composed of a first metallization layer on the surface of the substrate; forming a metal-insulator-metal (MIM) insulator layer on the first plate; forming a second plate on the MIM insulator layer; The method of clause 11 or 12, further comprising 14. Depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and on the first plate and the second plate, Forming a first plurality of vias that penetrate the first ILD layer and extend to the second plate, Forming a second plurality of vias that penetrate the first ILD layer and extend to the first plate, Forming a second portion of a third metallization layer on the first ILD layer and coupled to the second plate via the first plurality of vias, Forming a third portion of a third metallization layer on the first ILD layer and coupled to the first plate via the second plurality of vias, The method of clause 13, further comprising 15. Forming a third portion of a first metallization layer on the surface of the substrate, Depositing a first interlayer dielectric (ILD) layer on the surface of the substrate and on the third portion of the first metallization layer, Forming a plurality of vias that penetrate the first ILD layer and extend to the third portion of the first metallization layer, Forming a second portion of a third metallization layer on the first ILD layer and coupled to the third portion of the first metallization layer via the plurality of vias, The method of any one of clauses 11 to 14, further comprising The method of any one of clauses 11 to 15, further comprising directly depositing an oxide layer on the surface of the substrate. 17. The method of any one of clauses 11 to 16, wherein the substrate comprises a high resistivity silicon (HRS) substrate. 18. The method of any one of clauses 11 to 17, further comprising integrating a thin film resistor (TFR) device structure into an integrated passive device (IPD). 19. The method of clause 18, further comprising integrating the IPD into a radio frequency (RF) filter. The method of clause 19, further comprising incorporating an RF filter into a radio frequency front end (RFFE) module.

[0055] In the case of a firmware and / or software implementation, the method may be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described herein. A machine-readable medium tangibly embodying instructions may be used when implementing the methods described herein. For example, software code may be stored in memory and executed by a processor unit. The memory may be implemented inside or outside the processor unit. As used herein, the term "memory" refers to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory and is not limited to a particular type of memory or number of memories, or type of medium on which memories are stored.

[0056] When implemented in firmware and / or software, the functionality can be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure, and computer-readable media encoded with a computer program. The computer-readable media includes physical computer storage media. The storage media may be a available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disk typically magnetically reproduces data, while disc optically reproduces data with a laser. Combinations of the above are also included within the scope of computer-readable media.

[0057] In addition to storage on computer-readable media, the instructions and / or data can be provided as signals on a transmission medium included in a communication device. For example, the communication device can include a transceiver that has signals indicative of the instructions and data. The instructions and data are configured to cause one or more processors to perform the functions recited in the claims.

[0058] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made to the specification without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "upper" and "lower" are used with respect to a substrate or an electronic device. Of course, when the substrate or the electronic device is inverted, the upper becomes the lower and the lower becomes the upper. In addition, in the case of being horizontal, the upper and the lower may refer to the sides of the substrate or the electronic device. Moreover, the scope of the present application is not intended to be limited to the specific configurations of the processes, machines, manufactures, compositions, means, methods, and steps described in this specification. As can be easily understood by those skilled in the art from the present disclosure, existing or future-developed processes, machines, manufactures, compositions, means, methods, or steps that perform substantially the same function as the corresponding configurations described in this specification or achieve substantially the same result may be utilized in accordance with the present disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions, means, methods, or steps within their scope.

[0059] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0060] Various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0061] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), registers, hard disk, a removable disk, a Compact Disc Read Only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). The ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside as discrete components in a user terminal.

[0062] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The computer-readable medium includes both a computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one place to another. The storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), compact disc read only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Additionally, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.As used herein, the terms "disk" and "disc" include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray (registered trademark) discs. A disk typically magnetically reproduces data, while a disc optically reproduces data using a laser. Combinations of the foregoing are also included within the scope of computer-readable media.

[0063] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Description of Reference Numerals

[0064] 100 RFFE Module 102 Power Amplifier 104 Filter 106 RF Switch Module 108 Passive Combiner 110 Application Processor 112 Tuner Circuit 112A First Tuner Circuit 112B Second Tuner Circuit 114 Antenna 115 Ground Terminal 116 Capacitor 118 Inductor 120 Wireless Transceiver (WTR) 130 Modem 144 Capacitor 146 Inductor 148 Capacitor 150 Wi-Fi module 152 WLAN module 160 First RF switch 162 First diplexer 164 Antenna 170 RFFE module 172 Filter 180 Second RF switch 190 Second diplexer 192 Antenna 200 Chip 202 Power supply 204 Clock 210 Chipset 300 RFFE module 302 Package ball 310 Substrate 312 Rewiring layer 320 IPD filter die 330 Substrate 340 Layer 350 Semiconductor die 360 Semiconductor substrate 370 BEOL layer 400 RFIC chip 402 Substrate 404 Oxide layer 406 Passivation layer 408 First ILD layer 410 MIM capacitor 412 First plate 414 MIM insulator layer 416 Second plate 418 First part 419 Second part 420 TFR device structure 422 First part 424 Second part 426 Dielectric layer 428 Metallization layer 430 First part 432 Second part 450 RFIC chip 460 TFR device structure 462 First part 464 First part 466 First part 468 First part 469 Second part 470 Second part 472 Second part 474 Second part 476 Third part 480 Inductor 482 Third part 490 Pad 500 Divider filter 510 Capacitor 550 Device structure 560 First TFR device structure 570 Exploded view 580 Inductor 590 Cross-sectional view 602 Metallization layer 604 Dielectric layer 606 Metallization layer 610 Via opening 800 Wireless communication system 820 Remote unit 825A, 825B, 825C Integrated circuit (IC) device 830 Remote unit 840 Base station 850 Remote unit 880 Forward link signal 890 Reverse link signal 900 Design workstation 901 Hard disk 902 Display 903 Drive device 904 Storage medium 910 Circuit 912 RF component

Claims

1. circuit board and Thin-film resistor (TFR) device structure, An integrated circuit (IC) comprising, wherein the TFR device structure is A first portion of the divided first metallization layer on the substrate and a second portion of the first metallization layer, wherein the first and second portions of the first metallization layer are separated from each other within the first metallization layer, The first portion of the dielectric layer on the first portion of the first metallization layer and the second portion of the dielectric layer on the second portion of the first metallization layer, A first portion of a divided second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer, wherein the first and second portions of the second metallization layer are separated from each other within the second metallization layer, The first portion of the divided third metallization layer is bonded to the first portion of the second metallization layer, An IC equipped with this feature.

2. A first interlayer dielectric (ILD) layer on the surface of the substrate and on the first and second portions of the second metallization layer, A plurality of first vias extending through the first ILD layer to the first portion of the second metallization layer, A plurality of second vias extending through the first ILD layer to the second portion of the second metallization layer, A second portion of the third metallization layer on the first ILD layer, which is coupled to the first portion of the second metallization layer via a plurality of first vias, A third portion of the third metallization layer on the first ILD layer, which is coupled to the second portion of the second metallization layer via a plurality of vias of the second, wherein the first, second, and third portions of the third metallization layer are separated from each other within the third metallization layer, The IC according to claim 1, further comprising the above.

3. A first plate comprising the first metallization layer on the surface of the substrate, The MIM insulating layer on the first plate, The second plate on the aforementioned MIM insulating layer, A metal-insulating-metal (MIM) capacitor equipped with The IC according to claim 1, further comprising the above.

4. The first interlayer dielectric (ILD) layer on the surface of the substrate and on the first plate and the second plate of the MIM capacitor, A plurality of first vias extending through the first ILD layer to the second plate of the MIM capacitor, A plurality of second vias extending through the first ILD layer to the first plate of the MIM capacitor, A second portion of the third metallization layer on the first ILD layer, which is coupled to the second plate of the MIM capacitor via a plurality of first vias, A third portion of the third metallization layer on the first ILD layer, which is coupled to the first plate of the MIM capacitor via a plurality of second vias, wherein the first, second, and third portions of the third metallization layer are separated from each other within the third metallization layer, The IC according to claim 3, further comprising the above.

5. A third portion of the first metallization layer on the surface of the substrate, wherein the first, second, and third portions of the first metallization layer are separated from each other within the first metallization layer, A first interlayer dielectric (ILD) layer on the surface of the substrate and on the third portion of the first metallization layer, A plurality of vias extending through the first ILD layer to the third portion of the first metallization layer, A second portion of the third metallization layer on the first ILD layer, which is coupled to the third portion of the first metallization layer via a plurality of vias, wherein the first and second portions of the third metallization layer are separated from each other within the third metallization layer, An inductor equipped with The IC according to claim 1, further comprising the above.

6. The IC according to claim 1, further comprising an oxide layer directly on the surface of the substrate.

7. The IC according to claim 1, wherein the substrate comprises a high-resistivity silicon (HRS) substrate.

8. The IC according to claim 1, wherein the IC is incorporated into an integrated passive device (IPD).

9. The IC according to claim 8, wherein the IPD is incorporated into a radio frequency (RF) filter.

10. The IC according to claim 9, wherein the RF filter is incorporated into a radio frequency front-end (RFFE) module.

11. A method for manufacturing a thin-film resistor (TFR) device structure, The method involves forming a first portion of a divided first metallization layer and a second portion of the first metallization layer on a substrate, wherein the first and second portions of the first metallization layer are separated from each other within the first metallization layer. A first portion of the dielectric layer is formed on the first portion of the first metallization layer, and a second portion of the dielectric layer is formed on the second portion of the first metallization layer, The first portion of a divided second metallization layer is formed on the first portion of the dielectric layer, and the second portion of the second metallization layer is formed on the second portion of the dielectric layer, wherein the first and second portions of the second metallization layer are separated from each other within the second metallization layer. To bond the first portion of the second metallization layer to the second portion of the second metallization layer, the first portion of the divided third metallization layer is formed. A method that includes this.

12. A first interlayer dielectric (ILD) layer is deposited on the surface of the substrate and on the first and second portions of the second metallization layer. To form a plurality of first vias that penetrate the first ILD layer and extend to the first portion of the second metallization layer, To form a second plurality of vias that penetrate the first ILD layer and extend to the second portion of the second metallization layer, A second portion of the third metallization layer is formed on the first ILD layer, coupled to the first portion of the second metallization layer via a plurality of first vias. The third portion of the third metallization layer is formed on the first ILD layer, coupled to the second portion of the second metallization layer via a plurality of second vias, wherein the first, second, and third portions of the third metallization layer are separated from each other within the third metallization layer. The method according to claim 11, further comprising:

13. A first plate composed of the first metallization layer is formed on the surface of the substrate, Forming a metal-insulating film-metal (MIM) insulating layer on the first plate, Forming a second plate on the aforementioned MIM insulating layer, The method according to claim 11, further comprising:

14. A first interlayer dielectric (ILD) layer is deposited on the surface of the substrate and on the first plate and the second plate. To form a plurality of first vias that penetrate the first ILD layer and extend to the second plate, To form a plurality of second vias that penetrate the first ILD layer and extend to the first plate, A second portion of the third metallization layer is formed on the first ILD layer, which is bonded to the second plate via a plurality of first vias. Forming a third portion of the third metallization layer on the first ILD layer, which is bonded to the first plate via a plurality of second vias, wherein the first, second, and third portions of the third metallization layer are separated from each other within the third metallization layer. The method according to claim 13, further comprising:

15. The third portion of the first metallization layer is formed on the surface of the substrate, wherein the first, second, and third portions of the first metallization layer are separated from each other within the first metallization layer. A first interlayer dielectric (ILD) layer is deposited on the surface of the substrate and on the third portion of the first metallization layer. Forming a plurality of vias that penetrate the first ILD layer and extend to the third portion of the first metallization layer, Forming a second portion of the third metallization layer on the first ILD layer, which is coupled to the third portion of the first metallization layer via a plurality of vias, wherein the first and second portions of the third metallization layer are separated from each other within the third metallization layer, The method according to claim 11, further comprising:

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