Information processing system, program, and information processing method

Abstract

To enhance power saving effect compared to a case not performing energization control for a sub-processor when operating software by scheduling a main processor or the sub-processor for each of a plurality of threads constituting the software under a multi-processor environment including the main processor and the sub-processor.SOLUTION: In a kernel space 20 on a DRAM 10 which implements self- refresh operation, there are loaded a kernel power saving control function unit 22 which stops power supply to a sub-CPU 4 in response to a shift instruction to a power-saving mode, and a thread control function unit 23 which controls execution of threads so that not to be scheduled by the sub-CPU 4 by changing CPU flags of all threads that current CPU flag values are '0' which allows any of CPUs 2 and 4 to perform scheduling to '1' which allows the main CPU 2 only to perform scheduling.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing system, a program, and an information processing method. [Background technology]

[0002] Conventionally, when executing a single computer program, multithreading has been used, where the program is divided into multiple threads and processed in parallel. In order to process threads simultaneously in parallel, a computer equipped with multiple CPUs, a so-called multi-CPU computer, can dramatically improve the processing speed of the program.

[0003] Incidentally, many multifunction peripherals have a function that automatically switches to a power-saving state called a power-saving mode or a sleep mode in order to reduce power consumption if the device remains inactive for a predetermined period of time while in a state where normal operation is possible. When a multifunction peripheral is equipped with multiple CPUs and executes software with a multi-thread configuration (the above-mentioned "program"), the main CPU included in the multiple CPUs will switch to a power-saving state in cooperation with the other sub-CPUs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-156907 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-257578 Summary of the Invention [Problem to be solved by the invention]

[0005] However, some threads may use the processing results of other threads. In other words, when multiple processors process threads contained in a single piece of software simultaneously in parallel, the order in which the threads are processed must be taken into consideration. Therefore, multiple processors require software-level control, such as determining and adjusting whether threads are ready to switch to power-saving mode in response to a command to switch to power-saving mode.

[0006] On the other hand, multiple processors cannot independently switch to the power-saving mode in response to a command to switch to the power-saving mode, and it is necessary to take into consideration the execution state of threads in the other processors, etc. Therefore, the main processor, which operates primarily among the multiple processors, must perform hardware-level control, such as determining and adjusting whether the other sub-processors can switch to the power-saving mode.

[0007] In other words, in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, the main processor needs to control both the threads and the sub-processor in order to improve power saving effects.

[0008] The present invention aims to improve power saving effects when software is executed in a multiprocessor environment having a main processor and a sub-processor by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, compared to when power control to the sub-processor is not performed. [Means for solving the problem]

[0009] The information processing system of the present invention comprises a multiprocessor, the multiprocessor being composed of a main processor that controls the execution of software consisting of multiple threads, and one or more sub-processors, and the main processor, in normal operating mode, schedules and executes each of the multiple threads included in the software to one of the processors that make up the multiprocessor, and in response to an instruction to transition from normal operating mode to power saving mode, sets the threads so that they are not scheduled to the sub-processors, and then controls the power supply to the sub-processors to be stopped.

[0010] Furthermore, in normal operation mode, the main processor schedules each of the multiple threads to either the main processor or the sub-processor in accordance with operation attribute information that is pre-set for each of the multiple threads, and which is set to either first information indicating that the thread can be scheduled only to the main processor, or second information indicating that the thread can be scheduled to either processor, and in response to an instruction to transition from normal operation mode to power saving mode, changes all of the settings of the operation attribute information that are set to second information to first information, and then controls the power supply to the sub-processor to be stopped.

[0011] The main processor also controls the sub-processor to resume power supply in response to an instruction to return from the power saving mode to the normal operating mode, and after power supply to the sub-processor has begun, returns the operating attribute information of the thread whose setting of the operating attribute information was changed from second information to first information when transitioning to the power saving mode to the second information.

[0012] The program of the present invention realizes the following functions in a computer having a multiprocessor consisting of a main processor that controls the execution of software consisting of multiple threads and one or more sub-processors: a function that causes the main processor to execute, in normal operating mode, a function that schedules and executes each of the multiple threads included in the software to one of the processors that make up the multiprocessor; and a function that causes the main processor to execute, in response to an instruction to transition from normal operating mode to power saving mode, a function that sets the threads so that they are not scheduled to the sub-processor, and then controls the power supply to the sub-processor to be stopped.

[0013] The information processing method of the present invention is characterized in that a multiprocessor provided in an information processing system, which is composed of a main processor that controls the execution of software composed of multiple threads and one or more sub-processors, schedules and executes each of the multiple threads included in the software to one of the processors that make up the multiprocessor during normal operation mode, and in response to an instruction to transition from normal operation mode to power saving mode, sets the threads so that they are not scheduled to the sub-processors, and then controls the power supply to the sub-processors to be stopped. [Effects of the Invention]

[0014] According to the invention described in claim 1, in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, the power saving effect can be improved compared to when power control to the sub-processor is not performed.

[0015] According to the invention as set forth in claim 2, it is possible to prohibit threads from being scheduled to the sub-processor during the power saving mode.

[0016] According to the invention as set forth in claim 3, a thread that could be scheduled to a sub-processor can be returned to its original state and controlled so that it can be executed by the sub-processor.

[0017] According to the invention described in claim 4, in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, the power saving effect can be improved compared to when power control to the sub-processor is not performed.

[0018] According to the invention described in claim 5, in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, the power saving effect can be improved compared to when power control to the sub-processor is not performed. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic block diagram showing a hardware configuration of an image forming apparatus according to an embodiment of the present invention; [Figure 2] FIG. 2 is a block diagram showing a controller according to the present embodiment. [Figure 3] 3 is a diagram showing an example of the data configuration of a thread management table 34 in the present embodiment. FIG. [Figure 4] 10 is a diagram showing an example of a data structure of an attribute information management area in the present embodiment. FIG. [Figure 5] FIG. 2 is a diagram illustrating a configuration of a run queue according to the present embodiment. [Figure 6A] 5 is a flowchart showing an operation mode switching process in the image forming apparatus according to the present embodiment. [Figure 6B] 6B is a flowchart continuing from FIG. 6A. [Figure 7]10A and 10B are diagrams illustrating an example of changes to data settings in an attribute information management area when transitioning to a power saving mode in the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0021] FIG. 1 is a schematic block diagram showing the hardware configuration of an image forming apparatus 1 according to the present embodiment. The image forming apparatus 1 is a multifunction peripheral equipped with various functions such as a printing function, a copying function, and a scanning function, and is a device with a built-in computer. The image forming apparatus 1 has a controller 100, an operation panel 102, a scanner 103, a printer 104, and a network interface (IF) 105. The controller 100 is a control board corresponding to the computer. The computer according to the present embodiment is a computer equipped with multiple CPUs, including a main CPU as a main processor and one or more sub-CPUs as sub-processors.

[0022] 2 is a block diagram showing a controller 100 in this embodiment. The controller 100 in this embodiment is a control board on which a main CPU 2, a plurality of sub-CPUs 4-1 to 4-n, a storage 6, a boot ROM 8, and a DRAM 10 are mounted and connected to a control line 12. Components that are not used in the description of this embodiment are omitted from the figure. Furthermore, the sub-CPUs 4-1 to 4-n are collectively referred to as "sub-CPUs 4" when there is no need to distinguish them from one another. There may be one or more sub-CPUs 4 in constructing a multi-CPU environment.

[0023] The image forming apparatus 1 in this embodiment is capable of executing priority-based multi-thread software. "Multi-thread software" refers to software in which a single piece of software, such as a software program such as an application, is divided into multiple threads. "Priority-based" means that a priority is assigned to each of the multiple threads, and the threads are processed in the order of their assigned priorities.

[0024] The main CPU 2 and sub-CPU 4 are equivalent in that they both execute threads, and also control the operation of various mechanisms mounted on the image forming apparatus 1, such as the scanner 103 and printer 104, in accordance with the operating system (hereinafter referred to as "OS") and applications loaded into the DRAM 10. Of these, the main CPU 2 controls the execution of the multithreaded software described above. In other words, of the multiple CPUs 2 and 4, the CPU that controls the execution of the multithreaded software is referred to as the main CPU 2, and the other CPU is referred to as the sub-CPU 4. The main CPU 2 is the only CPU that starts operating first when the image forming apparatus 1 is started up, and executes a boot loader at that time.

[0025] The storage 6 is a storage means for storing software such as the OS and applications. The boot ROM 8 is a storage means for storing a computer program that is automatically executed immediately after the computer is started up. This computer program is generally called a "boot loader."

[0026] DRAM (Dynamic RAM) 10 is a volatile semiconductor memory device into which the OS, applications, and especially the threads that make up a program are loaded. DRAM 10 is divided into a storage area (hereinafter referred to as "kernel space") 20 into which the kernel, which is the core of the OS (hereinafter also referred to as "OS kernel"), is loaded, and a storage area (hereinafter referred to as "user space") 30 into which software other than the kernel is loaded. DRAM 10 can be used in the same way as before.

[0027] The DRAM 10 of this embodiment can operate in a self-refresh mode. "Self-refresh mode" is a method in which a refresh command signal is automatically generated inside the DRAM 10 when the DRAM 10 is not operating, and a refresh operation is performed. "Refresh" refers to the operation of periodically rewriting data while the DRAM 10 is operating by periodically replenishing charge in the memory cells. Refreshing preserves data in the DRAM 10 without erasing it, and can also be expected to have a power-saving effect. When the DRAM 10 of this embodiment transitions to a power-saving mode, power is no longer supplied, and therefore the DRAM 10 is subject to refresh operation control in the power-saving mode.

[0028] Incidentally, the "power saving mode" is an operation mode different from the normal mode, which is a normal state in which devices such as the scanner 103 mounted on the image forming apparatus 1 are operable, and is an operation mode in which the image forming apparatus 1 enters a power saving state by stopping the supply of power to devices such as the scanner 103. In the power saving mode of this embodiment, power supply to the DRAM 10 is stopped. If the image forming apparatus 1 remains inactive for a predetermined period of time, the operation mode of the image forming apparatus 1 automatically transitions from the normal mode to the power saving mode. This limits the operation of functions such as the scanner function provided by the image forming apparatus 1, but reduces power consumption.

[0029] In this embodiment, the user space 30 includes a thread initial setting unit 31, a user-level power saving control function unit 32, an OS API (Application Programming Interface) 33, and a thread management table .

[0030] The thread initial setting unit 31 performs initial settings for each thread that is created. The initial settings are registered in a thread management table 34. The user-level power saving control function unit 32 has a function for making requests to the OS kernel and controlling settings when transitioning to power saving mode. The OS API 33 is an API that is used when the user space 30 calls the OS kernel and exchanges information.

[0031] FIG. 3 is a diagram showing an example of the data configuration of the thread management table 34 in this embodiment. The thread management table 34 holds, in table format, operation attribute information for managing the content of attribute settings for each thread. As shown in FIG. 3, a record set for a thread is configured by associating the following items with thread identification information (tID) and the entry point, priority, stack address, stack size, and CPU flag. The items constituting the record may be the same as in the past. Among these, the priority and CPU flag used in this embodiment will be described. Priority is priority information regarding the execution order of the thread, and threads with higher priority are executed preferentially. The CPU flag is set to either a flag value "1" as first information indicating that the thread can be scheduled only on the main CPU 2, or a flag value "0" as second information indicating that the thread can be scheduled on any of the CPUs 2 and 4. Either flag value is set to the CPU flag by a user, such as the owner of the software constituting the thread.

[0032] Each of the components 31 to 33 in the user space 30 is realized by cooperative operation between the main CPU 2 or the sub CPU 4 and the programs running on the CPUs 2 and 4. In addition, the thread management table 34 is stored in the storage 6 and is loaded into the user space 30 in the DRAM 10 for use.

[0033] On the other hand, the kernel space 20 in this embodiment includes a scheduler 21, a kernel power saving control function unit 22, a thread control function unit 23, and a run queue 24.

[0034] The scheduler 21 schedules threads, such as allocating threads to either the CPUs 2 and 4. The kernel power saving control function unit 22 has a function of controlling the transition to the power saving mode in cooperation with the user level power saving control function unit 32 when transitioning to the power saving mode. The thread control function unit 23 controls the execution of threads connected to the run queue 24. Executable threads waiting to be processed by the CPUs 2 and 4 are queued in the run queue 24.

[0035] Each of the components 21 to 23 in the kernel space 20 is realized by cooperative operation between the main CPU 2 or the sub CPU 4 and programs running on the CPUs 2 and 4. The run queue 24 is stored in the storage 6 and is loaded into the kernel space 20 of the DRAM 10 for use.

[0036] The aforementioned components 21 to 23, 31 to 33 are naturally pre-installed in the image forming apparatus 1, but they can also be provided via a communication means or stored on a computer-readable recording medium such as a USB memory.

[0037] Next, the operation of this embodiment will be described.

[0038] The CPUs 2 and 4 in this embodiment execute threads assigned by the scheduler 21 from among a plurality of threads (hereinafter also referred to as "multi-threads") that make up the multi-thread software. Here, we will explain the initialization process of the multi-threads required for the scheduler 21 to perform scheduling.

[0039] As described above, the thread initial setting unit 31 initializes attribute information for each thread to be generated, and manages the attribute information by setting and registering it in the thread management table 34 shown in Fig. 3. The priority and CPU flag to be set in the thread management table 34 are set for each thread by the user with reference to the contents of the software.

[0040] The thread initial setting unit 31 calls the OS API 33 for thread initialization, and passes the operational attribute information of each thread set in the thread management table 34 to the thread control function unit 23 .

[0041] The thread control function unit 23 copies and stores the received operation attribute information of each thread in an internal attribute information management area. An example of the data structure of the attribute information management area set for each thread by the thread control function unit 23 to manage the operation attribute information of the thread is shown in Figure 4. As is clear from a comparison of Figures 3 and 4, although the data structures for managing the operation attribute information are different, they basically manage the same information.

[0042] Fig. 5 is a diagram showing a schematic configuration of the run queue 24 used when performing scheduling. In Fig. 5, priorities are listed in the priority index list in the order of priority 1 to priority n. Threads are associated with and queued to the priorities included in the priority index list.

[0043] When a thread becomes executable, the thread control function unit 23 refers to the priority set in the attribute information management area corresponding to the thread and registers it in the priority index list corresponding to the priority. If another thread is already registered at the priority to be registered, the thread control function unit 23 queues the thread at the end of the other thread. The queuing method used by the thread control function unit 23 may be the same as before.

[0044] After the multi-threads are initialized as described above, the scheduler 21 performs scheduling.

[0045] That is, when the scheduler 21 is started, it selects a thread with a high priority from the list of threads registered in the run queue 24, and allocates resources such as CPU 2 or 4 to the selected thread for execution. When scheduling, the scheduler 21 schedules the thread to the main CPU 2 or sub CPU 4 in accordance with the CPU flag set in the operation attribute information of the selected thread. Specifically, if the CPU flag of the selected thread is "1", the scheduler 21 allocates the main CPU 2 to the thread. If the CPU flag of the selected thread is "0", the scheduler 21 allocates the thread to either CPU 2 or 4 in accordance with a predetermined rule. The predetermined rule may be, for example, a CPU waiting for processing, a CPU with the smallest load, etc. The predetermined rule itself may be the same as before.

[0046] When the image forming apparatus 1 is started and operating in normal mode, a thread is registered in the run queue 24 under execution control by the OS kernel when it becomes executable, and is scheduled and executed. Execution of the thread causes the scanner 103 and printer 104 to operate.

[0047] Next, the operation mode switching process executed when the operation mode of the image forming apparatus 1 transitions from the normal mode to the power saving mode, or from the power saving mode to the normal mode, will be described using the flowcharts shown in Figures 6A and 6B.

[0048] When the image forming apparatus 1 is operating in the normal mode, it continues to operate in the normal mode unless a predetermined condition for transitioning to the power saving mode is met, such as there being no external input via the network for a certain period of time (N in step S101).When the predetermined condition for transitioning to the power saving mode is met (Y in step S101), it starts preparation for the power saving mode.

[0049] First, when the user level power saving control function unit 32 detects that it is time to transition to the power saving mode, it calls the OS API (system call) 33 and starts preparations for transition to the power saving mode in cooperation with the OS kernel.

[0050] The kernel power saving control function unit 22 constituting the OS kernel sets all the sub-CPUs 4 to an unavailable state (step S102) by setting an unavailable flag set corresponding to each of the sub-CPUs 4 in response to the call of the OS API 33. The unavailable flag is managed within the OS kernel.

[0051] Furthermore, the thread control function unit 23 constituting the OS kernel temporarily saves the current setting value of the CPU flag included in the attribute information management area corresponding to each thread (step S103), and then changes the CPU flag of all threads whose current setting value is "0" to "1" (step S104). In other words, the threads are scheduled only to the main CPU 2 and are set so as to be executable only by the main CPU 2. An example of a case where the setting of the CPU flag in the attribute information management area is changed when transitioning to this power saving mode is shown in FIG. 7. The example shown in FIG. 7 shows an example of a case where the changed setting value is temporarily saved in the setting area of ​​the CPU flag.

[0052] In this embodiment, control is performed in the above manner so that threads are not scheduled to the sub-CPU 4.

[0053] The user-level power saving control function unit 32 instructs the thread to prepare for transition to a power saving state in response to the invocation of the OS API (system call) 33 as described above (step S105). In response to this instruction, the thread transitions to a state that can accommodate transition to the power saving mode. The user-level power saving control function unit 32 waits until all threads return a power saving state transition possible status indicating that they are ready to transition to the power saving state (N in step S106). Then, when all threads return a status indicating that they are ready to transition to the power saving state (Y in step S106), the user-level power saving control function unit 32 instructs the OS kernel to transition to a power saving state. In response to this power saving transition instruction, the kernel power saving control function unit 22 stops power supply to the sub-CPU 4 to stop its operation (step S107).

[0054] The user-level power saving control function unit 32 also instructs each thread running on the main CPU 2 to transition to the power saving mode (step S108). At this point, since the CPU flags of all threads are set to "1" in step S104, all running threads are subject to the power saving mode transition instruction.

[0055] All running threads will transition to the power saving mode in response to this instruction, but the user level power saving control function unit 32 waits until all threads have transitioned to the power saving mode (N in step S109). Then, when it is confirmed that all threads have transitioned to the power saving mode (Y in step S109), the user level power saving control function unit 32 notifies the OS kernel of this fact. In response to this notification, the kernel power saving control function unit 22 transitions the image forming device 1 to the power saving mode (step S110).

[0056] When the image forming apparatus 1 shifts to the power saving mode, the supply of power to devices such as the scanner 103 and the printer 104 is stopped. In addition, the DRAM 10 in this embodiment enters a self-refresh state by starting a self-refresh operation.

[0057] In this way, the image forming apparatus 1 operates in the power saving mode, which results in power saving since the supply of power to the scanner 103, the sub-CPU 4, the DRAM 10, etc. is stopped.

[0058] Thereafter, the image forming apparatus 1 continues to operate in the power saving mode until a predetermined condition for transitioning to the normal mode, such as a user operating the operation panel 102, is met (N in step S111). When a predetermined condition for transitioning to the normal mode is met (Y in step S111), the OS kernel running on the main CPU 2 transitions the image forming apparatus 1 to the normal mode (step S112). Specifically, it starts supplying power to devices such as the scanner 103 and printer 104, making them operable. The OS kernel also controls the sub-CPU 4 to resume power supply. This causes the sub-CPU 4 to return to an operable state. In addition, the DRAM 10 in this embodiment returns from the self-refresh state.

[0059] Furthermore, the kernel power saving control function unit 22 sets all the sub CPUs 4 to an available state by, for example, clearing the unavailable flag set corresponding to each of the sub CPUs 4 (step S113). As a result, all the sub CPUs 4 return to a state in which they can execute threads.

[0060] Subsequently, when the transition from the power saving mode to the normal mode is completed, the user level power saving control function unit 32 calls the OS API (system call) 33.

[0061] The thread control function unit 23 constituting the OS kernel changes the CPU flag setting included in the attribute information management area for the threads that were changed from "0" to "1" when the OS kernel was switched to the power saving mode back to "0" (step S114). As a result, threads that were originally schedulable on any of the CPUs 2 and 4 are assigned resources of any of the CPUs 2 and 4 and become executable.

[0062] According to this embodiment, the operation mode of the image forming apparatus 1 is switched as described above.

[0063] When threads with priority control, specifically threads for which a priority item is set in the thread management table, are run in a multi-CPU environment, adjustments must be made between the threads distributed across multiple CPUs 2 and 4 when switching to power-saving mode; that is, adjustments must be made at the software level. Adjustments such as stop control between CPUs must also be made; that is, adjustments must be made at the hardware level. In other words, not only must adjustments be made separately for the hardware and software, but the two must also work together, which makes things complicated.

[0064] In this embodiment, when priority-based multithreaded software is operated in a multi-CPU environment, when the system transitions to power saving mode, all threads that can be executed by multiple CPUs 2 and 4 are changed to a state where they can be executed only by the main CPU 2, and the sub-CPU 4 is controlled to be stopped.In other words, by changing the system environment from a multi-CPU to a single CPU, the system can transition to power saving mode without making complex adjustments to the software and hardware.

[0065] Incidentally, the main CPU 2 is the first and only CPU to operate when the image forming apparatus 1 is turned on, and is the only CPU that executes the boot loader. Therefore, in this embodiment, the main CPU 2 is selected to represent the image forming apparatus 1 as a single CPU that can execute all threads when transitioning to power saving mode, but one sub-CPU 4 may also be selected.

[0066] In this embodiment, the "information processing system" is described as being composed of a single image forming device 1 with a built-in computer, as an example, but it may also be composed of an information processing device such as a PC or multiple devices.

[0067] In the above embodiments, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0068] Furthermore, the operation of the multiprocessor in the above embodiments may be performed by multiple processors located at physically separate locations working together. The order of the processor operations is not limited to the order described in the above embodiments, and may be changed as appropriate.

[0069] (Addendum) (((1))) It has multi-processors, The multiprocessor includes: a main processor that controls the execution of software that is configured by multiple threads; one or more sub-processors; It consists of The main processor In a normal operation mode, each of a plurality of threads included in the software is scheduled to be executed by one of the processors constituting the multiprocessor; In response to an instruction to transition from a normal operation mode to a power saving mode, a setting is made so that threads are not scheduled on the sub-processor, and then power to the sub-processor is stopped. An information processing system comprising: (((2))) The main processor In a normal operation mode, each of the plurality of threads is scheduled to either the main processor or the sub-processor in accordance with operation attribute information that is preset for each of the plurality of threads, and the operation attribute information is either first information indicating that the thread can be scheduled only to the main processor or second information indicating that the thread can be scheduled to any processor; in response to an instruction to transition from the normal operation mode to the power saving mode, change all of the settings of the operation attribute information in which the second information is set to the first information, and then control so as to stop power supply to the sub-processor; The information processing system according to (((1))) is characterized in that: (((3))) The main processor controlling the sub-processor to resume power supply in response to an instruction to return from the power saving mode to the normal operation mode; after the power supply to the sub-processor is started, returning the setting of the operation attribute information of the thread that changed the setting of the operation attribute information from the second information to the first information when the sub-processor was switched to the power saving mode to the second information; The information processing system according to (((2))) is characterized in that: (((4))) A computer having a multiprocessor consisting of a main processor that controls the execution of software consisting of multiple threads and one or more sub-processors, a function to be executed by the main processor, which, in a normal operation mode, schedules and executes each of a plurality of threads included in the software on one of the processors constituting the multiprocessor; a function to be executed by the main processor, which controls the sub-processor to stop power supply to the sub-processor after setting the sub-processor so that threads are not scheduled in response to an instruction to transition from a normal operation mode to a power saving mode; A program to achieve this. (((Claim 5))) A multiprocessor included in an information processing system is composed of a main processor that controls the execution of software composed of multiple threads and one or more sub-processors. In a normal operation mode, each of a plurality of threads included in the software is scheduled to be executed by one of the processors constituting the multiprocessor; In response to an instruction to transition from a normal operation mode to a power saving mode, a setting is made so that threads are not scheduled on the sub-processor, and then power to the sub-processor is stopped. An information processing method comprising:

[0070] According to the invention described in (((1))), in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, it is possible to improve the power saving effect compared to when power control to the sub-processor is not performed. According to the invention described in (((2))), it is possible to prohibit a thread from being scheduled to a sub-processor during power saving mode. According to the invention described in (((3))), a thread that could be scheduled to a sub-processor can be returned to its original state and controlled so that it can be executed by the sub-processor. According to the invention described in (((4))), in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, it is possible to improve the power saving effect compared to when power control to the sub-processor is not performed. According to the invention described in (((5))), in a multiprocessor environment having a main processor and a sub-processor, when software is executed by scheduling each of the multiple threads that make up the software to the main processor or the sub-processor, it is possible to improve the power saving effect compared to when power control to the sub-processor is not performed. [Explanation of symbols]

[0071] 1 image forming device, 2 main CPU, 4-1 to 4-n sub-CPUs, 6 storage, 8 boot ROM, 12 control line, 20 kernel space, 21 scheduler, 22 kernel power saving control function unit, 23 thread control function unit, 24 run queue, 30 user space, 31 thread initial setting unit, 32 user level power saving control function unit, 33 OS API, 34 thread management table, 100 controller, 102 operation panel, 103 scanner, 104 printer, 105 network interface (IF).

Claims

1. It has multi-processors, The multiprocessor includes: a main processor that controls the execution of software that is configured by multiple threads; one or more sub-processors; It consists of The main processor In a normal operation mode, each of a plurality of threads included in the software is scheduled to be executed by one of the processors constituting the multiprocessor; In response to an instruction to transition from the normal operation mode to the power saving mode, a setting is made so that threads are not scheduled on the sub-processor, and then power to the sub-processor is stopped. An information processing system comprising:

2. The main processor In a normal operation mode, each of the plurality of threads is scheduled to either the main processor or the sub-processor in accordance with operation attribute information that is preset for each of the plurality of threads, and the operation attribute information is either first information indicating that the thread can be scheduled only to the main processor or second information indicating that the thread can be scheduled to any processor; in response to an instruction to transition from the normal operation mode to the power saving mode, changing all of the settings of the operation attribute information currently set to second information to first information, and then controlling to stop power supply to the sub-processor; 2. The information processing system according to claim 1, wherein:

3. The main processor controlling the sub-processor to resume power supply in response to an instruction to return from the power saving mode to the normal operation mode; after the power supply to the sub-processor is started, returning the setting of the operation attribute information of the thread that has been changed from the second information to the first information when the sub-processor is switched to the power saving mode to the second information; 3. The information processing system according to claim 2.

4. A computer having a multiprocessor including a main processor that controls the execution of software consisting of multiple threads and one or more sub-processors, a function to be executed by the main processor, which, in a normal operation mode, schedules and executes each of a plurality of threads included in the software on one of the processors constituting the multiprocessor; a function to be executed by the main processor, which controls the sub-processor to stop power supply to the sub-processor after setting the sub-processor so that threads are not scheduled in response to an instruction to transition from a normal operation mode to a power saving mode; A program to achieve this.

5. A multiprocessor included in an information processing system and configured with a main processor that controls the execution of software configured with multiple threads and one or more sub-processors, In a normal operation mode, each of a plurality of threads included in the software is scheduled to be executed by one of the processors constituting the multiprocessor; In response to an instruction to transition from the normal operation mode to the power saving mode, a setting is made so that threads are not scheduled on the sub-processor, and then power to the sub-processor is stopped.

1. An information processing method comprising:

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