Display and head-mounted display device

Abstract

To provide a display and a head-mounted display device including a plurality of single crystal semiconductor substrates.SOLUTION: A display includes: a first single crystal semiconductor substrate that is formed with a plurality of pixel circuits arrayed in a first direction and a second direction intersecting the first direction and including first transistors; a second single crystal semiconductor substrate that is arranged on the first single crystal semiconductor substrate, includes a plurality of light-emitting devices, and is arranged with a plurality of sub-pixels arrayed in the first direction and the second direction; and a connection wiring layer that is arranged between the light-emitting device and the first single crystal semiconductor substrate, and includes a plurality of bridge lines each electrically connected with any one of the pixel circuits and any one of the sub-pixels. The second single crystal semiconductor substrate includes a plurality of through holes arranged with conductive vias electrically connected with the respective light-emitting devices of the plurality of sub-pixels and the bridge lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device and a head-mounted display device. [Background technology]

[0002] A head-mounted display device (HMD) is an image display device worn on the user's head in the form of glasses or a helmet, and focuses images at a short distance in front of the user's eyes. Head-mounted display devices can realize virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display device uses multiple lenses to magnify and display images displayed on a small display device. Therefore, the display device used in the head-mounted display device needs to provide high-resolution images, for example, images with a resolution of 3000 PPI (Pixels Per Inch) or more. For this reason, a high-resolution, small-sized organic light-emitting display device, called an OLEDoS (Organic Light Emitting Diode on Silicon), is used as the display device used in the head-mounted display device. An OLEDoS is a device that displays images by arranging organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 10-2020-0079389 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a micro-display device including a plurality of single crystal semiconductor substrates different from one another, and a head-mounted display device including the same.

[0006] SUMMARY OF THE INVENTION An object of the present invention is to provide a micro display device realized by an efficient layout design of interconnection wiring that connects two different semiconductor substrates, and a method for manufacturing the same.

[0007] The objectives of the present invention are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] a second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate and having a plurality of sub-pixels arranged in the first and second directions, the sub-pixels including a plurality of light-emitting elements; and a connecting wiring layer disposed between the light-emitting elements and the first single-crystal semiconductor substrate, the connecting wiring layer including a plurality of bridge lines electrically connected to any one of the pixel circuits and any one of the sub-pixels, respectively; the second single-crystal semiconductor substrate including a plurality of through-holes in which conductive vias electrically connected to the light-emitting elements and the bridge lines of each of the sub-pixels are disposed; the connecting wiring layer including a first conductive layer in which a first bridge line is disposed, a second conductive layer in which a second bridge line is disposed, and an interlayer insulating layer between the first conductive layer and the second conductive layer;

[0009] Among the plurality of sub-pixels, the outermost sub-pixels in the first direction and the outermost sub-pixels in the second direction may be electrically connected to different first bridge lines.

[0010] Among the plurality of sub-pixels, sub-pixels adjacent to the outermost sub-pixels in the first and second directions may be electrically connected to different second bridge lines.

[0011] The sub-pixels of a first pixel row arranged on one side in the first direction may be electrically connected to the pixel circuits positioned side by side in the first direction, and the sub-pixels of a second pixel row adjacent to one side of the first pixel row in the second direction may be electrically connected to the pixel circuits positioned not side by side in the first direction.

[0012] The bridge line electrically connected to the sub-pixels of the first pixel row may be disposed to overlap the sub-pixels of the first pixel row.

[0013] The bridge line electrically connected to the sub-pixels of the second pixel row may be disposed so as to at least partially overlap the sub-pixels of the first pixel row.

[0014] A first sub-pixel disposed at the outermost side of the first pixel row may be connected to the first bridge line, a second sub-pixel adjacent to the first sub-pixel in the first pixel row may be connected to the second bridge line, and the first bridge line connected to the first sub-pixel may be disposed on the other side of the second bridge line connected to the second sub-pixel in the second direction.

[0015] The sub-pixels of a first pixel column arranged on the other side of the second direction may be electrically connected to the pixel circuits positioned side by side in the second direction, and the sub-pixels of a second pixel column adjacent to the first pixel column on the other side of the first direction may be electrically connected to the pixel circuits positioned not side by side in the second direction.

[0016] A first sub-pixel disposed at the outermost side of the first pixel column may be connected to the first bridge line, a second sub-pixel adjacent to the first sub-pixel in the first pixel column may be connected to the second bridge line, and the first bridge line connected to the first sub-pixel may be disposed on one side of the second bridge line connected to the second sub-pixel in the first direction.

[0017] Among the plurality of sub-pixels arranged in a diagonal direction from the first single crystalline semiconductor substrate, a first sub-pixel arranged at an outermost position may be connected to the first bridge line, and a second sub-pixel diagonally adjacent to the first sub-pixel may be connected to the second bridge line, and the second bridge line may be arranged above the first bridge line.

[0018] A position of one end of the first bridge line within the sub-pixel may be different from a position of one end of the second bridge line within the sub-pixel adjacent to the sub-pixel connected to the first bridge line.

[0019] The plurality of sub-pixels may include overlapping sub-pixels that overlap the pixel circuit and non-overlapping sub-pixels that do not overlap the pixel circuit, and a portion of a bridge line connected to the non-overlapping sub-pixels among the plurality of bridge lines may not overlap the first single crystalline semiconductor substrate.

[0020] Among the plurality of bridge lines, the bridge lines connected to the non-overlapping sub-pixels may be longer than the bridge lines connected to the overlapping sub-pixels.

[0021] Among the plurality of bridge lines, the bridge line connected to the overlapping sub-pixel may have a zigzag shape.

[0022] The area of ​​the first single crystal semiconductor substrate may be smaller than the area of ​​the second single crystal semiconductor substrate.

[0023] A display device according to one embodiment for solving the above problem includes a first single-crystal semiconductor substrate on which a plurality of first transistors are formed and a plurality of pixel circuits including the first transistors are formed; a second single-crystal semiconductor substrate disposed on the first single-crystal semiconductor substrate and on which a plurality of sub-pixels including a plurality of light-emitting elements are disposed; and a connecting wiring layer disposed between the light-emitting elements and the first single-crystal semiconductor substrate, wherein the second single-crystal semiconductor substrate includes a plurality of through holes in which conductive vias electrically connected to the light-emitting elements of each of the sub-pixels are disposed, the connecting wiring layer including a plurality of conductive layers including a plurality of bridge lines and a plurality of bridge contacts, and an interlayer insulating layer disposed between the conductive layers, and the sub-pixels include a first sub-pixel connected to one of the pixel circuits via a first bridge line disposed in a first conductive layer of the connecting wiring layer, and a second sub-pixel connected to one of the pixel circuits via a second bridge line in a second conductive layer disposed on the first conductive layer of the connecting wiring layer.

[0024] The second bridge line may be electrically connected to a first bridge contact disposed on the first conductive layer, and the first bridge line may be electrically connected to a second bridge contact disposed on the second conductive layer.

[0025] The second bridge line and the second bridge contact may each be connected to one of the conductive vias.

[0026] At least a portion of the first bridge line may be connected to a second bridge line disposed on the second conductive layer.

[0027] According to one embodiment of the present invention, there is provided a head-mounted display device that is worn on a user's body and includes a frame corresponding to a left eye and a right eye, a plurality of display devices arranged on the frame, and lenses arranged on each of the plurality of display devices, the display devices being arranged in a first direction and a second direction intersecting the first direction, the head-mounted display device including a first single-crystal semiconductor substrate on which a plurality of pixel circuits each including a first transistor are formed, a second single-crystal semiconductor substrate arranged on the first single-crystal semiconductor substrate, the second single-crystal semiconductor substrate including a plurality of light-emitting elements and on which a plurality of sub-pixels arranged in the first direction and the second direction are arranged, and a second single-crystal semiconductor substrate arranged between the light-emitting elements and the first single-crystal semiconductor substrate, the second single-crystal semiconductor substrate including one of the pixel circuits and a front and a connecting wiring layer including a plurality of bridge lines electrically connected to any one of the sub-pixels, wherein the second single-crystal semiconductor substrate includes a plurality of through holes in which conductive vias electrically connected to the light-emitting elements of each of the plurality of sub-pixels and the bridge lines are disposed, the connecting wiring layer including a first conductive layer in which a first bridge line is disposed, a second conductive layer in which a second bridge line is disposed, and an interlayer insulating layer between the first conductive layer and the second conductive layer, wherein at least some of the plurality of sub-pixels are electrically connected to the first bridge line, and some of other sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line.

[0028] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0029] The display device according to one embodiment includes two different single crystal semiconductor substrates, and the manufacturing process of the lower single crystal semiconductor substrate allows multiple manufacturing processes per unit wafer substrate, thereby improving manufacturing yield.

[0030] A display device according to an embodiment may have an efficient layout design in which interconnection lines connecting two different single crystal semiconductor substrates do not interfere with each other even when the single crystal semiconductor substrates have relatively small areas.

[0031] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is an exploded perspective view of a display device according to an embodiment; [Figure 2] 2 is a plan view showing an example of a driving unit shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a plan view showing an example of a display unit shown in FIG. [Figure 4] 1 is a block diagram illustrating a display device according to an embodiment. [Figure 5] FIG. 2 is an equivalent circuit diagram of one pixel according to an embodiment. [Figure 6] 1 is a schematic cross-sectional view of a display device according to an embodiment. [Figure 7] FIG. 2 is a schematic diagram illustrating a rear surface of a display device according to an embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a display device according to another embodiment. [Figure 9] FIG. 2 is a schematic cross-sectional view of a drive unit according to an embodiment. [Figure 10] 3 is a plan view illustrating first electrodes, light-emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display area of ​​a display unit according to an embodiment. FIG. [Figure 11] 10 is a plan view showing first electrodes, light-emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display unit according to another embodiment. FIG. [Figure 12] FIG. 2 is a cross-sectional view showing a part of a display unit according to an embodiment. [Figure 13] 1 is a diagram illustrating a schematic layout of connecting lines that connect pixel circuit units and sub-pixels in a display area of ​​a display device according to an embodiment; [Figure 14] 1 is a schematic diagram illustrating a connection between a sub-pixel and a pixel circuit by a connecting line in a display device according to an embodiment; [Figure 15]3 is a schematic cross-sectional view illustrating an example of an interconnection layer of a display device according to an embodiment. FIG. [Figure 16] FIG. 10 is a schematic cross-sectional view showing an example of an interconnection layer of a display device according to another embodiment. [Figure 17] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in the first region of FIG. 14. FIG. [Figure 18] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in the first region of FIG. 14. FIG. [Figure 19] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in the second region of FIG. 14. FIG. [Figure 20] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in the second region of FIG. 14. FIG. [Figure 21] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in a third region of FIG. 14. FIG. [Figure 22] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in a third region of FIG. 14. FIG. [Figure 23] 15 is a schematic diagram showing connections between sub-pixels and pixel circuits by connecting lines in a third region of FIG. 14. FIG. [Figure 24] 1 is a schematic diagram illustrating an arrangement of connecting lines and vias connecting sub-pixels in a display device according to an embodiment; [Figure 25] FIG. 10 is a diagram illustrating an example of a shape of a bridge line according to an embodiment. [Figure 26] 1 is a diagram illustrating an example of a cross-sectional connection structure of a connection wiring according to an embodiment; [Figure 27] 10 is a diagram showing a schematic arrangement of connecting lines that connect pixel circuit units and sub-pixels in a display area of ​​a display device according to another embodiment. FIG. [Figure 28] FIG. 10 is a schematic cross-sectional view showing an example of an interconnection layer of a display device according to another embodiment. [Figure 29] 1 is a perspective view showing a head-mounted display device according to an embodiment. [Figure 30]FIG. 30 is an exploded perspective view showing an example of the head-mounted display device of FIG. 29. [Figure 31] 1 is a perspective view showing a head-mounted display device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0033] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0034] When an element or layer is referred to as being "on" another element or layer, this includes being immediately on top of or between other layers or elements. Similarly, when references are made to "below," "left," and "right," this includes being immediately adjacent to or between other layers or materials. Like reference numerals throughout the specification refer to like elements.

[0035] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0036] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0037] FIG. 1 is an exploded perspective view of a display device according to an embodiment.

[0038] Referring to FIG. 1, a display device 10 according to an embodiment is a device for displaying moving or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). For example, the display device 10 may be applied to a television, a laptop computer, a monitor, a billboard, or a display unit for the Internet of Things (IoT). Alternatively, the display device 10 may be applied to a smart watch, a watch phone, or a head-mounted display device (HMD) for implementing virtual reality and augmented reality.

[0039] A display device 10 according to an embodiment may include a driver unit 100, a display unit 200, and a circuit board 300. The display device 10 may further include a protective layer 900 disposed around the driver unit 100.

[0040] The actuator 100 may have a planar shape similar to a rectangle. For example, the actuator 100 may have a planar shape similar to a rectangle having one side in a first direction DR1 and another side in a second direction DR2 intersecting the first direction DR1. The lengths of the side in the first direction DR1 and the other side in the second direction DR2 of the actuator 100 may be different from each other. The corner where the side in the first direction DR1 and the other side in the second direction DR2 of the actuator 100 meet may be rounded or right-angled to have a predetermined curvature. The planar shape of the actuator 100 is not limited to a rectangle and may be other polygonal, circular, elliptical, or the like.

[0041] The display unit 200 may be disposed on the driver 100. In the display device 10, the driver 100 and the display unit 200 may be joined together. Unlike the driver 100, the display unit 200 may have a shape similar to a square. For example, the driver 100 may have a planar shape similar to a square in which one side in a first direction DR1 and the other side in a second direction DR2 intersecting the first direction DR1 have the same length. The planar shape of the display unit 200 is not limited to a rectangle and may be formed into other polygonal shapes, such as a circle or an ellipse. The planar shape of the display device 10 may follow the planar shape of the display unit 200, but is not limited thereto.

[0042] According to one embodiment, the display device 10 may have a display unit 200 with a larger planar area than the driver unit 100. The display device 10 includes a driver unit 100 and a display unit 200 that include different substrates, and these units may have different areas. The elements formed in the driver unit 100 and the elements formed in the display unit 200 may be different from each other, and the elements may be formed individually on different substrates. The display device 10 can be manufactured by forming multiple elements with different sizes, line widths, and manufacturing processes on different substrates and then bonding them together, which has the advantage of improving product performance and manufacturing yield.

[0043] The circuit board 300 may be electrically connected to a plurality of pads in the pad region of the display unit 200 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film made of a flexible material. Although FIG. 1 illustrates the circuit board 300 in an unfolded state, the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the bottom surface of the driver 100. The other end of the circuit board 300 may be connected to a plurality of pads in the pad region of the display unit 200 using a conductive adhesive member. In another embodiment, the circuit board 300 may be attached to the bottom surface of the driver 100.

[0044] The protective layer 900 may surround the driver 100 and be disposed on the lower surface of the display unit 200. The protective layer 900 may reduce a step due to an area difference between the driver 100 and the display unit 200, and may also protect the driver 100 and the display unit 200.

[0045] Fig. 2 is a plan view showing an example of the drive unit shown in Fig. 1. Fig. 3 is a plan view showing an example of the display unit shown in Fig. 1.

[0046] 2 and 3, the driver 100 of the display device 10 may include driving circuit elements of the display device 10. The driver 100 may include a first single-crystalline semiconductor substrate 110 and a driving circuit unit 400, a gate driver 600, a data driver 700, and a pixel circuit unit 800 formed on the first single-crystalline semiconductor substrate 110.

[0047] The first single-crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. A plurality of first transistors may be formed on the first single-crystal semiconductor substrate 110, and the plurality of first transistors may be electrically connected to each other to form the driving circuit unit 400, the gate driver 600, the data driver 700, and the pixel circuit unit 800. The first transistors may be formed by a semiconductor process. For example, the plurality of transistors may be formed as CMOS (Complementary Metal Oxide Semiconductor) transistors.

[0048] In the drawing, the pixel circuit unit 800 is disposed above the driver 100, the data driver 700, the driver 400, and the signal terminal area TDA are disposed below the pixel circuit unit 800, and the gate driver 600 is disposed on one side of the pixel circuit unit 800 in the first direction DR1, i.e., on the right side. However, the present invention is not limited to this. The positions of the driver 100, the driver 400, the gate driver 600, the data driver 700, and the pixel circuit unit 800 may be varied in various ways depending on the design structure of the plurality of circuit elements formed on the first single-crystalline semiconductor substrate 110.

[0049] A plurality of signal terminals STD may be arranged in the signal terminal area TDA in a first direction DR1. The signal terminals STD may be electrically connected to the display unit 200 and, through the display unit 200, may be electrically connected to the circuit board 300. The signal terminals STD may transmit electrical signals applied from the circuit board 300 to the driving circuit unit 400, the gate driver 600, the data driver 700, and the pixel circuit unit 800.

[0050] The display unit 200 may include a second single-crystal semiconductor substrate 210 and a plurality of pixels PX formed on the second single-crystal semiconductor substrate 210. The display unit 200 may include a display area DAA in which the plurality of pixels PX are arranged and a non-display area NA therearound. A through-hole area TSA and a pad area PDA may be arranged in the non-display area NDA.

[0051] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Unlike the first single crystal semiconductor substrate 110, transistors may not be formed on the second single crystal semiconductor substrate 210. A display layer ("230" in FIG. 6) in which a plurality of light-emitting elements are arranged may be disposed on the second single crystal semiconductor substrate 210, and the plurality of light-emitting elements included in the display layer may be electrically connected to the pixel circuit unit 800 formed on the first single crystal semiconductor substrate 110.

[0052] A plurality of pixels PX including light-emitting elements may be arranged in the display area DAA. Each of the pixels PX may include three sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 constitute one pixel PX and may display a color. However, without being limited thereto, one pixel PX may include three or more sub-pixels. The sub-pixels SP may be arranged in a matrix in the first direction DR1 and the second direction DR2. Each of the sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit (the pixel circuit of FIG. 5) of the pixel circuit unit 800 formed on the first single-crystal semiconductor substrate 110. Each of the sub-pixels SP1, SP2, and SP3 includes a light-emitting element, and the light-emitting element may emit light in response to an electrical signal applied from the pixel circuit arranged in the display area DAA.

[0053] Some of the sub-pixels SP1, SP2, and SP3 arranged in the display area DAA of the display unit 200 may overlap with the driver 100 in the thickness direction, and other parts may not overlap with the driver 100. The driver 100 may have a smaller area than the display unit 200 and may be arranged adjacent to one side of the display unit 200. Therefore, only some of the sub-pixels SP1, SP2, and SP3 may overlap with the driver 100 in the thickness direction.

[0054] According to an embodiment, the display unit 200 of the display device 10 may include a plurality of first through holes TSV1 overlapping the display area DAA. The first through holes TSV1 may be formed to penetrate the second single-crystal semiconductor substrate 210 of the display unit 200. The first through holes TSV1 may form connection paths between the pixel circuit unit 800 of the driver unit 100 and each of the subpixels SP1, SP2, and SP3 of the display unit 200. The plurality of first through holes TSV1 may be formed to correspond to each of the subpixels SP1, SP2, and SP3 of the display unit 200. In some embodiments, the number of first through holes TSV1 may be the same as the number of subpixels SP1, SP2, and SP3, and the first through holes TSV1 may be formed to overlap each of the subpixels SP1, SP2, and SP3, but are not limited thereto. The plurality of first through holes TSV1 may correspond to each of the subpixels SP1, SP2, and SP3, but they do not necessarily have to be formed to overlap each other. As will be described later, the sub-pixels SP1, SP2, and SP3 may be electrically connected to the pixel circuits of the pixel circuit unit 800 via connecting wires disposed in the first through-holes TSV1.

[0055] The non-display area NA may be arranged to surround the display area DAA. The non-display area NA may be an area where no pixels PX are arranged and therefore no light is emitted. The non-display area NA may be arranged with a through-hole area TSA and a pad area PDA.

[0056] The pad area PDA may be disposed on a lower side of the display area DAA in the second direction DR2. A plurality of pads PD may be disposed in the pad area PDA and arranged in the first direction DR1. A circuit board 300 may be attached to the plurality of pads PD. The pads PD are electrically connected to the circuit board 300 and can transmit an electrical signal applied from the circuit board 300 to the driver 100.

[0057] The through-hole area TSA may be disposed between the pad area PDA and the display area DAA. A plurality of second through-holes TSV2 may be formed in the through-hole area TSA. The second through-holes TSV2 may serve as connection paths for signal connection wiring that electrically connects the signal terminals STD of the driver 100 to the circuit board 300. The plurality of second through-holes TSV2 may be formed to correspond to the signal terminals STD of the driver 100, respectively. In some embodiments, the number of second through-holes TSV2 may be the same as the number of signal terminals STD, and the second through-holes TSV2 may be formed to overlap the signal terminals STD, although this is not limited thereto. The circuit board 300 may be electrically connected to the signal terminals STD of the driver 100 via the signal connection wiring disposed in the plurality of pads PD and the second through-holes TSV2.

[0058] FIG. 4 is a block diagram showing a display device according to an embodiment.

[0059] 4, the driving circuit unit 400 may include a timing control circuit and may further include various circuits, such as a gamma circuit and a logic circuit, involved in driving the display device 10. The driving circuit unit 400 may include driving circuit transistors formed on the first single crystal semiconductor substrate 110.

[0060] The driver circuit 400 may receive digital video data and timing signals from the outside. The timing control circuit may generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 in response to the timing signals. The timing control circuit may output the scan timing control signal SCS to the scan driver 610 of the gate driver 600 and the light emission timing control signal ECS to the light emission driver 620 of the gate driver 600. The timing control circuit may output the digital video data and the data timing control signal DCS to the data driver 700.

[0061] The power supply unit can generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit can generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT and supply them to the plurality of pixels PX.

[0062] The scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit unit 400 may be supplied to the pixels PX. The first driving voltage VSS, the second driving voltage VDD, and the initialization voltage VINT of the power supply unit may also be supplied to the pixels PX.

[0063] The gate driver 600 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the first single crystalline semiconductor substrate 110, and the emission driver 620 may include a plurality of emission transistors formed on the first single crystalline semiconductor substrate 110. The plurality of scan transistors and the plurality of emission transistors may be formed by a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed as CMOS transistors.

[0064] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the driver circuit unit 400. The first scan signal output unit 611 may generate write scan signals in response to the scan timing control signal SCS of the driver circuit unit 400 and sequentially output the write scan signals to the first scan lines GWL. The second scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and sequentially output the control scan signals to the second scan lines GCL. The third scan signal output unit 613 may generate bias scan signals in response to the scan timing control signal SCS and sequentially output the bias scan signals to the third scan lines GBL.

[0065] The light emitting driver 620 may include a first light emitting signal output unit 621 and a second light emitting signal output unit 622. The first light emitting signal output unit 621 and the second light emitting signal output unit 622 may each receive a light emitting timing control signal ECS from the driver circuit unit 400. The light emitting driver 620 may generate a light emitting control signal in response to the light emitting timing control signal ECS and sequentially output the signal to the first and second light emitting control lines EL1 and EL2.

[0066] The data driver 700 receives digital video data DATA and a data timing control signal DCS from the driver circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by a write scan signal from the scan driver 610, and data voltages are supplied to the selected sub-pixels SP1, SP2, and SP3.

[0067] The pixel circuit unit 800 includes a plurality of pixel transistors formed on the first single crystal semiconductor substrate 110. The pixel transistors may be formed by a semiconductor process. For example, the pixel transistors may be formed as CMOS transistors.

[0068] The pixel circuit unit 800 may include a plurality of data lines DL, a plurality of scan lines GWL, GCL, GBL, and a plurality of light-emitting control lines EL1, EL2. The plurality of scan lines GWL, GCL, GBL, and a plurality of light-emitting control lines EL1, EL2 may extend in a first direction DR1 and be spaced apart from each other in a second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1. The pixel circuit unit 800 is electrically connected to the pixels PX of the display unit 200 to transmit electrical signals required for light emission of the light-emitting elements. The plurality of data lines DL, the plurality of scan lines GWL, GCL, GBL, and a plurality of light-emitting control lines EL1, EL2 may be connected to the pixels PX of the display unit 200.

[0069] FIG. 5 is an equivalent circuit diagram of one pixel according to one embodiment.

[0070] 5, the pixel circuit PXC of the subpixel may be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first light-emitting control line EL1, the second light-emitting control line EL2, and the data line DL. The pixel circuit PXC may also be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. Here, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0071] The pixel circuit PXC includes a plurality of transistors T1 to T6, a light emitting element (LE), a first capacitor C1, and a second capacitor C2.

[0072] The light emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light emitting element LE is proportional to the driving current Ids. The light emitting element LE may be disposed between the fourth transistor T4 and the first driving voltage line VSL. A first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode electrode, and the second electrode of the light emitting element LE may be a cathode electrode. The light emitting element LE may be, but is not limited to, an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first and second electrodes. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light emitting element LE may be a micro light emitting diode.

[0073] The first transistor T1 may be a driving transistor that controls a source-drain current (Ids, hereinafter referred to as a "driving current") flowing between its source electrode and drain electrode in response to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0074] The second transistor T2 may be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal on the first scan line GWL to connect one electrode of the first capacitor C1 to the data line DL, so that the data voltage of the data line DL can be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0075] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal of the second scan line GCL to connect the first node N1 to the second node N2. As a result, the gate electrode and source electrode of the first transistor T1 are connected to each other, allowing the first transistor T1 to operate like a diode. The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0076] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first light-emitting control signal from the first light-emitting control line EL1 to connect the second node N2 to the third node N3, so that the driving current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light-emitting control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0077] The fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the third scan line GBL to connect the third node N3 to the third driving voltage line VIL. This allows the third driving voltage VINT of the third driving voltage line VIL to be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0078] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second light-emitting control signal from the second light-emitting control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. This allows the second driving voltage VDD from the second driving voltage line VDL to be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light-emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0079] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2, and has one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0080] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL, and has one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0081] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0082] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be a P-type MOSFET, and the remaining transistors may be an N-type MOSFET.

[0083] 5 illustrates an example in which the pixel circuit PXC includes six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the pixel circuit PXC is not limited to that shown in FIG. 5. For example, the number of transistors and the number of capacitors in the pixel circuit PXC are not limited to that shown in FIG.

[0084] Fig. 6 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 7 is a schematic view showing the rear surface of a display device according to an embodiment. Fig. 6 shows a schematic connection relationship of routing wiring RM1, RM2 that electrically connects the display unit 200 and the driver 100, and Fig. 7 shows the arrangement of through-holes TSV1, TSV2 and routing wiring RM1, RM2 as viewed from the rear surface of the display device 10.

[0085] 6 and 7 in addition to Fig. 4, a display device 10 according to an embodiment may include a driving unit 100 including a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110, and a display unit 200 including a second single crystal semiconductor substrate 210 and a display layer 230 disposed on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 overlapping in a third direction DR3, which is a thickness direction of the display device 10.

[0086] The driver 100 may include circuit elements necessary for emitting light from the light-emitting elements included in the display layer 230 of the display unit 200. As described above, the driver circuit layer 120 of the driver 100 may include the driver circuit 400, the gate driver 600, the data driver 700, and the pixel circuit 800, and the circuit elements constituting these elements, such as transistors and capacitors, may be formed on the first single-crystal semiconductor substrate 110 using CMOS.

[0087] The display unit 200 may include a plurality of light emitting elements that emit light to display an image on the display device 10. The light emitting elements are electrically connected to circuit elements formed in the driver unit 100 to emit light.

[0088] According to an embodiment, the display device 10 may have a planar area of ​​the driver 100 or the first single crystalline semiconductor substrate 110 smaller than the planar area of ​​the display unit 200 or the second single crystalline semiconductor substrate 210. The plurality of transistors formed in the driver 100 may be formed using a semiconductor microfabrication process and may have very small sizes and line widths. The driver 100 has the advantage that a large number of circuit elements can be arranged with high integration, and power consumption can be reduced by miniaturizing the size of the elements.

[0089] Furthermore, since the driver unit 100 includes only circuit elements formed using CMOS on the first single crystal semiconductor substrate 110 and does not include light emitting elements, it is sufficient to provide a space sufficient to accommodate elements formed using a micro-process. The first single crystal semiconductor substrate 110 may have a smaller area than the second single crystal semiconductor substrate 210, and multiple driver units 100 can be manufactured using a single wafer substrate on which the process of forming the driver circuit layer 120 is performed, thereby improving manufacturing yield. In particular, since the driver unit 100 is manufactured using a high-cost semiconductor process, improving manufacturing yield of the driver unit 100 can also have a cost-reducing effect. Furthermore, since the display unit 200 includes multiple light emitting elements formed on the second single crystal semiconductor substrate 210, which has a relatively large area, a high-resolution display device can be realized.

[0090] The display device 10 may include a connecting wiring layer 500 disposed between the second single-crystal semiconductor substrate 210 of the display unit 200 and the driving circuit layer 120 of the driving unit 100. The connecting wiring layer 500 may be disposed on the lower surface of the second single-crystal semiconductor substrate 210. The connecting wiring layer 500 has a portion of a plurality of routing wires RM1 and RM2 disposed thereon, and the routing wires RM1 and RM2 may connect the display layer 230 of the display unit 200 and the circuit board 300 to the driving unit 100. The driving circuit layer 120 of the driving unit 100 is electrically connected to the display unit 200 and the circuit board 300 via the routing wires RM1 and RM2, and may transmit an electrical signal for light emission.

[0091] The first routing wiring RM1 may be connected to the subpixels SP1, SP2, and SP3 arranged in the display layer 230 of the display unit 200 and the pixel circuit unit 800 of the driver 100. In one embodiment, the display device 10 includes a plurality of first through holes TSV1 arranged corresponding to the subpixels SP1, SP2, and SP3 of the display unit 200, and the first routing wiring RM1 may connect the first through holes TSV1 to the pixel circuit unit 800, respectively. The first through holes TSV1 are arranged throughout the display unit 200, which has a large area, while the pixel circuit unit 800 has a relatively small area. The first routing wiring RM1 may include conductive vias (“RVA” in FIG. 12 ) arranged throughout the display unit 200, which has a large area, and connecting wiring (“RML” in FIG. 12 ) connecting the conductive vias to the pixel circuit unit 800, which has a small area. The distance between the first routing wires RM1 and other adjacent first routing wires RM1 in a plan view may be narrower in the portion overlapping with the driver unit 100 than in the display area DAA.

[0092] In some embodiments, some of the multiple first through holes TSV1 may overlap the driving unit 100 in the thickness direction, and other parts may not overlap the driving unit 100 in the thickness direction. The first routing wiring RM1 arranged in the first through hole TSV1 that does not overlap the driving unit 100 may have a portion of the connecting wiring ("RML" in FIG. 12) that does not overlap the driving unit 100. However, the arrangement of the first through holes TSV1 may vary depending on the position of the layer in which the connecting wiring RML of the first routing wiring RM1 is arranged.

[0093] According to an embodiment, the number of first through holes TSV1 may be the same as the number of subpixels SP1, SP2, and SP3 arranged in the display area DAA. For example, the subpixels SP1, SP2, and SP3 may be arranged in the first direction DR1 and the second direction DR2 in the display area DAA, and the first through holes TSV1 may also be arranged in the first direction DR1 and the second direction DR2, corresponding one-to-one to each of the subpixels SP1, SP2, and SP3. The first through holes TSV1 may be formed to overlap each of the subpixels SP1, SP2, and SP3. The number of first routing wirings RM1 may also be the same as the number of subpixels SP1, SP2, and SP3.

[0094] The plurality of second through holes TSV2 may be disposed in the through hole area TSA of the display unit 200 and may be formed to overlap the signal terminal area TDA of the driver 100. Second routing wiring RM2 connected to the signal terminals STD of the driver 100 may be disposed in the second through holes TSV2. Unlike the first through holes TSV1, the second through holes TSV2 may be formed to overlap the signal terminals STD of the driver 100, respectively. Therefore, the second routing wiring RM2 may also correspond to the signal terminals STD, respectively, and may be disposed to overlap therewith. The second routing wiring RM2 may be wiring that transmits signals applied from the circuit board 300 to the driver 100.

[0095] FIG. 8 is a schematic cross-sectional view of a display device according to another embodiment.

[0096] 8, in the display device 10 according to the embodiment, a connecting wiring layer 500 may be disposed between the display layer 230 and the second single crystal semiconductor substrate 210. The connecting wiring layer 500 is disposed on the upper surface of the second single crystal semiconductor substrate 210 instead of the lower surface thereof, which differs from the embodiments of FIGS. 6 and 7 in that the positions of the connecting wiring RML, the conductive via RVA, and the first through hole TSV1 are different.

[0097] The interconnection layer 500 may be disposed on the upper surface of the second single crystal semiconductor substrate 210. An interlayer insulating layer RINS of the interconnection layer 500 may be disposed on the upper surface of the second single crystal semiconductor substrate 210.

[0098] According to one embodiment, the plurality of first through holes TSV1 overlap the driver 100 in the thickness direction, and the first routing wiring RM1 is electrically connected to the subpixels SP1, SP2, and SP3 arranged throughout the display area DAA, and can connect the first through holes TSV1 and the subpixels SP1, SP2, and SP3 that overlap the driver 100. For example, the connecting wiring RML of the first routing wiring RM1 is concentrated in the area where the first through holes TSV1 are arranged, and can connect the terminals STD connected to the subpixels SP1, SP2, and SP3, respectively, and the conductive vias RVA arranged in the first through holes TSV1. In the display device 10, the plurality of first through holes TSV1 and the conductive vias RVA may each overlap the first single crystal semiconductor substrate 110 in the thickness direction. However, at least a portion of the connecting wiring RML does not need to overlap the first single crystal semiconductor substrate 110 in the thickness direction.

[0099] As described above, the planar area of ​​the first single crystal semiconductor substrate 110 may be smaller than the planar area of ​​the second single crystal semiconductor substrate 210, and only a portion of the connecting wiring RML disposed over the entire surface of the second single crystal semiconductor substrate 210 may overlap with the first single crystal semiconductor substrate 110 in the thickness direction. Therefore, the connecting wiring RML is disposed over the entire surface of the second single crystal semiconductor substrate 210, and ends of the connecting wiring RML composed of multiple layers may overlap with the first single crystal semiconductor substrate 110 in the thickness direction and be connected to the multiple first through holes TSV1 and conductive vias RVA. The connecting wiring RML can form a path that electrically connects light emitting elements disposed over the entire surface of the display area DAA, which has a larger area, to the pixel circuit unit 800, which has a relatively smaller area.

[0100] Hereinafter, the structures of the driving circuit layer 120 of the driving unit 100 and the display layer 230 of the display unit 200 will be described in detail with reference to other drawings.

[0101] FIG. 9 is a schematic cross-sectional view of a drive unit according to an embodiment.

[0102] Referring to FIG. 9, the driver 100 may include a first single-crystal semiconductor substrate 110 and a driver circuit layer 120 disposed thereon.

[0103] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with a first type impurity. A plurality of well regions WA may be disposed on the upper surface of the first single crystal semiconductor substrate 110. The plurality of well regions WA may be regions doped with a second type impurity. The second type impurity may be different from the first type impurity described above. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0104] Each of the plurality of well regions WA includes a source region SA corresponding to the source electrode of the first transistor PTR1, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0105] A lower insulating film BINS may be disposed between the gate electrode GE and the well region WA. A side insulating film SINS may be disposed on a side surface of the gate electrode GE. The side insulating film SINS may be disposed on the lower insulating film BINS.

[0106] The source region SA and the drain region DA may each be a region doped with a first type impurity. The gate electrode GE of the first transistor PTR1 may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the other side of the gate electrode GE.

[0107] Each of the plurality of well regions WA further includes a first lightly doped impurity region LDD1 disposed between the channel region CH and the source region SA and a second lightly doped impurity region LDD2 disposed between the channel region CH and the drain region DA. The first lightly doped impurity region LDD1 may have a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second lightly doped impurity region LDD2 may have a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2 may increase the distance between the source region SA and the drain region DA. Therefore, the length of the channel region CH of each first transistor PTR1 may be increased, thereby preventing punch-through and hot carrier phenomena due to a short channel.

[0108] The first single crystalline semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driver 100. The first transistors PTR1 formed on the first single crystalline semiconductor substrate 110 may constitute the driver circuit 400, the gate driver 600, the data driver 700, or the pixel circuit 800.

[0109] The first single crystal semiconductor substrate 110 may be subjected to a process for reducing its thickness when the driving circuit layer 120 is formed on the silicon wafer substrate. The first single crystal semiconductor substrate 110 may have a thickness thinner than that of the wafer substrate on which the semiconductor process for forming the driving circuit layer 120 is performed. In some embodiments, the thickness of the first single crystal semiconductor substrate 110 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0110] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The driving circuit layer 120 may include wiring electrically connected to a plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0111] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be disposed on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 may be an insulating layer disposed on the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer disposed on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In the drawings, the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each formed of a single layer having a predetermined thickness, but are not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may also have a structure in which at least one layer is stacked on top of each other.

[0112] The plurality of contact electrodes CTE may be disposed on the first single crystal semiconductor substrate 110. The plurality of contact electrodes CTE may be connected to one of the gate electrode GE, source region SA, and drain region DA of each first transistor PTR1 formed on the first single crystal semiconductor substrate 110 via holes penetrating the semiconductor insulating layers SINS1 and SINS2. The plurality of contact electrodes CTE may be made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The upper surfaces of the plurality of contact electrodes CTE may be exposed and not covered by the semiconductor insulating layers SINS1 and SINS2.

[0113] The first interlayer insulating layer INS1 may be disposed on the contact electrodes CTE and the semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but is not limited thereto. In the drawings, the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are each formed as a single layer, but are not limited thereto. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may each have a structure in which at least one layer is stacked on top of each other, and these may be disposed between a plurality of first to eighth conductive layers ML1 to ML8 described below.

[0114] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are electrically connected to the plurality of contact electrodes CTE to form the driving circuit unit 400 or the data driver 700 of the driver 100. The plurality of first transistors PTR1 formed on the first single crystal semiconductor substrate 110 are electrically connected to each other via the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 to form the driving circuit unit 400 and the data driver 700 of the driver 100.

[0115] The first conductive layer ML1 may be connected to the contact electrode CTE through a first via VA1. The first conductive layer ML1 may be disposed on the contact electrode CTE, and the first via VA1 may be disposed between the first conductive layer ML1 and the contact electrode CTE to contact them, respectively. The second conductive layer ML2 may be connected to the first conductive layer ML1 through a second via VA2. The second conductive layer ML2 may be disposed on the first conductive layer ML1, and the second via VA2 may be disposed between the first conductive layer ML1 and the second conductive layer ML2 to contact them, respectively.

[0116] The third conductive layer ML3 may be connected to the second conductive layer ML2 through a third via VA3. The fourth conductive layer ML4 may be connected to the third conductive layer ML3 through a fourth via VA4, the fifth conductive layer ML5 may be connected to the fourth conductive layer ML4 through a fifth via VA5, and the sixth conductive layer ML6 may be connected to the fifth conductive layer ML5 through a sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be sequentially arranged on the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be arranged between them. The third to sixth vias VA3 to VA6 may be in contact with different metal layers arranged above and below them, respectively. The seventh via VA7 may be arranged on the sixth conductive layer ML6. The seventh via VA7 may be in contact with the seventh conductive layer ML7 and the sixth conductive layer ML6 arranged above it, respectively.

[0117] The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 may be disposed on the first interlayer insulating layer INS1. The first to sixth conductive layers ML1 to ML6 and the first to seventh vias VA1 to VA7 may form a first drive circuit layer disposed on the first interlayer insulating layer INS1 of the drive circuit layer 120.

[0118] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through a seventh via VA7. The seventh conductive layer ML7 may be disposed on the first interlayer insulating layer INS1 and the sixth conductive layer ML6, and the seventh via VA7 may be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 and be in contact with them, respectively. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through an eighth via VA8. The eighth conductive layer ML8 may be disposed on the seventh conductive layer ML7, and the eighth via VA8 may be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 and be in contact with them, respectively. The top surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2, and may be electrically connected to the routing wiring RM disposed in the display unit 200 described above.

[0119] The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 may be disposed on the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via VA8, and the eighth conductive layer ML8 may constitute a second drive circuit layer of the drive circuit layer 120 that is disposed on the second interlayer insulating layer INS2.

[0120] Although the drawings illustrate a structure in which the first through eighth conductive layers ML1-ML8 and the first through eighth vias VA1-VA8 are sequentially stacked, their arrangement and connection may be modified in various ways depending on the circuits of the driving circuit unit 400 and the data driver 700 of the driver 100. The connection structure shown in the drawings is one example, and the connection of the driving circuit layer 120 arranged in the driver 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 does not necessarily have to include the first through eighth conductive layers ML1-ML8 and the first through eighth vias VA1-VA8, and some of these layers may be omitted or a greater number of layers may be arranged.

[0121] The first through eighth conductive layers ML1 through ML8 and the first through eighth vias VA1 through VA8 are made of substantially the same material, for example, copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these materials.

[0122] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360 Å, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may each be approximately 1440 Å, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 may each be approximately 1150 Å.

[0123] The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6, respectively. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thicknesses of the seventh via VA7 and the eighth via VA8, respectively. The thicknesses of the seventh via VA7 and the eighth via VA8 may be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thicknesses of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0124] FIG. 10 is a plan view showing first electrodes, light-emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display unit according to an embodiment.

[0125] 10, each of the pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first to third sub-pixels SP1, SP2, and SP3 may include light-emitting regions EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first light-emitting region EA1, the second sub-pixel SP2 may include a second light-emitting region EA2, and the third sub-pixel SP3 may include a third light-emitting region EA3.

[0126] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each have a quadrilateral planar shape such as a rectangle, a square, or a diamond. For example, the third light-emitting region EA3 may have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. Also, the second light-emitting region EA2 and the first light-emitting region EA1 may each have a rectangular planar shape with a long side in the first direction DR1 and a short side in the second direction DR2.

[0127] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each be a region defined by a pixel defining film PDL. For example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each be a region defined by a first pixel defining film PDL1.

[0128] The length in the first direction DR1 of the third light-emitting region EA3 may be smaller than the length in the first direction DR1 of the first light-emitting region EA1 and may be smaller than the length in the first direction DR1 of the second light-emitting region EA2. The length in the first direction DR1 of the first light-emitting region EA1 and the length in the first direction DR1 of the second light-emitting region EA2 may be substantially the same.

[0129] In each of the pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in the second direction DR2. The first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different.

[0130] Although the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 each have a rectangular planar shape in the drawings, the planar shape is not limited thereto. For example, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a polygonal, circular, or elliptical planar shape other than a rectangular shape.

[0131] The first light-emitting region EA1 may emit light of a first color, the second light-emitting region EA2 may emit light of a second color, and the third light-emitting region EA3 may emit light of a third color. Here, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. For example, the blue wavelength band refers to light whose main peak wavelength is approximately 370 nm to 460 nm, the green wavelength band refers to light whose main peak wavelength is approximately 480 nm to 560 nm, and the red wavelength band refers to light whose main peak wavelength is approximately 600 nm to 750 nm.

[0132] The first electrode AND of the light-emitting element may have a rectangular planar shape. The planar shapes of the first electrode AND of the light-emitting element may differ among the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape with a longer side in a first direction DR1 and a shorter side in a second direction DR2. The first electrode AND of the third subpixel SP3 may have a rectangular planar shape with a shorter side in the first direction DR1 and a longer side in the second direction DR2. The length in the first direction DR1 of the first electrode AND of the third subpixel SP3 may be shorter than the length in the second direction DR2 of the first electrode AND of the first subpixel SP1 and the second subpixel SP2. The length in the second direction DR2 of the first electrode AND of the first subpixel SP1 may be longer than the length in the second direction DR2 of the first electrode AND of the second subpixel SP2.

[0133] The first electrode AND of the light emitting element may be connected to the reflective electrode layer (RL in FIG. 12) through an electrode via VAP. The electrode via VAP may overlap the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 in the third direction DR3.

[0134] At least one trench TRC may be a structure for cutting at least one charge generation layer of the light-emitting stack IL between adjacent light-emitting regions EA1, EA2, and EA3. At least one trench TRC may be disposed between the first light-emitting region EA1 and the second light-emitting region EA2, between the first light-emitting region EA1 and the third light-emitting region EA3, and between the second light-emitting region EA2 and the third light-emitting region EA3. More specifically, at least one trench TRC may be disposed between the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2, between the first electrode AND of the first subpixel SP1 and the first electrode AND of the third subpixel SP3, and between the first electrode AND of the second subpixel SP2 and the first electrode AND of the third subpixel SP3.

[0135] FIG. 11 is a plan view showing first electrodes, light-emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display unit according to another embodiment.

[0136] Referring to Figure 11, the planar shapes of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are different from those of the embodiment of Figure 10, and therefore, the same description as that of the embodiment of Figure 10 will be omitted.

[0137] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be arranged in a hexagonal structure having a hexagonal planar shape. In this case, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in a first direction DR1, the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in a first diagonal direction DD1, and the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in a second diagonal direction DD2. The first diagonal direction DD1 is a direction between the first direction DR1 and the second direction DR2 and is tilted 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 may be perpendicular to the first diagonal direction DD1.

[0138] 10 and 11 show an example in which each of the plurality of pixels PX includes three light-emitting areas EA1, EA2, and EA3, but this is not limiting. That is, each of the plurality of pixels PX may include four light-emitting areas.

[0139] The arrangement of the light emitting regions of the pixels PX is not limited to that shown in the drawings. For example, the light emitting regions of the pixels PX may be arranged in a stripe structure in which the light emitting regions are arranged in a first direction DR1, a PenTile (registered trademark) structure in which the light emitting regions are arranged in a diamond shape, or a hexagonal structure in which light emitting regions having hexagonal planar shapes are arranged.

[0140] 12 is a cross-sectional view showing a part of a display unit according to an embodiment of the present invention, showing a cross-section of a part of a display area DAA of the display unit 200.

[0141] 12 , the display unit 200 may include a second single crystal semiconductor substrate 210, a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, and a cover layer DCL. The display element layer EML, the encapsulation layer TFE, the adhesive layer ADL, the color filter layer CFL, the lens LNS, and the cover layer DCL of the display unit 200 may constitute a display layer 230. Although not shown in the drawing, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The connecting wiring layer 500 may be disposed between the second single crystal semiconductor substrate 210 and the first single crystal semiconductor substrate 110. Alternatively, the connecting wiring layer 500 may be disposed between the display element layer EML and the first single crystal semiconductor substrate 110.

[0142] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. Unlike the first single crystal semiconductor substrate 110, the second single crystal semiconductor substrate 210 may not have a transistor formed thereon. The second single crystal semiconductor substrate 210 serves as a lower substrate on which the display element layer EML is disposed, and may form a connection path on which a routing wiring RM1 is disposed, which electrically connects the light emitting elements of the display element layer EML to the pixel circuit unit 800 of the driving unit 100.

[0143] As described above, the first single crystal semiconductor substrate 110 of the driver unit 100 may have a smaller planar area than the second single crystal semiconductor substrate 210 of the display unit 200, and small-sized elements can be arranged with high integration, thereby reducing power consumption and improving manufacturing yield. Meanwhile, the second single crystal semiconductor substrate 210 of the display unit 200 may have a larger planar area than the first single crystal semiconductor substrate 110, and processes with relatively large line widths may be performed on the second single crystal semiconductor substrate 210. Unlike circuit elements formed on the first single crystal semiconductor substrate 110, elements of the display layer 230 formed on the second single crystal semiconductor substrate 210 do not require high integration. Therefore, semiconductor processes performed on the first wafer substrate are high-cost processes with small line widths, and semiconductor processes performed on the second wafer substrate are low-cost processes with relatively large line widths.

[0144] The second single crystal semiconductor substrate 210 may include a plurality of first through holes TSV1 spaced apart from one another. The first through holes TSV1 may penetrate from the top surface to the bottom surface of the second single crystal semiconductor substrate 210. A conductive via RVA of the first routing wiring RM1 may be disposed in the first through holes TSV1. The first through holes TSV1 may form a connection path of the first routing wiring RM1 that electrically connects the pixel circuit unit 800 of the driving unit 100 and the light emitting elements of the display unit 200.

[0145] Although not shown in the drawings, the second single-crystal semiconductor substrate 210 includes a plurality of second through-holes TSV2 formed in the non-display area NA, and conductive vias of the second routing wiring RM2 may be disposed in the second through-holes TSV2, respectively. The signal terminals STD of the circuit board 300 and the driver 100 may be electrically connected to each other via the second routing wiring RM2.

[0146] In some embodiments, the first through holes TSV1 of the second single crystal semiconductor substrate 210 may be formed by a TSV (Through Silicon Via) process for forming holes that penetrate a wafer substrate. The display layer 230 and the driver 100 may be electrically connected to each other via the through holes TSV1 and routing wiring RM1 formed in the second single crystal semiconductor substrate 210 without additional wires.

[0147] The second single crystal semiconductor substrate 210 may be subjected to a process of reducing its thickness after the actuator 100 is bonded onto the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness thinner than that of the wafer substrate on which the process for forming the conductive layer is performed. In some embodiments, the thickness of the second single crystal semiconductor substrate 210 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0148] The interconnection layer 500 may be disposed on the lower surface of the second single crystal semiconductor substrate 210. The interconnection layer 500 may include an interlayer insulating layer RINS and a plurality of interconnections RML.

[0149] An interlayer insulating layer RINS may be disposed on the lower surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x Although the drawings illustrate the case where each interlayer insulating layer RINS is formed of a single layer, the present invention is not limited thereto and may have a structure in which at least one layer or more layers are stacked on top of each other, and these may be disposed between the connecting wires RML.

[0150] The connecting wiring RML, together with the conductive via RVA, forms routing wiring RM1, RM2. The connecting wiring RML may include at least one conductive layer and one or more vias connecting these layers to each other. The connections and structure of the connecting wiring RML are the same as those described above for the plurality of conductive layers ML1 to ML8 and vias VA1 to VA8. The connecting wiring RML is electrically connected to the light-emitting elements of the sub-pixels SP1, SP2, SP3 or the circuit board 300 via the conductive vias RVA arranged in the through-holes TSV1, TSV2 of the second single-crystal semiconductor substrate 210, and can electrically connect these to the driving circuit layer 120 of the driving unit 100, respectively.

[0151] A conductive via RVA of the first routing wiring RM1 may be disposed in the first through hole TSV1. The conductive via RVA of the first routing wiring RM1 may be disposed in the first through hole TSV1 and may be disposed from the lower surface of the reflective electrode layer RL (described later) to the lower surface of the second single-crystal semiconductor substrate 210. The conductive via RVA may be electrically connected to the first electrodes AND disposed in each of the sub-pixels SP1, SP2, and SP3 via the reflective electrode layer RL. The conductive via RVA may be connected to the reflective electrode layer RL and the connecting wiring RML, respectively, and the connecting wiring RML may be connected to the pixel circuit unit 800. The connecting wiring RML may be the wiring shown on the back surface of the display unit 200 in FIG. 7. The first routing wiring RM1 may connect the light emitting elements of each of the sub-pixels SP1, SP2, and SP3 to the pixel circuit unit 800 of the driving unit 100.

[0152] The display layer 230 may be disposed on the second single-crystal semiconductor substrate 210. The display layer 230 may include a display element layer EML, a sealing layer TFE, an optical layer OPL, and a cover layer DCL. The display layer 230 includes a light-emitting element electrically connected to the driver 100 and can emit light.

[0153] The display element layer EML may be disposed on the second single-crystal semiconductor substrate 210. The display element layer EML may include a reflective electrode layer RL, interlayer insulating layers INS3, INS4, an electrode via VAP, a light-emitting element each including a first electrode AND, a light-emitting stack IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0154] The reflective electrode layer RL may be disposed on the second single crystal semiconductor substrate 210. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include first to fourth reflective electrodes RL1, RL2, RL3, and RL4 as shown in FIG. 12.

[0155] Each of the first reflective electrodes RL1 is disposed on the second single-crystal semiconductor substrate 210 and may be connected to a conductive via RVA disposed in the first through hole TSV1. The first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0156] Each second reflective electrode RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0157] Each third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0158] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0159] The second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element, and the thickness of the second reflective electrode RL2 may be greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may each be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å.

[0160] The third interlayer insulating layer INS3 may be disposed on the second single crystal semiconductor substrate 210. The third interlayer insulating layer INS3 may be disposed between adjacent reflective electrode layers RL. The third interlayer insulating layer INS3 may be disposed on the reflective electrode layer RL in the first subpixel SP1. The third interlayer insulating layer INS3 may be formed of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0161] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the reflective electrode layer RL. The fourth interlayer insulating layer INS4 may be formed of silicon oxide (SiO x )-based inorganic film, but is not limited thereto.

[0162] In at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the third interlayer insulating layer INS3 and the fourth interlayer insulating layer INS4 may not be arranged below the first electrode AND, taking into account the resonance distance of the light emitted from the light-emitting element.

[0163] For example, the first electrode AND of the third subpixel SP3 may be disposed directly on the fourth reflective electrode RL4, and the first electrode AND of the third subpixel SP3 may not overlap the third interlayer insulating layer INS3 and the fourth interlayer insulating layer INS4. The first electrode AND of the second subpixel SP2 may be disposed on the fourth interlayer insulating layer INS4, and the fourth interlayer insulating layer INS4 may be disposed directly on the fourth reflective electrode RL4. That is, the first electrode AND of the second subpixel SP2 may not overlap the third interlayer insulating layer INS3. The first electrode AND of the first subpixel SP1 may be disposed on the fourth interlayer insulating layer INS4 and may overlap the third interlayer insulating layer INS3.

[0164] In one embodiment, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. To adjust the distance from the reflective electrode layer RL to the second electrode CAT depending on the main wavelength of light emitted from the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may each include or not include a third interlayer insulating layer INS3 and a fourth interlayer insulating layer INS4. For example, in FIG. 12 , the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3. However, this is not limiting. The distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3 can be varied and designed in various ways.

[0165] Each of the electrode vias VAP may be connected to the fourth reflective electrode RL4 exposed through the third interlayer insulating layer INS3 and / or the fourth interlayer insulating layer INS4 in the first subpixel SP1 and the second subpixel SP2. The electrode vias VAP may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The thickness of the electrode via VAP in the second subpixel SP2 may be smaller than the thickness of the electrode via VAP in the first subpixel SP1.

[0166] The first electrode AND of each light emitting element LE may be disposed on the fourth interlayer insulating layer INS4 or the reflective electrode layer RL and connected to the electrode via VAP. The first electrode AND of each light emitting element LE may be connected to the pixel circuit unit 800 via the electrode via VAP, the first to fourth reflective electrodes RL1 to RL4, and the first routing wiring RM1. The first electrode AND of each light emitting element LE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first electrode AND of each light emitting element may be titanium nitride (TiN).

[0167] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each light emitting element, and may cover an edge of the first electrode AND of each light emitting element. The pixel defining layer PDL serves to divide the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0168] The first light-emitting region EA1 may be defined as a region in the first sub-pixel SP1 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The second light-emitting region EA2 may be defined as a region in the second sub-pixel SP2 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The third light-emitting region EA3 may be defined as a region in the third sub-pixel SP3 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light.

[0169] The pixel defining layer PDL may include first to third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND of each light-emitting element LE, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be formed of silicon oxide (SiO x The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about 500 Å.

[0170] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as a single pixel defining layer, the height of the single pixel defining layer increases, and the first inorganic encapsulation layer TFE1 may be cut due to step coverage. Step coverage indicates the ratio of the extent to which a thin film is applied to a sloped portion to the extent to which a thin film is applied to a flat portion. The lower the step coverage, the higher the possibility that the thin film may be cut at a sloped portion.

[0171] To prevent the first inorganic encapsulation layer TFE1 from being cut due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure with a staircase-like step. For example, the width of the first pixel defining layer PDL1 may be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined by the first direction DR1 and the second direction DR2.

[0172] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In each of the plurality of trenches TRC, a portion of the third interlayer insulating layer INS3 may be recessed, and the fourth interlayer insulating layer INS4 may penetrate through the trenches TRC.

[0173] At least one trench TRC may be disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Fig. 12 illustrates an example in which two trenches TRC are disposed between adjacent sub-pixels SP1, SP2, and SP3, the present invention is not limited thereto.

[0174] The light emitting stack IL may include a plurality of light emitting stacks IL1, IL2, and IL3. In the drawings, the light emitting stack IL has a three-tandem structure including a first light emitting stack IL1, a second light emitting stack IL2, and a third light emitting stack IL3, but is not limited thereto. For example, the light emitting stack IL may have a two-tandem structure including two stacks.

[0175] In the three-tandem structure, the light-emitting stack IL may have a tandem structure including multiple light-emitting stacks IL1, IL2, and IL3 that emit different light from each other. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a third color, and a third light-emitting stack IL3 that emits light of a second color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 may be stacked sequentially.

[0176] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked.

[0177] A first charge generation layer may be disposed between the first light emitting stack IL1 and the second light emitting stack IL2 to supply charges to the second light emitting stack IL2 and electrons to the first light emitting stack IL1. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first light emitting stack IL1 and a P-type charge generation layer that supplies holes to the second light emitting stack IL2. The N-type charge generation layer may include a metal dopant.

[0178] A second charge generation layer may be disposed between the second light-emitting stack IL2 and the third light-emitting stack IL3 to supply charges to the third light-emitting stack IL3 and to supply electrons to the second light-emitting stack IL2. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second light-emitting stack IL2 and a P-type charge generation layer that supplies holes to the third light-emitting stack IL3.

[0179] The first light-emitting stack IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each trench TRC. The trench TRC may separate the first light-emitting stack IL1 between adjacent subpixels SP1, SP2, and SP3. The second light-emitting stack IL2 may be disposed on the first light-emitting stack IL1. The trench TRC may separate the second light-emitting stack IL2 between adjacent subpixels SP1, SP2, and SP3. A cavity or empty space may be disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. The third light-emitting stack IL3 may be disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 may be unseparated by the trench TRC and may be disposed to cover the second light-emitting stack IL2 in each trench TRC. That is, in the three-tandem structure, each of the trenches TRC may be a structure for cutting the first and second light-emitting stacks IL1 and IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between the adjacent subpixels SP1, SP2, and SP3. Also, in the two-tandem structure, each of the trenches TRC may be a structure for cutting the charge generation layer and the lower intermediate layer disposed between the lower intermediate layer and the upper intermediate layer.

[0180] To stably cut the first through second light-emitting stacks IL1, IL2 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, the height of each of the trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the trenches TRC refers to the length of each of the trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To cut the first through third light-emitting stacks IL1, IL2, and IL3 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, other structures may be present instead of the trenches TRC. For example, instead of the trenches TRC, a reverse-tapered barrier rib may be disposed on the pixel defining layer PDL.

[0181] The number of light-emitting stacks IL1, IL2, and IL3 that emit different light rays is not limited to that shown in the drawings. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the intermediate layers and charge to the other intermediate layer.

[0182] 12 illustrates an example in which the first to third light-emitting stacks IL1, IL2, and IL3 are disposed in all of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, but this is not limiting. For example, the first light-emitting stack IL1 may be disposed in the first light-emitting region EA1, but not in the second light-emitting region EA2 and the third light-emitting region EA3. The second light-emitting stack IL2 may be disposed in the second light-emitting region EA2, but not in the first light-emitting region EA1 and the third light-emitting region EA3. The third light-emitting stack IL3 may be disposed in the third light-emitting region EA3, but not in the first light-emitting region EA1 and the second light-emitting region EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0183] The second electrode CAT may be disposed on the third light-emitting stack IL3. The second electrode CAT may be disposed on the third light-emitting stack IL3 in each of the trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) that transmits light, such as ITO or IZO, or a semi-transmissive metal material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive metal material, the microcavities increase the light output efficiency of each of the first to third sub-pixels SP1, SP2, and SP3.

[0184] The encapsulating layer TFE may be disposed on the display element layer EML. The encapsulating layer TFE may include at least one inorganic encapsulating layer TFE1, TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The encapsulating layer TFE may also include at least one organic film to protect the display element layer EML from foreign matter such as dust. For example, the encapsulating layer TFE may include a first inorganic encapsulating layer TFE1, an organic encapsulating layer TFE2, and a second inorganic encapsulating layer TFE3.

[0185] The first inorganic sealing layer TFE1 may be disposed on the second electrode CAT, the organic sealing layer TFE2 may be disposed on the first inorganic sealing layer TFE1, and the second inorganic sealing layer TFE3 may be disposed on the organic sealing layer TFE2. The first inorganic sealing layer TFE1 and the second inorganic sealing layer TFE3 may be formed of silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), and an aluminum oxide layer (AlO x The organic encapsulation layer TFE2 may be formed of a multi-layer structure in which one or more inorganic layers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. are alternately stacked. The organic encapsulation layer TFE2 may be a monomer. Alternatively, the organic encapsulation layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0186] The adhesive layer ADL may be disposed on the sealing layer TFE. The adhesive layer ADL may be a layer for adhering the sealing layer TFE to a layer disposed thereon. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may also be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0187] The optical layer OPL may include a color filter layer CFL, a plurality of lenses LNS, and a filler layer FIL. The color filter layer CFL may include first, second, and third color filters CF1, CF2, and CF3. The first, second, and third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0188] The first color filter CF1 may overlap the first light-emitting area EA1. The first color filter CF1 may transmit light of a first color, i.e., light in the red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. The first color filter CF1 may transmit light of the first color emitted from the first light-emitting area EA1.

[0189] The second color filter CF2 may overlap the second light-emitting area EA2. The second color filter CF2 may transmit light of a second color, i.e., light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. The second color filter CF2 may transmit light of the second color emitted from the second light-emitting area EA2.

[0190] The third color filter CF3 may overlap the third light-emitting area EA3. The third color filter CF3 may transmit a third color light, i.e., light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. The third color filter CF3 may transmit the third color light emitted from the third light-emitting area EA3.

[0191] Each of the plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex upward.

[0192] The filler layer FIL may be disposed on the lenses LNS. The filler layer FIL may have a predetermined refractive index so that light travels in the third direction DR3 at the interface between the lenses LNS and the filler layer FIL. The filler layer FIL may also be a planarization layer. The filler layer FIL may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0193] The cover layer DCL can be disposed on the filler layer FIL. The cover layer DCL can be a glass substrate or a polymer resin such as resin. If the cover layer DCL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can serve to adhere the cover layer DCL. If the cover layer DCL is a glass substrate, it can serve as a sealing substrate. If the cover layer DCL is a polymer resin such as resin, it can be applied directly on the filler layer FIL.

[0194] Although not shown in the drawings, the display unit 200 may further include a polarizer disposed on the cover layer DCL. The polarizer may be disposed on one surface of the cover layer DCL. The polarizer may be a structure for preventing a decrease in visibility due to external light reflection. The polarizer may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but is not limited thereto. However, if the visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, and CF3, the polarizer may be omitted.

[0195] 13 is a diagram illustrating a schematic layout of interconnection lines connecting pixel circuits and sub-pixels in a display area of ​​a display device according to an embodiment. The relative layout of interconnection lines RML connecting the pixel circuits 800 included in the driver 100 of the display device 10 to the display area DAA of the display unit 200 is shown in FIG.

[0196] 13, in the display device 10 according to an embodiment, the driver 100 and the display unit 200 may have different areas, and the pixel circuit unit 800 and the display area DAA may also have different areas. However, the pixel circuits (PXC in FIG. 5) of the pixel circuit unit 800 correspond to the sub-pixels (SP1, SP2, and SP3 in FIG. 3) of the display area DAA, respectively, and may be connected to each other by connecting wires RML. In an embodiment, the number of pixel circuits PXC arranged in the driver 100 of the display device 10 may be the same as the number of sub-pixels SP1, SP2, and SP3 of the display unit 200, and the respective numbers of these may be the same as the number of connecting wires RML and first through holes TSV1 formed in the second single-crystal semiconductor substrate 210.

[0197] The connecting wires RML of the connecting wire layer 500 may connect the pixel circuits PXC to the sub-pixels SP1, SP2, and SP3 so that they correspond to each other. The connecting wires RML may be arranged so that the pixel circuits PXC arranged in the pixel circuit unit 800, which has a small area, correspond to the sub-pixels SP1, SP2, and SP3 arranged in the display area DAA, which has a large area. Some of the sub-pixels SP1, SP2, and SP3 in the display area DAA may overlap with the pixel circuit unit 800, while others may not. Therefore, some of the connecting wires RML may extend beyond the pixel circuit unit 800 to the display area DAA, where they do not overlap with the pixel circuit unit 800, and other parts may be arranged in the overlapping area within the pixel circuit unit 800. The spacing between the connecting wires RML is wide in the area of ​​the display area DAA that does not overlap with the pixel circuit unit 800, but the spacing between them is narrow in the area of ​​the display area DAA that overlaps with the pixel circuit unit 800 because the connecting wires RML are concentrated. According to one embodiment, the connecting wiring RML may include a plurality of bridge lines RBL1, RBL2, and RBL3 and bridge contacts RCT1, RCT2, and RCT3 arranged in different layers, and the bridge lines RBL1, RBL2, and RBL3 may be arranged adjacent to each other in a plan view but may be arranged in different layers, thereby preventing electrical interference.

[0198] The structure of the interconnection wiring RML will be described in more detail below with reference to other drawings.

[0199] 14 is a schematic diagram showing the connection between sub-pixels and pixel circuits by connecting wiring in a display device according to one embodiment, and schematically shows the relative arrangement of the sub-pixels SP in the display area DAA and the pixel circuits PXC in the pixel circuit unit 800, as well as the layout design of the connecting wiring RML suitable for this.

[0200] 14, the pixel circuit unit 800 includes a plurality of pixel circuits PXC, which may be arranged in a first direction DR1 and a second direction DR2. The pixel circuits PXC may include first to eighth circuit columns PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8 arranged in the first direction DR1 and first to eighth circuit rows PR1, PR2, PR3, PR4, PR5, PR6, PR7, and PR8 arranged in the second direction DR2. Figure 14 illustrates an arrangement of eight circuit columns and eight circuit rows, totaling 64 pixel circuits PXC.

[0201] The display unit 200 includes a plurality of subpixels SP arranged in the display area DAA, which may also be arranged in the first direction DR1 and the second direction DR2. The subpixels SP may include first through eighth pixel columns EC1, EC2, EC3, EC4, EC5, EC6, EC7, and EC8 arranged in the first direction DR1 and first through eighth pixel rows ER1, ER2, ER3, ER4, ER5, ER6, ER7, and ER8 arranged in the second direction DR2. FIG. 14 illustrates an example of an arrangement of eight pixel columns and eight pixel rows, totaling 64 subpixels SP. Of the plurality of subpixels SP, 16 subpixels SP belonging to the first through fourth pixel rows ER1, ER2, ER3, and ER4 and the fifth through eighth pixel columns EC5, EC6, EC7, and EC8 may overlap with the pixel circuit unit 800. The other subpixels SP may not overlap with the pixel circuit unit 800.

[0202] As described above, the 64 pixel circuits PXC of the pixel circuit unit 800 correspond to the 64 sub-pixels SP of the display area DAA, and these may be connected to each other via connecting wires RML. The sub-pixels SP arranged in the first pixel row ER1 in the first direction DR1 of the pixel circuit unit 800 may be connected to the pixel circuits PXC via connecting wires RML extending generally in the first direction DR1. The sub-pixels SP arranged in the eighth pixel column EC8 in the second direction DR2 of the pixel circuit unit 800 may be connected to the pixel circuits PXC via connecting wires RML extending generally in the second direction DR2. The sub-pixels SP arranged in a diagonal direction between the first direction DR1 and the second direction DR2 of the pixel circuit unit 800 may be connected to the pixel circuits PXC via connecting wires RML extending generally in the diagonal direction. Although not shown in the drawing, other sub-pixels SP may also be connected to the pixel circuits PXC via connecting wires RML.

[0203] Although the drawing shows connecting wires RML connecting some subpixels SP and pixel circuits PXC, the same number of connecting wires RML may be arranged corresponding to the subpixels SP and pixel circuits PXC in the portion shown in Fig. 14. For example, Fig. 14 shows 64 subpixels SP and 64 pixel circuits PXC, and 64 connecting wires RML may be arranged in the corresponding region. In addition to the 12 connecting wires RML shown in the drawing, a total of 52 connecting wires RML may be arranged corresponding to each subpixel SP and pixel circuit PXC.

[0204] If the connecting wires RML are arranged randomly to connect the sub-pixels SP and the pixel circuits PXC, interference may occur between adjacent connecting wires RML. However, the connecting wires RML can be divided by bridge lines arranged on different layers, and the connecting wires RML can be arranged on different layers or arranged sequentially according to the distance, thereby minimizing the interference between the connecting wires RML.

[0205] FIG. 15 is a schematic cross-sectional view showing an example of an interconnection layer of a display device according to an embodiment.

[0206] 15, the interconnection layer 500 of the display device 10 may include a plurality of conductive layers and interlayer insulating layers RINS1, RINS2, and RINS3 therebetween. The first interlayer insulating layer RINS1 may be disposed on the driving circuit layer 120, and the second interlayer insulating layer RINS2 and the third interlayer insulating layer RINS3 may be disposed sequentially on the first interlayer insulating layer RINS1. The second single-crystal semiconductor substrate 210 may be disposed on the third interlayer insulating layer RINS3. The first conductive layer of the interconnection layer 500 may be disposed on the first interlayer insulating layer RINS1, the second conductive layer may be disposed on the second interlayer insulating layer RINS2, and the third conductive layer may be disposed on the third interlayer insulating layer RINS3.

[0207] The first conductive layer may include a first bridge line RBL1 and a plurality of first bridge contacts RCT1, the second conductive layer may include a second bridge line RBL2 and a plurality of second bridge contacts RCT2, and the third conductive layer may include a third bridge line RBL3 and a plurality of third bridge contacts RCT3. The plurality of bridge lines RBL1, RBL2, and RBL3 may include interlayer insulating layers RINS1, RINS2, and RINS3 disposed therebetween, so that they can be electrically insulated even when disposed adjacent to each other.

[0208] In the display device 10, the connecting wiring RML may be composed of bridge lines RBL1, RBL2, and RBL3, bridge contacts RCT1, RCT2, and RCT3, and bridge vias between them. The connecting wiring RML may be connected to the reflective electrode RL of the display layer 230 through the conductive via RVA disposed in the first through hole TSV1 of the second single crystal semiconductor substrate 210.

[0209] For example, one connecting wiring RML may include one bridge line RBL1, RBL2, RBL3 and two bridge contacts RCT1, RCT2, RCT3. The first bridge line RBL1 may be connected to the conductive via RVA through the second bridge contact RCT2 and the third bridge contact RCT3. The first bridge line RBL1 may be connected to the driving circuit layer 120 through the bridge via. The second bridge line RBL2 may be connected to the driving circuit layer 120 through the first bridge contact RCT1 and may be connected to the conductive via RVA through the third bridge contact RCT3. The third bridge line RBL3 may be connected to the conductive via RVA and may be connected to the driving circuit layer 120 through the second bridge contact RCT2 and the first bridge contact RCT1.

[0210] One side of each of the bridge lines RBL1, RBL2, and RBL3 may overlap a sub-pixel SP or a reflective electrode RL of the display unit 200, and the other side may overlap a pixel circuit PXC of the driving circuit layer 120 of the driver 100. One connecting wiring RML may include one bridge line RBL1, RBL2, and RBL3 and bridge contacts RCT1, RCT2, and RCT3 at both ends of the bridge line RBL1, RBL2, and RBL3. One bridge line RBL1, RBL2, and RBL3 is disposed between a pair of connected sub-pixels SP and a pair of connected pixel circuits PXC, and may be electrically connected to the sub-pixel SP and the pixel circuit PXC via the bridge contacts RCT1, RCT2, and RCT3 at both ends of the corresponding bridge line RBL1, RBL2, and RBL3.

[0211] FIG. 16 is a schematic cross-sectional view showing an example of an interconnection layer of a display device according to another embodiment.

[0212] 16 , in an embodiment in which the connecting wiring layer 500 is disposed on the second single-crystal semiconductor substrate 210, a first conductive layer of the connecting wiring layer 500 may be disposed on the second single-crystal semiconductor substrate 210. A reflective electrode RL of the display element layer EML may be disposed on a third interlayer insulating layer RINS3. The first conductive layer of the connecting wiring layer 500 may be connected to the driving circuit layer 120 of the driving unit 100 or the pixel circuit PXC through a conductive via RVA, and the third conductive layer may be connected to the reflective electrode RL through a bridge via.

[0213] The different connecting wires RML of the display device 10 may differ in the positions of the conductive layer on which the bridge lines RBL1, RBL2, and RBL3 are arranged, and may also differ in the lengths or extension directions of the bridge lines RBL1, RBL2, and RBL3. Furthermore, the different connecting wires RML may differ in the positions of the bridge contacts RCT1, RCT2, and RCT3 or bridge vias connected to both ends of the bridge lines RBL1, RBL2, and RBL3. The display device 10 is designed so that the positions of the conductive layer on which the bridge lines RBL1, RBL2, and RBL3 of the connecting wires RML are arranged are different from each other, thereby preventing interference between adjacent connecting wires RML.

[0214] In addition, when the connecting wires RML are arranged in a concentrated manner in the pixel circuit unit 800 having a small area, the display device 10 may have a layout design that can secure sufficient space in a plan view so that the connecting wires RML are not arranged too closely to each other.

[0215] Figures 17 and 18 are schematic diagrams showing the connection of sub-pixels and pixel circuits by connecting wiring in the first region of Figure 14. Figures 17 and 18 show the arrangement of bridge lines RBL1, RBL2, and RBL3 of connecting wiring RML that connects a first pixel row ER1 and a second pixel row ER2, which are arranged in a first direction DR1 of the pixel circuit unit 800, to pixel circuits PXC among the sub-pixels SP arranged in the display region DAA.

[0216] 17 and 18 , the subpixel SP farthest from the pixel circuit unit 800 or the subpixel SP arranged at the outermost side of the display area DAA may be connected to the pixel circuit PXC arranged at the outermost side of the pixel circuit unit 800. The subpixels SP arranged inward from the outermost subpixel SP may be connected to the pixel circuits PXC arranged inward from the outermost pixel circuit PXC. For example, the subpixels SP arranged in the first pixel column EC1 of the first pixel row ER1 may be connected to the pixel circuits PXC of the first circuit row PR1 and the first circuit column PC1. The other subpixels SP of the first pixel row ER1 may be connected to the pixel circuits PXC of the first circuit row PR1. The subpixels SP arranged in the first pixel column EC1 of the second pixel row ER2 may be connected to the pixel circuits PXC of the second circuit row PR2 and the first circuit column PC1. The other subpixels SP of the second pixel row ER2 may be connected to the pixel circuits PXC of the second circuit row PR2.

[0217] Among the sub-pixels SP arranged in the first pixel row ER1, four sub-pixels SP that do not overlap with the pixel circuit unit 800 may be arranged such that bridge lines RBL1, RBL2, and RBL3 of the connecting wiring RML extend outside the pixel circuit unit 800. Among them, the first sub-pixel SP#1 at the outermost position of the display area DAA may be connected to the pixel circuit PXC via a connecting wiring including a first bridge line RBL1 disposed on a first conductive layer of the connecting wiring layer 500. The second sub-pixel SP#2 adjacent to the first sub-pixel SP#1 in the first direction DR1 may be connected to the pixel circuit PXC via a connecting wiring including a second bridge line RBL2 disposed on a second conductive layer of the connecting wiring layer 500. The third sub-pixel SP#3 adjacent to the second sub-pixel SP#2 in the first direction DR1 may be connected to the pixel circuit PXC via a connecting wiring including a third bridge line RBL3 disposed on a third conductive layer of the connecting wiring layer 500. The third sub-pixel SP#3 and a fourth sub-pixel SP#4 adjacent in the first direction DR1 may be connected to the pixel circuit PXC via a connecting wiring including a first bridge line RBL1 disposed in a first conductive layer of the connecting wiring layer 500. Each of the four sub-pixels SP may be connected to the pixel circuit PXC via a connecting wiring including bridge lines RBL1, RBL2, and RBL3 disposed in another layer and adjacent to the other sub-pixels SP.

[0218] In addition, the first bridge line RBL1 connected to the outermost first sub-pixel SP#1 of the display area DAA may be connected to the pixel circuit PXC of the pixel circuit unit 800 via the second to fourth sub-pixels SP#2, SP#3, and SP#4. The second bridge line RBL2 connected to the second sub-pixel SP#2 is also connected to the pixel circuit PXC of the pixel circuit unit 800 via the third and fourth sub-pixels SP#3 and SP#4. That is, the fourth sub-pixel SP#4 needs to have enough space to accommodate at least four bridge lines RBL1, RBL2, and RBL3. In consideration of this, the first bridge line RBL1 connected to the outermost first sub-pixel SP#1 among the plurality of bridge lines RBL1, RBL2, and RBL3 may be biased downward from the center of the first sub-pixel SP#1, which is the other side in the second direction DR2. The second bridge line RBL2 and the third bridge line RBL3 may be sequentially arranged above the first bridge line RBL1, which is the other side in the second direction DR1. That is, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP arranged relatively outside may be arranged to be biased to one side from the center of the sub-pixel SP compared to the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP arranged further inside.

[0219] Therefore, the positions of the ends (starting points) of the bridge lines RBL1, RBL2, and RBL3 may be different among the four subpixels SP in the first pixel row ER1. For example, the end position of the first bridge line RBL1 in the outermost first subpixel SP#1 may be different from the end position of the second bridge line RBL2 in the second subpixel SP#2 adjacent to the first subpixel SP#1 in the first direction DR1, and the relative positions of the bridge lines in each of the corresponding subpixels SP may also be different.

[0220] Among the sub-pixels SP arranged in the second pixel row ER2, four sub-pixels SP that do not overlap with the pixel circuit unit 800 may also be arranged such that the bridge lines RBL1, RBL2, and RBL3 of the connecting wiring RML extend outside the pixel circuit unit 800. The first to fourth sub-pixels SP#1, SP#2, SP#3, and SP#4 of the second pixel row ER2 may also be connected to the pixel circuits PXC of the second circuit row PR2 via the connecting wiring RML including the first bridge line RBL1, the second bridge line RBL2, and the third bridge line RBL3, respectively.

[0221] The subpixels SP of the first pixel row ER1 may be connected to the first circuit row PR1 aligned in the first direction DR1. Meanwhile, the subpixels SP of the second pixel row ER2 may be connected to the second circuit row PR2 and may not be aligned in the first direction DR1. Therefore, the bridge lines RBL1, RBL2, and RBL3 connected to the second pixel row ER2 may extend diagonally. However, because the bridge lines RBL1, RBL2, and RBL3 connected to the first pixel row ER1 are biased downward relative to the subpixels SP, the bridge lines RBL1, RBL2, and RBL3 connected to the subpixels SP of the second pixel row ER2 are also diagonally aligned, ensuring sufficient space.

[0222] This can be similarly applied to the sub-pixels SP in the first pixel row ER1 and the second pixel row ER2 that overlap the pixel circuit unit 800. For example, the sub-pixels SP in the fifth through eighth pixel columns EC5, EC6, EC7, and EC8 in the first pixel row ER1 and the second pixel row ER2 may be connected to the pixel circuits PXC via connecting wires RML or bridge lines RBL1, RBL2, and RBL3 that overlap the pixel circuit unit 800. As described above, adjacent sub-pixels SP are connected to the pixel circuits PXC via connecting wires RML including bridge lines RBL1, RBL2, and RBL3 in different layers, and the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP located relatively outside may be offset to one side from the center of the sub-pixels SP compared to the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP located further inside.

[0223] Figures 19 and 20 are schematic diagrams showing the connection of sub-pixels and pixel circuits by connecting wiring in the second region of Figure 14. Figures 19 and 20 show the arrangement of bridge lines RBL1, RBL2, and RBL3 of connecting wiring RML that connects the seventh pixel column EC7 and the eighth pixel column EC8, which are arranged in the second direction DR2 of the pixel circuit section 800, to the pixel circuits PXC, among the sub-pixels SP arranged in the display region DAA.

[0224] 19 and 20, the subpixels SP arranged sequentially inward from the outermost subpixel SP may be connected to the pixel circuits PXC arranged sequentially inward from the outermost subpixel SP. For example, the subpixel SP arranged in the eighth pixel row ER8 of the eighth pixel column EC8 may be connected to the pixel circuits PXC of the eighth circuit column PC8 and the first circuit row PR1. The other subpixels SP of the eighth pixel column EC8 may be connected to the pixel circuits PXC of the eighth circuit column PC8. The subpixels SP arranged in the eighth pixel row ER8 of the seventh pixel column EC7 may be connected to the pixel circuits PXC of the seventh circuit column PC7 and the first circuit row PR1. The other subpixels SP of the seventh pixel column EC7 may be connected to the pixel circuits PXC of the seventh circuit column PC7.

[0225] Among the sub-pixels SP arranged in the eighth pixel column EC8, four sub-pixels SP that do not overlap with the pixel circuit unit 800 may be arranged such that bridge lines RBL1, RBL2, and RBL3 of the connecting wiring RML extend outside the pixel circuit unit 800. Among them, the first sub-pixel SP#1 at the outermost position in the display area DAA may be connected to the pixel circuit PXC via a connecting wiring including a first bridge line RBL1 of the connecting wiring layer 500. The second sub-pixel SP#2 adjacent to the first sub-pixel SP#1 in the second direction DR2 may be connected to the pixel circuit PXC via a connecting wiring including a second bridge line RBL2 of the connecting wiring layer 500. The third sub-pixel SP#3 adjacent to the second sub-pixel SP#2 in the second direction DR2 may be connected to the pixel circuit PXC via a connecting wiring including a third bridge line RBL3 of the connecting wiring layer 500. The third sub-pixel SP#3 and a fourth sub-pixel SP#4 adjacent in the second direction DR2 may be connected to the pixel circuit PXC via a connecting wiring including a first bridge line RBL1 of the connecting wiring layer 500. Each of the four sub-pixels SP may be connected to the pixel circuit PXC via a connecting wiring including bridge lines RBL1, RBL2, and RBL3 disposed in another layer and adjacent to the other sub-pixels SP.

[0226] In addition, the first bridge line RBL1 connected to the outermost first sub-pixel SP#1 of the display area DAA may be connected to the pixel circuit PXC of the pixel circuit unit 800 via the second to fourth sub-pixels SP#2, SP#3, and SP#4. The second bridge line RBL2 connected to the second sub-pixel SP#2 is also connected to the pixel circuit PXC of the pixel circuit unit 800 via the third and fourth sub-pixels SP#3 and SP#4. That is, the fourth sub-pixel SP#4 needs to have enough space to accommodate at least four bridge lines RBL1, RBL2, and RBL3. In consideration of this, the first bridge line RBL1 connected to the outermost first sub-pixel SP#1 among the plurality of bridge lines RBL1, RBL2, and RBL3 may be disposed offset to the right side, which is one side of the center of the first sub-pixel SP#1 in the first direction DR1. The second bridge line RBL2 and the third bridge line RBL3 may be sequentially disposed to the left side, which is the other side of the first direction DR1, of the first bridge line RBL1. That is, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP arranged relatively outside may be arranged to be biased to one side from the center of the sub-pixel SP compared to the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP arranged further inside.

[0227] Therefore, the positions of the ends, which are the starting points of the bridge lines RBL1, RBL2, and RBL3, may be different from one another within the four subpixels SP in the eighth pixel column EC8. For example, the end position of the first bridge line RBL1 in the outermost first subpixel SP#1 may be different from the end position of the second bridge line RBL2 in the second subpixel SP#2 adjacent to the first subpixel SP#1 in the second direction DR2, and the relative positions of the bridge lines in each of the corresponding subpixels SP may also be different.

[0228] Among the sub-pixels SP arranged in the seventh pixel column EC7, four sub-pixels SP that do not overlap with the pixel circuit unit 800 may also be arranged such that the bridge lines RBL1, RBL2, and RBL3 of the connecting wiring RML extend outside the pixel circuit unit 800. The first to fourth sub-pixels SP#1, SP#2, SP#3, and SP#4 of the seventh pixel column EC7 may also be connected to the pixel circuits PXC of the seventh circuit column PC7 via the connecting wiring RML including the first bridge line RBL1, the second bridge line RBL2, the third bridge line RBL3, and the first bridge line RBL1, respectively.

[0229] The subpixels SP of the eighth pixel column EC8 may be connected to the eighth circuit column PC8 aligned in the second direction DR2. Meanwhile, the subpixels SP of the seventh pixel column EC7 are connected to the seventh circuit column PC7 and are not aligned in the second direction DR2. Therefore, the bridge lines RBL1, RBL2, and RBL3 connected to the seventh pixel column EC7 may extend diagonally. However, because the bridge lines RBL1, RBL2, and RBL3 connected to the eighth pixel column EC8 are biased to the right of the subpixels SP, sufficient space may be secured for the bridge lines RBL1, RBL2, and RBL3 connected to the subpixels SP of the seventh pixel column EC7 to extend diagonally.

[0230] This can be similarly applied to the sub-pixels SP in the eighth pixel column EC8 and the seventh pixel column EC7 that overlap the pixel circuit unit 800. For example, the sub-pixels SP in the first to fourth pixel rows ER1, ER2, ER3, and ER4 in the eighth pixel column EC8 and the seventh pixel column EC7 may be connected to the pixel circuits PXC via connecting wires RML or bridge lines RBL1, RBL2, and RBL3 that overlap the pixel circuit unit 800.

[0231] Figures 21 to 23 are schematic diagrams showing connections between subpixels and pixel circuits by connecting wiring in the third region of Figure 14. Figures 21 to 23 show the arrangement of bridge lines RBL1, RBL2, and RBL3 of connecting wiring RML that connects subpixels SP arranged in the diagonal direction between the first direction DR1 and the second direction DR2 of the pixel circuit unit 800, among the subpixels SP arranged in the display area DAA, to pixel circuits PXC.

[0232] 21 to 23, first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 sequentially arranged in a diagonal direction among the subpixels SP in the display area DAA may be sequentially connected to pixel circuits PXC sequentially arranged in a diagonal direction among the pixel circuits PXC in the pixel circuit unit 800. For example, in FIG. 21, the first subpixel SP#1 arranged in the first pixel column EC1 and the eighth pixel row ER8 is the outermost subpixel in the diagonal direction and may be connected to the pixel circuits PXC in the first circuit column PC1 and the eighth circuit row PR8 in the pixel circuit unit 800. The second to fourth subpixels SP#2, SP#3, and SP#4 arranged in a diagonal direction from the first subpixel SP#1 in FIG. 21 may be respectively connected to the pixel circuits PXC arranged in a diagonal direction from the pixel circuit PXC connected to the first subpixel SP#1.

[0233] The first subpixel SP#1 in FIG. 21 may be connected to the pixel circuit PXC via a connecting wire RML including a first bridge line RBL1. The second to fourth subpixels SP#2, SP#3, and SP#4 in FIG. 21 may be connected to the pixel circuit PXC via connecting wires RML including a second bridge line RBL2, a third bridge line RBL3, and a first bridge line RBL1, respectively. As described above, the fourth subpixel SP#4 in FIG. 21 needs space for four bridge lines RBL1, RBL2, and RBL3. The first bridge line RBL1 connected to the first subpixel SP#1 may be positioned diagonally toward one side of the center of the subpixel, for example, toward the bottom left. The other bridge lines connected to the second to fourth subpixels SP#2, SP#3, and SP#4 may be positioned sequentially toward the upper right from the first bridge line RBL1 connected to the first subpixel SP#1.

[0234] The first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 22 may be adjacent in the second direction DR2 to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 21. In addition, the pixel circuits PXC connected to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 22 may also be adjacent in the second direction DR2 to the pixel circuits PXC connected to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 21.

[0235] The first subpixel SP#1, which is the outermost subpixel among the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in FIG. 22, may be connected to the pixel circuit PXC via a connecting wire RML including a first bridge line RBL1. The second to fourth subpixels SP#2, SP#3, and SP#4 in FIG. 22 may be connected to the pixel circuit PXC via a connecting wire RML including a second bridge line RBL2, a third bridge line RBL3, and a first bridge line RBL1, respectively. As described above, the fourth subpixel SP#4 in FIG. 22 must have sufficient space for the four bridge lines RBL1, RBL2, and RBL3. However, unlike the arrangement of the bridge lines RBL1, RBL2, and RBL3 in FIG. 21, the first bridge line RBL1 connected to the first subpixel SP#1 may be biased to one side of the center of the subpixel, for example, toward the upper right corner in the diagonal direction. The other bridge lines connected to the second to fourth sub-pixels SP#2, SP#3, and SP#4 may be sequentially arranged on the lower left side of the first bridge line RBL1 connected to the first sub-pixel SP#1.

[0236] The first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 23 may be adjacent in the first direction DR1 to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 21. In addition, the pixel circuits PXC connected to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 23 may also be adjacent in the first direction DR1 to the pixel circuits PXC connected to the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in Fig. 21.

[0237] The first subpixel SP#1, which is the outermost subpixel among the first to fourth subpixels SP#1, SP#2, SP#3, and SP#4 in FIG. 23, may be connected to the pixel circuit PXC via a connecting wire RML including a first bridge line RBL1. The second to fourth subpixels SP#2, SP#3, and SP#4 in FIG. 23 may be connected to the pixel circuit PXC via a connecting wire RML including a second bridge line RBL2, a third bridge line RBL3, and a first bridge line RBL1, respectively. As described above, the fourth subpixel SP#4 in FIG. 23 must have sufficient space to accommodate the four bridge lines RBL1, RBL2, and RBL3. Similar to the arrangement of the bridge lines RBL1, RBL2, and RBL3 in FIG. 21, the first bridge line RBL1 connected to the first subpixel SP#1 may be arranged offset to one side of the center of the subpixel, for example, toward the diagonal lower left. Other bridge lines connected to the second to fourth sub-pixels SP#2, SP#3, and SP#4 may be sequentially arranged on the upper right side from the first bridge line RBL1 connected to the first sub-pixel SP#1.

[0238] The first bridge line RBL1 connected to the first sub-pixel SP#1 in Fig. 22 may be arranged so as not to interfere with the first bridge line RBL1 connected to the first sub-pixel SP#1 in Fig. 21. In addition, the first bridge line RBL1 connected to the first sub-pixel SP#1 in Fig. 23 may be arranged so as not to interfere with the first bridge line RBL1 connected to the fourth sub-pixel SP#4 in Fig. 21. As described above with reference to Figs. 17 to 20, the bridge lines RBL1, RBL2, and RBL3 arranged in two regions (first region and second region) aligned in the first direction DR1 or the second direction DR2 from the pixel circuit unit 800 are arranged offset to one side from the center of the sub-pixel SP, thereby ensuring sufficient space for the bridge lines RBL1, RBL2, and RBL3 arranged in the region (third region) aligned diagonally from the pixel circuit unit 800. In addition, if the space separating two adjacent bridge lines RBL1, RBL2, and RBL3 is insufficient or they interfere with each other, the adjacent bridge lines RBL1, RBL2, and RBL3 may be disposed on different conductive layers.

[0239] 24 is a schematic diagram illustrating the arrangement of vias connecting sub-pixels to connecting wirings of a display device according to an embodiment, and illustrates the regions where vias connecting bridge lines RBL1, RBL2, and RBL3 of the connecting wiring RML to sub-pixels SP or one end of the bridge lines RBL1, RBL2, and RBL3 are located.

[0240] 24, the outermost subpixels SP of the display area DAA may be subpixels arranged in the first pixel column EC1 and the eighth pixel row ER8. The subpixels arranged in the first pixel column EC1 and the eighth pixel row ER8 may be connected to the pixel circuit PXC via connecting wiring RML including the first bridge line RBL1. A via connected to the first bridge line RBL1, for example, a via between the first bridge line RBL1 and the second bridge contact RCT2 in FIG. 15 or a conductive via RVA arranged in the first through hole TSV1, may overlap the first pixel column EC1 and the eighth pixel row ER8. The first contact region CNA1 in FIG. 24 may be a region in which the bridge contact, via, or conductive via RVA connected to the first bridge line RBL1 is arranged.

[0241] The sub-pixels arranged in the second pixel column EC2 and the seventh pixel row ER7 may be connected to the pixel circuits PXC through connecting wiring RML including the second bridge line RBL2. Vias connected to the second bridge line RBL2, such as the via between the second bridge line RBL2 and the third bridge contact RCT3 in FIG. 15 or the conductive via RVA arranged in the first through-hole TSV1, may overlap the second pixel column EC2 and the seventh pixel row ER7. The second contact region CNA2 in FIG. 24 may be a region where bridge contacts or vias connected to the second bridge line RBL2 are arranged.

[0242] The sub-pixels arranged in the third pixel column EC3 and the sixth pixel row ER6 may be connected to the pixel circuits PXC through connecting wiring RML including the third bridge line RBL3. A via connected to the third bridge line RBL3, for example, a conductive via RVA connected to the third bridge line RBL3 in FIG. 15, may overlap the third pixel column EC3 and the sixth pixel row ER6. A third contact region CNA3 in FIG. 24 may be a region where the conductive via RVA connected to the third bridge line RBL3 is arranged.

[0243] Ends of the bridge lines RBL1, RBL2, and RBL3 arranged on the same conductive layer, connected to the subpixels SP, may be arranged in the same pixel row or pixel column. For example, one end of the first bridge line RBL1 may be arranged in the first pixel column EC1 and the eighth pixel row ER8. Although not shown in the drawings, the opposite ends of the bridge lines RBL1, RBL2, and RBL3, connected to the pixel circuits PXC of the pixel circuit unit 800, may also be arranged in the same circuit row or circuit column. For example, the other end of the first bridge line RBL1 may be arranged in the first circuit column PC1 and the eighth circuit row PR8. Although FIGS. 17 to 24 illustrate only the arrangement of the connecting wires RML connected to the subpixels SP arranged in the upper left of the pixel circuit unit 800, the connecting wires RML connected to the subpixels SP arranged in the lower left, upper right, and lower right of the pixel circuit unit 800 may be arranged in the same manner.

[0244] The display device 10 includes a plurality of bridge lines RBL1, RBL2, and RBL3 arranged in different conductive layers in the interconnection layer 500, and these are arranged according to the rules described above in Figures 17 to 24, so that a plurality of interconnection lines RML arranged in a small area can be arranged so as not to electrically interfere with each other.

[0245] 17 to 20 , among the plurality of bridge lines RBL1, RBL2, and RBL3, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP that overlap the pixel circuit unit 800 may be shorter in length than the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP that do not overlap the pixel circuit unit 800. In this case, the length and conductor resistance of the connecting wires RML connected to the pixel circuit unit 800 may vary depending on the position of the sub-pixels SP, which may cause signal deviation between the sub-pixels SP. In consideration of this, the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP that overlap the pixel circuit unit 800 may have different wiring routings from the bridge lines RBL1, RBL2, and RBL3 connected to the sub-pixels SP that do not overlap the pixel circuit unit 800.

[0246] 25 is a diagram illustrating an example of the shape of a bridge line according to an embodiment of the present invention, and shows an example of a bridge line RBL connected to a sub-pixel SP overlapping with a pixel circuit unit 800.

[0247] 25, the bridge lines RBL may generally have a linear shape as described above, but the bridge lines RBL connected to the sub-pixels SP overlapping the pixel circuit unit 800 may have a partially bent shape to extend the wiring length. Because the sub-pixels SP overlapping the pixel circuit unit 800 have a short planar distance from the pixel circuit PXC, the bridge lines RBL connecting them can have a sufficient space to be partially bent. Therefore, the bridge lines RBL connected to the sub-pixels SP overlapping the pixel circuit unit 800 or the bridge lines RBL completely overlapping the pixel circuit unit 800 may have a zigzag shape to extend the wiring length relative to the planar distance. Therefore, the wiring resistance of the wiring to which signals are applied from the driver 100 can be designed to be uniform regardless of the position of the sub-pixels SP.

[0248] 26 is a diagram illustrating an example of a cross-sectional connection structure of a connection line according to an embodiment of the present invention, and illustrates an example of bridge lines RBLa, RBLb, and RBLc connected to sub-pixels SP overlapping with the pixel circuit unit 800.

[0249] 26 , the plurality of connecting wires RML may include one bridge line RBL and two bridge contacts RCT as described above. However, the bridge line RBL connected to the sub-pixels SP overlapping the pixel circuit unit 800 may include multiple bridge lines RBLa, RBLb, and RBLc to extend the wiring length. Because the sub-pixels SP overlapping the pixel circuit unit 800 have a short planar distance from the pixel circuit PXC, sufficient space can be secured for the connecting wires connecting them to the multiple bridge lines RBLa, RBLb, and RBLc disposed in different conductive layers. The bridge line RBL connected to the sub-pixels SP overlapping the pixel circuit unit 800 or the bridge line RBL completely overlapping the pixel circuit unit 800 may have an extended wiring length relative to the planar distance. For example, one connecting wire RML may include a first bridge line RBLa of a first conductive layer, a second bridge line RBLb of a second conductive layer, and a third bridge line RBLc of a third conductive layer. Therefore, regardless of the position of the sub-pixel SP, the wiring resistance of the wiring to which the signal is applied from the driving section 100 can be designed to be uniform.

[0250] Various embodiments of the display device 10 will now be described with reference to other drawings.

[0251] FIG. 27 is a diagram showing a schematic arrangement of connecting lines that connect pixel circuit units and sub-pixels in a display area of ​​a display device according to another embodiment.

[0252] 27, the display device 10 includes a small-area driver 100 including a plurality of first single-crystal semiconductor substrates 110a, 110b, 110c, and 110d, and a plurality of pixel circuit units 800a, 800b, 800c, and 800d arranged on each of the first single-crystal semiconductor substrates 110a, 110b, 110c, and 110d are connected to the sub-pixels SP in the display area DAA. If one pixel circuit unit 800 is connected to the sub-pixels SP arranged in the display area DAA with a large area, there is insufficient space for the connecting wires RML. On the other hand, if the driver 100 includes a plurality of first single-crystal semiconductor substrates 110a, 110b, 110c, and 110d and includes a plurality of pixel circuit units 800a, 800b, 800c, and 800d, the pixel circuit units 800a, 800b, 800c, and 800d partially cover the sub-pixels SP in the display area DAA, which is advantageous in securing space for the connecting wires RML.

[0253] FIG. 28 is a schematic cross-sectional view showing an example of an interconnection wiring layer of a display device according to another embodiment.

[0254] 28, in the display device 10, the first single crystal semiconductor substrate 110 of the driver unit 100 may have a larger area than the second single crystal semiconductor substrate 210 of the display unit 200. Therefore, the protective layer 900 may surround the second single crystal semiconductor substrate 210.

[0255] Fig. 29 is a perspective view showing a head-mounted display device according to one embodiment, and Fig. 30 is an exploded perspective view showing an example of the head-mounted display device of Fig. 29.

[0256] Referring to Figures 29 and 30, a head-mounted display device 1000 according to one embodiment includes a first display device 11, a second display device 12, a display device storage section 1100, a storage section cover 1200, a first eyepiece lens 1210, a second eyepiece lens 1220, a head-mounted band 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0257] The first display device 11 provides an image to the user's left eye, and the second display device 12 provides an image to the user's right eye. Since the first display device 11 and the second display device 12 are each substantially similar to the display device 10 described with reference to FIG. 1, a description of the first display device 11 and the second display device 12 will be omitted.

[0258] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0259] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The middle frame 1400 serves to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0260] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 via a connector. The control circuit board 1600 converts an externally input image source into digital video data DATA and transmits the digital video data DATA to the first display device 11 and the second display device 12 via the connector.

[0261] The control circuit board 1600 transmits digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and transmits digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 11 and the second display device 12.

[0262] The display device housing 1100 houses the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and a connector. The housing cover 1200 is disposed to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for receiving the user's left eye and a second eyepiece 1220 for receiving the user's right eye. Although the drawings illustrate a case in which the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, the present invention is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be integrated.

[0263] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Thus, the user can view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0264] The head mount band 1300 serves to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be maintained in a state where they are positioned over the user's left and right eyes, respectively. If the display device housing 1100 is realized to be lightweight and compact, the head mounted display device 1000 may include an eyeglass frame instead of the head mount band 1300.

[0265] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving a video source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0266] FIG. 31 is a perspective view showing a head-mounted display device according to an embodiment.

[0267] 31, the head mounted display device 1000_1 according to an embodiment may be a display device in the form of glasses, in which a lightweight and compact display device housing 1200_1 is realized. The head mounted display device 1000_1 according to an embodiment may include a display device 13, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path converting member 1070, and the display device housing 1200_1.

[0268] The display device housing 1200_1 may include a display device 13, an optical member 1060, and an optical path converting member 1070. An image displayed on the display device 13 is enlarged by the optical member 1060, and the optical path is converted by the optical path converting member 1070, so that the image can be provided to the right eye of the user through the right eye lens 1020. As a result, the user can view an augmented reality image, which is a combination of a virtual image displayed on the display device 13 and a real image viewed through the right eye lens 1020, through his or her right eye.

[0269] Although the drawings illustrate an example in which the display device housing 1200_1 is disposed at the right end of the support frame 1030, the present invention is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, in which case an image from the display device 13 may be provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user may view an image displayed on the display device 13 through both the left and right eyes.

[0270] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and is not limiting.

Claims

1. a first single-crystal semiconductor substrate on which a plurality of pixel circuits, each including a first transistor, are formed and which are arranged in a first direction and a second direction intersecting the first direction; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate including a plurality of sub-pixels arranged in the first direction and the second direction, the sub-pixels including a plurality of light-emitting elements; a connecting wiring layer disposed between the light emitting element and the first single crystal semiconductor substrate, the connecting wiring layer including a plurality of bridge lines electrically connected to any one of the pixel circuits and any one of the sub-pixels, the second single crystal semiconductor substrate includes a plurality of through holes in which conductive vias electrically connected to the light emitting elements of the respective sub-pixels and the bridge lines are disposed, the connecting wiring layer includes a first conductive layer in which a first bridge line is disposed, a second conductive layer in which a second bridge line is disposed, and an interlayer insulating layer between the first conductive layer and the second conductive layer; At least some of the plurality of sub-pixels are electrically connected to the first bridge line, and some of other sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line.

2. The display device of claim 1 , wherein the outermost subpixels in the first direction and the outermost subpixels in the second direction among the plurality of subpixels are electrically connected to different first bridge lines.

3. The display device of claim 2 , wherein the sub-pixels adjacent to the outermost sub-pixels in the first and second directions are electrically connected to different second bridge lines.

4. The sub-pixels of a first pixel row arranged on one side in the first direction are electrically connected to the pixel circuits arranged side by side in the first direction, The display device of claim 1 , wherein the sub-pixels of a second pixel row adjacent to one side of the first pixel row in the second direction are electrically connected to the pixel circuits not aligned in the first direction.

5. The display device according to claim 4 , wherein the bridge line electrically connected to the sub-pixels in the first pixel row is arranged to overlap the sub-pixels in the first pixel row.

6. The display device according to claim 4 , wherein the bridge line electrically connected to the sub-pixels of the second pixel row is arranged so that at least a portion of the bridge line overlaps with the sub-pixels of the first pixel row.

7. a first sub-pixel disposed at the outermost side of the first pixel row is connected to the first bridge line; a second sub-pixel adjacent to the first sub-pixel in the first pixel row is connected to the second bridge line; The display device of claim 4 , wherein the first bridge line connected to the first sub-pixel is disposed on the other side of the second bridge line connected to the second sub-pixel in the second direction.

8. the sub-pixels of a first pixel column arranged on the other side in the second direction are electrically connected to the pixel circuits arranged side by side in the second direction, 5. The display device according to claim 4, wherein the sub-pixels of a second pixel column adjacent to the first pixel column on the other side in the first direction are electrically connected to the pixel circuits positioned not aligned in the second direction.

9. a first sub-pixel disposed at the outermost side of the first pixel column is connected to the first bridge line; a second sub-pixel adjacent to the first sub-pixel in the first pixel column is connected to the second bridge line; The display device of claim 8 , wherein the first bridge line connected to the first sub-pixel is disposed on one side of the second bridge line connected to the second sub-pixel in the first direction.

10. a first sub-pixel disposed at the outermost side of the plurality of sub-pixels arranged in a diagonal direction from the first single crystal semiconductor substrate is connected to the first bridge line; The display device of claim 1 , wherein a second sub-pixel diagonally adjacent to the first sub-pixel is connected to the second bridge line, and the second bridge line is disposed above the first bridge line.

11. 2. The display device of claim 1, wherein a position of one end of the first bridge line in the sub-pixel is different from a position of one end of the second bridge line in the sub-pixel adjacent to the sub-pixel connected to the first bridge line on the inner side.

12. the plurality of sub-pixels include overlapping sub-pixels that overlap with the pixel circuit and non-overlapping sub-pixels that do not overlap with the pixel circuit, The display device of claim 1 , wherein a portion of the bridge line connected to the non-overlapping sub-pixels among the plurality of bridge lines does not overlap the first single-crystalline semiconductor substrate.

13. The display device of claim 12 , wherein the bridge lines connected to the non-overlapping sub-pixels are longer than the bridge lines connected to the overlapping sub-pixels.

14. The display device of claim 12 , wherein the bridge line connected to the overlapping sub-pixel among the plurality of bridge lines has a zigzag shape.

15. The display device according to claim 1 , wherein an area of ​​the first single crystal semiconductor substrate is smaller than an area of ​​the second single crystal semiconductor substrate.

16. a first single-crystal semiconductor substrate on which a plurality of first transistors are formed and a plurality of pixel circuits including the first transistors are formed; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate and having a plurality of sub-pixels, each including a plurality of light-emitting elements, disposed thereon; an interconnection layer disposed between the light emitting element and the first single crystal semiconductor substrate; the second single crystal semiconductor substrate includes a plurality of through holes in which conductive vias electrically connected to the light emitting elements of the respective sub-pixels are disposed; the interconnection layer includes a plurality of conductive layers including a plurality of bridge lines and a plurality of bridge contacts, and an interlayer insulating layer disposed between the conductive layers; the sub-pixels include a first sub-pixel connected to one of the pixel circuits via a first bridge line disposed in a first conductive layer of the connecting wiring layer, and a second sub-pixel connected to one of the pixel circuits via a second bridge line in a second conductive layer disposed on the first conductive layer of the connecting wiring layer.

17. the second bridge line is electrically connected to a first bridge contact disposed on the first conductive layer; The display device of claim 16 , wherein the first bridge line is electrically connected to a second bridge contact disposed on the second conductive layer.

18. The display device of claim 17 , wherein the second bridge line and the second bridge contact are each connected to one of the conductive vias.

19. The display device of claim 16, wherein at least a portion of the first bridge line is connected to a second bridge line disposed on the second conductive layer.

20. a frame attached to a user's body and corresponding to the left and right eyes; a plurality of display devices disposed on the frame; a lens disposed on each of the plurality of display devices; The display device includes a first single-crystal semiconductor substrate on which a plurality of pixel circuits, each including a first transistor, are formed and which are arranged in a first direction and a second direction intersecting the first direction; a second single crystal semiconductor substrate disposed on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate including a plurality of sub-pixels arranged in the first direction and the second direction, the sub-pixels including a plurality of light-emitting elements; a connecting wiring layer disposed between the light emitting element and the first single crystal semiconductor substrate, the connecting wiring layer including a plurality of bridge lines electrically connected to any one of the pixel circuits and any one of the sub-pixels, the second single crystal semiconductor substrate includes a plurality of through holes in which conductive vias electrically connected to the light emitting elements of the respective sub-pixels and the bridge lines are disposed, the connecting wiring layer includes a first conductive layer in which a first bridge line is disposed, a second conductive layer in which a second bridge line is disposed, and an interlayer insulating layer between the first conductive layer and the second conductive layer; At least some of the plurality of sub-pixels are electrically connected to the first bridge line, and some of other sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line.

Images