Silicon carbide substrate, silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and method for manufacturing silicon carbide crystal

Abstract

To provide a silicon carbide substrate that can improve reliability of a silicon carbide semiconductor device, and to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device and a method for manufacturing a silicon carbide crystal.SOLUTION: A silicon carbide substrate has a principal plane. The principal plane is formed with an outer edge, an outer peripheral region within 5 mm from the outer edge, and a center region surrounded by the outer peripheral region. A value obtained by dividing the surface density of penetration edge dislocation in the center region by a surface density of basal plane dislocation in the center region is 120 or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a silicon carbide substrate, a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide crystal. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2019-112269 (Patent Document 1) discloses a silicon carbide single crystal substrate having basal plane dislocations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-112269 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a silicon carbide substrate, a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide crystal, which are capable of improving the reliability of silicon carbide semiconductor devices. [Means for solving the problem]

[0005] A silicon carbide substrate according to the present disclosure has a main surface. The main surface is formed by an outer edge, a peripheral region within 5 mm of the outer edge, and a central region surrounded by the peripheral region. The value obtained by dividing the areal density of threading edge dislocations in the central region by the areal density of basal plane dislocations in the central region is 120 or greater. This can improve the reliability of the silicon carbide semiconductor device. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a silicon carbide substrate, a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide crystal, which are capable of improving the reliability of silicon carbide semiconductor devices. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view schematically showing the configuration of a silicon carbide substrate in accordance with this embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a flow diagram that schematically illustrates the method for manufacturing silicon carbide crystal according to this embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view for explaining the preparation step. [Figure 5] FIG. 5 is a schematic diagram showing the relationship between the flow rates of hydrogen and argon and time. [Figure 6] FIG. 6 is a schematic diagram showing the relationship between the temperature inside the crucible and time. [Figure 7] FIG. 7 is a cross-sectional view showing the crystal growth process. [Figure 8] FIG. 8 is a cross-sectional view schematically illustrating the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate according to this embodiment. [Figure 9] FIG. 9 is a cross-sectional view schematically illustrating the configuration of a silicon carbide epitaxial substrate according to this embodiment. [Figure 10] FIG. 10 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to this embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a step of forming a body region. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a step of forming a source region. [Figure 13] FIG. 13 is a cross-sectional view schematically illustrating a step of forming a trench in the third main surface of the silicon carbide epitaxial layer. [Figure 14] FIG. 14 is a cross-sectional view showing a process of forming a gate insulating film. [Figure 15] FIG. 15 is a cross-sectional view showing a process of forming a gate electrode and an interlayer insulating film. [Figure 16]FIG. 16 is a cross-sectional view schematically showing the configuration of a silicon carbide semiconductor device in accordance with this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Summary of the embodiments of the present disclosure] First, an overview of the embodiments of the present disclosure will be described. In the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually represented by placing a "-" (bar) above the number, but in this specification, a negative crystallographic index is represented by placing a negative sign before the number.

[0009] (1) A silicon carbide substrate according to the present disclosure has a main surface. The main surface is formed by an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. The value obtained by dividing the areal density of threading edge dislocations in the central region by the areal density of basal plane dislocations in the central region is 120 or greater. This can improve the reliability of the silicon carbide semiconductor device.

[0010] (2) A silicon carbide substrate according to the present disclosure has a main surface. The main surface is formed by an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region. The value obtained by dividing the areal density of threading edge dislocations in the central region by the areal density of basal plane dislocations in the central region is 80 or more. The areal density of threading edge dislocations in the central region is 3000 cm -2 As a result, the reliability of the silicon carbide semiconductor device can be improved.

[0011] (3) In the silicon carbide substrate according to (1) or (2) above, the areal density of basal plane dislocations in the central region is 50 cm -2 This can further improve the reliability of the silicon carbide semiconductor device.

[0012] (4) In the silicon carbide substrate according to any one of (1) to (3) above, the areal density of threading edge dislocations in the central region is 4000 cm-2 This can further improve the reliability of the silicon carbide semiconductor device.

[0013] (5) In the silicon carbide substrate according to any one of (1) to (4), when viewed perpendicular to the main surface, the central region may be formed by a first region having a diameter two-thirds of the diameter of the main surface and surrounded by a circle centered at the center of the main surface, and a second region surrounding the first region. The areal density of basal plane dislocations in the second region may be higher than the areal density of basal plane dislocations in the first region.

[0014] (6) In the silicon carbide substrate according to (5) above, the areal density of basal plane dislocations in the first region is 20 cm -2 It may be the following:

[0015] (7) In the silicon carbide substrate according to (5) or (6), the areal density of basal plane dislocations in the second region is 60 cm -2 It may be the following:

[0016] (8) In the silicon carbide substrate according to any one of (5) to (7) above, the areal density of basal plane dislocations in the second region may be three or more times the areal density of basal plane dislocations in the first region.

[0017] (9) In the silicon carbide substrate according to any one of (1) to (8) above, the diameter of the main surface may be 150 mm or more.

[0018] (10) A silicon carbide epitaxial substrate according to the present disclosure includes the silicon carbide substrate according to (1) or (9) above, and a silicon carbide epitaxial layer provided on the silicon carbide substrate.

[0019] (11) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the steps of preparing the silicon carbide epitaxial substrate described in (10) above, and forming an electrode on the silicon carbide epitaxial substrate.

[0020] (12) A method for producing a silicon carbide crystal according to the present disclosure includes the steps of placing a seed substrate and a silicon carbide source material in a crucible, etching the seed substrate using hydrogen, and growing a silicon carbide crystal on the seed substrate by sublimating the silicon carbide source material after the step of etching the seed substrate using hydrogen. The temperature in the step of etching the seed substrate using hydrogen is 2050°C or higher and 2150°C or lower. This increases the conversion rate of basal plane dislocations to threading edge dislocations. As a result, the areal density of basal plane dislocations can be reduced. This can improve the reliability of silicon carbide semiconductor devices.

[0021] (13) According to the method for producing a silicon carbide crystal according to (12) above, in the step of etching the seed substrate using hydrogen, the flow rate of the hydrogen may be 1400 sccm or more and 1600 sccm or less, thereby further increasing the conversion rate of basal plane dislocations to threading edge dislocations.

[0022] (14) According to the method for producing a silicon carbide crystal according to (12) or (13) above, in the step of etching the seed substrate using hydrogen, the seed substrate may be etched using a mixed gas of hydrogen and argon. The ratio of the flow rate of hydrogen to the flow rate of argon may be 3 to 8 times. This can further increase the conversion rate of basal plane dislocations to threading edge dislocations.

[0023] [Details of the embodiments of the present disclosure] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements will be denoted by the same reference numerals, and the same description thereof will not be repeated.

[0024] Fig. 1 is a plan view schematically showing the configuration of a silicon carbide substrate according to this embodiment. Fig. 2 is a cross-sectional view schematically showing the configuration along line II-II in Fig. 1. As shown in Figs. 1 and 2, silicon carbide substrate 10 according to this embodiment has a first main surface 1 and a second main surface 2. First main surface 1 is the front surface of silicon carbide substrate 10. Second main surface 2 is the back surface of silicon carbide substrate 10. Second main surface 2 is opposite first main surface 1.

[0025] 1, when viewed along a line perpendicular to the first main surface 1, the first main surface 1 extends along a first direction 101 and a second direction 102. When viewed along a line perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101.

[0026] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0027] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component. A direction perpendicular to each of the first direction 101 and the second direction 102 is defined as a third direction 103.

[0028] Silicon carbide substrate 10 contains n-type impurities such as nitrogen (N). Silicon carbide substrate 10 has an n-type conductivity type, for example.

[0029] As shown in FIG. 1, the first main surface is formed by an outer edge 8, a peripheral region 11, and a central region 12. The outer edge 8 has, for example, an orientation flat portion 6 and an arc-shaped portion 7. The orientation flat portion 6 extends along a first direction 101. As shown in FIG. 1, the orientation flat portion 6 is linear when viewed along a line perpendicular to the first main surface 1. The arc-shaped portion 7 is continuous with the orientation flat portion 6. The arc-shaped portion 7 is arc-shaped when viewed along a line perpendicular to the first main surface 1. When viewed along a line perpendicular to the first main surface 1, the center O of the first main surface 1 is the center of a circle that includes an arc along the arc-shaped portion 7.

[0030] As shown in FIG. 1, the diameter of the first main surface 1 (first diameter W1) is, for example, 150 mm (6 inches). The first diameter W1 may be 150 mm (6 inches) or more, or may be 200 mm (8 inches) or more. The first diameter W1 may be, for example, 400 mm (16 inches) or less. The first diameter W1 is the longest linear distance between two different points on the outer edge 8.

[0031] In this specification, 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches means 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0032] 1, the outer peripheral region 11 is a region within 5 mm from the outer edge 8. When viewed along a line perpendicular to the first main surface 1, the distance E between the outer edge 8 and the boundary between the outer peripheral region 11 and the central region 12 is 5 mm. From another perspective, the width (distance E) of the outer peripheral region 11 in the direction extending radially from the center O of the first main surface 1 (radial direction) is 5 mm.

[0033] The central region 12 is surrounded by the outer peripheral region 11. The central region 12 is continuous with the outer peripheral region 11. The central region 12 is a region that is more than 5 mm away from the outer edge 8. The central region 12 is formed by a first region 21 and a second region 22. When viewed in a direction perpendicular to the first main surface 1, the first region 21 has a diameter (second diameter W2) that is two-thirds the diameter (first diameter W1) of the first main surface 1, and is a region that is surrounded by a circle centered at the center O of the first main surface 1. The second region 22 is a region that surrounds the first region 21.

[0034] As shown in FIG. 2 , the first main surface 1 is a surface inclined with respect to the {0001} plane. The inclination angle (off angle θ) of the first main surface 1 with respect to the {0001} plane is, for example, 1° or more and 8° or less. Specifically, the first main surface 1 may be a surface inclined by the off angle θ with respect to the (0001) plane. The first main surface 1 may be a surface inclined by the off angle θ with respect to the (000-1) plane. The inclination direction (off direction) of the first main surface 1 with respect to the {0001} plane is, for example, the <11-20> direction. The upper limit of the off angle θ may be, for example, 7° or less, 6° or less, or 5° or less. The lower limit of the off angle θ may be, for example, 2° or more, or 3° or more.

[0035] As shown in Fig. 2, silicon carbide substrate 10 has basal plane dislocations 32 and threading edge dislocations 31. Basal plane dislocations 32 are located in the basal plane. Basal plane dislocations 32 may be exposed at first main surface 1. Threading edge dislocations 31 may be exposed at both first main surface 1 and second main surface.

[0036] (Basal plane dislocations and threading edge dislocations) The value obtained by dividing the areal density of threading edge dislocations 31 in the central region 12 by the areal density of basal plane dislocations 32 in the central region 12 is 80 or more. The value obtained by dividing the areal density of threading edge dislocations 31 in the central region 12 by the areal density of basal plane dislocations 32 in the central region 12 may be 90 or more, 100 or more, 110 or more, or 120 or more. The value obtained by dividing the areal density of threading edge dislocations 31 in the central region 12 by the areal density of basal plane dislocations 32 in the central region 12 may be 400 or less, 350 or less, 300 or less, 250 or less, 200 or less, 180 or less, 160 or less, or 140 or less.

[0037] The areal density of threading edge dislocations 31 in the central region 12 is 3000 cm -2 The areal density of threading edge dislocations 31 in the central region 12 may be 3300 cm -2It may be more than 3600 cm -2 It may be more than 4000 cm -2 The areal density of threading edge dislocations 31 in the central region 12 may be 7000 cm -2 It may be less than 6000 cm -2 It may be less than 5000 cm -2 It may be the following:

[0038] The areal density of basal plane dislocations 32 in the central region 12 is 50 cm -2 The areal density of basal plane dislocations 32 in the central region 12 may be 45 cm -2 May be less than 40cm -2 May be less than 35cm -2 The areal density of basal plane dislocations 32 in the central region 12 may be 5 cm -2 May be more than 10cm -2 May be more than 15cm -2 It may be more than that.

[0039] The areal density of basal plane dislocations 32 in second region 22 may be higher than the areal density of basal plane dislocations 32 in first region 21. The areal density of basal plane dislocations 32 in second region 22 may be two or more times, or three or more times, the areal density of basal plane dislocations 32 in first region 21. The areal density of basal plane dislocations 32 in second region 22 may be seven or five times or less the areal density of basal plane dislocations 32 in first region 21.

[0040] The areal density of the basal plane dislocations 32 in the first region 21 is, for example, 20 cm -2 The areal density of basal plane dislocations 32 in the first region 21 is 18 cm -2 May be less than 16cm -2 The areal density of basal plane dislocations 32 in the first region 21 may be 2 cm -2 May be more than 5cm -2 May be more than 10cm -2 It may be more than that.

[0041] The areal density of basal plane dislocations 32 in the second region 22 is 60 cm -2 The areal density of basal plane dislocations 32 in the second region 22 may be 58 cm -2 May be less than 56cm -2 The areal density of basal plane dislocations 32 in the first region 21 may be 20 cm -2 May be more than 30cm -2 May be more than 40cm -2 It may be more than that.

[0042] Next, a method for measuring the areal density of each of the basal plane dislocations 32 and the threading edge dislocations 31 will be described.

[0043] The areal densities of basal plane dislocations 32 and threading edge dislocations 31 are measured using molten potassium hydroxide (KOH melt). Specifically, first main surface 1 of silicon carbide substrate 10 is etched with molten KOH. As a result, silicon carbide regions near basal plane dislocations 32 and threading edge dislocations 31 exposed on first main surface 1 are etched, and etch pits are formed on first main surface 1.

[0044] The temperature of the KOH melt is, for example, about 500°C or higher and 550°C or lower. The etching time is about 5 minutes or higher and 10 minutes or lower. After etching, the etch pits formed on the first main surface 1 are observed using a Normarski differential interference microscope. The observation area may be divided into multiple square areas. The length of one side of the square areas may be 10 mm.

[0045] Etch pits caused by threading edge dislocations 31 and etch pits caused by basal plane dislocations 32 are distinguished by the following method. Etch pits caused by basal plane dislocations 32 have an elliptical planar shape. Etch pits caused by threading edge dislocations 31 have a round or hexagonal planar shape and a small pit size. Etch pits caused by threading screw dislocations have a round or hexagonal planar shape and a large pit size.

[0046] The areal density of basal plane dislocations 32 is the value obtained by dividing the number of etch pits caused by basal plane dislocations 32 by the area of ​​the observation region. Similarly, the areal density of threading edge dislocations 31 is the value obtained by dividing the number of etch pits caused by threading edge dislocations 31 by the area of ​​the observation region.

[0047] (Method for producing silicon carbide crystal) Next, a method for manufacturing a silicon carbide crystal according to this embodiment will be described. Fig. 3 is a flow diagram that schematically illustrates the method for manufacturing a silicon carbide crystal according to this embodiment. As shown in Fig. 3, the method for manufacturing a silicon carbide crystal according to this embodiment mainly includes a preparation step (S10), a hydrogen etching step (S20), and a crystal growth step (S30).

[0048] First, a preparation step (S10) is performed. FIG. 4 is a cross-sectional view illustrating the preparation step. As shown in FIG. 4, a seed substrate 80 and a silicon carbide raw material 81 are placed in a crucible 130. The crucible 130 has a lid member 131 and a raw material storage portion 132. The seed substrate 80 is attached to the lower surface of the lid member 131. The silicon carbide raw material 81 is placed in the raw material storage portion 132. The surface of the seed substrate 80 faces the surface of the silicon carbide raw material 81.

[0049] Next, the hydrogen etching step (S20) is performed. Fig. 5 is a schematic diagram showing the relationship between the flow rates of hydrogen and argon and time. Fig. 6 is a schematic diagram showing the relationship between the temperature inside the crucible 130 and time.

[0050] In the hydrogen etching step (S20), seed substrate 80 is etched using hydrogen. First, the temperature of crucible 130 is increased. Crucible 130 is heated until the temperature of seed substrate 80 reaches first temperature B1. First temperature B1 is the temperature at the center of the surface of seed substrate 80 in the step of etching seed substrate 80 using hydrogen. First temperature B1 is 2050°C or higher and 2150°C or lower. First temperature B1 may be 2060°C or higher, or 2080°C or higher. First temperature B1 may be 2140°C or lower, or 2120°C or lower.

[0051] Next, hydrogen is introduced into crucible 130. At first time point T1, the flow rate of hydrogen is set to first flow rate A1. First flow rate A1 is, for example, 1400 sccm or more and 1600 sccm or less. First flow rate A1 may be 1430 sccm or more, or 1460 sccm or more. First flow rate A1 may be 1570 sccm or less, or 1530 sccm or less. From first time point T1 to second time point T2, the temperature of seed substrate 80 is first temperature B1, and the flow rate of hydrogen is first flow rate A1. As a result, the surface of seed substrate 80 is etched by hydrogen.

[0052] The time from the first time T1 to the second time T2 is, for example, 60 minutes. In the hydrogen etching step (S20), argon is introduced into the crucible 130. The seed substrate 80 is etched using a mixed gas of hydrogen and argon. The flow rate of the argon is set to a second flow rate A2. The second flow rate A2 is smaller than the first flow rate A1. The second flow rate A2 is, for example, 300 sccm. The ratio of the flow rate of hydrogen to the flow rate of argon is, for example, 3 times or more and 8 times or less. The ratio of the flow rate of hydrogen to the flow rate of argon may be 4 times or more, or 5 times or more. The ratio of the flow rate of hydrogen to the flow rate of argon may be 7 times or less, or 6 times or less.

[0053] Next, the supply of hydrogen to the crucible 130 is stopped. The flow rate of hydrogen is reduced from the second time point T2 to the third time point T3. This completes the hydrogen etching step (S20). Note that argon continues to be introduced into the crucible 130 at the third time point T3.

[0054] In the hydrogen etching step (S20), no temperature gradient is provided in crucible 130 in the vertical direction (the direction from seed substrate 80 toward silicon carbide raw material 81). That is, the temperature of seed substrate 80 is substantially the same as the temperature of silicon carbide raw material 81. On the other hand, a temperature gradient may be provided in crucible 130 in the horizontal direction (the direction parallel to the surface of seed substrate 80). The temperature of the periphery of the surface of seed substrate 80 may be lower than the temperature of the center of the surface of seed substrate 80.

[0055] Next, the crystal growth step (S30) is performed. Specifically, from fourth point in time T4 to fifth point in time T5, the temperature of crucible 130 increases from first temperature B1 to second temperature B2. Second temperature B2 is higher than first temperature B1. Second temperature B2 is, for example, 2200°C or higher and 2300°C or lower. In crystal growth step (S30), the temperature distribution in crucible 130 is controlled so that the temperature of the surface of seed substrate 80 is lower than the temperature of the surface of silicon carbide source material 81. Note that fourth point in time T4 may be after third point in time T3 or may be before third point in time T3.

[0056] Fig. 7 is a cross-sectional schematic diagram showing the crystal growth step. By sublimating silicon carbide raw material 81, silicon carbide crystal 50 grows on seed substrate 80. As shown in Fig. 7, silicon carbide crystal 50 grows from seed substrate 80 toward silicon carbide raw material 81. Next, silicon carbide crystal 50 is sliced ​​using, for example, a saw wire, to obtain silicon carbide substrate 10.

[0057] (Silicon carbide epitaxial substrate manufacturing equipment) 8 is a cross-sectional view showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate according to this embodiment. As shown in FIG. 8, the apparatus for manufacturing a silicon carbide epitaxial substrate is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. The apparatus for manufacturing a silicon carbide epitaxial substrate 250 mainly includes a reaction chamber 201, a gas supply unit 235, a flow rate control unit 245, a heating element 203, a quartz tube 204, a heat insulating material (not shown), and an induction heating coil (not shown).

[0058] The heating element 203 has, for example, a rectangular cylindrical shape, and defines the reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound around, for example, the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0059] The reaction chamber 201 is surrounded by an inner wall surface 205 of a heating element 203. A susceptor 210 that holds a silicon carbide substrate 10 is provided in the reaction chamber 201. The susceptor 210 is made of, for example, silicon carbide. The silicon carbide substrate 10 is placed on the susceptor 210. The susceptor 210 is placed on a stage 206. The stage 206 is rotatably supported by a rotation shaft 209. The rotation of the stage 206 causes the susceptor 210 to rotate.

[0060] The manufacturing apparatus 250 further has a gas inlet 207 and a gas outlet 208. The gas outlet 208 is connected to an exhaust pump (not shown). The arrows in FIG. 8 indicate the flow of gas. The gas is introduced into the reaction chamber 201 from the gas inlet 207 and exhausted from the gas exhaust outlet 208. The pressure inside the reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0061] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0062] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C3H8) gas. The first gas may also be, for example, methane (CH4) gas, ethane (C2H6) gas, acetylene (C2H2) gas, ethylene (C2H4) gas, etc.

[0063] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH4) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

[0064] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, ammonia gas. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas containing nitrogen atoms (N). Ammonia gas is more susceptible to thermal decomposition than nitrogen gas having a triple bond. The third gas may be nitrogen gas.

[0065] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen, etc. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.

[0066] The flow rate control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the flow rate control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The flow rate control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207. In other words, the flow rate control unit 245 is disposed in a flow path connecting the gas supply unit 235 and the gas inlet 207.

[0067] (Method for manufacturing silicon carbide epitaxial substrate) Next, a method for manufacturing silicon carbide substrate 10 according to this embodiment will be described. First, buffer layer 41 is formed on silicon carbide substrate 10. Specifically, for example, silane gas, propane gas, and ammonia gas begin to be supplied to reaction chamber 201. As a result, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into reaction chamber 201. In reaction chamber 201, each gas is thermally decomposed. The flow rates of silane and propane are controlled so that the C / Si ratio is, for example, not less than 1.0 and not more than 1.1. The flow rate of ammonia is, for example, not less than 10 sccm and not more than 500 sccm. The temperature inside reaction chamber 201 is, for example, 1600°C. The pressure inside reaction chamber 201 is, for example, not less than 2 kPa and not more than 6 kPa. As a result, buffer layer 41 is formed on silicon carbide substrate 10.

[0068] Next, drift layer 42 is formed on buffer layer 41. The flow rates of silane and propane are controlled so that the C / Si ratio is, for example, 1.25 or more and 1.35 or less. The flow rate of ammonia is set to, for example, 0.2 sccm. In the step (S50) of forming drift layer 42 on buffer layer 41, the temperature inside reaction chamber 201 is, for example, 1600°C. The pressure inside reaction chamber 201 is, for example, 2 kPa or more and 6 kPa or less. Thus, drift layer 42 is formed on buffer layer 41.

[0069] 9 is a cross-sectional schematic diagram showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. As shown in FIG. 9, silicon carbide epitaxial substrate 100 has a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. Silicon carbide epitaxial layer 20 has a buffer layer 41 and a drift layer 42. Buffer layer 41 is provided on silicon carbide substrate 10. Drift layer 42 is provided on buffer layer 41. Drift layer 42 forms a third main surface 3. Third main surface 3 is the surface of silicon carbide epitaxial substrate 100.

[0070] (Method for manufacturing silicon carbide semiconductor device) Next, a method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 10 is a flowchart that schematically shows the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 10, the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing a silicon carbide epitaxial substrate 100 and a step (S2) of forming an electrode on the silicon carbide epitaxial substrate 100.

[0071] First, there is performed a step (S1) of preparing a silicon carbide epitaxial substrate 100. In the step (S1) of preparing a silicon carbide epitaxial substrate 100, a silicon carbide epitaxial substrate 100 according to this embodiment is prepared.

[0072] Next, ions are implanted into silicon carbide substrate 10. FIG. 11 is a cross-sectional view schematically illustrating a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into third main surface 3 of silicon carbide epitaxial layer 20. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. Body region 113 has a thickness of, for example, 0.9 μm. Silicon carbide epitaxial layer 20 includes buffer layer 41, drift layer 42, and body region 113.

[0073] Next, a step of forming a source region is performed. FIG. 12 is a cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities in the source region 114 is higher than the concentration of the p-type impurities in the body region 113.

[0074] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity in the contact region 118 is higher than the concentration of the n-type impurity in the source region 114.

[0075] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500°C or higher and 1900°C or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere for the activation annealing is, for example, an argon atmosphere.

[0076] Next, a step of forming trenches in the third main surface 3 of the silicon carbide epitaxial layer 20 is performed. FIG. 13 is a cross-sectional schematic diagram showing the step of forming trenches in the third main surface 3 of the silicon carbide epitaxial layer 20. A mask 117 having openings is formed on the first main surface 1 formed of the source region 114 and the contact region 118. The source region 114, the body region 113, and a portion of the drift layer 42 are removed by etching using the mask 117. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF or a mixed gas of SF and O as a reactive gas is used. Recesses are formed in the first main surface 1 by the etching.

[0077] Next, thermal etching is performed on the recesses. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with mask 117 formed on first main surface 1. For example, the thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as the reactive gas, and at a heat treatment temperature of, for example, 700°C or higher and 1000°C or lower.

[0078] 13 , a trench 56 is formed in the third main surface 3 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the third main surface 3.

[0079] Next, a step of forming a gate insulating film is performed. Fig. 14 is a cross-sectional schematic view showing the step of forming a gate insulating film. Specifically, silicon carbide substrate 10 having trench 56 formed in third main surface 3 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C or higher and 1400°C or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at side wall surface 53, and in contact with source region 114 and contact region 118 at third main surface 3.

[0080] Next, a step (S2) of forming an electrode on silicon carbide epitaxial substrate 100 is performed. FIG. 15 is a cross-sectional view schematically showing the step of forming a gate electrode and an interlayer insulating film. Gate electrode 127 is formed inside trench 56 so as to be in contact with gate insulating film 115. Gate electrode 127 is disposed inside trench 56 and is formed on gate insulating film 115 so as to face each of sidewall surface 53 and bottom wall surface 54 of trench 56. Gate electrode 127 is formed by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method.

[0081] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is formed of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and the gate insulating film 115 are partially etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0082] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is formed from a material including, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0083] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. This causes at least a portion of the source electrode 116 to be silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0084] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0085] Next, a step of forming a drain electrode is carried out. First, the silicon carbide substrate 10 is polished at the second main surface 2. This reduces the thickness of the silicon carbide substrate 10. Next, the drain electrode 123 is formed. The drain electrode 123 is formed so as to be in contact with the second main surface 2. In this manner, the silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0086] FIG. 16 is a cross-sectional view schematically illustrating a configuration of a silicon carbide semiconductor device 400 according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 100, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. The silicon carbide epitaxial layer 20 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. The silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0087] Next, the effects of the method for manufacturing silicon carbide substrate 10 and silicon carbide crystal 50 according to this embodiment will be described.

[0088] When basal plane dislocations 32 are present in the device active region, they reduce the reliability of gate insulating film 115. Therefore, when silicon carbide semiconductor device 400 is fabricated using silicon carbide substrate 10 including a large number of basal plane dislocations 32, the reliability of silicon carbide semiconductor device 400 may be reduced.

[0089] As a method for reducing basal plane dislocations 32, technology has been developed to convert basal plane dislocations 32 contained in silicon carbide substrate 10 into threading edge dislocations 31, which have little effect on device quality, during the epitaxial growth process. However, when silicon carbide substrate 10 contains a large number of basal plane dislocations 32, it has been difficult to sufficiently reduce basal plane dislocations 32 in the epitaxial growth layer, even if the conversion rate from basal plane dislocations 32 to threading edge dislocations 31 is increased.

[0090] As a result of extensive investigation, the inventors came up with the idea of ​​converting basal plane dislocations 32 into threading edge dislocations 31 at the stage of producing silicon carbide crystal 50 (ingot), which is an upstream step of epitaxial growth.

[0091] A method for manufacturing silicon carbide crystal 50 according to the present disclosure includes the steps of placing seed substrate 80 and silicon carbide raw material 81 in crucible 130, etching seed substrate 80 using hydrogen, and growing silicon carbide crystal 50 on seed substrate 80 by sublimating silicon carbide raw material 81 after the step of etching seed substrate 80 using hydrogen. The temperature in the step of etching seed substrate 80 using hydrogen is 2050°C or higher and 2150°C or lower. This increases the conversion rate of basal plane dislocations 32 to threading edge dislocations 31. As a result, the areal density of basal plane dislocations 32 in silicon carbide substrate 10 can be reduced. This improves the reliability of silicon carbide semiconductor device 400. [Example]

[0092] (Sample preparation) Silicon carbide substrates 10 according to Samples 1 to 6 were prepared. Silicon carbide substrates 10 according to Samples 1, 2 and 6 are comparative examples. Silicon carbide substrates 10 according to Samples 3 to 5 are examples.

[0093] Silicon carbide substrates 10 according to Samples 1 to 6 were manufactured using the method for manufacturing silicon carbide crystal 50 shown in Fig. 3. Silicon carbide crystal 50 was obtained by sublimation deposition, and then silicon carbide crystal 50 was sliced ​​to obtain silicon carbide substrates 10. Note that the hydrogen etching step (S20) was not performed in the method for manufacturing silicon carbide substrate 10 according to Samples 1 to 6. On the other hand, the hydrogen etching step (S20) was performed in the method for manufacturing silicon carbide substrate 10 according to Samples 2 to 6.

[0094] In the hydrogen etching step (S20) of the method for manufacturing silicon carbide substrate 10 according to Samples 2 to 6, the temperatures of crucible 130 were set to 2000°C, 2100°C, 2100°C, 2100°C, and 2200°C, respectively. In the hydrogen etching step (S20) of the method for manufacturing silicon carbide substrate 10 according to Samples 2 to 6, the hydrogen supply rates were set to 2000 sccm, 1500 sccm, 1500 sccm, 1500 sccm, and 1000 sccm, respectively. In the hydrogen etching step (S20) of the method for manufacturing silicon carbide substrate 10 according to Samples 2 to 6, the hydrogen supply time was 60 minutes.

[0095] (Evaluation method) The areal densities of basal plane dislocations 32 and threading edge dislocations 31 were measured on first main surface 1 of silicon carbide substrate 10 according to samples 1 to 6. Specifically, the areal densities of basal plane dislocations 32 (BPD) and threading edge dislocations 31 (TED) were measured in central region 12. The areal densities of basal plane dislocations 32 (BPD) were measured in each of first region 21 and second region 22.

[0096] Etch pits were formed on the first main surface 1 of the silicon carbide substrate 10 by etching the first main surface 1 with molten KOH. The temperature of the KOH melt was approximately 500°C or higher and 550°C or lower. The etching time was approximately 5 minutes or higher and 10 minutes or lower. After etching, the etch pits formed on the first main surface 1 were observed using a Normarski differential interference microscope. The areal density of basal plane dislocations 32 is the value obtained by dividing the number of etch pits caused by basal plane dislocations 32 by the measured area. The areal density of threading edge dislocations 31 is the value obtained by dividing the number of etch pits caused by threading edge dislocations 31 by the measured area.

[0097] (Evaluation results)

[0098] [Table 1]

[0099] As shown in Table 1, the areal density of basal plane dislocations 32 (BPD) in central region 12 of first main surface 1 of silicon carbide substrate 10 according to Samples 1 to 6 was 1000 cm -2 , 472cm -2 , 33cm -2 , 14cm -2 , 17cm -2 , and 102 cm -2 The areal density of threading edge dislocations 31 (TED) in central region 12 of first main surface 1 of silicon carbide substrate 10 in samples 1 to 6 was 3811 cm -2 , 3820cm -2 , 4001cm -2 , 4758cm -2 , 3770cm -2 , and 3881 cm -2 The ratios of TED to BPD (TED / BPD) of the silicon carbide substrates 10 according to Samples 1 to 6 were 3.8, 8.1, 121.2, 339.9, 221.8, and 38.0, respectively.

[0100] As shown in Table 1, the areal density of basal plane dislocations 32 (BPD) in first region 21 of first main surface 1 of silicon carbide substrate 10 in samples 1 to 3 and 6 was 882 cm -2 , 332cm -2 , 15cm -2 , and 62cm -2 The areal density of basal plane dislocations 32 (BPD) in second region 22 of first main surface 1 of silicon carbide substrate 10 in samples 1 to 3 and 6 was 1211 cm -2 , 592cm -2 , 54cm -2 , and 131 cm -2 It was.

[0101] It was confirmed that the silicon carbide substrates 10 according to Samples 2 to 6 had a larger ratio of TED to BPD (TED / BPD) than the silicon carbide substrate 10 according to Sample 1. Furthermore, it was confirmed that the silicon carbide substrates 10 according to Samples 3 to 5 had an even larger ratio of TED to BPD (TED / BPD) than the silicon carbide substrates 10 according to Samples 2 and 6.

[0102] When the effect of hydrogen etching is excessively strong or excessively weak, as in silicon carbide substrate 10 according to Sample 2 or Sample 6, it may not be possible to sufficiently reduce the areal density of basal plane dislocations 32. To effectively reduce the areal density of basal plane dislocations 32 as in silicon carbide substrate 10 according to Samples 3 to 5, it is desirable to adjust the hydrogen etching temperature, the hydrogen supply amount, and the like.

[0103] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims rather than the above-described embodiments and examples, and it is intended to include all modifications within the scope of the claims and meanings equivalent to the claims. [Explanation of symbols]

[0104] 1 First main surface 2 Second main surface 3 Third principal surface 6 Orientation Flat 7 Arc-shaped part 8 Outer Edge 10 Silicon carbide substrate 11 Outer area 12 Central area 20 Silicon carbide epitaxial layer 21 First area 22 Second area 31 Threading edge dislocation 32 Basal plane dislocations 41 Buffer layer 42 Drift Layer 50 Silicon carbide crystal 53 Side wall 54 Bottom wall 56 Trench 80 types of substrates 81 Silicon carbide raw material 100 Silicon carbide epitaxial substrate 101 1st direction 102 Second direction 103 Third direction 113 Body Region 114 Source Region 115 Gate insulating film 116 Source electrode 117 Mask 118 Contact Area 119 Source wiring 123 Drain electrode 126 Interlayer insulating film 127 Gate electrode 130 Crucible 131 Cover member 132 Raw material storage section 201 Reaction Chamber 203 Heating element 204 Quartz tube 205 Inner wall surface 206 Stages 207 Gas inlet 208 Gas exhaust port 209 Rotational Axis 210 Susceptor 231 First Gas Supply Unit 232 Second gas supply unit 233 Third Gas Supply Section 234 4th Gas Supply Section 235 Gas Supply Section 241 First gas flow control section 242 Second gas flow control section 243 Third gas flow control section 244 Fourth gas flow control section 245 Flow control section 250 Manufacturing equipment 400 Silicon carbide semiconductor device A1 1st flow rate A2 2nd flow rate B1 1st temperature B2 2nd temperature E distance O center T1 Time 1 T2 Second time point T3 Time 3 T4 Time 4 T5 5th time point W1 1st diameter W2 Second diameter

Claims

1. A silicon carbide substrate having a main surface, the main surface is formed by an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region, a value obtained by dividing an areal density of threading edge dislocations in the central region by an areal density of basal plane dislocations in the central region is 120 or greater.

2. A silicon carbide substrate having a main surface, the main surface is formed by an outer edge, a peripheral region within 5 mm from the outer edge, and a central region surrounded by the peripheral region, a value obtained by dividing the areal density of threading edge dislocations in the central region by the areal density of basal plane dislocations in the central region is 80 or more; The areal density of threading edge dislocations in the central region is 3000 cm -2 This is the silicon carbide substrate.

3. The areal density of basal plane dislocations in the central region is 50 cm -2 3. The silicon carbide substrate according to claim 1, wherein:

4. The areal density of threading edge dislocations in the central region is 4000 cm -2 The silicon carbide substrate according to claim 1 or 2.

5. When viewed in a direction perpendicular to the main surface, the central region has a diameter that is two-thirds of a diameter of the main surface, and is formed by a first region that is surrounded by a circle centered at the center of the main surface, and a second region that surrounds the first region, 3 . The silicon carbide substrate according to claim 1 , wherein an areal density of basal plane dislocations in said second region is higher than an areal density of basal plane dislocations in said first region.

6. The areal density of basal plane dislocations in the first region is 20 cm -2 The silicon carbide substrate according to claim 5 , wherein:

7. The areal density of basal plane dislocations in the second region is 60 cm -2 The silicon carbide substrate according to claim 5 , wherein:

8. 6. The silicon carbide substrate according to claim 5, wherein an areal density of basal plane dislocations in said second region is at least three times the areal density of basal plane dislocations in said first region.

9. 3. The silicon carbide substrate according to claim 1, wherein said main surface has a diameter of 150 mm or greater.

10. A silicon carbide substrate according to claim 1 or 2; a silicon carbide epitaxial layer provided on the silicon carbide substrate.

11. preparing the silicon carbide epitaxial substrate according to claim 10; and forming an electrode on the silicon carbide epitaxial substrate.

12. placing a seed substrate and a silicon carbide source material in a crucible; Etching the seed substrate using hydrogen; and after the step of etching the seed substrate using hydrogen, sublimating the silicon carbide source material to grow a silicon carbide crystal on the seed substrate, a temperature in the step of etching the seed substrate using hydrogen being equal to or higher than 2050°C and equal to or lower than 2150°C;

13. 13. The method for producing silicon carbide crystal according to claim 12, wherein in the step of etching the seed substrate using hydrogen, the flow rate of the hydrogen is equal to or greater than 1400 sccm and equal to or less than 1600 sccm.

14. In the step of etching the seed substrate using hydrogen, the seed substrate is etched using a mixed gas of hydrogen and argon, 14. The method for producing silicon carbide crystal according to claim 12 or 13, wherein a ratio of the flow rate of said hydrogen to the flow rate of said argon is 3 times or more and 8 times or less.

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