Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device whose withstanding voltage can be improved.SOLUTION: A semiconductor device 10 includes a semiconductor substrate 20, a plurality of trenches 30, an insulating layer 41, and a plurality of electrode parts 60. The semiconductor substrate 20 includes a first surface 20S and a second surface 20R on the opposite side of the first surface 20S. The trenches 30 are depressed from the first surface 20S toward the second surface 20R, extend in a Y-axis direction and are arranged in an X-axis direction in a plan view. The insulating layer 41 is disposed on an inner surface 31 of each of the trenches 30. The electrode parts 60 are provided in the trenches 30 while being surrounded by the corresponding insulating layer 41. The semiconductor substrate 20 includes a plurality of wall parts 50 disposed between the trenches 30 and section the trenches 30. A capacitor C1 is formed in such a way that the wall part 50 and the electrode part 60 face each other with the insulating layer 41 held therebetween. A thickness T13 of the insulating layer 41 is more than or equal to a thickness T14 of the wall part 50.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a chip capacitor comprising a substrate, a first conductive film formed on the substrate, a dielectric film disposed on the first conductive film and on the substrate, and a second conductive film disposed on the dielectric film. The first conductive film includes a first connection region and a first capacitor-forming region. The second conductive film includes a second capacitor-forming region facing the first capacitor-forming region across the dielectric film. A first external electrode is connected to the first connection region of the first conductive film, and a second external electrode is connected to the second connection region of the second conductive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195321

[0004] [overview] 2. Description of the Related Art Semiconductor devices including capacitors are required to have high breakdown voltage.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor substrate including a first surface and a second surface opposite the first surface, a plurality of trenches recessed from the first surface toward the second surface, extending in a first direction when viewed from the thickness direction of the semiconductor substrate, and arranged in a second direction perpendicular to the first direction when viewed from the thickness direction, an insulating layer disposed on the inner surface of each of the plurality of trenches, and a plurality of conductive electrode portions disposed within the plurality of trenches and surrounded by corresponding insulating layers, wherein the semiconductor substrate includes a plurality of wall portions disposed between the plurality of trenches and partitioning the plurality of trenches, and the wall portions and the electrode portions face each other across the insulating layer to form a capacitor, and the thickness of the insulating layer is greater than or equal to the thickness of the wall portions.

[0006] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes forming a plurality of trenches in a semiconductor substrate including a first surface, the trenches being recessed from the first surface, extending in a first direction when viewed from a thickness direction of the semiconductor substrate, and aligned in a second direction perpendicular to the first direction when viewed from the thickness direction; forming an insulating layer on an inner surface of each of the plurality of trenches; and forming a plurality of conductive electrode portions within the plurality of trenches, the electrode portions being surrounded by corresponding insulating layers, wherein the semiconductor substrate includes a plurality of wall portions disposed between the plurality of trenches and partitioning the plurality of trenches, the wall portions and the electrode portions opposing each other with the insulating layer sandwiched therebetween to form a capacitor, and the thickness of the insulating layer is greater than or equal to the thickness of the wall portions. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic plan view of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5]FIG. 5 is a schematic cross-sectional view showing an enlarged portion of the semiconductor device of FIG. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating exemplary manufacturing steps for the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 20] 20A to 20C are schematic cross-sectional views showing exemplary manufacturing steps for the semiconductor device of FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 27] FIG. 27 is a schematic perspective view of an exemplary semiconductor device according to the second embodiment. [Figure 28] FIG. 28 is a schematic plan view of the semiconductor device of FIG. [Figure 29] FIG. 29 is a schematic plan view of the semiconductor device of FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view of the semiconductor device taken along line F30-F30 in FIG. [Figure 31] FIG. 31 is a schematic cross-sectional view of the semiconductor device taken along line F31-F31 in FIG. [Figure 32] FIG. 32 is a schematic cross-sectional view of the semiconductor device taken along line F32-F32 in FIG. [Figure 33] FIG. 33 is a schematic cross-sectional view of the semiconductor device taken along line F33-F33 in FIG. [Figure 34] FIG. 34 is a schematic cross-sectional view showing an enlarged portion of the semiconductor device of FIG. [Figure 35] 35A to 35C are schematic cross-sectional views showing exemplary manufacturing steps for the semiconductor device of FIG. [Figure 36] FIG. 36 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 37] FIG. 37 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 40] FIG. 40 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 41]FIG. 41 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 42] FIG. 42 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 43] FIG. 43 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 44] FIG. 44 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 45] FIG. 45 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 46] FIG. 46 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 47] FIG. 47 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 48] FIG. 48 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 49] FIG. 49 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 50] FIG. 50 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 51] FIG. 51 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 52] FIG. 52 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 53] FIG. 53 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 54] FIG. 54 is a schematic cross-sectional view showing a semiconductor device according to a modified example.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] (First embodiment) (Schematic configuration of semiconductor device) FIG. 1 is a schematic perspective view of an exemplary semiconductor device 10 according to a first embodiment. FIG. 2 is a schematic plan view of the semiconductor device 10 of FIG. 1. FIG. 3 is a schematic plan view of the semiconductor device of FIG. 1. In FIG. 3, an electrode portion 60 is shown transparently through a first conductive layer 70. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 of FIG. 3. FIG. 5 is a schematic cross-sectional view showing an enlarged portion of the semiconductor device of FIG. 4.

[0011] The semiconductor device 10 has a roughly rectangular parallelepiped shape. The semiconductor device 10 includes a semiconductor substrate 20. The semiconductor substrate 20 has a rectangular parallelepiped shape. The semiconductor substrate 20 includes a first surface 20S and a second surface 20R opposite the first surface 20S. The semiconductor substrate 20 includes multiple side surfaces 21 to 24 intersecting the first surface 20S and the second surface 20R. For ease of explanation, two mutually orthogonal directions within the first surface 20S of the semiconductor substrate 20 are defined as the X-axis direction and the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. The Z-axis direction may be perpendicular to the first surface 20S. Viewing a target component from the Z-axis direction is referred to as a planar view. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20. The X-axis direction corresponds to the "second direction," and the Y-axis direction corresponds to the "first direction." In one example, the first side surface 21 and the second side surface 22 extend along the Y-axis direction and face opposite each other. In one example, the third side surface 23 and the fourth side surface 24 extend along the X-axis direction and face in opposite directions.

[0012] The semiconductor substrate 20 may have a rounded shape with chamfered corners in a plan view. The side surfaces of the semiconductor substrate 20 do not have to be clearly divided into the first to fourth side surfaces 21 to 24.

[0013] The semiconductor substrate 20 may be made of a material containing Si (silicon). For example, the semiconductor substrate 20 may be a silicon substrate. The semiconductor substrate 20 may contain impurities or may not contain impurities. The impurities may be impurities of a first conductivity type. For example, the semiconductor substrate 20 may be a silicon substrate containing impurities of the first conductivity type. The first conductivity type may be, for example, p-type. The resistivity of the semiconductor substrate 20 may be 5 mΩ·cm or more and 100 mΩ·cm or less by introducing p-type impurities.

[0014] The semiconductor device 10 may include a surface insulating layer 42. The surface insulating layer 42 may cover the entire first surface 20S of the semiconductor substrate 20. The surface insulating layer 42 includes a first surface 42S and a second surface 42R opposite to the first surface 42S. The second surface 42R of the surface insulating layer 42 contacts the first surface 20S of the semiconductor substrate 20. The surface insulating layer 42 may have side surfaces that are flush with the side surfaces 21 to 24 of the semiconductor substrate 20.

[0015] The surface insulating layer 42 has insulating properties. The surface insulating layer 42 is made of a material containing at least one of SiO2 (silicon oxide), SiN (silicon nitride), SiON (silicon oxynitride), and Al2O3 (aluminum oxide). In one example, the surface insulating layer 42 is made of SiO2. The surface insulating layer 42 may have a structure in which a plurality of insulating films are stacked.

[0016] The semiconductor device 10 may include a first conductive layer 70. The first conductive layer 70 is disposed on the semiconductor substrate 20. The first conductive layer 70 is disposed on a surface insulating layer 42 that covers the first surface 20S of the semiconductor substrate 20. The surface insulating layer 42 may include a first portion 42A covered by the first conductive layer 70 and a second portion 42B exposed from the first conductive layer 70. In the Z-axis direction, the thickness of the second portion 42B may be equal to the thickness of the first portion 42A. The thickness of the second portion 42B may be thinner than the thickness of the first portion 42A.

[0017] The first conductive layer 70 includes a first surface 70S and a second surface 70R opposite to the first surface 70S. The second surface 70R of the first conductive layer 70 is in contact with the first surface 42S of the surface insulating layer 42. The first conductive layer 70 is disposed in a central region of the semiconductor substrate 20 in a plan view. The first conductive layer 70 is formed in a region spaced inward from the side surfaces 21 to 24 of the semiconductor substrate 20. In a plan view, the first conductive layer 70 can be said to be surrounded by the surface insulating layer 42 on the first surface 20S of the semiconductor substrate 20. The first conductive layer 70 can be said to be spaced apart from the periphery of the first surface 20S of the semiconductor substrate 20.

[0018] The first conductive layer 70 includes a plurality of side surfaces 71, 72, 73, and 74 connecting the first surface 70S and the second surface 70R. The side surfaces 71 to 74 of the first conductive layer 70 are arranged inwardly from the side surfaces 21 to 24 of the semiconductor substrate 20 at intervals. It can be said that the first conductive layer 70 includes the side surfaces 71 to 74 arranged inwardly from the side surfaces 21 to 24 of the semiconductor substrate 20 at intervals. The side surfaces 71 to 74 of the first conductive layer 70 may also be referred to as the edges or end faces of the first conductive layer 70. The region between the side surfaces 71 to 74 of the first conductive layer 70 and the side surfaces 21 to 24 of the semiconductor substrate 20 may be an insulating region 44 where the surface insulating layer 42 on the first surface 20S of the semiconductor substrate 20 is exposed.

[0019] The first conductive layer 70 may be made of one or more metal materials such as Cu (copper), Al (aluminum), Ni (nickel), Pd (palladium), Au (gold), etc. In one example, the first conductive layer 70 may be made of a material containing Al.

[0020] The semiconductor device 10 may include a second conductive layer 80. The second conductive layer 80 is disposed on the second surface 20R of the semiconductor substrate 20. The second conductive layer 80 may cover the second surface 20R of the semiconductor substrate 20. The second conductive layer 80 may have a side surface that is flush with the side surfaces 21 to 24 of the semiconductor substrate 20. In one example, the second conductive layer 80 may be composed of a plurality of stacked metal layers. The second conductive layer 80 may be composed of, for example, a Ni layer, a Pd layer, and an Au layer stacked one on top of the other. The semiconductor device 10 may not include the second conductive layer 80.

[0021] (Internal structure of semiconductor device) The semiconductor device 10 includes a plurality of trenches 30 provided in a semiconductor substrate 20. The plurality of trenches 30 are recessed from the first surface 20S of the semiconductor substrate 20 toward the second surface 20R. The plurality of trenches 30 are aligned in the X-axis direction in a plan view. The plurality of trenches 30 extend in the Y-axis direction. It can be said that the plurality of trenches 30 extend such that the Y-axis direction is the longitudinal direction and the X-axis direction is the width direction. The widths of the plurality of trenches 30 may be the same. The plurality of trenches 30 may extend linearly in the Y-axis direction. The plurality of trenches 30 are formed by removing a portion of the semiconductor substrate 20 from the first surface 20S.

[0022] The semiconductor substrate 20 includes a plurality of wall portions 50 arranged between the plurality of trenches 30. The plurality of wall portions 50 are aligned in the X-axis direction in a plan view. The plurality of wall portions 50 extend in the Y-axis direction. The plurality of wall portions 50 may extend linearly in the Y-axis direction. It can be said that the plurality of wall portions 50 extend with the Y-axis direction as their longitudinal direction and the X-axis direction as their width direction. The widths of the plurality of wall portions 50 may be the same. The widths of the plurality of wall portions 50 may be narrower than the widths of the plurality of trenches 30. It can be said that the plurality of wall portions 50 partition the plurality of trenches 30.

[0023] The semiconductor device 10 includes an insulating layer 41. The insulating layer 41 has insulating properties. The insulating layer 41 is provided within the trenches 30. The inner surface 31 of each trench 30 includes a pair of opposing side surfaces 32 and a bottom surface 33 connecting the pair of side surfaces. The side surfaces 32 of each trench 30 are formed by wall portions 50 that define each trench 30. The insulating layer 41 covers the inner surface 31 of the trench 30. It can be said that the insulating layer 41 is formed on the inner surfaces 31 of the multiple trenches 30. It can be said that the semiconductor device 10 includes multiple insulating layers 41 formed in each of the multiple trenches 30. The multiple insulating layers 41 may be formed integrally with a surface insulating layer 42 that covers the first surface 20S of the semiconductor substrate 20.

[0024] The semiconductor device 10 includes a plurality of grooves 45 formed by an insulating layer 41 provided on the inner surfaces 31 of a plurality of trenches 30. The plurality of grooves 45 are aligned in the X-axis direction in a plan view. The plurality of grooves 45 extend in the Y-axis direction. The plurality of grooves 45 may extend linearly in the Y-axis direction. It can be said that the plurality of grooves 45 extend with the Y-axis direction as their longitudinal direction and the X-axis direction as their width direction. The widths of the plurality of grooves 45 may be the same.

[0025] The semiconductor device 10 includes a plurality of electrode portions 60 provided in a plurality of trenches 30. The plurality of electrode portions 60 are provided in the plurality of trenches 30 while being surrounded by corresponding insulating layers 41. The insulating layers 41 in the plurality of trenches 30 form a plurality of groove portions 45. It can be said that the plurality of electrode portions 60 are arranged in a plurality of groove portions 45.

[0026] The multiple electrode portions 60 are conductive. The multiple electrode portions 60 are embedded in the multiple trenches 30. The multiple electrode portions 60 are exposed from the surface insulating layer 42. The surface insulating layer 42 has openings 421 that expose the multiple electrode portions 60. Surfaces 60S of the multiple electrode portions 60 are exposed through the openings 421 in the surface insulating layer 42. The surfaces 60S of the multiple electrode portions 60 may be flush with the first surface 42S of the surface insulating layer 42. The surfaces 60S of the multiple electrode portions 60 may be flat. The surfaces 60S of the multiple electrode portions 60 may include recesses that are recessed toward the inside of the electrode portions 60.

[0027] The plurality of electrode portions 60 are made of a material such as Cu or Al. The material making up the plurality of electrode portions 60 may be the same as or different from the material making up the first conductive layer 70. In one example, the plurality of electrode portions 60 are made of a material containing Cu. The plurality of electrode portions 60 may also be made of a material containing Al.

[0028] The electrode portion 60 faces the wall portion 50 with the insulating layer 41 sandwiched therebetween. The electrode portion 60 and the wall portion 50 facing each other with the insulating layer 41 sandwiched therebetween constitute a capacitor C1. The semiconductor device 10 includes a capacitor C1 constituted by a plurality of electrode portions 60, a plurality of wall portions 50, and a plurality of insulating layers 41 sandwiched between the plurality of electrode portions 60 and the plurality of wall portions 50.

[0029] 3 and 4, the first conductive layer 70 covers the entire region including the plurality of trenches 30 in a plan view. The first conductive layer 70 covers the plurality of electrode portions 60 embedded in the plurality of trenches 30. A second surface 70R of the first conductive layer 70 contacts the surfaces 60S of the plurality of electrode portions 60. The first conductive layer 70 is electrically connected to the plurality of electrode portions 60. Therefore, it can be said that the first conductive layer 70 electrically connects the plurality of electrode portions 60.

[0030] As shown in FIG. 5 , the semiconductor substrate 20 has a thickness T11 in the Z-axis direction. The thickness T11 of the semiconductor substrate 20 may be 100 μm or more and 500 μm or less. The width W11 of the trench 30 may be the distance between two wall portions 50 adjacent to each other in the X-axis direction. The width W11 of the trench 30 may be 10 μm or more and 20 μm or less. The width W11 of the trench 30 may be the length of the bottom surface 33 in the X-axis direction. The depth D12 of the trench 30 may be the distance in the Z-axis direction from the first surface 20S of the semiconductor substrate 20 to the bottom surface 33 of the trench 30. The depth D12 of the trench 30 may be shorter than the distance T12 in the Z-axis direction between the bottom surface 33 of the trench 30 and the second surface 20R of the semiconductor substrate 20. The depth D12 of the trench 30 may be 30 μm or more and 50 μm or less. A distance T12 in the Z-axis direction from the bottom surface 33 of the trench 30 to the second surface 20R of the semiconductor substrate 20 may be 50 μm or more and 100 μm or less.

[0031] The thickness T13 of the insulating layer 41 may be equal to or greater than the thickness T14 of the wall portion 50. The thickness T14 of the wall portion 50 may be the thickness of the thinnest wall portion among the plurality of wall portions 50. The average value of the thicknesses of the plurality of wall portions 50 may be used as the thickness T14 of the wall portion 50. The thickness T14 of the wall portion 50 may be the thickness of the thinnest portion of one of the wall portions 50. The thickness T14 of the wall portion 50 may be narrower than the width of the trench 30. The thickness T13 of the insulating layer 41 may be equal to or greater than 3 μm and equal to or less than 5 μm. The thickness T14 of the wall portion 50 may be equal to or greater than 3 μm and equal to or less than 5 μm.

[0032] The width W12 of the multiple grooves 45 may be the distance between the insulating layers 41 covering the pair of side surfaces 32 of the trench 30 in the X-axis direction. The width W12 of the grooves 45 may be 4 μm or more and 10 μm or less. The multiple electrode portions 60 are arranged in the multiple grooves 45. The width W12 of the multiple grooves 45 may also be referred to as the width of the electrode portion 60. The length of the electrode portion 60 in the Z-axis direction may be the distance in the Z-axis direction from the bottom surface of the groove 45 to the first surface 42S of the surface insulating layer 42. The length of the electrode portion 60 in the Z-axis direction may be 30 μm or more and 50 μm or less.

[0033] 2, distances L11, L12, L13, and L14 between side surfaces 71, 72, 73, and 74 of the first conductive layer 70 and side surfaces 21, 22, 23, and 24 of the semiconductor substrate 20 may be approximately 50 μm. The distances L11 to L14 may be 50 μm, for example. The distances L11 to L14 are the widths of the insulating regions 44. The widths of the insulating regions 44 may be the same or different in the circumferential direction of the semiconductor device 10.

[0034] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 of the first embodiment shown in FIGS. 1 to 5 will be described.

[0035] 6 to 17 are schematic cross-sectional views showing exemplary manufacturing processes for the semiconductor device 10 of the first embodiment. FIGS. 6 to 17 correspond to the cross-sectional structure of the semiconductor device 10 shown in FIG. 4. FIGS. 6 to 17 show the range for producing one semiconductor device 10. For ease of understanding, in FIGS. 6 to 17, the same reference numerals as in FIG. 4 are used to denote components that are the same as the final components of the semiconductor device 10.

[0036] 6, the method for manufacturing the semiconductor device 10 includes preparing a semiconductor substrate 800. The semiconductor substrate 800 may be, for example, a silicon wafer containing impurities of a first conductivity type. By using a silicon wafer, multiple semiconductor devices 10 can be manufactured simultaneously. The semiconductor substrate 800 includes a first surface 800S and a second surface 800R opposite to the first surface 800S.

[0037] 7, the method for manufacturing the semiconductor device 10 includes forming a mask 801 including a plurality of openings 802. The plurality of openings 802 are provided corresponding to the positions of the plurality of trenches 30. The mask 801 is formed of, for example, a photosensitive resin. The mask 801 is formed, for example, by patterning a sheet-like resist material attached to the first surface 800S of the semiconductor substrate 800, for example, by photolithography.

[0038] 8, the method for manufacturing the semiconductor device 10 includes forming a plurality of trenches 30. The plurality of trenches 30 are formed by, for example, dry etching the semiconductor substrate 800 through openings 802 in a mask 801 shown in Fig. 7. After the plurality of trenches 30 are formed, the mask 801 shown in Fig. 7 is removed.

[0039] 9, the method for manufacturing the semiconductor device 10 includes forming an insulating layer 40. The insulating layer 40 includes an insulating layer 41 that covers the inner surface 31 of the trench 30 and a surface insulating layer 42 that covers the first surface 800S of the semiconductor substrate 800. The insulating layer 40 is formed by thermally oxidizing the semiconductor substrate 800. The insulating layer 40 may be formed by, for example, a CVD method so as to cover the first surface 20S of the semiconductor substrate 800 and the inner surface of the trench 30.

[0040] 10 to 12, the method for manufacturing the semiconductor device 10 includes forming the electrode portion 60. The electrode portion 60 may include forming a seed layer 804, forming a first metal layer 805, and partially removing the first metal layer 805 to form the electrode portion 60.

[0041] 10, a seed layer 804 is formed. The seed layer 804 may be made of the material of the electrode portion 60. In one example, the seed layer 804 may be made of a material containing Cu. The seed layer 804 may be a layer used to form the electrode portion 60. The seed layer 804 is formed on the surface of the insulating layer 41 and the surface of the surface insulating layer 42 by, for example, sputtering.

[0042] 11, a first metal layer 805 is formed. The first metal layer 805 is made of the material of the electrode portion 60 shown in FIGS. 4 and 5. The first metal layer 805 is formed by electrolytic plating using a seed layer 804.

[0043] 12, the electrode section 60 is formed. The electrode section 60 is formed by removing the portions of the first metal layer 805 and the seed layer 804 shown in FIG. 11 that protrude upward from the surface insulating layer 42, for example, by a chemical mechanical polishing (CMP) method. The electrode section 60 is composed of the seed layer 804 and the first metal layer 805 (see 10) that remain in the recess surrounded by the insulating layer 41.

[0044] 13 to 15, the method for manufacturing a semiconductor device includes forming a first conductive layer 70. The first conductive layer 70 may include forming a second metal layer 806 shown in FIG. 13 and partially removing the second metal layer 806.

[0045] As shown in Fig. 13, a second metal layer 806 is formed. The second metal layer 806 is made of the material of the first conductive layer 70 shown in Figs. 1 to 5. In one example, the second metal layer 806 is made of a material containing Al. The second metal layer 806 is formed by, for example, sputtering, so as to cover the surface 60S of the electrode portion 60 and the first surface 42S of the surface insulating layer 42.

[0046] As shown in FIG. 14 , a mask 807 is formed to partially cover the second metal layer 806. The mask 807 is provided to correspond to the first conductive layer 70 shown in FIGS. 1 to 5 . The mask 807 is formed so as to cover the trenches 30 and the electrode portions 60 in plan view. The mask 807 is formed of, for example, a photosensitive resin. The mask 807 is formed by patterning, for example, a seed-shaped resist material by, for example, photolithography.

[0047] 15, the second metal layer 806 is partially removed to form the first conductive layer 70. The first conductive layer 70 is formed by removing the second metal layer 806 exposed from the mask 807 shown in FIG. 14 by, for example, dry etching. After the first conductive layer 70 is formed, the mask 807 shown in FIG. 14 is removed.

[0048] As shown in FIG. 16, the manufacturing method of the semiconductor device 10 includes forming a semiconductor substrate 20. The semiconductor substrate 20 is formed by thinning the semiconductor substrate 800 shown in FIG. 15 to the thickness indicated by the dashed line. The thinning of the semiconductor substrate 800 is performed, for example, by grinding the semiconductor substrate 800 from the second surface 800R of the semiconductor substrate 800. The thinning of the semiconductor substrate 800 may be performed by etching, or by grinding and etching. The second surface 20R of the semiconductor substrate 20 is formed by the thinning.

[0049] 17, the method for manufacturing the semiconductor device 10 includes forming a second conductive layer 80. The second conductive layer 80 is formed by sputtering, for example, so as to cover the second surface 20R of the semiconductor substrate 20. Through the above steps, the semiconductor device 10 is manufactured.

[0050] (Operation of the first embodiment) The semiconductor device 10 includes a semiconductor substrate 20, multiple trenches 30, an insulating layer 41, and multiple electrode portions 60. The semiconductor substrate 20 includes a first surface 20S and a second surface 20R opposite the first surface 20S. The multiple trenches 30 are recessed from the first surface 20S toward the second surface 20R, extend in the Y-axis direction in a plan view, and are aligned in the X-axis direction. An insulating layer 41 is disposed on the inner surface 31 of each of the multiple trenches 30. The multiple electrode portions 60 are provided within the multiple trenches 30 and are surrounded by the corresponding insulating layer 41. The semiconductor substrate 20 includes multiple wall portions 50 disposed between the multiple trenches 30 and partitioning the multiple trenches 30. The wall portions 50 and the electrode portions 60 face each other with the insulating layer 41 sandwiched therebetween, thereby forming a capacitor C1. The thickness T13 of the insulating layer 41 is equal to or greater than the thickness T14 of the wall portions 50.

[0051] The semiconductor device 10 includes a capacitor C1 configured with a wall portion 50, an insulating layer 41, and an electrode portion 60. The capacitor C1 has a breakdown voltage corresponding to the thickness T13 of the insulating layer 41. Therefore, the insulating layer 41 having a thickness T13 equal to or greater than the thickness T14 of the wall portion 50 can improve the breakdown voltage of the capacitor C1, and therefore the breakdown voltage of the semiconductor device 10.

[0052] The insulating layer 41 is disposed on the inner surfaces 31 of the plurality of trenches 30. The plurality of trenches 30 has a width W11 necessary for disposing the insulating layer 41 with a desired thickness T13. The plurality of trenches 30 extend with their longitudinal direction in the Y-axis direction and their width direction in the X-axis direction. This allows the plurality of trenches 30 to be easily formed. Furthermore, the wall portions 50 with a desired thickness T14 can be easily formed.

[0053] The thickness T14 of the wall portion 50 may be narrower than the width of the trench 30. This allows the number of trenches 30 included in the semiconductor device 10, i.e., the number of wall portions 50, to be increased. This allows the capacitance value of the capacitor C1 included in the semiconductor device 10 to be ensured.

[0054] The depth D12 of the trenches 30 is shorter than the distance T12 between the bottom surfaces 33 of the trenches 30 and the second surface 20R of the semiconductor substrate 20. That is, in the Z-axis direction, the thickness of the portion without the trenches 30 is thicker than the thickness of the portion where the trenches 30 are provided. This ensures the strength of the semiconductor substrate 20, that is, the strength of the semiconductor device 10. Note that it is preferable that the distance T12 between the bottom surfaces 33 of the trenches 30 and the second surface 20R of the semiconductor substrate 20 is short. This reduces the resistance value of the parasitic resistance of the semiconductor substrate 20 between the capacitor C1 and the second conductive layer 80.

[0055] The first conductive layer 70 covers the entire area including the plurality of trenches 30. A plurality of electrode portions 60 surrounded by an insulating layer 41 are arranged in the plurality of trenches 30. Therefore, the plurality of electrode portions 60 arranged in the plurality of trenches 30 can be electrically connected to the first conductive layer 70.

[0056] As shown in FIG. 4 , a connection member WB is bonded to the first conductive layer 70 of the semiconductor device 10. The second conductive layer 80 of the semiconductor substrate 20 is mounted on a mounting substrate (not shown). The connection member WB may be a bonding wire, a ribbon, or the like. The connection member WB may be made of a material such as Cu, Al, or Au. The second conductive layer 80 is connected to the mounting substrate by solder or conductive paste. The second conductive layer 80 may be omitted, and the semiconductor substrate 20 may be connected to the mounting substrate by conductive paste. The first conductive layer 70 may be made of a material containing Cu and Al. In the case of a first conductive layer 70 made of a material containing Al, using a connection member WB made of a soft metal such as Au reduces the influence of bonding to the semiconductor device 10 and ensures reliable connection of the connection member WB to the first conductive layer 70.

[0057] (Effects of the first embodiment) As described above, the semiconductor device 10 of the first embodiment provides the following advantages. (1-1) The semiconductor device 10 includes a semiconductor substrate 20, multiple trenches 30, an insulating layer 41, and multiple electrode portions 60. The semiconductor substrate 20 includes a first surface 20S and a second surface 20R opposite the first surface 20S. The multiple trenches 30 are recessed from the first surface 20S toward the second surface 20R, extend in the Y-axis direction in a plan view, and are aligned in the X-axis direction. An insulating layer 41 is disposed on the inner surface 31 of each of the multiple trenches 30. The multiple electrode portions 60 are provided within the multiple trenches 30 and are surrounded by the corresponding insulating layer 41. The semiconductor substrate 20 includes multiple wall portions 50 disposed between the multiple trenches 30 and partitioning the multiple trenches 30. The wall portions 50 and the electrode portions 60 face each other with the insulating layer 41 interposed therebetween, thereby forming a capacitor C1. The thickness T13 of the insulating layer 41 is equal to or greater than the thickness T14 of the wall portions 50.

[0058] The semiconductor device 10 includes a capacitor C1 configured with a wall portion 50, an insulating layer 41, and an electrode portion 60. The capacitor C1 has a breakdown voltage corresponding to the thickness T13 of the insulating layer 41. Therefore, the insulating layer 41 having a thickness T13 equal to or greater than the thickness T14 of the wall portion 50 can improve the breakdown voltage of the capacitor C1, and therefore the breakdown voltage of the semiconductor device 10.

[0059] (1-2) The insulating layer 41 is disposed on the inner surfaces 31 of the plurality of trenches 30. The plurality of trenches 30 has a width W11 necessary for disposing the insulating layer 41 with a desired thickness T13. The plurality of trenches 30 extend such that the longitudinal direction is the Y-axis direction and the width direction is the X-axis direction. This allows the plurality of trenches 30 to be easily formed. Furthermore, the wall portion 50 with a desired thickness T14 can be easily formed.

[0060] (1-3) The thickness T14 of the wall portion 50 may be narrower than the width of the trench 30. This allows the number of trenches 30 included in the semiconductor device 10, i.e., the number of wall portions 50, to be increased. This allows the capacitance value of the capacitor C1 included in the semiconductor device 10 to be ensured.

[0061] (1-4) The depth D12 of the trenches 30 is shorter than the distance T12 between the bottom surfaces 33 of the trenches 30 and the second surface 20R of the semiconductor substrate 20. That is, in the Z-axis direction, the thickness of the portion without the trenches 30 is thicker than the thickness of the portion where the trenches 30 are provided. This ensures the strength of the semiconductor substrate 20, that is, the strength of the semiconductor device 10. Note that it is preferable that the distance T12 between the bottom surfaces 33 of the trenches 30 and the second surface 20R of the semiconductor substrate 20 is short. This reduces the resistance value of the parasitic resistance of the semiconductor substrate 20 between the capacitor C1 and the second conductive layer 80.

[0062] (1-5) The first conductive layer 70 covers the entire area including the plurality of trenches 30. A plurality of electrode portions 60 surrounded by an insulating layer 41 are arranged in the plurality of trenches 30. Therefore, the plurality of electrode portions 60 arranged in the plurality of trenches 30 can be electrically connected to the first conductive layer 70.

[0063] (1-6) A connection member WB is bonded to the first conductive layer 70 of the semiconductor device 10. The second conductive layer 80 of the semiconductor substrate 20 is mounted on a mounting substrate (not shown). The connection member WB may be a bonding wire, a ribbon, or the like. The connection member WB may be made of a material such as Cu, Al, or Au. The second conductive layer 80 is connected to the mounting substrate by solder or conductive paste. The second conductive layer 80 may be omitted, and the semiconductor substrate 20 may be connected to the mounting substrate by conductive paste. The first conductive layer 70 may be made of a material containing Cu or Al. In the case of a first conductive layer 70 made of a material containing Al, using a connection member WB made of a soft metal such as Au reduces the influence of bonding to the semiconductor device 10, allowing the connection member WB to be reliably connected to the first conductive layer 70.

[0064] (Modification of the first embodiment) The first embodiment can be modified, for example, as follows. The first embodiment and each of the modified examples can be combined with each other as long as no technical contradiction occurs. In the modified examples, parts common to the first embodiment will be assigned the same reference numerals as in the first embodiment, and their description will be omitted.

[0065] 18, the semiconductor device 10A of the modified example may include a passivation layer 90. The passivation layer 90 may be made of an inorganic material. For example, the passivation layer 90 may be made of a material including at least one of SiO2, SiN, SiON, and Al2O3.

[0066] The passivation layer 90 covers the surface insulating layer 42 and the first conductive layer 70. The passivation layer 90 includes an opening 90A that exposes a portion of the first conductive layer 70. In one example, the opening 90A in the passivation layer 90 exposes a portion of the first surface 70S of the first conductive layer 70 that is more inward than the peripheral edge portion.

[0067] The passivation layer 90 includes a first portion 91 covering the surface insulating layer 42, a second portion 92 covering the side surfaces 71 to 74 of the first conductive layer 70, and a third portion 93 covering the peripheral portion of the first surface 70S of the first conductive layer 70. The passivation layer 90 may include only the first portion 91 covering the surface insulating layer 42. Alternatively, the passivation layer 90 may include the first portion 91 covering the surface insulating layer 42 and the second portion 92 covering the side surfaces 71 to 74 of the first conductive layer 70.

[0068] The first portion 91 of the passivation layer 90 covers the surface insulating layer 42, thereby ensuring the creepage distance between the first conductive layer 70 and the semiconductor substrate 20. The first portion 91 of the passivation layer 90 also protects the surface insulating layer 42. The second portion 92 of the passivation layer 90 covers the side surfaces 71 to 74 of the first conductive layer 70, thereby increasing the creepage distance between the first conductive layer 70 and the semiconductor substrate 20. The third portion 93 of the passivation layer 90 covers the peripheral portion of the first surface 70S of the first conductive layer 70, thereby further increasing the creepage distance between the first conductive layer 70 and the semiconductor substrate 20. The second portion 92 and the third portion 93 of the passivation layer 90 also protect the peripheral portion of the first conductive layer 70.

[0069] As shown in FIG. 19, the semiconductor device 10B of the modified example differs from the semiconductor device 10 of the first embodiment in the configuration of the first conductive layer 270. The first conductive layer 270 of the semiconductor device 10B of the modified example has a stacked structure of multiple metal layers. The first conductive layer 270 may include a first metal layer 271 and a second metal layer 272. The first metal layer 271 is disposed so as to cover the multiple trenches 30 and the multiple electrode portions 60.

[0070] For example, the first metal layer 271 may be a seed layer. The seed layer may be a sputtered layer formed by sputtering. The first metal layer 271 may be made of a material containing Cu.

[0071] The second metal layer 272 may be a plating layer formed using the first metal layer 271. The second metal layer 272 may be composed of a plurality of plating layers. For example, the second metal layer 272 may include a first plating layer 281 and a second plating layer 282. The first plating layer 281 is disposed on the first metal layer 271. For example, the first plating layer 281 may be composed of a material containing Cu. The second plating layer 282 is disposed on the first plating layer 281. The second plating layer 282 may cover the entire upper surface of the first plating layer 281. For example, the second plating layer 282 may be composed of a material containing Ni. The second metal layer 272 may further include a third plating layer 283. The third plating layer 283 is disposed on the second plating layer 282. The third plating layer 283 may cover the entire upper surface of the second plating layer 282. The third plating layer 283 may be made of a material containing Pd or Au, and may include a Pd film and an Au film.

[0072] Next, an example of a method for manufacturing the semiconductor device 10B of the modified example shown in FIG. 19 will be described. 20 to 26 are schematic cross-sectional views showing exemplary manufacturing steps of a modified semiconductor device 10B. Figures 20 to 26 correspond to the cross-sectional structure of the semiconductor device 10B shown in Figure 20. For ease of understanding, in Figures 20 to 26, components that are the same as the final components of the semiconductor device 10B are denoted by the same reference numerals as in Figure 19.

[0073] 20 to 26 are schematic cross-sectional views showing an example of a manufacturing process for the semiconductor device 10B of Fig. 19, illustrating the process for forming the first conductive layer 270. That is, the semiconductor device 10B of the modified example is formed by the manufacturing process for the semiconductor device 10 of the first embodiment according to the schematic cross-sectional views shown in Figs. 6 to 12 and the manufacturing process according to the schematic cross-sectional views shown in Figs. 20 to 28.

[0074] 20, the method for manufacturing the semiconductor device 10B includes forming an electrode portion 60. This electrode portion 60 may be formed by the steps shown in FIGS. 10 to 12 of the first embodiment.

[0075] 21 to 24, the method for manufacturing the semiconductor device 10B includes forming a first conductive layer 270. The first conductive layer 270 may include forming a seed layer 810, forming a second metal layer 272, and forming a first metal layer 271.

[0076] As shown in FIG. 21 , a seed layer 810 is formed. The seed layer 810 may be a layer used to form the second metal layer 272. The seed layer 810 may be made of the material of the first plating layer 281. The seed layer 810 may be a layer used to form the electrode portion 60. In one example, the seed layer 810 is made of a material containing Cu. The seed layer 810 is formed on the surface 60S of the electrode portion 60 and the first surface 42S of the surface insulating layer 42 by, for example, sputtering.

[0077] 22, a mask 811 including an opening 812 exposing a portion of the seed layer 810 is formed on the seed layer 810. The opening 812 is disposed at a position corresponding to the second metal layer 272. The mask 811 is formed of, for example, a photosensitive resin. The mask 811 is formed, for example, by patterning a sheet-like resist material attached on the seed layer 810 by, for example, photolithography.

[0078] As shown in FIG. 23 , a second metal layer 272 is formed. In one example, the second metal layer 272 includes a first plating layer 281, a second plating layer 282, and a third plating layer 283. First, the first plating layer 281 is formed on the seed layer 810. The first plating layer 281, the second plating layer 282, and the third plating layer 283 can be formed by, for example, an electrolytic plating method. The first plating layer 281 is made of a material containing Cu. The first plating layer 281 is formed on the seed layer 810 exposed by the opening 812 of the mask 811.

[0079] The second plating layer 282 is made of a material containing Ni. The second plating layer 282 is formed on the first plating layer 281. The second plating layer 282 is formed so as to cover the entire upper surface of the first plating layer 281. The third plating layer 283 is made of a material containing Pd or Au. The third plating layer 283 is formed on the second plating layer 282. The third plating layer 283 is formed so as to cover the entire upper surface of the second plating layer 282. In this way, the second metal layer 272 is formed.

[0080] After forming the third plating layer 283, the mask 811 is removed. Then, the seed layer 810 exposed from the second metal layer 272 is removed. The exposed seed layer 810 may be removed by, for example, wet etching. As a result, the first metal layer 271 shown in FIG. 24 is obtained.

[0081] The manufacturing process according to FIGS. 25 and 26 is similar to the manufacturing process according to FIGS. 16 and 17 of the first embodiment. 25, the manufacturing method of the semiconductor device 10B includes forming a semiconductor substrate 20. The semiconductor substrate 20 is formed by thinning the semiconductor substrate 800 shown in FIG. 24 to the thickness indicated by the dashed line. The semiconductor substrate 800 is thinned, for example, by grinding the semiconductor substrate 800 from the second surface 800R of the semiconductor substrate 800. The semiconductor substrate 800 may be thinned by etching, or by grinding and etching.

[0082] 26, the method for manufacturing the semiconductor device 10B includes forming a second conductive layer 80. The second conductive layer 80 is formed by sputtering, for example, so as to cover the second surface 20R of the semiconductor substrate 20. Through the above steps, the semiconductor device 10B is manufactured.

[0083] The first conductive layer 270 of the semiconductor device 10B of the modified example includes a first metal layer 271 and a second metal layer 272. The second metal layer 272 includes Ni. Ni is a metal harder than Al that constitutes the first conductive layer 70 of the first embodiment. Therefore, a connection member WB made of a metal harder than Au, such as Cu or Al, can be used.

[0084] (Second embodiment) (Schematic configuration of semiconductor device) FIG. 27 is a schematic perspective view of an exemplary semiconductor device 310 according to the second embodiment. FIG. 28 is a schematic plan view of the semiconductor device 310 of FIG. 27. FIG. 29 is a schematic plan view of the semiconductor device 310 of FIG. 27. FIG. 30 is a schematic cross-sectional view of the semiconductor device 310 taken along line F30-F30 of FIG. 27. FIG. 31 is a schematic cross-sectional view of the semiconductor device 310 taken along line F31-F31 of FIG. 27. FIG. 32 is a schematic cross-sectional view of the semiconductor device 310 taken along line F32-F32 of FIG. 30. FIG. 33 is a schematic cross-sectional view of the semiconductor device 310 taken along line F33-F33 of FIG. 30. FIG. 34 is a schematic cross-sectional view showing an enlarged portion of the semiconductor device 310 of FIG. 30.

[0085] In the semiconductor device 310 of the second embodiment, the same components as those in the semiconductor device 10 of the first embodiment are denoted by the same reference numerals. The semiconductor device 310 has a roughly rectangular parallelepiped shape. The semiconductor device 310 includes a semiconductor substrate 320. The semiconductor substrate 320 has a rectangular parallelepiped shape. The semiconductor substrate 320 includes a first surface 320S and a second surface 320R opposite the first surface 320S. The semiconductor substrate 320 includes a plurality of side surfaces 321-324 that intersect with the first surface 320S and the second surface 320R. For ease of explanation, the two mutually orthogonal directions within the first surface 320S of the semiconductor substrate 320 are referred to as the X-axis direction and the Y-axis direction, and the direction orthogonal to the X-axis direction and the Y-axis direction is referred to as the Z-axis direction. The Z-axis direction may be perpendicular to the first surface 320S. Viewing a target component from the Z-axis direction is referred to as a planar view. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 320. The X-axis direction corresponds to the "second direction," and the Y-axis direction corresponds to the "first direction." In one example, the first side surface 321 and the second side surface 322 extend along the Y-axis direction and face opposite each other. In another example, the third side surface 323 and the fourth side surface 324 extend along the X-axis direction and face opposite each other.

[0086] The semiconductor substrate 320 may have a rounded shape with chamfered corners in a plan view. The side surfaces of the semiconductor substrate 320 do not have to be clearly divided into the first to fourth side surfaces 321 to 324.

[0087] The semiconductor substrate 320 may be made of a material containing Si. In one example, the semiconductor substrate 320 may be a silicon substrate. The semiconductor substrate 320 may contain impurities or may not contain impurities. The impurities may be impurities of a first conductivity type. In one example, the semiconductor substrate 320 may be a silicon substrate containing impurities of the first conductivity type. The first conductivity type may be, for example, p-type. The resistivity of the semiconductor substrate 320 may be 5 mΩ·cm or more and 100 mΩ·cm or less by introducing p-type impurities.

[0088] The semiconductor device 310 may include a surface insulating layer 343. The surface insulating layer 343 may cover the entire first surface 320S of the semiconductor substrate 320. The surface insulating layer 343 includes a first surface 343S and a second surface 343R opposite to the first surface 343S. The second surface 343R of the surface insulating layer 343 contacts the first surface 320S of the semiconductor substrate 320. The surface insulating layer 343 may have side surfaces that are flush with the side surfaces 321 to 324 of the semiconductor substrate 320.

[0089] The surface insulating layer 343 has insulating properties. The surface insulating layer 343 is made of a material containing at least one of SiO2, SiN, SiON, and Al2O3. In one example, the surface insulating layer 343 is made of SiO2. The surface insulating layer 343 may have a structure in which a plurality of insulating films are stacked.

[0090] The semiconductor device 310 may include a first conductive layer 70. The first conductive layer 70 is disposed on a semiconductor substrate 320. The first conductive layer 70 is disposed on a surface insulating layer 343 that covers a first surface 320S of the semiconductor substrate 320.

[0091] The first conductive layer 70 includes a first surface 70S and a second surface 70R opposite to the first surface 70S. The second surface 70R of the first conductive layer 70 is in contact with the first surface 343S of the surface insulating layer 343. The first conductive layer 70 is disposed in a central region of the semiconductor substrate 320 in a plan view. The first conductive layer 70 is formed in a region spaced inward from the side surfaces 321 to 324 of the semiconductor substrate 320. In a plan view, the first conductive layer 70 can be said to be surrounded by the surface insulating layer 343 on the first surface 320S of the semiconductor substrate 320. The first conductive layer 70 can be said to be spaced apart from the periphery of the first surface 320S of the semiconductor substrate 320.

[0092] The first conductive layer 70 includes a plurality of side surfaces 71, 72, 73, and 74 connecting the first surface 70S and the second surface 70R. The side surfaces 71 to 74 of the first conductive layer 70 are arranged inwardly from the side surfaces 321 to 324 of the semiconductor substrate 320 at intervals. It can be said that the first conductive layer 70 includes the side surfaces 71 to 74 arranged inwardly from the side surfaces 321 to 324 of the semiconductor substrate 320 at intervals. The side surfaces 71 to 74 of the first conductive layer 70 may also be referred to as the edges or end faces of the first conductive layer 70. The region between the side surfaces 71 to 74 of the first conductive layer 70 and the side surfaces 321 to 324 of the semiconductor substrate 320 may be an insulating region 344 where the surface insulating layer 343 on the first surface 320S of the semiconductor substrate 320 is exposed.

[0093] The first conductive layer 70 may be made of one or more metal materials such as Cu, Al, Ni, Pd, Au, etc. In one example, the first conductive layer 70 may be made of a material containing Al.

[0094] The semiconductor device 310 may include a second conductive layer 80. The second conductive layer 80 is disposed on the second surface 320R of the semiconductor substrate 320. The second conductive layer 80 may cover the second surface 320R of the semiconductor substrate 320. The second conductive layer 80 may have a side surface that is flush with the side surfaces 321 to 324 of the semiconductor substrate 320. For example, the second conductive layer 80 may be composed of a plurality of stacked metal layers. The second conductive layer 80 may be composed of, for example, a Ni layer, a Pd layer, and an Au layer stacked one on top of the other. The semiconductor device 310 may not include the second conductive layer 80.

[0095] (Internal structure of semiconductor device) As shown in FIGS. 29 to 32, a first surface 320S of a semiconductor substrate 320 includes a first region 320A and a second region 320B surrounding the first region 320A.

[0096] The semiconductor device 310 includes a plurality of first trenches 330A and a plurality of second trenches 330B formed in a semiconductor substrate 320. (1st trench) The multiple first trenches 330A are provided in a first region 320A of a first surface 320S of the semiconductor substrate 320. The multiple first trenches 330A are recessed from the first surface 320S of the semiconductor substrate 320 toward the second surface 320R. The multiple first trenches 330A are aligned in the X-axis direction in a plan view. The multiple first trenches 330A extend in the Y-axis direction. It can be said that the multiple first trenches 330A extend such that the Y-axis direction is the longitudinal direction and the X-axis direction is the width direction. The multiple first trenches 330A may have the same width. The multiple first trenches 330A may extend linearly in the Y-axis direction. The multiple first trenches 330A are formed by removing a portion of the semiconductor substrate 320 from the first surface 320S.

[0097] The semiconductor substrate 320 includes a plurality of first wall portions 351 arranged between the plurality of first trenches 330A. The plurality of first wall portions 351 are aligned in the X-axis direction in a plan view. The plurality of first wall portions 351 extend in the Y-axis direction. The plurality of first wall portions 351 may extend linearly in the Y-axis direction. It can be said that the plurality of first wall portions 351 extend such that the Y-axis direction is the longitudinal direction and the X-axis direction is the width direction. The widths of the plurality of first wall portions 351 may be the same. The widths of the plurality of first wall portions 351 may be narrower than the widths of the plurality of first trenches 330A. It can be said that the plurality of first wall portions 351 partition the plurality of first trenches 330A.

[0098] As shown in FIGS. 30 and 31 , the semiconductor device 310 includes a first insulating layer 341. The first insulating layer 341 has insulating properties. The first insulating layer 341 is provided in each first trench 330A. The inner surface 331A of each first trench 330A includes a pair of opposing side surfaces 332A and a bottom surface 333A connecting the pair of side surfaces. The side surface 332A of each first trench 330A is formed by a first wall portion 351 that separates the multiple first trenches 330A. The first insulating layer 341 covers the inner surface 331A of each first trench 330A. It can be said that the first insulating layer 341 is formed on the inner surfaces 331A of the multiple first trenches 330A. It can be said that the semiconductor device 310 includes multiple first insulating layers 341 formed in each of the multiple first trenches 330A. The plurality of first insulating layers 341 may be formed integrally with a surface insulating layer 343 that covers the first surface 320S of the semiconductor substrate 320.

[0099] The semiconductor device 310 includes a plurality of first grooves 345A formed by a first insulating layer 341 provided on the inner surfaces 331A of a plurality of first trenches 330A. The plurality of first grooves 345A are aligned in the X-axis direction in a plan view. The plurality of grooves 45 extend in the Y-axis direction. The plurality of first grooves 345A may extend linearly in the Y-axis direction. It can be said that the plurality of first grooves 345A extend such that the Y-axis direction is the longitudinal direction and the X-axis direction is the width direction. The widths of the plurality of first grooves 345A may be the same.

[0100] The semiconductor device 310 includes a plurality of electrode portions 60 provided in a plurality of first trenches 330A. The plurality of electrode portions 60 are provided in the plurality of first trenches 330A while being surrounded by corresponding first insulating layers 341. The first insulating layers 341 in the plurality of first trenches 330A form a plurality of first groove portions 345A. It can be said that the plurality of electrode portions 60 are arranged in a plurality of first groove portions 345A.

[0101] The plurality of electrode portions 60 are conductive. The plurality of electrode portions 60 are embedded in the plurality of first trenches 330A. The plurality of electrode portions 60 are exposed from the surface insulating layer 343. The surface insulating layer 343 has first openings 343A that expose the plurality of electrode portions 60. Surfaces 60S of the plurality of electrode portions 60 are exposed through the first openings 343A of the surface insulating layer 343. The surfaces 60S of the plurality of electrode portions 60 may be flush with the first surface 343S of the surface insulating layer 343. The surfaces 60S of the plurality of electrode portions 60 may be flat. The surfaces 60S of the plurality of electrode portions 60 may include recesses that are recessed toward the inside of the electrode portions 60.

[0102] The plurality of electrode portions 60 are made of a material such as Cu or Al. The material making up the plurality of electrode portions 60 may be the same as or different from the material making up the first conductive layer 70. In one example, the plurality of electrode portions 60 are made of a material containing Cu. The plurality of electrode portions 60 may also be made of a material containing Al.

[0103] The electrode portion 60 faces the first wall portion 351 with the first insulating layer 341 sandwiched therebetween. The electrode portion 60 and the first wall portion 351 facing each other with the first insulating layer 341 sandwiched therebetween constitute a capacitor C2. The semiconductor device 310 includes a capacitor C2 constituted by a plurality of electrode portions 60, a plurality of first wall portions 351, and a plurality of first insulating layers 341 sandwiched between the plurality of electrode portions 60 and the plurality of first wall portions 351.

[0104] 29 to 32, the first conductive layer 70 covers the entire region including the multiple first trenches 330A in plan view. The first conductive layer 70 covers the multiple electrode units 60 embedded in the multiple first trenches 330A. The second surface 70R of the first conductive layer 70 contacts the surfaces 60S of the multiple electrode units 60. The first conductive layer 70 is electrically connected to the multiple electrode units 60. Therefore, it can be said that the first conductive layer 70 electrically connects the multiple electrode units 60.

[0105] (Second trench) 29 to 32, the multiple second trenches 330B are provided in the second region 320B of the first surface 320S of the semiconductor substrate 320. The second region 320B may be a region between the first region 320A of the first surface 320S of the semiconductor substrate 320 and the end 320SE of the first surface 320S. It can be said that the multiple second trenches 330B are arranged between the capacitor C2 and the end 320SE of the first surface 320S of the semiconductor substrate 320.

[0106] As shown in FIGS. 29 and 32, the plurality of second trenches 330B are arranged to surround the plurality of first trenches 330A. The second trench 330B includes first peripheral trenches 330BA arranged to sandwich the multiple first trenches 330A in the Y-axis direction. The first peripheral trenches 330BA are arranged on both sides of the multiple first trenches 330A in the X-axis direction. The multiple first peripheral trenches 330BA extend along the side surfaces 321, 322 of the semiconductor substrate 320. The multiple first peripheral trenches 330BA extend in the Y-axis direction. The multiple first peripheral trenches 330BA are arranged at a distance in the X-axis direction. It can be said that the multiple second trenches 330B are arranged at a distance in the X-axis direction. The arrangement interval (arrangement pitch) of the multiple first peripheral trenches 330BA in the X-axis direction may be equal to the arrangement interval (arrangement pitch) of the multiple first trenches 330A in the X-axis direction. The arrangement interval of the multiple first peripheral trenches 330BA may be different from the arrangement interval of the multiple first trenches 330A. In the X-axis direction, the spacing between the first trench 330A and the first peripheral trench 330BA may be equal to the spacing between the multiple first trenches 330A. In the X-axis direction, the spacing between the first trench 330A and the first peripheral trench 330BA may be different from the spacing between the multiple first trenches 330A.

[0107] The second trench 330B includes second peripheral trenches 330BB arranged to sandwich the multiple first trenches 330A in the Y-axis direction. The second peripheral trenches 330BB are arranged on both sides of the multiple first trenches 330A in the Y-axis direction. The multiple second peripheral trenches 330BB extend along the side surfaces 323, 324 of the semiconductor substrate 320. The multiple second peripheral trenches 330BB extend in the X-axis direction. The multiple second peripheral trenches 330BB are arranged at a distance in the Y-axis direction. It can be said that the multiple second trenches 330B are arranged at a distance in the Y-axis direction.

[0108] The arrangement interval (arrangement pitch) of the multiple second peripheral trenches 330BB in the Y-axis direction may be equal to the arrangement interval (arrangement pitch) of the multiple first trenches 330A in the X-axis direction. The arrangement interval of the multiple second peripheral trenches 330BB may be different from the arrangement interval of the multiple first trenches 330A. In the Y-axis direction, the interval between the first trench 330A and the first peripheral trench 330BA may be equal to the arrangement interval of the multiple first trenches 330A. In the Y-axis direction, the interval between the first trench 330A and the first peripheral trench 330BA may be different from the arrangement interval of the multiple first trenches 330A.

[0109] In one example, the plurality of first peripheral trenches 330BA are sandwiched between a plurality of second peripheral trenches 330BB arranged on both sides of the plurality of first trenches 330A in the Y-axis direction. The plurality of second peripheral trenches 330BB can be said to be arranged so as to sandwich the plurality of first trenches 330A and the plurality of first peripheral trenches 330BA. The plurality of second peripheral trenches 330BB can be said to be arranged so as to sandwich the plurality of first peripheral trenches 330BA in the Y-axis direction.

[0110] As shown in FIGS. 30 and 31 , the semiconductor device 310 includes a second insulating layer 342. The second insulating layer 342 has insulating properties. The second insulating layer 342 is provided in each second trench 330B. The inner surface 331B of each second trench 330B includes a pair of opposing side surfaces 332B and a bottom surface 333B connecting the pair of side surfaces. The side surfaces 332B of each second trench 330B are formed by second wall portions 352 that separate the multiple second trenches 330B. The second insulating layer 342 covers the inner surface 331B of each second trench 330B. It can be said that the second insulating layer 342 is formed on the inner surfaces 331B of the multiple second trenches 330B. It can be said that the semiconductor device 310 includes multiple second insulating layers 342 formed in each of the multiple second trenches 330B. The plurality of second insulating layers 342 may be formed integrally with a surface insulating layer 343 that covers the first surface 320S of the semiconductor substrate 320.

[0111] The semiconductor device 310 includes a plurality of second grooves 345B surrounded by a second insulating layer 342. The second insulating layer 342 covers the inner surfaces 331B of the plurality of second trenches 330B. The second insulating layer 342 covers the inner surfaces 331B of the second trenches 330B, forming a void surrounded by the second insulating layer 342. The void in the second insulating layer 342 communicates with the outside through a second opening 343B in the surface insulating layer 343. The second insulating layer 342 and the second opening 343B in the surface insulating layer form a second groove 345B surrounded by the surface insulating layer 343 and the second insulating layer 342. This second groove 345B is formed by the plurality of second trenches 330B and the plurality of second insulating layers 342. That is, as shown in FIGS. 27 and 28, the semiconductor device 310 includes a plurality of second grooves 345B on the surface of the surface insulating layer 343. The plurality of second grooves 345B are arranged to surround the first conductive layer 70.

[0112] 34, the semiconductor substrate 320 has a thickness T21 in the Z-axis direction. The thickness T21 of the semiconductor substrate 320 may be not less than 100 μm and not more than 500 μm. The width W21 of the first trench 330A may be the distance between two first wall portions 351 adjacent to each other in the X-axis direction. The width W21 of the first trench 330A may be 10 μm or more and 20 μm or less. The width W21 of the first trench 330A may be the length of the bottom surface 333A of the first trench 330A in the X-axis direction. The depth D22 of the first trench 330A may be the distance in the Z-axis direction from the first surface 320S of the semiconductor substrate 320 to the bottom surface 333A of the first trench 330A. The depth D22 of the first trench 330A may be shorter than the distance T22 in the Z-axis direction between the bottom surface 333A of the first trench 330A and the second surface 320R of the semiconductor substrate 320. The depth D22 of the first trench 330A may be 30 μm or more and 50 μm or less. A distance T22 in the Z-axis direction from the bottom surface 333A of the first trench 330A to the second surface 320R of the semiconductor substrate 320 may be 50 μm or more and 100 μm or less.

[0113] The thickness T23 of the first insulating layer 341 may be equal to or greater than the thickness T24 of the first wall portion 351. The thickness T24 of the first wall portion 351 may be the thickness of the thinnest wall portion among the plurality of first wall portions 351. The average value of the thicknesses of the plurality of first wall portions 351 may be used as the thickness T24 of the first wall portion 351. The thickness T24 of the first wall portion 351 may be the thickness of the thinnest portion of one of the first wall portions 351. The thickness T23 of the first insulating layer 341 may be equal to or greater than 3 μm and equal to or less than 5 μm.

[0114] The width W22 of the multiple first grooves 345A may be the distance in the X-axis direction between the first insulating layers 341 covering the pair of side surfaces 332A of the first trench 330A. The width W22 of the first grooves 345A may be 4 μm or more and 10 μm or less. The depth of the first grooves 345A may be the distance in the Z-axis direction from the bottom surface of the first grooves 345A to the first surface 343S of the surface insulating layer 343. The depth of the first grooves 345A may be 30 μm or more and 50 μm or less.

[0115] The multiple electrode portions 60 are arranged in the multiple first groove portions 345A. The width W22 of the multiple first groove portions 345A may be referred to as the width of the electrode portion 60. The length of the electrode portion 60 in the Z-axis direction may be the distance in the Z-axis direction from the bottom surface of the first groove portion 345A to the first surface 42S of the surface insulating layer 42. The length of the electrode portion 60 in the Z-axis direction may be 30 μm or more and 50 μm or less.

[0116] The width W31 of the second trench 330B may be the distance between two second wall portions 352 adjacent to each other in the X-axis direction. The width W31 of the second trench 330B may be 10 μm or more and 20 μm or less. The width W31 of the second trench 330B may be the length of the bottom surface 333B in the X-axis direction. The depth D32 of the second trench 330B may be the distance in the Z-axis direction from the second surface 320R of the semiconductor substrate 320 to the bottom surface 333B of the second trench 330B. The depth D32 of the second trench 330B may be shorter than the distance T32 in the Z-axis direction between the bottom surface 333B of the second trench 330B and the second surface 320R of the semiconductor substrate 320. The depth D32 of the second trench 330B may be 30 μm or more and 50 μm or less. A distance T32 in the Z-axis direction from the bottom surface 333B of the second trench 330B to the second surface 320R of the semiconductor substrate 320 may be 50 μm or more and 100 μm or less.

[0117] The thickness T33 of the second insulating layer 342 may be equal to or greater than the thickness T34 of the second wall portion 352. The thickness T34 of the second wall portion 352 may be the thickness of the thinnest second wall portion 352 among the plurality of second wall portions 352. The average value of the thicknesses of the plurality of second wall portions 352 may be used as the thickness T34 of the second wall portion 352. The thickness T34 of the second wall portion 352 may be the thickness of the thinnest portion of one second wall portion 352. The thickness T33 of the second insulating layer 342 may be equal to or greater than 3 μm and equal to or less than 5 μm.

[0118] The width W32 of the multiple second grooves 345B may be the distance between the first insulating layers 341 covering the pair of side surfaces 332A of the first trench 330A in the X-axis direction. The width W32 of the second grooves 345B may be 4 μm or more and 10 μm or less. The depth of the second grooves 345B may be the distance in the Z-axis direction from the bottom surface of the second grooves 345B to the first surface 343S of the surface insulating layer 343. The depth of the second grooves 345B may be 30 μm or more and 50 μm or less.

[0119] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 310 of the second embodiment shown in FIGS. 27 to 34 will be described.

[0120] 35 to 48 are schematic cross-sectional views showing exemplary manufacturing steps of the semiconductor device 310. Figures 35 to 48 correspond to the cross-sectional structure of the semiconductor device 310 shown in Figure 30. For ease of understanding, in Figures 35 to 48, components that are the same as the final components of the semiconductor device 310 are denoted by the same reference numerals as in Figure 30.

[0121] 35, the method for manufacturing the semiconductor device 310 includes preparing a semiconductor substrate 820. The semiconductor substrate 820 may be, for example, a silicon wafer containing impurities of a first conductivity type. By using a silicon wafer, multiple semiconductor devices 310 can be manufactured simultaneously. The semiconductor substrate 820 includes a first surface 820S and a second surface 820R opposite to the first surface 820S.

[0122] 36, the manufacturing method of the semiconductor device 310 includes forming a mask 821 including a plurality of openings 822. The plurality of openings 822 may include a plurality of first openings 822A provided corresponding to the positions of the plurality of first trenches 330A and a plurality of second openings 822B provided corresponding to the positions of the plurality of second trenches 330B. The mask 821 is formed, for example, from a photosensitive resin. The mask 821 is formed, for example, by patterning a sheet-like resist material attached to the semiconductor substrate 820, for example, by photolithography.

[0123] 37, the method for manufacturing the semiconductor device 310 includes forming a plurality of first trenches 330A and a plurality of second trenches 330B. The plurality of first trenches 330A and the plurality of second trenches 330B are formed by, for example, dry etching the semiconductor substrate 820 through openings 822 of a mask 821 shown in FIG. 36. After the plurality of first trenches 330A and the plurality of second trenches 330B are formed, the mask 821 of FIG. 36 is removed.

[0124] 38, the method for manufacturing the semiconductor device 310 includes forming an insulating layer 340. The insulating layer 340 includes a first insulating layer 341 in the first trench 330A, a second insulating layer 342 in the second trench 330B, and a surface insulating layer 343 covering the first surface 820S of the semiconductor substrate 820. The insulating layer 340 is formed by thermally oxidizing the semiconductor substrate 820. The insulating layer 340 may be formed by, for example, a CVD method so as to cover the first surface 820S of the semiconductor substrate 820, the inner surfaces of the plurality of first trenches 330A, and the inner surfaces of the plurality of second trenches 330B.

[0125] 39 to 41 , the method for manufacturing the semiconductor device 310 includes forming a buried electrode portion 860. The buried electrode portion 860 may include an electrode portion 60 in the first trench 330A and an electrode portion 60B in the second trench 330B. The method for forming the buried electrode portion 860 may include forming a seed layer 824, forming a first metal layer 825, and forming the buried electrode portion 860.

[0126] 39, a seed layer 824 is formed. The seed layer 824 may be made of the material of the buried electrode portion 860. In one example, the seed layer 824 may be made of a material containing Cu. The seed layer 824 may be a layer used to form the buried electrode portion 860. The seed layer 824 is formed on the surface of the insulating layer 340 by, for example, sputtering.

[0127] As shown in Fig. 40, a first metal layer 825 is formed. The first metal layer 825 is made of the material of the electrode portion 60 shown in Fig. 30 and Fig. 31. The first metal layer 825 is formed by electrolytic plating using a seed layer 824.

[0128] As shown in Fig. 41, the buried electrode portion 860 is formed by removing the portion of the first metal layer 825 shown in Fig. 11 that protrudes above the surface insulating layer 343, for example, by the CMP method.

[0129] 42 to 44, a method for manufacturing a semiconductor device includes forming a first conductive layer 70. The first conductive layer 70 may include forming a second metal layer 826 shown in FIG. 42 and partially removing the second metal layer 826.

[0130] As shown in FIG. 42, a second metal layer 826 is formed. The second metal layer 826 is made of the material of the first conductive layer 70 shown in FIGS. 1 to 5. In one example, the second metal layer 826 is made of a material containing Al. The second metal layer 826 is formed by, for example, sputtering, so as to cover the surface 60S of the embedded electrode portion 860 and the first surface 343S of the surface insulating layer 343.

[0131] As shown in FIG. 43, a mask 827 is formed to partially cover the second metal layer 826. The mask 827 is provided to correspond to the first conductive layer 70 shown in FIGS. 27 to 34. The mask 827 is formed so as to cover the portion of the second metal layer 826 that will become the first conductive layer 70 in plan view. The mask 827 is formed of, for example, a photosensitive resin. The mask 827 is formed by patterning, for example, a seed-shaped resist material by, for example, photolithography.

[0132] 44, the second metal layer 826 is partially removed to form the first conductive layer 70. The first conductive layer 70 is formed by removing the second metal layer 826 exposed from the mask 827 shown in FIG. 43 by, for example, dry etching. After the first conductive layer 70 is formed, the mask 827 shown in FIG. 43 is removed.

[0133] 45, the method for manufacturing a semiconductor device includes removing the electrode portion 60B in the second trench 330B. The removal of the electrode portion 60B includes forming a mask 828 that covers the first conductive layer 70, and removing the electrode portion 60B in the second trench 330B.

[0134] 45, a mask 828 is formed to cover the first conductive layer 70. The mask 828 is made of, for example, a photosensitive resin. The mask 828 is formed by, for example, patterning a sheet-like resist material attached to the semiconductor substrate 820 by, for example, photolithography.

[0135] 46, the electrode portion 60B in the second trench 330B is removed. The electrode portion 60B can be removed by, for example, wet etching. 47, the method for manufacturing the semiconductor device 310 includes forming a semiconductor substrate 320. The semiconductor substrate 320 is formed by thinning the semiconductor substrate 820 shown in FIG. 46 to the thickness indicated by the dashed line. The thinning of the semiconductor substrate 820 is performed, for example, by grinding the semiconductor substrate 820 from the second surface 320R of the semiconductor substrate 820. The thinning of the semiconductor substrate 820 may be performed by etching, or by grinding and etching.

[0136] 48, the method for manufacturing the semiconductor device 310 includes forming the second conductive layer 80. The second conductive layer 80 is formed by sputtering, for example, so as to cover the second surface 320R of the semiconductor substrate 320. Through the above steps, the semiconductor device 310 is manufactured.

[0137] (Operation of the second embodiment) The semiconductor device 310 includes a semiconductor substrate 320, a plurality of first trenches 330A, a second trench 330B, a first insulating layer 341, and an electrode portion 60. The semiconductor substrate 320 includes a first surface 320S and a second surface 320R opposite the first surface 320S. The first surface 320S of the semiconductor substrate 320 includes a first region 320A and a second region 320B surrounding the first region 320A. The plurality of first trenches 330A are disposed in the first region 320A. The first trenches 330A are recessed from the first surface 320S of the semiconductor substrate 320, extend in the Y-axis direction in a plan view, and are arranged in the X-axis direction in a plan view. The second trenches 330B are disposed in the second region 320B. The first insulating layer 341 is disposed on inner surfaces 331A of the plurality of first trenches 330A. The plurality of electrode portions 60 are conductive and provided in the plurality of first trenches 330A while being surrounded by corresponding first insulating layers 341. The semiconductor substrate 320 is disposed between the plurality of first trenches 330A and includes a plurality of first wall portions 351 that partition the plurality of first trenches 330A. The first wall portions 351 and the electrode portions 60 face each other with the first insulating layer 341 interposed therebetween, thereby constituting a capacitor C2. The second trench 330B is disposed between the capacitor C2 and an end 320SE of the first surface 320S.

[0138] The semiconductor device 310 has unevenness between the first conductive layer 70 and the end 320SE of the first surface 320S of the semiconductor substrate 320 due to the second trench 330B. The second trench 330B increases the creepage distance in the X-axis direction between the first conductive layer 70 and the end of the first surface 320S of the semiconductor substrate 320, i.e., the insulation distance between the first conductive layer 70 and the semiconductor substrate 320. This makes it possible to suppress the occurrence of creepage discharge in the region between the first conductive layer 70 and the semiconductor substrate 320. As a result, the breakdown voltage of the semiconductor device 310 can be improved.

[0139] (Effects of the second embodiment) As described above, the semiconductor device 310 of the second embodiment provides the following advantages.

[0140] (2-1) The semiconductor device 310 has the same effects as the semiconductor device 10 of the first embodiment. (2-2) The semiconductor device 310 includes a semiconductor substrate 320, a plurality of first trenches 330A, a second trench 330B, a first insulating layer 341, and an electrode portion 60. The semiconductor substrate 320 includes a first surface 320S and a second surface 320R opposite the first surface 320S. The first surface 320S of the semiconductor substrate 320 includes a first region 320A and a second region 320B surrounding the first region 320A. The plurality of first trenches 330A are arranged in the first region 320A. The second trench 330B is arranged in the second region 320B. The second trench 330B is arranged between a capacitor C2 formed by a first wall portion 351 and the electrode portion 60 facing each other across the first insulating layer 341, and an end portion 320SE of the first surface 320S.

[0141] The semiconductor device 310 has unevenness between the first conductive layer 70 and the end 320SE of the first surface 320S of the semiconductor substrate 320 due to the second trench 330B. The second trench 330B increases the creepage distance in the X-axis direction between the first conductive layer 70 and the end of the first surface 320S of the semiconductor substrate 320, i.e., the insulation distance between the first conductive layer 70 and the semiconductor substrate 320. This makes it possible to suppress the occurrence of creepage discharge in the region between the first conductive layer 70 and the semiconductor substrate 320. As a result, the breakdown voltage of the semiconductor device 310 can be improved.

[0142] (Modification of the second embodiment) The second embodiment can be modified, for example, as follows. The second embodiment and each of the modified examples can be combined with each other as long as no technical contradiction occurs. In the modified examples, parts common to the second embodiment are assigned the same reference numerals as in the second embodiment, and their description will be omitted.

[0143] 49, a modified semiconductor device 310A may include a passivation layer 390. The passivation layer 390 may be made of a material including at least one of SiO, SiN, SiON, and AlO, for example.

[0144] The passivation layer 390 covers the surface insulating layer 343 and the first conductive layer 70. The passivation layer 390 may extend into the second groove portion 345B formed by the second trench 330B and the second insulating layer 342.

[0145] The passivation layer 390 includes an opening 390X that exposes a portion of the first conductive layer 70. In one example, the opening 390X in the passivation layer 390 exposes a portion of the first surface 70S of the first conductive layer 70 that is more inward than the peripheral portion. The passivation layer 390 includes a first portion 391 that covers the surface insulating layer 343, a second portion 392 that covers the side surfaces 71 to 74 of the first conductive layer 70, and a third portion 393 that covers the peripheral portion of the first surface 70S of the first conductive layer 70. The passivation layer 390 may include a fourth portion 395 that is disposed in the second trench 330B. The fourth portion 395 is filled in the second groove portion 345B. The fourth portion 395 may be an example of an insulating material surrounded by the second insulating layer 342. The passivation layer 390 may include only a first portion 391 that covers the surface insulating layer 343. Alternatively, the passivation layer 390 may include the first portion 391 that covers the surface insulating layer 343, and a second portion 392 that covers the side surfaces 71 to 74 of the first conductive layer 70.

[0146] The first portion 391 of the passivation layer 390 covers the surface insulating layer 343, thereby ensuring the creepage distance between the first conductive layer 70 and the semiconductor substrate 320. The first portion 391 of the passivation layer 390 also protects the surface insulating layer 343. The second portion 392 of the passivation layer 390 covers the side surfaces 71 to 74 of the first conductive layer 70, thereby increasing the creepage distance between the first conductive layer 70 and the semiconductor substrate 320. The third portion 393 of the passivation layer 390 covers the peripheral portion of the first surface 70S of the first conductive layer 70, thereby further increasing the creepage distance between the first conductive layer 70 and the semiconductor substrate 320. The second portion 392 and the third portion 393 of the passivation layer 390 also protect the peripheral portion of the first conductive layer 70.

[0147] As shown in FIG. 50, a modified semiconductor device 310B may include an insulating material 390B embedded in the second groove portion 345B. The modified semiconductor device 310B may include a passivation layer 390A covering the surface insulating layer 343, the insulating material 390B, and the first conductive layer 70. The passivation layer 390A may be made of a material containing at least one of SiO2, SiN, SiON, and Al2O3. The insulating material 390B may be made of the same material as the passivation layer 390A or may be made of a different material from the passivation layer 390A. The insulating material 390B may be made of a resin material such as polyimide resin or epoxy resin.

[0148] 51, a modified semiconductor device 310C may include an annular second trench 330C. Also, the modified semiconductor device 310C may include an annular second groove portion 345C disposed in the annular second trench 330C.

[0149] As shown in FIG. 52, a semiconductor device 310D according to a modified example may include a plurality of second trenches 330D. The plurality of second trenches 330D includes a plurality of first peripheral trenches 330DA and a plurality of second peripheral trenches 330DB. The plurality of first peripheral trenches 330DA may have different lengths. The plurality of first peripheral trenches 330DA may be configured so that their lengths in the Y-axis direction increase from the first region 320A in which the plurality of first trenches 330A are arranged toward the end 320SE of the first surface 320S of the semiconductor substrate 320. The plurality of second peripheral trenches 330DB may have different lengths. The plurality of second peripheral trenches 330DB may be configured so that their lengths in the X-axis direction increase from the first region 320A in which the plurality of first trenches 330A are arranged toward the end 320SE of the first surface 320S of the semiconductor substrate 320.

[0150] As shown in FIG. 53, a semiconductor device 310E of a modified example may include a plurality of second trenches 330B spaced apart from a plurality of first trenches 330A. The plurality of second trenches 330B includes a plurality of first peripheral trenches 330BA and a plurality of second peripheral trenches 330BB. The plurality of first peripheral trenches 330BA are arranged on both sides of the plurality of first trenches 330A in the X-axis direction. The distance between the first trenches 330A and the first peripheral trenches 330BA may be greater than the spacing between the plurality of first trenches 330A in the X-axis direction. The spacing between the plurality of first peripheral trenches 330BA in the X-axis direction may be equal to the spacing between the plurality of first trenches 330A in the X-axis direction. The spacing between the plurality of first peripheral trenches 330BA may be different from the spacing between the plurality of first trenches 330A.

[0151] The second peripheral trenches 330BB are arranged on both sides of the first trenches 330A in the Y-axis direction. The distance between the first trenches 330A and the second peripheral trenches 330BB may be greater than the spacing between the first trenches 330A in the X-axis direction. The spacing between the second peripheral trenches 330BB in the Y-axis direction may be equal to the spacing between the first trenches 330A in the X-axis direction. The spacing between the second peripheral trenches 330BB in the Y-axis direction may be different from the spacing between the first trenches 330A in the X-axis direction.

[0152] As shown in FIG. 54, a semiconductor device 310F of a modified example may include a first conductive layer 270 made up of a plurality of metal layers, instead of the first conductive layer 70 of the second embodiment. The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0153] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0154] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0155] (Appendix A1) a semiconductor substrate (20) including a first surface (20S) and a second surface (20R) opposite to the first surface (20S); a plurality of trenches (30) recessed from the first surface (20S) toward the second surface (20R), extending in a first direction as viewed from the thickness direction (Z) of the semiconductor substrate (20), and arranged in a second direction (X) perpendicular to the first direction (Y) as viewed from the thickness direction (Z); an insulating layer (41) disposed on the inner surface of each of the plurality of trenches (30); a plurality of conductive electrode portions (60) provided in the plurality of trenches (30) and surrounded by the corresponding insulating layers (41); Including, The semiconductor substrate (20) includes a plurality of wall portions (50) disposed between the plurality of trenches (30) and dividing the plurality of trenches (30); The wall portion (50) and the electrode portion (60) face each other with the insulating layer (41) interposed therebetween to form a capacitor (C1), The thickness (T13) of the insulating layer (41) is equal to or greater than the thickness (T14) of the wall portion (50). Semiconductor device.

[0156] (Appendix A2) The plurality of trenches (30) extend in the first direction (Y) as a longitudinal direction and in the second direction (X) as a width direction. The semiconductor device according to Appendix A1.

[0157] (Appendix A3) The widths of the trenches (30) are the same. The semiconductor device according to Appendix A1 or Appendix A2.

[0158] (Appendix A4) The thickness of the walls (50) is the same. A semiconductor device according to any one of Appendix A1 to Appendix A3.

[0159] (Appendix A5) The thickness of the wall portion (50) is narrower than the width of the plurality of trenches (30). A semiconductor device according to any one of Appendix A1 to Appendix A4.

[0160] (Appendix A6) The depth (D12) of the plurality of trenches (30) is shorter than the distance (T12) between the bottom surface of the plurality of trenches (30) and the second surface (20R); A semiconductor device according to any one of Appendix A1 to Appendix A5.

[0161] (Appendix A7) The length (L30) of the plurality of trenches (30) is longer than the depth (D12) of the plurality of trenches (30); A semiconductor device according to any one of Appendix A1 to Appendix A6.

[0162] (Appendix A8) a first conductive layer (70, 270) provided on the first surface (20S); The first conductive layer (70, 270) covers the plurality of electrode portions (60) and electrically connects the plurality of electrode portions (60). A semiconductor device according to any one of Appendix A1 to Appendix A7.

[0163] (Appendix A9) The first conductive layer (70, 270) covers the entire area including the plurality of trenches (30) when viewed from the thickness direction (Z). The semiconductor device according to Appendix A8.

[0164] (Appendix A10) The first conductive layer (70) is made of a material different from that of the electrode portion (60). The semiconductor device according to Appendix A8 or Appendix A9.

[0165] (Appendix A11) The electrode portion (60) and the first conductive layer (70) are made of a material containing Al. The semiconductor device according to any one of Appendix A8 to Appendix A10.

[0166] (Appendix A12) The first conductive layer (70) is made of the same material as the electrode portion (60). The semiconductor device according to any one of Appendix A8 to Appendix A11.

[0167] (Appendix A13) The electrode portion (60) is made of a material containing Cu, and the first conductive layer (70) is made of a material containing Al. The semiconductor device according to any one of Appendix A8 to Appendix A12.

[0168] (Appendix A14) The first conductive layer (270) a sputtered layer (271); a plating layer (272) disposed on the sputtered layer (271); Including, The semiconductor device according to any one of Appendix A8 to Appendix A13.

[0169] (Appendix A15) The plating layer (272) is a first plating layer (281) disposed on the sputtered layer (271) and made of a material containing Cu; a second plating layer (282) disposed on the first plating layer (281) and made of a material containing Ni; Including, The semiconductor device according to Appendix A14.

[0170] (Appendix A16) The plating layer (272) includes a third plating layer (283) disposed on the second plating layer (282) and made of a material containing Pd or Au. The semiconductor device according to Appendix A15.

[0171] (Appendix A17) a surface insulating layer (42) that insulates the first conductive layer (70, 270) from the semiconductor substrate (20); The semiconductor device according to any one of Appendix A8 to Appendix A16.

[0172] (Appendix A18) The end face of the first conductive layer (70, 270) is spaced apart from the side face of the semiconductor substrate (20), and the surface insulating layer (42) is exposed at the periphery of the first face (20S). The semiconductor device according to Appendix A17.

[0173] (Appendix A19) a passivation layer (90) covering the surface insulating layer (42); The semiconductor device according to Appendix A17 or Appendix A18.

[0174] (Appendix A20) the passivation layer (90) covers the first conductive layer (70, 270) and includes an opening (90A) exposing a portion of the first conductive layer (70, 270); The semiconductor device according to Appendix A19.

[0175] (Appendix A21) a second conductive layer (80) disposed on the second surface (20R) of the semiconductor substrate (20); A semiconductor device according to any one of appendices A1 to A20.

[0176] (Appendix A22) forming a plurality of trenches (30) in a semiconductor substrate (20) including a first surface (20S), recessed from the first surface (20S), extending in a first direction (Y) when viewed in a thickness direction (Z) of the semiconductor substrate (20), and aligned in a second direction (X) perpendicular to the first direction (Y) when viewed in the thickness direction (Z); forming an insulating layer (41) on the inner surface of each of the plurality of trenches (30); forming a plurality of conductive electrode portions (60) surrounded by the corresponding insulating layers (41) in the plurality of trenches (30); Including, The semiconductor substrate (20) includes a plurality of wall portions (50) disposed between the plurality of trenches (30) and dividing the plurality of trenches (30); The wall portion (50) and the electrode portion (60) face each other with the insulating layer (41) interposed therebetween to form a capacitor (C1), The thickness of the insulating layer (41) is equal to or greater than the thickness of the wall portion (50). A method for manufacturing a semiconductor device.

[0177] (Appendix A23) The formation of the plurality of electrode portions (60) is forming a seed layer covering the insulating layer (41); forming a first metal layer over the seed layer; removing the first metal layer that protrudes above the upper surface of the insulating layer (41) to form the plurality of electrode portions (60) surrounded by the insulating layer (41); A method for manufacturing a semiconductor device according to Appendix A22, comprising:

[0178] (Appendix A24) forming a surface insulating layer (42) covering the first surface (20S) of the semiconductor substrate (20); forming a first conductive layer (70, 270) on the first surface (20S) of the semiconductor substrate (20) to cover the plurality of electrode portions (60) and electrically connect the plurality of electrode portions (60); Including, The first conductive layer (70, 270) is insulated from the first conductive layer (70, 270) by the surface insulating layer (42). A method for manufacturing a semiconductor device according to Appendix A22 or Appendix A23.

[0179] (Appendix A25) The surface insulating layer (42) is an integral part formed simultaneously with the insulating layer (41). A method for manufacturing a semiconductor device according to Appendix A24.

[0180] (Appendix B1) a semiconductor substrate (320) including a first surface (320S) and a second surface (320R) opposite to the first surface (320S), the first surface (320S) including a first region and a second region (320B) surrounding the first region (320A); a plurality of first trenches (330A) disposed in the first region (320A), recessed from the first surface (320S), extending in a first direction (Y) when viewed from the thickness direction (Z) of the semiconductor substrate (320), and arranged in a second direction (X) perpendicular to the first direction (Y) when viewed from the thickness direction (Z); a second trench (330B) disposed in the second region (320B); a first insulating layer (341) disposed on the inner surfaces of the plurality of first trenches (330A); a plurality of conductive electrode portions (60) provided in the plurality of first trenches (330A) and surrounded by the corresponding first insulating layers (341); Including, the semiconductor substrate (320) includes a plurality of first wall portions (351) disposed between the plurality of first trenches (330A) and partitioning the plurality of first trenches (330A); The first wall portion (351) and the electrode portion (60) face each other with the first insulating layer (341) interposed therebetween to form a capacitor (C2), the second trench (330B) is disposed between the capacitor (C2) and an end (320SE) of the first surface (320S); Semiconductor device.

[0181] (Appendix B2) The second trenches (330B) are arranged on both sides of the plurality of first trenches (330A) in the first direction (Y) and extend in the second direction (X). 10. The semiconductor device according to claim 8, wherein the semiconductor device is a semiconductor device according to claim 9.

[0182] (Appendix B3) The second trenches (330B) are arranged in a plurality of locations spaced apart from one another in the first direction (Y). The semiconductor device according to Appendix B1 or Appendix B2.

[0183] (Appendix B4) The second trenches (330B) are arranged on both sides of the plurality of first trenches (330A) in the second direction (X) and extend in the first direction (Y). The semiconductor device according to any one of Appendix B1 to Appendix B3.

[0184] (Appendix B5) The second trenches (330B) are arranged in a plurality of locations spaced apart from one another in the second direction (X). A semiconductor device according to any one of Appendix B1 to Appendix B4.

[0185] (Appendix B6) a second insulating layer (342) disposed on the inner surface of the second trench (330B); A semiconductor device according to any one of Appendix B1 to Appendix B5.

[0186] (Appendix B7) An insulating material (395, 390B) surrounded by the second insulating layer (342) is disposed in the second trench (330B). The semiconductor device according to Appendix B6.

[0187] (Appendix B8) The width of the first trench (330A) and the width of the second trench (330B) are the same. A semiconductor device according to any one of Appendix B1 to Appendix B7.

[0188] (Appendix B9) The depth of the first trench (330A) and the depth of the second trench (330B) are the same. A semiconductor device according to any one of Appendix B1 to Appendix B8.

[0189] (Appendix B10) The plurality of first trenches (330A) extend in the first direction (Y) as a longitudinal direction and in the second direction (X) as a width direction. A semiconductor device according to any one of Appendix B1 to Appendix B9.

[0190] (Appendix B11) The widths of the plurality of first trenches (330A) are the same. The semiconductor device according to any one of Appendix B1 to Appendix B10.

[0191] (Appendix B12) The thickness of the plurality of first walls (351) is the same. The semiconductor device according to any one of Appendix B1 to Appendix B11.

[0192] (Appendix B13) The thickness of the first wall portion (351) is narrower than the width of the plurality of first trenches (330A), The semiconductor device according to any one of Appendix B1 to Appendix B12.

[0193] (Appendix B14) The depth of the plurality of first trenches (330A) is shorter than the distance between the bottom surfaces of the plurality of first trenches (330A) and the second surface (320R); The semiconductor device according to any one of Appendix B1 to Appendix B13.

[0194] (Appendix B15) The length of the plurality of first trenches (330A) is longer than the depth of the plurality of first trenches (330A); The semiconductor device according to any one of Appendix B1 to Appendix B14.

[0195] (Appendix B16) a first conductive layer (70, 270) provided on the first region (320A) and covering the first trench (330A); The second region (320B) is exposed without being covered by the first conductive layer (70, 270). The semiconductor device according to any one of Appendix B1 to Appendix B15.

[0196] (Appendix B17) The first conductive layer (70, 270) covers the plurality of electrode portions (60) and electrically connects the plurality of electrode portions (60). The semiconductor device according to Appendix B16.

[0197] (Appendix B18) the first conductive layer (70, 270) covers the entire first region (320A) including the plurality of first trenches (330A) when viewed from the thickness direction (Z); The semiconductor device according to Appendix B16 or Appendix B17.

[0198] (Appendix B19) The first conductive layer (70) is made of a material different from that of the electrode portion (60). The semiconductor device according to any one of Appendix B16 to Appendix B18.

[0199] (Appendix B20) The electrode portion (60) and the first conductive layer (70) are made of a material containing Al. The semiconductor device according to any one of Appendix B16 to Appendix B19.

[0200] (Appendix B21) The first conductive layer (70) is made of the same material as the electrode portion (60). The semiconductor device according to any one of Appendix B16 to Appendix B20.

[0201] (Appendix B22) The electrode portion (60) is made of a material containing Cu, and the first conductive layer (70) is made of a material containing Al. The semiconductor device according to any one of Appendix B16 to Appendix B21.

[0202] (Appendix B23) The first conductive layer (270) a sputtered layer; a plating layer disposed on the sputtered layer; Including, The semiconductor device according to any one of appendices B16 to B22.

[0203] (Appendix B24) The plating layer is a first plating layer disposed on the sputtered layer and made of a material containing Cu; a second plating layer disposed on the first plating layer and made of a material containing Ni; Including, The semiconductor device according to Appendix B23.

[0204] (Appendix B25) The plating layer includes a third plating layer disposed on the second plating layer and made of a material containing Pd or Au. The semiconductor device according to Appendix B24.

[0205] (Appendix B26) a surface insulating layer (343) that insulates the first conductive layer (70, 270) from the semiconductor substrate (320); A semiconductor device according to any one of appendices B16 to B25.

[0206] (Appendix B27) a passivation layer (390) covering the surface insulating layer (343); The semiconductor device according to Appendix B26.

[0207] (Appendix B28) the passivation layer (390) covers the first conductive layer (70, 270) and includes an opening (390X) exposing a portion of the first conductive layer (70, 270); The semiconductor device according to Appendix B27.

[0208] (Appendix B29) the passivation layer (390) includes a portion (395) embedded in the second trench (330B); The semiconductor device according to Appendix B27 or Appendix B28.

[0209] (Appendix B30) An insulating material (390B) is buried in the second trench (330B), The passivation layer (390) covers the insulating material (390B). The semiconductor device according to Appendix B27 or Appendix B28.

[0210] (Appendix B31) a second conductive layer (80) disposed on the second surface (320R) of the semiconductor substrate (320); The semiconductor device according to any one of Appendix B1 to Appendix B30.

[0211] (Appendix B32) forming a plurality of first trenches (330A) in a first region (320A) of a first surface (320S) of a semiconductor substrate (320), and forming a second trench (330B) in a second region (320B) surrounding the first region (320A); forming a first insulating layer (341) on the inner surfaces of the plurality of first trenches (330A); forming a plurality of electrode portions (60) surrounded by the corresponding first insulating layers (341) in the plurality of first trenches (330A); Including, the plurality of first trenches (330A) are recessed from the first surface (320S), extend in a first direction (Y) when viewed from a thickness direction (Z) of the semiconductor substrate (320), and are arranged in a second direction (X) perpendicular to the first direction (Y) when viewed from the thickness direction (Z); the semiconductor substrate (320) includes a plurality of first wall portions (351) disposed between the plurality of first trenches (330A) and partitioning the plurality of first trenches (330A); The first wall portion (351) and the electrode portion (60) face each other with the first insulating layer (341) interposed therebetween to form a capacitor (C2), The second trench (330B) is disposed between the capacitor (C2) and an edge (320SE) of the semiconductor substrate (320). A method for manufacturing a semiconductor device.

[0212] (Appendix B33) The formation of the plurality of electrode portions (60) is forming a seed layer (824) covering the first insulating layer (341); forming a first metal layer (825) on the seed layer (824); removing the seed layer (824) and the first metal layer that protrude above the upper surface of the first insulating layer (341) to form the plurality of electrode portions (60) surrounded by the first insulating layer (341); A method for manufacturing a semiconductor device according to Appendix B32, comprising:

[0213] (Appendix B34) forming a second insulating layer (342) on the inner surface of the second trench (330B); The seed layer (824) is formed to cover the second insulating layer (342), removing the seed layer (824) and the first metal layer (825) that protrude above the upper surface of the first insulating layer to form a plurality of electrode portions (60B) surrounded by the second insulating layer (342); removing the plurality of electrode portions (60B) in the second trench (330B); A method for manufacturing a semiconductor device according to Appendix B33.

[0214] (Appendix B35) forming the plurality of electrode portions (60) in the first trench (330A) and the plurality of electrode portions (60B) in the second trench (330B), and then forming a first conductive layer (70) that covers the plurality of electrode portions (60) in the first trench (330A); After forming the first conductive layer (70), the plurality of electrode portions (60B) in the second trench (330B) are removed. A method for manufacturing a semiconductor device according to Appendix B34.

[0215] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0216] 10, 10A, 10B Semiconductor device 20 Semiconductor substrate 20S 1st page 20R, Side 2 21~24 Side 30 Trench 31 Inner 32 Side 33 bottom 40 insulating layer 41 Insulating layer 42 Surface insulating layer 42A Part 1 42B 2nd part 42S 1st page 42R 2nd side 44 Insulation Area 45 Groove 50 Wall 60 Electrode section 60B Electrode part 60S surface 70 First conductive layer 70R 2nd side 70S 1st page 71~74 Side 80 Second conductive layer 90 Passivation Layer 90A aperture 91 Part 1 92 Part 2 93 Part 3 270 First conductive layer 271 1st metal layer 272 2nd metal layer 281 First plating layer 282 Second plating layer 283 Third plating layer 310, 310A to 310F Semiconductor device 320 Semiconductor Substrate 320A 1st area 320B 2nd area 320S 1st page 320SE end 320R 2nd side 321~324 Side 330A First Trench 330B~330D Second Trench 330BA, 330DA First Peripheral Trench 330BB, 330DB Second peripheral trench 331A, 331B inner surface 332A, 332B side 333A, 333B bottom 340 Insulating Layer 341 First insulating layer 342 Second insulating layer 343 Surface Insulation Layer 343A 1st opening 343B 2nd opening 343S 1st page 343R 2nd side 344 Insulation Area 345A 1st groove 345B, 345C 2nd groove 351 1st wall section 352 2nd wall section 390, 390A passivation layer 390B Insulation 800 semiconductor substrates 800S Page 1 800R 2nd side 804 seed layer 805 1st metal layer 806 2nd metal layer 810 seed layer 820 Semiconductor substrate 820S Page 1 820R 2nd page 824 seed layer 825 1st metal layer 826 2nd metal layer C1, C2 capacitors D12, D22, D32 depth T11, T13, T14 thickness T12 Distance T21, T23, T24 thickness T22 Distance T32 distance T33, T34 thickness W11, W12 width W21, W22 width W31, W32 width

Claims

1. a semiconductor substrate including a first surface and a second surface opposite the first surface; a plurality of trenches recessed from the first surface toward the second surface, extending in a first direction as viewed in a thickness direction of the semiconductor substrate, and arranged in a second direction perpendicular to the first direction as viewed in the thickness direction; an insulating layer disposed on an inner surface of each of the plurality of trenches; a plurality of conductive electrode portions provided in the plurality of trenches and surrounded by the corresponding insulating layers; Including, the semiconductor substrate includes a plurality of wall portions disposed between the plurality of trenches and partitioning the plurality of trenches; a capacitor is formed by the wall portion and the electrode portion facing each other with the insulating layer interposed therebetween, The thickness of the insulating layer is equal to or greater than the thickness of the wall portion. Semiconductor device.

2. The plurality of trenches extend such that the first direction is a longitudinal direction and the second direction is a width direction. The semiconductor device according to claim 1 .

3. The widths of the trenches are the same. The semiconductor device according to claim 1 .

4. The thickness of the walls is the same. The semiconductor device according to claim 1 .

5. the thickness of the wall portion is narrower than the width of the plurality of trenches; The semiconductor device according to claim 1 .

6. The depth of the plurality of trenches is shorter than the distance between the bottom surfaces of the plurality of trenches and the second surface. The semiconductor device according to claim 1 .

7. The length of the plurality of trenches is greater than the depth of the plurality of trenches. The semiconductor device according to claim 1 .

8. a first conductive layer disposed on the first surface; the first conductive layer covers the plurality of electrode portions and electrically connects the plurality of electrode portions; The semiconductor device according to claim 1 .

9. the first conductive layer covers an entire region including the plurality of trenches when viewed from the thickness direction; The semiconductor device according to claim 8 .

10. the first conductive layer is made of a material different from that of the electrode portion; The semiconductor device according to claim 8 .

11. the electrode portion and the first conductive layer are made of a material containing Al; The semiconductor device according to claim 8 .

12. the first conductive layer is made of the same material as the electrode portion; The semiconductor device according to claim 8 .

13. the electrode portion is made of a material containing Cu, and the first conductive layer is made of a material containing Al; The semiconductor device according to claim 8 .

14. The first conductive layer is a sputtered layer; a plating layer disposed on the sputtered layer; Including, The semiconductor device according to claim 8 .

15. a surface insulating layer that insulates the first conductive layer from the semiconductor substrate; The semiconductor device according to claim 8 .

16. an end face of the first conductive layer and a side face of the semiconductor substrate are spaced apart, and the surface insulating layer is exposed at a periphery of the first surface; The semiconductor device according to claim 15.

17. a passivation layer covering the surface insulating layer; The semiconductor device according to claim 15.

18. the passivation layer covers the first conductive layer and includes an opening exposing a portion of the first conductive layer; The semiconductor device according to claim 17.

19. a second conductive layer disposed on the second surface of the semiconductor substrate; The semiconductor device according to claim 1 .

20. forming a plurality of trenches in a semiconductor substrate including a first surface, the trenches being recessed from the first surface, extending in a first direction as viewed in a thickness direction of the semiconductor substrate, and aligned in a second direction perpendicular to the first direction as viewed in the thickness direction; forming an insulating layer on an interior surface of each of the plurality of trenches; forming a plurality of conductive electrode portions surrounded by the corresponding insulating layers in the plurality of trenches; Including, the semiconductor substrate includes a plurality of wall portions disposed between the plurality of trenches and partitioning the plurality of trenches; a capacitor is formed by the wall portion and the electrode portion facing each other with the insulating layer interposed therebetween, The thickness of the insulating layer is equal to or greater than the thickness of the wall portion. A method for manufacturing a semiconductor device.

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