Wafer mounting device, semiconductor manufacturing apparatus, method for manufacturing semiconductor apparatus, and semiconductor apparatus

Abstract

To provide a wafer mounting device capable of improving in-plane uniformity of an epitaxial layer formed on a surface of a semiconductor wafer.SOLUTION: A ring 12 is placed on a satellite disk 13 in such a manner that a terrace part 12t is supported by a peripheral portion surface 13d of a peripheral portion 13p of the satellite disk 13. A SiC wafer 14 is placed on three lift-up pins 15 mounted on a surface of the terrace part 12t. A disk upper space S13 is formed between a surface 13s of an upper layer part 13u of the satellite disk 13 and a back surface of the SiC wafer 14. A wall part 12b of the ring 12 is disposed so as to face an orientation flat part 14k with a gap space S12 therebetween. On the back surface side of the SiC wafer 14, an annular groove 2 (groove 2k) is formed along an outer periphery of an opening O12 in plan view, and one side surface of the groove 2 becomes a side surface of the upper layer part 13u.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a wafer mounting device for mounting a semiconductor wafer, such as a susceptor used for epitaxial growth of a SiC film on a SiC single crystal wafer. [Background technology]

[0002] A typical conventional wafer mounting device is a susceptor used for epitaxial growth of a SiC film on a SiC single crystal wafer. A conventional susceptor is disclosed in, for example, Patent Document 1.

[0003] Patent Document 1 is characterized by a technology that sets the step between the upper surface of the susceptor and the upper surface of the silicon wafer to 1 mm or more, and by using a susceptor with this feature, the epi-crown phenomenon described below is suppressed. Furthermore, Patent Document 2 and Patent Document 3 also disclose conventional technologies for suppressing the epi-crown phenomenon.

[0004] As a technology developed from a wafer mounting device typified by a susceptor, a SiC epitaxial growth device, which is a semiconductor manufacturing device equipped with a wafer mounting device, can be considered. Furthermore, a semiconductor device manufacturing method using a SiC epitaxial growth device and a semiconductor device manufactured by the semiconductor device manufacturing method can be considered. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-119472 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-27006 [Patent Document 3] Japanese Patent Application Publication No. 7-226349 Summary of the Invention [Problem to be solved by the invention]

[0006] When forming an epitaxial layer on the surface of a semiconductor wafer such as a silicon wafer, the wafer-susceptor top distance, which indicates the height between the top surface of the susceptor and the surface of the semiconductor wafer, is an indicator related to the thickness of the epitaxial layer. If the wafer-susceptor top distance is set relatively large, it will affect the epitaxial layer thickness, which is the thickness of the epitaxial layer in the peripheral region at the outermost periphery of the semiconductor wafer, and the within-surface uniformity of the epitaxial thickness will deteriorate.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a wafer mounting device that improves the in-plane uniformity of an epitaxial layer formed on the surface of a semiconductor wafer. [Means for solving the problem]

[0008] A wafer mounting device according to the present disclosure is a wafer mounting device for mounting a semiconductor wafer having a cutout portion, and comprises: a disk having a convex upper layer portion; a ring disposed on the disk and having an opening in the center; and a plurality of lift-up members disposed on a lift-up area provided on the disk or the ring for supporting the semiconductor wafer from the backside thereof, the ring having a cutout-side protruding wall portion protruding toward the opening side, and in a semiconductor wafer-mounted state in which the semiconductor wafer is placed on the plurality of lift-up members so that the semiconductor wafer fits within the opening in a planar view without coming into contact with the ring, the cutout-side protruding wall portion faces the cutout portion of the semiconductor wafer, and a space above the disk is formed between the surface of the upper layer portion of the disk and the backside of the semiconductor wafer, excluding the area in which the plurality of lift-up members are formed, and an annular groove is formed between the upper layer portion of the disk on the backside of the semiconductor wafer and the ring along the outer periphery of the opening in a planar view, and the side surface of the upper layer portion of the disk forms the side surface of the annular groove. [Effects of the Invention]

[0009] The wafer loading device of the present disclosure can provide a space above the disk between the rear surface of the semiconductor wafer and the front surface of the disk when the semiconductor wafer is loaded.

[0010] Furthermore, in the wafer mounting device of the present disclosure, when a semiconductor wafer is mounted, an annular groove is formed between the upper layer of the disk and the ring on the back side of the semiconductor wafer, and the side surface of the upper layer of the disk becomes the side surface of the annular groove.

[0011] Therefore, when a source gas is supplied above the front surface of a semiconductor wafer mounted thereon, a portion of the source gas can be intentionally released into the space above the disk on the rear surface side of the semiconductor wafer via the annular groove.

[0012] Therefore, when an epitaxial layer is formed on the surface of a semiconductor wafer by epitaxial growth processing while the semiconductor wafer is mounted, it is possible to suppress the occurrence of the epicrown phenomenon in which the epitaxial thickness, which is the film thickness of the epitaxial growth layer, becomes locally thick.

[0013] As a result, the wafer mounting device of the present disclosure has the effect of being able to form an epitaxial layer with excellent in-plane uniformity of epitaxial thickness on the surface of a semiconductor wafer in a mounted state. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is an explanatory diagram schematically showing a planar configuration of a susceptor which is a basic configuration of the first embodiment. [Figure 2] FIG. 2 is an explanatory diagram schematically illustrating the configuration of the A1-A1 cross section of FIG. [Figure 3] FIG. 2 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line B1-B1 in FIG. [Figure 4] FIG. 2 is an explanatory diagram schematically illustrating the configuration of a cross section taken along C1-C1 in FIG. [Figure 5] FIG. 3 is an explanatory diagram showing an enlarged cross-sectional configuration of FIG. 2. [Figure 6] FIG. 2 is an explanatory diagram schematically showing a planar configuration of a susceptor according to a first modified example of the first embodiment. [Figure 7] FIG. 7 is an explanatory diagram schematically illustrating the configuration of the A11-A11 cross section of FIG. [Figure 8] FIG. 7 is an explanatory diagram schematically illustrating the configuration of a cross section taken along line B11-B11 in FIG. [Figure 9] FIG. 7 is an explanatory diagram schematically illustrating the configuration of a cross section taken along C11-C11 in FIG. 6. [Figure 10] FIG. 10 is an explanatory view schematically showing a planar configuration of a susceptor according to a second modified example of the first embodiment. [Figure 11] 11 is an explanatory diagram schematically showing the configuration of a cross section taken along the line A12-A12 in FIG. 10. [Figure 12] 11 is an explanatory diagram schematically illustrating the configuration of a cross section taken along line B12-B12 in FIG. 10. [Figure 13] 11 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line C12-C12 of FIG. 10. [Figure 14] FIG. 10 is an explanatory diagram schematically showing a planar configuration of a susceptor which is a basic configuration of the second embodiment. [Figure 15] 15 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line A2-A2 in FIG. 14. [Figure 16] 15 is an explanatory diagram schematically illustrating the configuration of a cross section taken along line B2-B2 in FIG. 14. [Figure 17] 15 is an explanatory diagram showing an enlarged view of a region of interest R2 in FIG. 14. [Figure 18] FIG. 11 is an explanatory diagram schematically showing a planar configuration of a susceptor which is a basic configuration of a third embodiment. [Figure 19] 19 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line A3-A3 in FIG. 18. [Figure 20] 19 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line B4-B4 of FIG. 18. [Figure 21] 19 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line C4-C4 of FIG. 18. [Figure 22] FIG. 10 is an explanatory diagram schematically showing a planar configuration of a susceptor which is a basic configuration of a fourth embodiment. [Figure 23] 23 is an explanatory diagram schematically illustrating the configuration of a cross section taken along the line A4-A4 in FIG. 22. FIG. [Figure 24] 23 is an explanatory diagram schematically illustrating the configuration of a cross section taken along line B4-B4 in FIG. 22. [Figure 25] 1 is an explanatory diagram schematically illustrating a cross-sectional structure of a semiconductor manufacturing apparatus including a susceptor used in an embodiment of the present disclosure. [Figure 26] FIG. 1 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor manufacturing apparatus. [Figure 27] 1 is a flowchart showing a processing procedure of a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus. [Figure 28] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor device manufactured by a semiconductor device manufacturing method. [Figure 29] FIG. 1 is an explanatory diagram schematically illustrating the epicrown phenomenon. [Figure 30] FIG. 1 is an explanatory diagram schematically showing a conventional susceptor. [Figure 31] 31 is a graph showing the epi-crown height when an epitaxial layer is grown using the susceptor shown in FIG. 30. [Figure 32] FIG. 2 is a diagram illustrating the relationship between measurement points and reference points on the surface of a SiC wafer. [Figure 33] 10 is a graph showing the correlation of the height of the epitaxial crown at the center of the OF when the wafer-susceptor top distance is changed. [Figure 34] 10 is a graph showing the correlation between the average epitaxial thickness at the wafer periphery and the wafer-susceptor top distance. [Figure 35] This is a graph showing the epitaxial thickness when the wafer-susceptor top distance is 0.7 mm. [Figure 36] This is a graph showing the epitaxial thickness when the wafer-susceptor top distance is 2.5 mm. [Figure 37] FIG. 1 is an explanatory diagram schematically illustrating a planar configuration of a conventional susceptor. [Figure 38] 38 is a graph showing an example of an epi-crown height when an epitaxial layer is formed on the surface of a semiconductor wafer using the susceptor shown in FIG. 37. [Figure 39] FIG. 10 is an explanatory diagram showing the results of a fluid simulation regarding the fluid velocity of a source gas. [Figure 40]10 is a graph showing epi-crown heights based on different SiC wafer mounting methods. [Figure 41] 10 is a graph showing epitaxial thicknesses based on different methods of mounting a SiC wafer. DETAILED DESCRIPTION OF THE INVENTION

[0015] <Basis of this Disclosure> As a basic technology related to the susceptor, which is the wafer loading device of the present disclosure, a conventional example and its problems will be described. In recent years, there has been an increasing demand for single crystal epitaxial wafers made of SiC as a constituent material for use as substrates for high-voltage electronic devices and the like.

[0016] When fabricating power devices using SiC single crystal wafers (hereinafter abbreviated as "SiC wafers"), a SiC single crystal thin film is typically grown on the SiC wafer by thermal chemical vapor deposition (hereinafter referred to as "thermal CVD (Chemical Vapor Deposition) method") to block basal plane dislocations (BPDs) on the SiC wafer and form devices on a layer with a controlled impurity doping concentration. When performing epitaxial growth using the thermal CVD method, the SiC wafer is placed on a susceptor in a device, and while the susceptor is rotating, a silicon source gas, such as silane gas or chlorosilane gas, and a carbon source gas, such as propane or methane, are supplied onto the wafer along with a carrier gas, such as hydrogen, to perform epitaxial growth. The silicon source gas and carbon source gas described above serve as source gases for epitaxial growth.

[0017] To prevent the SiC wafer from shifting during epitaxial growth, a recess (concave) equivalent to the wafer thickness is typically provided in the susceptor, and the SiC wafer is placed there, and the source gases described above are then flowed from the side so that they are approximately parallel to the surface of the SiC wafer.

[0018] For SiC wafers 6 inches or larger, the warping of the SiC wafer becomes significant during epitaxial growth, so the bowl-shaped (concave) counterbore bottom is often used as the wafer mounting surface. Holding the SiC wafer at its periphery prevents contact between the wafer center and the counterbore bottom during film formation, preventing a drop in temperature at the wafer center. This effect improves the in-plane uniformity of film thickness and carrier concentration for the epitaxial layer.

[0019] The uniformity of film thickness and carrier concentration within the wafer is an important indicator of epitaxial growth layers. For example, film thickness unevenness is likely to occur at the outer periphery of a SiC wafer, and the region several millimeters from the outermost periphery of the wafer cannot be used for device fabrication. This unusable region is called edge exclusion or end cut, and if this region can be reduced, the area in which semiconductor chips can be formed can be expanded, improving the yield of semiconductor chips. For this reason, it is preferable to have as little edge exclusion and end cut as possible.

[0020] 29 is an explanatory diagram showing the epi-crown phenomenon. As shown in the figure, N - An epitaxial layer 62 is formed.

[0021] In epitaxial growth in the semiconductor field, as shown in FIG. 29, N is present in the wafer periphery, which is the region near the edge of the surface of the SiC wafer 61w. - As a result of the increased thickness of the epitaxial layer 62, - It is known that an epi-crown 62t, which is higher by an epi-crown height H62 than the surface of other regions of the epitaxial layer 62, occurs. When the epi-crown 62t occurs, it becomes necessary to increase the edge exclusion, and therefore, there is a need to eliminate the epi-crown 62t.

[0022] Several methods have been proposed to eliminate epicrowns. The technology disclosed in Patent Document 3 is a technology that, in conjunction with the growth of epicrowns, makes the film thickness of the outer periphery of a SiC wafer thinner than other regions in advance, so that even if epicrowns occur, the film thickness of the outer periphery of the wafer does not become thicker than other regions.

[0023] The technology disclosed in Patent Document 2 is a technology for removing the formed epi-crown after epitaxial growth, while the technology disclosed in Patent Document 1 is a technology for increasing the wafer-susceptor top distance, which is the step length between the surface of the SiC wafer and the top surface of the susceptor, in order to prevent the source gas from being supplied to the outer periphery of the wafer.

[0024] However, in the method of thinning the outer periphery of the wafer in advance, such as the technology disclosed in Patent Document 3, it is necessary to remove the outer periphery in accordance with the thickness of the epitaxial layer to be formed and the thickness of the epicrown formed at that time, and the wafer with the thinned outer periphery becomes a wafer dedicated to forming an epitaxial layer of a specific thickness.

[0025] In actual production, the specifications of the epitaxial layer required vary depending on the type of device being manufactured, so producing and stocking wafers specifically for specific film formation conditions is undesirable because it significantly reduces production efficiency.

[0026] In the case of removing the epicrown after growing the epitaxial layer, as in the technique disclosed in Patent Document 2, the area around the removed epicrown is polished, which can cause damage during polishing and lead to roughness of the epitaxial layer. Semiconductor devices formed on such polished surfaces are likely to have inferior performance, and the yield of semiconductor chips is not necessarily improved. Furthermore, the methods disclosed in Patent Documents 2 and 3 also have the problem of requiring an additional step for removing the epicrown.

[0027] In contrast, the technology disclosed in Patent Document 1 is superior to Patent Documents 2 and 3 in that it does not require wafer processing. However, further investigation revealed the following drawbacks.

[0028] 30 is an explanatory diagram showing a schematic diagram of a conventional susceptor used in film formation, in which (a) shows the planar configuration of the susceptor, and (b) shows the cross-sectional structure of the susceptor.

[0029] As shown in the figure, a SiC wafer 73 is accommodated in a circular counterbore 72 of a susceptor 71. A source gas G1 is supplied along a source supply direction F1 above the surface of the SiC wafer 73. In this manner, the source gas G1, which serves as a source gas for epitaxial growth, is supplied along a source gas flow F2.

[0030] Here, as shown in FIG. 30(b), the distance between the top surface of the susceptor 71 and the surface of the SiC wafer 73 is the wafer-susceptor top distance DT.

[0031] While the source gas G1 is being supplied, a thermal CVD method is performed in which the SiC wafer 73 is heated by a heating mechanism (not shown) provided in the susceptor 71, thereby forming an epitaxial layer on the surface of the SiC wafer 73.

[0032] Fig. 31 is a graph showing the results of normalizing the epi-crown height (four points on the surface) by the average epitaxial thickness of the wafer when an epitaxial layer is grown on the surface of a 6-inch SiC wafer 73 using the susceptor 71 shown in Fig. 30. Fig. 32 is a schematic diagram illustrating the relationship between measurement points P1 to P4 and reference points B1 to B4 on the surface of the SiC wafer 73.

[0033] The four in-plane points shown in Figure 31 are measurement points P1 to P4 along the outer periphery of the SiC wafer 73. The epi-crown height indicated by the epi-crown height change L1 in Figure 31 indicates the difference between the epi-thickness at the outermost periphery and the epi-thickness at a point approximately 5 mm inward from the edge of the SiC wafer 73. In other words, it indicates the difference in epi-thickness between measurement point Pi (i = any one of 1 to 4) and reference point Bi shown in Figure 32. The distance DP shown in Figure 32 indicates the distance of approximately 5 mm inward from the edge of the SiC wafer 73.

[0034] As shown in Figure 31, the epitaxial crown height reaches its maximum at measurement point P1, where the measurement angle θ is 0° (360°). As can be seen, a high epitaxial crown protrudes from the center of orientation flat 73k at the outer periphery of the surface of SiC wafer 73. Hereinafter, the orientation flat center will sometimes be referred to simply as the "OF center," and the orientation flat will sometimes be referred to simply as the "OF portion."

[0035] The index corresponding to the "difference in level between the top surface of the susceptor and the top surface of the silicon wafer" disclosed in Patent Document 1 is the wafer-susceptor top distance DT shown in FIG.

[0036] Figure 33 is a graph showing the results of investigating the correlation between the epitaxial crown height (normalized by the average epitaxial thickness) at the center of the OF when the wafer-susceptor top distance DT is changed. From the change in epitaxial crown height L2 at the center of the OF shown in Figure 33, it can be seen that as the wafer-susceptor top distance DT is increased, the epitaxial crown at the center of the OF decreases, making the technology disclosed in Patent Document 1 appear to be effective. However, it has been newly discovered that the wafer-susceptor top distance DT is a parameter that not only affects the epitaxial crown, but also influences the epitaxial thickness of the entire wafer periphery.

[0037] 34 is a graph showing the correlation between the average epitaxial thickness at the wafer periphery and the wafer-susceptor top distance DT. The average epitaxial thickness is calculated by normalizing the measurements at seven measurement points P11 to P17, which are located 5 mm from the edge of the SiC wafer 73 and excluding the area close to the OF portion, as shown in FIG. 34, by the average epitaxial thickness of the SiC wafer 73.

[0038] From the average epitaxial thickness change L3 at the wafer periphery shown in FIG. 34, it can be seen that as the wafer-susceptor top distance DT increases, the epitaxial thickness at the periphery of the SiC wafer 73 decreases.

[0039] Figure 35 is a graph showing the epitaxial thickness along the X direction when the wafer-susceptor top distance DT is 0.7 mm. Figure 36 is a graph showing the epitaxial thickness along the X direction when the wafer-susceptor top distance DT is 2.5 mm. The epitaxial thickness is shown as a value normalized by the average epitaxial thickness on the SiC wafer 73.

[0040] In each of Figures 35 and 36, the origin "0" where the X axis and Y axis intersect is the position where the predetermined distance ΔD is "0", and the predetermined distance ΔD on the +X direction side is a positive distance [mm], and the predetermined distance ΔD on the -X direction side is a negative distance [mm].

[0041] It is clear from the epitaxial thickness change L4 shown in Fig. 35 and the epitaxial thickness change L5 shown in Fig. 36 that as the wafer-susceptor top distance DT increases, the epitaxial thickness at the outer periphery of the SiC wafer 73 changes significantly. Furthermore, as can be seen from the epitaxial thickness change L5 shown in Fig. 36, the epitaxial thickness decreases rapidly near the edge of the SiC wafer 73 where the predetermined distance ΔD is approximately ±70 mm.

[0042] Even if the epitaxial crown occurring at the outermost periphery of the SiC wafer 73 can be suppressed, if the epitaxial thickness at the wafer periphery is significantly reduced, the technology disclosed in Patent Document 1 cannot be applied to the semiconductor chip manufacturing process, and this is undesirable because it would result in a decrease in wafer yield in the epitaxial growth process.

[0043] The wafer mounting device (susceptor) of the present disclosure reduces the ineffective area of ​​the wafer by suppressing the epitaxial crown without drastically reducing the epitaxial thickness at the wafer periphery.

[0044] The inventors of the wafer loading device of the present disclosure conducted various studies to investigate the cause of the formation of a high epi-crown in the OF portion and its surrounding area, and discovered one factor: the distance between the wafer and the inner wall of the counterbore.

[0045] 37 is an explanatory diagram showing a schematic planar configuration of a conventional susceptor. As shown in the figure, a susceptor 132 has three semiconductor wafers 131, such as SiC wafers, mounted within a counterbore 133. While the susceptor 132 is rotated in a susceptor rotation direction R132, a source gas G1 is supplied above the three semiconductor wafers 131 in a source supply direction F1.

[0046] Fig. 38 is a graph showing an example of the epitaxial crown height when an epitaxial layer is formed on the surface of a semiconductor wafer 131 using the susceptor 132 shown in Fig. 37. The epitaxial crown height indicated by the epitaxial crown height change L6 is normalized by the average epitaxial thickness.

[0047] As shown in Figure 38, the epicrown has two peaks on the opposite side of the OF portion, and the location of the peaks corresponds to the location indicated by "A" in Figure 37. Considering this together with the results shown in Figure 31, it is clear that the distance between the wafer outer periphery and the inner wall of the counterbore affects the epicrown.

[0048] From these results, it can be said that in order to suppress epi-crown, it is important to prevent the inner wall of the counterbore from being too far away from the wafer edge, that is, to use a counterbore with a shape that matches the wafer shape.

[0049] 39 is an explanatory diagram showing the results of a fluid simulation regarding the flow velocity of the source gas G1. In this figure, the dot density has a negative correlation with the flow velocity of the source gas G1, and the higher the dot density in an area, the slower the flow velocity of the source gas G1.

[0050] 39, the source gas G1 that has passed above the susceptor 132 passes through the wafer mounting surface, collides with the edge of the SiC wafer 73, such as the orientation flat 73k, and is then supplied to the surface of the SiC wafer 73. That is, the region R73 around the edge of the SiC wafer 73 is the region where the flow rate of the source gas G1 is the slowest.

[0051] Therefore, it is believed that the edge peripheral region R73, where the flow rate of the source gas G1 for epitaxial growth is the slowest, is the region where the degree of epitaxial growth is highest, and as a result, an epicrown is formed in the edge peripheral region R73.

[0052] Therefore, when the inner wall of the recess and the edge of the SiC wafer 73 are close to each other, the source gas G1 is supplied to the surface of the semiconductor wafer 131 without passing through the wafer mounting surface of the recess 133, which prevents the formation of an area where the flow rate of the source gas G1 drops, such as the edge peripheral area R73 in Figure 39, and is therefore considered to be effective in suppressing epicrown.

[0053] Next, we investigated the method of holding the semiconductor wafer. Figure 40 is a graph showing the epi-crown height based on different methods of placing the SiC wafer.

[0054] The epi-crown height change L8 indicates the normalized value of the epitaxial thickness when a 6-inch SiC wafer is used as the SiC wafer 73 and the SiC wafer 73 is placed directly on the mounting surface. The epi-crown height change L7 indicates the normalized value of the epitaxial thickness when the SiC wafer 73 is lifted up at several points and the back surface of the wafer is separated from the susceptor (hereinafter, this may be referred to as "lift-up").

[0055] The counterbore is shaped to fit the shape of the SiC wafer 73, and the wafer-susceptor top distance DT is equal between the epitaxial crown height change L7 and the epitaxial crown height change L8. As shown by the epitaxial crown height change L8, even when the counterbore shape fits the shape of the SiC wafer 73, a high epitaxial crown is still formed in the OF portion when the wafer is placed flat. On the other hand, as shown by the epitaxial crown height change L7, when the SiC wafer 73 is lifted up, the epitaxial crown in the OF portion is reduced.

[0056] This is thought to be because a space is formed on the back surface of the SiC wafer 73 due to the listing, and part of the source gas G1 escapes to the back surface of the SiC wafer 73.

[0057] 41 is a graph showing the epitaxial thickness along the X direction based on different SiC wafer mounting methods. Epitaxial thickness change L9 indicates the normalized value of the epitaxial thickness when the SiC wafer 73 is lifted up and mounted, and epitaxial thickness change L10 indicates the normalized value of the epitaxial thickness when the SiC wafer 73 is placed flat.

[0058] In Figure 41, the origin "0" where the X axis and Y axis intersect is the position where the predetermined distance ΔD is "0", and the predetermined distance ΔD on the +X direction side is a positive distance [mm], and the predetermined distance ΔD on the -X direction side is a negative distance [mm].

[0059] As shown by the epitaxial thickness changes L9 and L10 in FIG. 41, when the wafer-susceptor top distance DT is the same for both wafers, no significant change occurs in the in-plane distribution shape of the epitaxial thickness.

[0060] Based on the above experimental results, the inventors have provided the wafer loading device of the present disclosure, which is provided with a susceptor having an opening with walls corresponding to the shape of the semiconductor wafer so that the distance between the inner wall of the counterbore and the wafer edge is not too great, and is also capable of performing epitaxial growth processing on the semiconductor wafer in a lifted-up state.

[0061] By lifting up the semiconductor wafer, a space is created on the back surface of the semiconductor wafer, and part of the source gas is allowed to escape into this space, thereby reducing the epi-crown.

[0062] The key to reducing epi-crown is to allow a portion of the source gas G1 supplied to the surface of the semiconductor wafer to escape to the backside of the semiconductor wafer. For this reason, the wafer mounting device of the present disclosure is characterized in that an annular groove is provided on the wafer mounting surface below the outermost periphery of the semiconductor wafer to ensure a flow path for the source gas G1, and the flow path for the source gas G1 formed around the OF portion where a high epi-crown is formed is deeper than in other regions.

[0063] The wafer mounting device of the present disclosure, which was obtained based on the above technical considerations, will be the wafer mounting devices shown in the following first to fourth embodiments.

[0064] <Wafer Mounting Device of the Present Disclosure> (Introduction) The following describes a susceptor, which is a wafer mounting device according to the present disclosure, and a semiconductor manufacturing device for SiC wafers (SiC epitaxial wafers). The drawings used in the following description may show enlarged, characteristic portions of the wafer mounting device according to the present disclosure for ease of understanding, and the dimensional ratios of each component may differ from the actual values. Furthermore, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present disclosure is not limited thereto. Appropriate modifications may be made within the scope of the present disclosure.

[0065] (Semiconductor manufacturing equipment) 25 is an explanatory diagram schematically illustrating a cross-sectional structure of a semiconductor manufacturing apparatus 50 including a susceptor 11 and the like according to a first embodiment of the present disclosure. This semiconductor manufacturing apparatus 50 is also called an "SiC epitaxial wafer manufacturing apparatus" and is an apparatus for forming an epitaxial layer on the surface of a SiC wafer. Although the semiconductor manufacturing apparatus 50 is not limited to the configuration shown in FIG. 25, for ease of understanding, the following embodiments will be described based on the semiconductor manufacturing apparatus 50 shown in FIG. 25.

[0066] The semiconductor manufacturing apparatus 50 shown in Figure 25 is an apparatus called a planetary susceptor type, and has a top plate 185 at the top inside a chamber 181, a planetary susceptor 182 and an induction heating coil 188 at the bottom, and an injector 186 that runs vertically through the chamber 181 from the center of the top plate 185.

[0067] Above the planetary susceptor 182, a plurality of satellite disks 183 are arranged in a plurality of accommodation regions 189 around a center part 187, and SiC wafers 184 are set on the satellite disks 183, and raw material gas G1 is caused to flow radially from injectors 186 to perform epitaxial growth on the surfaces of the SiC wafers 184. The epitaxial growth on the surfaces of the satellite disks 183 is performed at a temperature range of approximately 1400°C to 1700°C by heat treatment using an induction heating coil 188.

[0068] Then, when the interior of semiconductor manufacturing equipment 50 reaches the desired temperature, epitaxial growth processing is performed by flowing source gas G1, which includes a silicon-based gas (silicon source gas), a hydrocarbon gas, and a dopant gas carried on a carrier gas, from the side so as to be approximately parallel to SiC wafer 184. Possible silicon source gases include silane (SiH4), dichlorosilane (SiCl2H2), trichlorosilane (SiCl3), silicon tetrachloride (SiCl4), etc., and possible hydrocarbon gases, which are carbon source gases, include propane (C3H8), ethane (C2H6), etc.

[0069] To improve the growth rate in the epitaxial growth process, HCl may be added or a source gas G1 containing Cl, such as SiH2Cl2, may be used. The source gas G1 for epitaxial growth introduced from the injector 186 reaches the outside of the chamber 181 while being consumed in the epitaxial growth, resulting in different growth rates and carrier concentrations upstream and downstream. Therefore, while the source gas G1 is being supplied, the planetary susceptor 182 is mechanically rotated along the susceptor rotation direction R182, and the satellite disk 183 is rotated along the disk rotation direction R183 by the disk rotation gas G2 blown onto the underside of the satellite disk 183.

[0070] This epitaxial growth process is performed to improve the uniformity of the carrier concentration and film thickness of the epitaxial layer. When the epitaxial layer reaches the desired film thickness, the supply of source gas G1 is stopped and the temperature is lowered. After the temperature has dropped to the predetermined level, the SiC wafer 184 is removed, completing the epitaxial growth process.

[0071] Next, the susceptor of the present disclosure will be described. A ring is set on the satellite disk 183 described above to prevent the SiC wafer 184 from shifting during film formation. The wafer holder that is heated by induction heating using the induction heating coil 188, a heater, or the like is collectively called a "susceptor."

[0072] Therefore, in the embodiments described below, it is acceptable to refer to the combination of a satellite disk and a ring as a susceptor, and for simplicity, hereafter, the structure having this combination as its main component will be referred to as the "susceptor" of this disclosure.

[0073] The advantage of a susceptor consisting of a satellite disk and a ring is that it allows for greater freedom in the materials and coatings that can be used, such as combining a TaC-coated satellite disk with a SiC ring. For example, when performing multiple epitaxial growth processes, deposits that adhere to the inner wall of the ring can interfere with the semiconductor wafer, making it impossible to set the semiconductor wafer. However, if a bulk SiC ring is used, the strength of SiC makes it possible to mechanically remove the deposits and reuse them, thereby reducing parts costs.

[0074] Furthermore, when comparing the center of a semiconductor wafer with the outer periphery, which is the region surrounding the center, the temperature of the outer periphery is more likely to drop, but if a ring covered with some kind of coating material is applied to a carbon base material and the resistivity of the ring base material is made higher than that of the satellite disk base material, the ring will generate more heat than the satellite disk during induction heating, making it possible to suppress the temperature drop at the outer periphery of the semiconductor wafer.To achieve this high degree of flexibility, the present disclosure employs a susceptor whose main components are a combination of a satellite disk and a ring.

[0075] <First Embodiment> (Basic configuration) Fig. 1 is an explanatory diagram schematically showing the planar configuration of a susceptor 11, which is a basic configuration of a first embodiment of the present disclosure. Fig. 2 is an explanatory diagram schematically showing the configuration of the A1-A1 cross section of Fig. 1, Fig. 3 is an explanatory diagram schematically showing the configuration of the B1-B1 cross section of Fig. 1, and Fig. 4 is an explanatory diagram schematically showing the configuration of the C1-C1 cross section of Fig. 1. Fig. 5 is an explanatory diagram showing an enlarged view of the cross-sectional configuration of Fig. 2. Note that Fig. 1 schematically shows the planar structures of a ring 12 and satellite disks 13, which are main components of the susceptor 11, in an easily recognizable manner.

[0076] Susceptor 11, which is the basic configuration of the wafer mounting device of embodiment 1, is intended to mount SiC wafers 14 having orientation flats 14k. That is, susceptor 11 of embodiment 1 is a wafer mounting device that mounts SiC wafers 14 having orientation flats 14k. SiC wafers 14 are semiconductor wafers that have orientation flats 14k as cutouts.

[0077] 1 to 5, the susceptor 11 includes, as its main components, a combination of satellite disks 13, which are disks that are circular and have a convex cross section in plan view, and a ring 12. The ring 12 has walls 12a and 12b on its upper side, and has an opening O12 whose outer periphery is defined by the walls 12a and 12b. The opening O12 has a shape similar to the wafer shape of the SiC wafer 14, and the opening O12 has a planar shape that includes the SiC wafer 14 and is slightly wider than the SiC wafer 14 in plan view.

[0078] As shown in FIGS. 2 to 5, the cross-sectional structure of the portion of the ring 12 having the terrace portion 12t has a modified T-shape with regions protruding in the directions toward and away from the opening O12.

[0079] Satellite disk 13, which is a disk with a basic configuration, has upper layer 13u, which is a convex portion, and peripheral portion 13p around upper layer 13u. Peripheral surface 13d of peripheral portion 13p is formed lower in height than surface 13s of upper layer 13u, and as shown in Figure 5, there is a step Δ13 in the height direction from peripheral surface 13d to surface 13s.

[0080] Wall 12b of ring 12 functions as a notch-side protruding wall that protrudes toward opening O12 in correspondence with orientation flat 14k, which is a notch in SiC wafer 14. As shown in Fig. 1, wall 12b is arranged parallel to orientation flat 14k in a plan view, and a gap space S12 with a constant length in the short direction exists between wall 12b and orientation flat 14k.

[0081] 2 and 5, the upper surface of wall portion 12b, which forms the notch-side protruding wall portion, is provided so as to form part of the upper surface of the entire ring 12. In other words, the formed height of the upper surface of wall portion 12b matches the formed height of the upper surface of ring 12. Furthermore, the lower surface of wall portion 12b does not come into contact with peripheral surface 13d of peripheral portion 13p of satellite disk 13.

[0082] The ring 12 further has a terrace portion 12t protruding toward the opening O12 in an intermediate region in the height direction, and as shown in FIG. 1, the terrace portion 12t does not overlap with the wall portion 12b, which is the notch-side protruding wall portion, in a plan view.

[0083] The ring 12 is placed on the satellite disk 13 in such a manner that the terrace portion 12t of the ring 12 is supported by the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13. In other words, the satellite disk 13 supports the ring 12 by supporting the terrace portion 12t from the backside with the peripheral surface 13d.

[0084] Three lift-up pins 15, which are a plurality of lift-up members each having the same formed height, are placed on the surface of the terrace portion 12t of the ring 12 so as to be spaced apart from one another.

[0085] The three lift-up pins 15 support the back surface of the SiC wafer 14, thereby holding the SiC wafer 14. In the first embodiment, the surface of the terrace portion 12t serves as a lift-up region for the three lift-up pins 15.

[0086] Since the upper surface of the wall portion 12b becomes part of the upper surface of the ring 12, the formed height of the upper surface of the wall portion 12b matches the formed height of the upper surface of the entire ring 12. The upper surface of the wall portion 12b is set to be higher than the formed height of the upper surfaces of the three lift-up pins 15.

[0087] As described above, the susceptor 11, which is the basic configuration of the first embodiment, includes the ring 12, the satellite disks 13, and the three lift-up pins 15 as main components.

[0088] In the susceptor 11 of the first embodiment having such a configuration, the SiC wafer 14 can be held by placing the SiC wafer 14 on the three lift-up pins 15 so that the SiC wafer 14 fits within the opening O12 in plan view without coming into contact with the ring 12. This state is the semiconductor wafer-mounted state for the SiC wafer 14.

[0089] When the SiC wafer 14 is in the above-described semiconductor wafer state, the wall portion 12b, which is the notch-side protruding wall portion, and the orientation flat portion 14k are positioned opposite each other with a gap space S12 at a fixed interval therebetween.

[0090] The SiC wafer 14 thus placed is disposed in the opening O12 in plan view without contacting the ring 12, so that an annular gap is always formed between the outer peripheral surface of the SiC wafer 14 and the opening O12. The annular gap includes the clearance space S12 described above.

[0091] In addition, the openings O12 are formed to approximate the shape of the SiC wafer 14, so that the annular gaps are provided at regular intervals without deviation. These annular gaps also function as gas escape channels, which will be described later.

[0092] When the SiC wafer 14 is placed on the three lift-up pins 15, a space S13 above the disk is formed between the surface 13s of the upper layer 13u of the satellite disk 13 and the back surface of the SiC wafer 14, except for the area where the three lift-up pins 15 are formed.

[0093] Furthermore, between the upper layer 13u of the satellite disk 13 on the rear surface side of the SiC wafer 14 and the ring 12, a groove 2 is formed, which is an annular groove that is annular along the outer periphery of the opening O12 in plan view.

[0094] One side of the annular groove 2 is the side of the upper layer 13u, and the other side is the wall 12a. The groove 2 formed in the region where the terrace 12t is formed serves as the space above the terrace 12t, with the terrace 12t as its bottom.

[0095] 2 and 5, in the region where the terrace portion 12t is not formed, the grooves 2 directly below the wall portion 12b are grooves 2k. Also, as shown in Fig. 4, the grooves 2 located directly below the peripheral regions at both ends of the wall portion 12b are grooves 2m. Both the grooves 2k and 2m have the peripheral surface 13d of the peripheral portion 13p as their bottom surfaces and form spaces above the peripheral surface 13d.

[0096] Hereinafter, in this specification, the annular groove 2 will be described as including groove 2k (groove 2n) and groove 2m (groove 2m2) in a broad sense, and as referring only to groove 2 having terrace portion 12t as its bottom surface in a narrow sense.

[0097] The annular gap formed between the outer peripheral surface of the SiC wafer 14 and the opening O12 and the annular groove 2 described above serve as a gas escape flow path for allowing the raw material gas G1 supplied to the surface of the SiC wafer 14 to escape to the space S13 above the disk.

[0098] The terrace portion 12t of the ring 12 is provided so as not to come into contact with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2X that communicates with the groove 2 in the depth direction can be provided between the tip of the terrace portion 12t and the side surface of the upper layer portion 13u. This auxiliary groove 2X can increase the depth of a portion of the groove 2, thereby increasing the volume of the gas escape channel.

[0099] 1, 2 and 5, the lift-up pins 15 are shown as cylindrical, but may be of any shape. At least three pins are required to hold the SiC wafer 14, but the number is not limited as long as it is three or more.

[0100] The temperature at the contact points between the lift-up pins 15 and the SiC wafer 14 may differ from that of other regions, potentially affecting the film quality, so it is desirable to hold the SiC wafer 14 in, for example, the edge exclusion region. Therefore, it is desirable to position the lift-up pins 15 as far outward as possible, in a manner that allows them to contact the wall portion 12a of the ring 12.

[0101] Although there is no problem if the lift-up pins 15 are provided so as not to come into contact with the wall portion 12a, it may become difficult to manufacture the ring 12 by machining using an NC machine or the like.

[0102] 2 to 5, the thickness in the height direction of the terrace portion 12t is formed to be thinner than the step Δ13 between the upper layer portion 13u and the peripheral portion 13p of the satellite disk 13. Therefore, when the satellite disk 13 and the ring 12 are combined into a ring, the annular groove 2 is always formed also in the formation region of the terrace portion 12t.

[0103] As described above, the lower surface of the wall portion 12b is located between the surface of the ring 12 and the rear surface of the SiC wafer 14, and it is preferable that the lower surface be located between the surface and rear surface of the SiC wafer 14.

[0104] 5, the lower surface of wall 12b corresponding to orientation flat 14k of SiC wafer 14 is aligned with the height of the upper surfaces of three lift-up pins 15 (the back surface of SiC wafer 14). Furthermore, ring 12 is configured so that terrace 12t is not formed in the area corresponding to orientation flat 14k. This allows groove 2k, which serves as a gas escape path for source gas G1 to escape to upper disk space S13 on the back surface of SiC wafer 14, to be formed deeper than groove 2, whose bottom surface is terrace 12t.

[0105] Similarly, as shown in FIG. 4, since terrace portion 12t is not formed in the peripheral region of the end of orientation flat portion 14k, groove 2m, which serves as a gas escape path, can be made deeper than groove 2, which has terrace portion 12t as its bottom surface.

[0106] When the susceptor 11 of embodiment 1 having such a configuration is applied to the semiconductor manufacturing apparatus 50 shown in Figure 25, the satellite disk 183 is replaced with a susceptor 11 including a ring 12, a satellite disk 13, and three lift-up pins 15, and the SiC wafer 184 is replaced with a SiC wafer 14.

[0107] 1 to 5 according to the first embodiment is applied to the semiconductor manufacturing apparatus 50 shown in Fig. 25. In a planetary susceptor-type CVD apparatus, source gas G1 is supplied from the outside of the rotating susceptor 132. When the orientation flat 14k of the SiC wafer 14 approaches the injector 186 and source gas G1 is supplied from the orientation flat 14k side, part of the source gas G1 flows into the space above the disk S13 via the gap space S12 between the SiC wafer 14 and the wall portion 12b and the groove 2k.

[0108] As mentioned above, the groove 2k is formed relatively deep, so that the raw material gas G1 flowing from the gap space S12 between the SiC wafer 14 and the wall portion 12b can be smoothly released to the space S13 above the disk on the back side of the SiC wafer 14 via the groove 2k, which serves as a gas escape flow path.

[0109] On the other hand, if the lower surface of the wall portion 12b is lower than the back surface of the SiC wafer 14, the wall portion 12b may extend into the groove 2k, which may hinder the function of the groove 2k as a gas escape channel. For this reason, the position of the lower surface of the wall portion 12b is set to be higher than the height of the surfaces of the three lift-up pins 15 (the back surface of the SiC wafer 14).

[0110] In the susceptor 11, which is the basic configuration of embodiment 1, the ring 12 is held by supporting the terrace portion 12t from below on the surface of the peripheral portion 13p of the satellite disk 13, and the formation of the terrace portion 12t in the orientation flat portion 14k and its surrounding area is omitted.

[0111] However, if there are no problems in terms of strength, multiple partial terraces may be provided discretely instead of the continuously formed terrace 12t in areas other than the orientation flat 14k and its surrounding area. Note that "there are no problems in terms of strength" here means that the weight of the ring 12 can be supported by the terrace 12t and that there is no problem with the terrace 12t.

[0112] The susceptor 11, which is the basic configuration of the wafer loading device according to the first embodiment of the present disclosure, places a semiconductor wafer, that is, an SiC wafer 14, on three lift-up pins 15, which are a plurality of lift-up members, to achieve a semiconductor wafer loading state for the SiC wafer 14. Therefore, a space S13 above the disk can be provided between the back surface of the SiC wafer 14 and the front surface 13s of the satellite disk 13.

[0113] Furthermore, in the susceptor 11 of the first embodiment, when the semiconductor wafer is mounted, a groove 2, which is an annular groove, is formed between the upper layer 13u of the satellite disk 13 and the ring 12 on the back surface side of the SiC wafer 14.

[0114] Therefore, when the raw material gas G1 is supplied above the surface of the SiC wafer 14 in the semiconductor wafer-mounted state, a portion of the raw material gas G1 can be intentionally released into the disk-above space S13 on the back side of the SiC wafer 14 through the annular gap and groove 2 along the outer periphery of the SiC wafer 14.

[0115] As a result, when the susceptor 11 of the first embodiment performs an epitaxial growth process to form an epitaxial growth layer on the surface of the SiC wafer 14 with the semiconductor wafer mounted thereon, it is possible to suppress the occurrence of an epi-crown phenomenon, in which the epitaxial thickness of the epitaxial growth layer increases locally. This epi-crown phenomenon occurs mainly in the outer periphery of the surface of the SiC wafer 14.

[0116] As a result, the susceptor 11 of the first embodiment has the effect of being able to form an epitaxial layer with an epitaxial thickness having excellent in-plane uniformity on the surface of the SiC wafer 14 in the state where the semiconductor wafer is mounted thereon. Note that the in-plane uniformity can be measured using the epitaxial thickness and the carrier concentration (impurity concentration).

[0117] Furthermore, since the height of the top surface of the ring 12 can be set arbitrarily, the wafer-susceptor top distance DT, which is the difference in height between the surface of the SiC wafer 14 placed on the three lift-up pins 15 and the top surface of the ring 12, can be set to an optimal length that does not result in an extreme reduction in epitaxial thickness at the outer periphery of the surface of the SiC wafer 14.

[0118] In the susceptor 11 of embodiment 1, the ring 12 is placed on the satellite disk 13 in such a manner that the terrace portion 12t is supported on the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13, so that a combined structure of the satellite disk 13 and the ring 12 can be realized without affecting the SiC wafer 14 to be mounted.

[0119] Furthermore, by forming the height-wise thickness of the terrace portion 12t thinner than the step Δ13 between the upper layer portion 13u and the peripheral portion 13p of the satellite disk 13, a groove 2 can be formed in the formation area of ​​the terrace portion 12t, with the terrace portion 12t as the bottom surface.

[0120] The susceptor 11 of the first embodiment has a lift-up region that is the surface region of the terrace portion 12t, and can support the SiC wafer 14 by three lift-up pins 15, which are multiple lift-up members placed on the terrace portion 12t of the ring 12.

[0121] In the susceptor 11 of embodiment 1, the terrace portion 12t is not in contact with the side surface of the upper layer portion 13u, and therefore an auxiliary groove 2X that communicates with the groove 2 in the depth direction can be formed between the side surface of the upper layer portion 13u and the protruding tip of the terrace portion 12t.

[0122] As a result, the susceptor 11 of embodiment 1 can increase the volume of the groove 2 by the amount of the auxiliary groove 2X, thereby improving the function of the groove 2 as a gas escape flow path that allows a portion of the raw material gas G1 to escape to the space S13 above the disk on the back side of the SiC wafer 14, and effectively suppressing the epicrown phenomenon.

[0123] The opening O12 of the ring 12 includes the SiC wafer 14 and has a larger formation area than the SiC wafer 14, so that the SiC wafer 14 can be securely placed on the three lift-up pins 15 without coming into contact with the ring 12, including the wall portion 12b that becomes the notch-side protruding wall portion.

[0124] Furthermore, by forming the opening O12 in an approximate shape to match the shape of the SiC wafer 14, the susceptor 11 of the first embodiment can effectively suppress the occurrence of epi-crowns.

[0125] In addition, since the wall portion 12b, which is the notch-side protruding wall portion, is not in contact with the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13, the function of the groove 2k formed below the wall portion 12b as a gas escape flow path is not degraded.

[0126] In the susceptor 11 of embodiment 1, the formation height of the lower surface of the wall portion 12b, which is the notch-side protruding wall portion, is set to be equal to or greater than the formation height of the upper surfaces of the three lift-up pins 15, so that the function of the groove 2k formed below the wall portion 12b as a gas escape flow path is not deteriorated.

[0127] Additionally, in the susceptor 11 of the first embodiment, the upper surface of the wall portion 12b, which is the notch-side protruding wall portion, is provided so as to form part of the upper surface of the ring 12. That is, the formation height of the upper surface of the wall portion 12b is the same as the formation height of the upper surface of the ring 12. Therefore, the groove 2k serving as a gas escape flow path can be formed below the wall portion 12b, which has a sufficient thickness.

[0128] Wall 12b, which is the notch-side protruding wall, is arranged to face orientation flat 14k across gap space S12 at a fixed distance when a semiconductor wafer is mounted, thereby restricting the amount of source gas G1 flowing through groove 2k via gap space S12 so as not to exceed the allowable upper limit. If source gas G1 exceeding the allowable upper limit flows into groove 2k via gap space S12, the amount of source gas G1 supplied to the surface of SiC wafer 14 may fall below an appropriate amount.

[0129] Therefore, the susceptor 11 of the first embodiment can supply an appropriate amount of source gas G1 to the surface of the SiC wafer 14 having the orientation flat portion 14k.

[0130] (First Modification) Fig. 6 is an explanatory diagram illustrating a planar configuration of a susceptor 11B according to a first modified example of the first embodiment of the present disclosure. Fig. 7 is an explanatory diagram illustrating a cross-sectional configuration taken along the line A11-A11 in Fig. 6, Fig. 8 is an explanatory diagram illustrating a cross-sectional configuration taken along the line B11-B11 in Fig. 6, and Fig. 9 is an explanatory diagram illustrating a cross-sectional configuration taken along the line C11-C11 in Fig. 6. Note that Fig. 6 illustrates the planar structures of the ring 12 and satellite disks 13B, which are the main components of the susceptor 11B, in an easily recognizable manner.

[0131] The susceptor 11B, which is a first modified example of the wafer mounting device of the first embodiment, is designed to mount a SiC wafer 14 having an orientation flat portion 14k, similar to the basic configuration.

[0132] Hereinafter, the same components as those of the susceptor 11 having the basic configuration shown in FIGS. 1 to 5 will be denoted by the same reference numerals, and the description will be omitted as appropriate, and the features of the susceptor 11B, which is the first modified example, will be mainly described.

[0133] As shown in Figures 6 to 9, the susceptor 11B includes, as its main components, a combination of a satellite disk 13B, which is a disk that is circular in plan view and has a convex cross section, and a ring 12 that has a modified T-shaped cross section and a terrace portion 12t.

[0134] The satellite disk 13B, which is a disk of the first modification, has an upper layer portion 13u that is a convex portion, and has a peripheral portion 13p around the upper layer portion 13u.

[0135] The surface 13s of the upper layer 13u of the satellite disk 13B is characterized by a concave shape with a recessed center, that is, the surface 13s has a concave portion that becomes deeper from the outer periphery toward the center.

[0136] In the susceptor 11B, which is a first modified example of the first embodiment having such a configuration, when the SiC wafer 14 is placed on the three lift-up pins 15, as in the basic configuration, a space above the disk S13B is formed between the surface 13s of the upper layer 13u of the satellite disk 13B and the back surface of the SiC wafer 14, except for the area where the three lift-up pins 15 are formed.

[0137] Compared to the above-disk space S13 of the basic configuration, the above-disk space S13B has a larger volume than the above-disk space S13 because the formation depth on the back side of the SiC wafer 14 is deeper from the outer periphery to the center of the SiC wafer 14.

[0138] The susceptor 11B of the first modified example has the same effects as the susceptor 11 of the basic configuration, and further has the following unique effects.

[0139] Since the surface 13s of the upper layer 13u of the satellite disk 13 in the susceptor 11B of the first modified example has a concave shape with a recessed center, a disk-above space S13B that is larger than the disk-above space S13 of the basic configuration can be formed on the back side of the SiC wafer 14.

[0140] As a result, the susceptor 11B of the first modified example can release a portion of the raw material gas G1 into the relatively large space above the disk S13B through the annular groove 2, thereby making the flow of the gas to the back side of the SiC wafer 14 smoother.

[0141] (Second Modification) Figure 10 is an explanatory diagram illustrating a planar configuration of a susceptor 11C according to a second modified example of the first embodiment of the present disclosure. Figure 11 is an explanatory diagram illustrating a cross-sectional configuration taken along the line A12-A12 in Figure 10, Figure 12 is an explanatory diagram illustrating a cross-sectional configuration taken along the line B12-B12 in Figure 10, and Figure 13 is an explanatory diagram illustrating a cross-sectional configuration taken along the line C12-C12 in Figure 10. Note that Figure 10 illustrates the planar structures of the ring 121 and satellite disks 13, which are the main components of the susceptor 11C, in an easily recognizable manner.

[0142] The susceptor 11C, which is the second modification of the wafer mounting device according to the first embodiment, has the SiC wafer 14 having the orifice portion 14k as the mounting target, similar to the basic configuration.

[0143] Hereinafter, the same configurations as those of the susceptor 11 having the basic configuration shown in FIGS. 1 to 5 are denoted by the same reference numerals, and the description thereof will be appropriately omitted, and the description will be centered on the features of the susceptor 11C which is the second modification.

[0144] As shown in FIGS. 10 to 13, the susceptor 11C mainly includes a combination of a satellite disk 13 which is a disk having a circular shape in plan view and a convex cross section, and a ring 121 having a terraced portion 121t and a deformed T-shaped cross section.

[0145] The ring 121 in the susceptor 11C of the second modification is characterized in that, in addition to the terraced portion 12t, it further has two terraced portions 121t which are auxiliary terraced portions protruding toward the opening O12 side.

[0146] As shown in FIG. 10, the two terraced portions 121t which are auxiliary terraced portions are provided adjacent to both ends of the wall portion 12b. That is, the two terraced portions 121t are respectively provided between the terraced portion 12t and the wall portion 12b in plan view.

[0147] As shown in FIG. 13, the formed height of the back surfaces of the two terraced portions 121t coincides with the formed height of the back surface of the terraced portion 12t. The terraced portion 12t has a terrace thickness T1 in the height direction, and the terraced portion 121t has a terrace thickness T2 (<T1) in the height direction. Thus, the terraced portion 121t which is the auxiliary terraced portion is set to be thinner in thickness in the height direction than the terraced portion 12t.

[0148] 13, the ring 121 is placed on the satellite disk 13 in such a manner that the terrace portions 12t and 121t are supported on the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13. The space above the terrace portions 121t forms a groove 2m2 that serves as a gas escape path. That is, the groove 2m has the terrace portion 121t as its bottom surface, the side surface of the upper layer portion 13u as one side, and the wall portion 12a as the other side.

[0149] The susceptor 11C of the second modified example having such a configuration provides the same effects as the susceptor 11 of the basic configuration, and also provides the following unique effects.

[0150] In the susceptor 11C, which is a wafer mounting device of the second modified example, the ring 121 is placed on the satellite disk 13 in such a manner that the terrace portion 12t and the terrace portion 121t are supported on the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13, so that the combined structure of the satellite disk 13 and the ring 121 can be realized with good stability.

[0151] Furthermore, by setting the height direction thickness of terrace portion 121t, which is the auxiliary terrace portion, thinner than terrace portion 12t, groove 2m2, which is the space above terrace portion 121t, can be formed deeper than groove 2, which is the space above terrace portion 12t. In other words, the depth of groove 2m2, which is the region around both ends of orientation flat portion 14k, can be made deeper than the depth of groove 2, which has terrace portion 12t as its bottom surface.

[0152] As a result, the susceptor 11C of the second modified example can minimize deterioration of the function of the groove 2m2 as a gas escape flow path for allowing the raw material gas G1 supplied around the cutout portion, the orientation flat portion 14k, to escape to the disk-above space S13 on the back side of the SiC wafer 14.

[0153] <Embodiment 2> (Basic configuration) Fig. 14 is an explanatory diagram schematically showing the planar configuration of susceptor 21, which is the basic configuration of embodiment 2 of the present disclosure. Fig. 15 is an explanatory diagram schematically showing the configuration of the A2-A2 cross section of Fig. 14, Fig. 16 is an explanatory diagram schematically showing the configuration of the B2-B2 cross section of Fig. 14, and Fig. 17 is an explanatory diagram showing an enlarged view of region R2 of interest in Fig. 14. Note that Fig. 14 schematically illustrates the planar structures of ring 122 and satellite disks 13, which are main components of susceptor 21, in an easily recognizable manner.

[0154] The susceptor 21, which is the basic configuration of the wafer mounting device of the second embodiment, is intended to mount a SiC wafer 24 having a notch portion 24n with a notch depth of notch length Ln (see FIG. 17). That is, the susceptor 21 of the second embodiment is a wafer mounting device that mounts a SiC wafer 24 having the notch portion 24n. The SiC wafer 24 is a semiconductor wafer having the notch portion 24n as a cutout portion.

[0155] Hereinafter, the same reference numerals will be used to designate components similar to those of the susceptor 11 having the basic configuration of the first embodiment shown in Figures 1 to 5, and explanations will be omitted as appropriate. The following description will focus on the features of the susceptor 21 having the basic configuration of the second embodiment.

[0156] As shown in Figures 14 to 17, the susceptor 21 includes, as its main components, a combination of a satellite disk 13, which is a disk that is circular in plan view and has a convex cross section, and a ring 122 that has a modified T-shaped cross section and a terrace portion 12t.

[0157] The ring 122 has walls 12a and 12c provided on the upper side thereof, and has an opening O122 whose outer periphery is defined by the walls 12a and 12c. The opening O122 has a shape similar to the wafer shape of the SiC wafer 24, includes the SiC wafer 24 in plan view, and has a planar shape slightly wider than the SiC wafer 24.

[0158] The wall portion 12c of the ring 122 functions as a notch-side protruding wall portion that protrudes toward the opening portion O122 in correspondence with the notch portion 24n that is a cutout portion of the SiC wafer 24. As shown in Fig. 14, the wall portion 12c that is the notch-side protruding wall portion is disposed so as to fill a part of the notch portion 24n without coming into contact with the SiC wafer 24 that is a semiconductor wafer.

[0159] As shown in FIG. 15, the wall portion 12c that becomes the notch-side protruding wall portion is not in contact with the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13.

[0160] The ring 122 further has a terrace portion 12t protruding toward the opening O122 in an intermediate region in the height direction, and as shown in FIG. 14, the terrace portion 12t does not overlap with the wall portion 12c, which is the notch-side protruding wall portion, in plan view.

[0161] The ring 122 is placed on the satellite disk 13 in such a manner that the terrace portion 12t is supported on the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13.

[0162] In the susceptor 21 having the basic configuration of the second embodiment, the surface of the terrace portion 12t serves as a lift-up region for the three lift-up pins 15.

[0163] Three lift-up pins 15, which are a plurality of lift-up members each having the same height, are placed on the surface of the terrace portion 12t of the ring 122. The three lift-up pins 15 support the SiC wafer 24 from the backside, thereby holding the SiC wafer 24.

[0164] As described above, the susceptor 21, which is the basic configuration of the second embodiment, includes the ring 121, the satellite disk 13, and the three lift-up pins 15 as main components.

[0165] In the susceptor 21 of the second embodiment having such a configuration, the SiC wafer 24 can be held by placing the SiC wafer 24 on the three lift-up pins 15 so that the SiC wafer 24 fits within the opening O122 in plan view without coming into contact with the ring 122. This state is the semiconductor wafer-mounted state for the SiC wafer 24.

[0166] When the SiC wafer 24 is in the semiconductor wafer-mounted state, the wall portion 12c, which is the notch-side protruding wall portion, faces the notch portion 24n and is disposed so as to fill a part of the notch portion 24n.

[0167] The SiC wafer 24 thus placed is disposed in the opening O122 in plan view without contacting the ring 122, so that an annular gap is always formed between the outer peripheral surface of the SiC wafer 24 and the opening O122. In addition, because the opening O112 is formed to approximate the shape of the SiC wafer 24, the annular gaps are provided at regular intervals without bias. These annular gaps also function as gas escape paths.

[0168] When the SiC wafer 24 is placed on the three lift-up pins 15, a space S13 above the disk is formed between the surface 13s of the upper layer 13u of the satellite disk 13 and the back surface of the SiC wafer 24, except for the area where the three lift-up pins 15 are formed.

[0169] Furthermore, between the upper layer 13u of the satellite disk 13 on the rear surface side of the SiC wafer 24 and the ring 122, a groove 2 is formed, which is an annular groove that is annular in shape along the outer periphery of the opening O122 in plan view.

[0170] One side of the annular groove 2 is the side of the upper layer 13u, and the other side is the wall 12a. The groove 2 formed in the region where the terrace 12t is formed serves as the space above the terrace 12t, with the terrace 12t as its bottom.

[0171] 15, in the region where the terrace portion 12t is not formed, the groove 2 directly below the wall portion 12c becomes a groove 2n. The groove 2n has the peripheral surface 13d of the peripheral portion 13p as its bottom surface and becomes a space above the peripheral surface 13d.

[0172] The terrace portion 12t of the ring 122 is provided so as not to come into contact with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2X that communicates with the groove 2 in the depth direction can be provided between the tip of the terrace portion 12t and the side surface of the upper layer portion 13u.

[0173] The lower surface of the wall 12c is located between the surface of the ring 122 and the rear surface of the SiC wafer 24, similar to the wall 12b in the first embodiment, but is preferably located between the surface and rear surface of the SiC wafer 24.

[0174] In the susceptor 21 of the second embodiment, the lower surface of the wall portion 12c corresponding to the notch portion 24n of the SiC wafer 24 is aligned in height with the upper surfaces (the back surface of the SiC wafer 24) of the three lift-up pins 15. In addition, the ring 122 is configured so that the terrace portion 12t is not formed in the area corresponding to the notch portion 24n and its surrounding area. Therefore, the groove 2n, which serves as a gas escape flow path for releasing the source gas G1 into the space S13 above the disk, can be made deeper than the groove 2 having the terrace portion 12t as its bottom surface.

[0175] When the susceptor 21 of embodiment 2 is applied to the semiconductor manufacturing apparatus 50 shown in Figure 25, the satellite disk 183 is replaced with a susceptor 21 including a ring 122, a satellite disk 13, and three lift-up pins 15, and the SiC wafer 184 is replaced with a SiC wafer 24.

[0176] 14 to 17 according to the second embodiment is applied to the semiconductor manufacturing apparatus 50 shown in Fig. 25. In a planetary susceptor-type CVD apparatus, the source gas G1 is supplied from the outside of the rotating susceptor 132. When the notch portion 24n of the SiC wafer 24 approaches the injector 186 and the source gas G1 is supplied from the notch portion 24n side, part of the source gas G1 flows into the space above the disk S13 through the gap between the SiC wafer 24 and the wall portion 12c and the groove 2n.

[0177] As mentioned above, groove 2n is formed deeper than groove 2, which has terrace portion 12t as its bottom surface, so that the raw material gas G1 supplied above notch portion 24n of SiC wafer 24 can be smoothly released into the disk upper space S13 on the back side of SiC wafer 24.

[0178] On the other hand, if the lower surface of the wall portion 12c becomes lower than the back surface of the SiC wafer 24, there is a concern that the wall portion 12c will extend into the groove 2n, thereby hindering the function of the groove 2n as a gas escape path. Therefore, the position of the lower surface of the wall portion 12c is set to be higher than the height of the upper surfaces of the three lift-up pins 15 (the back surface of the SiC wafer 24).

[0179] The susceptor 21, which is the basic configuration of the wafer loading device according to the second embodiment of the present disclosure, places a semiconductor wafer, i.e., an SiC wafer 24, on three lift-up pins 15, thereby realizing a semiconductor wafer loading state for the SiC wafer 24. This allows a space S13 above the disk to be provided between the rear surface of the SiC wafer 24 and the front surface 13s of the satellite disk 13.

[0180] Furthermore, in the susceptor 21 of the second embodiment, when the semiconductor wafer is mounted, a groove 2, which is an annular groove, is formed between the upper layer 13u of the satellite disk 13 and the ring 122 on the back surface side of the SiC wafer 24.

[0181] Therefore, when the raw material gas G1 is supplied above the surface of the SiC wafer 24 in the semiconductor wafer-mounted state, a portion of the raw material gas G1 can be intentionally released into the disk-above space S13 on the back side of the SiC wafer 24 through the annular gap and groove 2 along the outer periphery of the SiC wafer 24.

[0182] As a result, when the susceptor 21 of the second embodiment performs an epitaxial growth process to form an epitaxial growth layer on the surface of the SiC wafer 24 with the semiconductor wafer mounted thereon, it is possible to suppress the occurrence of an epi-crown phenomenon, in which the epitaxial thickness of the epitaxial growth layer increases locally. This epi-crown phenomenon occurs mainly in the outer periphery of the surface of the SiC wafer 24.

[0183] As a result, the susceptor 21 of the second embodiment has the effect of being able to form an epitaxial layer with excellent in-plane uniformity on the surface of the SiC wafer 24 in the state where the semiconductor wafer is mounted thereon. Note that the in-plane uniformity can be measured by the epitaxial thickness and the carrier concentration (impurity concentration).

[0184] Furthermore, since the height of the top surface of the ring 122 can be set arbitrarily, the wafer-susceptor top distance DT, which is the difference in height between the surface of the SiC wafer 24 placed on the three lift-up pins 15 and the top surface of the ring 122, can be set to an optimal length that does not result in an extreme reduction in epitaxial thickness at the outer periphery of the surface of the SiC wafer 24.

[0185] The opening O122 of the ring 122 includes the SiC wafer 24 and has a formation area larger than that of the SiC wafer 24, so that the SiC wafer 24 can be securely placed on the three lift-up pins 15 without coming into contact with the ring 122, including the wall portion 12c that becomes the notch-side protruding wall portion.

[0186] Furthermore, by forming the opening O122 in an approximate shape to the shape of the SiC wafer 24, the susceptor 21 of the second embodiment can effectively suppress the occurrence of epi-crowns.

[0187] In addition, the wall portion 12c, which is the notch-side protruding wall portion, is not in contact with the peripheral surface 13d of the peripheral portion 13p of the satellite disk 13, and therefore does not degrade the function of the groove 2n formed below the wall portion 12c as a gas escape flow path.

[0188] In the susceptor 21 of embodiment 2, the formation height of the lower surface of the wall portion 12c, which is the notch-side protruding wall portion, is set to be greater than the formation height of the upper surfaces of the three lift-up pins 15, so that the function of the groove 2n as a gas escape flow path is not deteriorated.

[0189] Additionally, in the susceptor 21 of the second embodiment, the upper surface of the wall portion 12c, which is the notch-side protruding wall portion, is provided so as to form part of the upper surface of the ring 122. That is, the formation height of the upper surface of the wall portion 12c is the same as the formation height of the upper surface of the ring 122. Therefore, the groove 2n serving as a gas escape channel can be formed below the wall portion 12c, which has a sufficient thickness.

[0190] Furthermore, in the semiconductor wafer-mounted state, the wall portion 12c, which is the notch-side protruding wall portion, faces the SiC wafer 24 and is disposed so as to fill a portion of the notch portion 24n without contacting the SiC wafer 24, thereby restricting the amount of source gas G1 flowing into the groove 2n via the notch portion 24n so as not to exceed the allowable upper limit. If the source gas G1 exceeds the allowable upper limit and flows into the groove 2n via the notch portion 24n, the amount of source gas G1 supplied to the surface of the SiC wafer 24 may fall below an appropriate amount.

[0191] Therefore, the susceptor 21 of the second embodiment can supply an appropriate amount of source gas G1 to the surface of the SiC wafer 24 having the notch portion 24n.

[0192] Thus, the susceptor 21 having the basic configuration of the second embodiment has the same effects as the susceptor 11 having the basic configuration of the first embodiment, except that the mounting target is changed from the SiC wafer 14 to the SiC wafer 24.

[0193] Also in the second embodiment, modifications similar to the first and second modifications of the first embodiment shown in FIGS. 6 to 13 can be configured.

[0194] That is, as a first modification, the surface 13s of the upper layer 13u of the satellite disk 13 may be modified to have a concave shape with a recessed center. Also, as a second modification, two auxiliary terrace portions may be provided between the terrace portion 12t and the wall portion 12c in plan view.

[0195] 17, the radial length of the notch 24n, i.e., the notch length Ln, is shorter than the length of the orientation flat 14k, so the possibility of epi-crown occurrence is expected to be relatively low. In this case, it is possible to suppress the epi-crown phenomenon simply by not forming the terrace 12t in the notch 24n or its vicinity, without providing the wall 12c. If this possibility is realized, a configuration in which the wall 12c is omitted may be considered.

[0196] However, if the wall portion 12c is not formed on the ring 121, it may be difficult to align the notch portion 24n of the SiC wafer 24 with the non-terrace region where the terrace portion 12t is not formed when the SiC wafer 24 is mounted. Therefore, it is desirable to form the wall portion 12c on the ring 121. If the wall portion 12c is not formed, the difficulty in alignment can be alleviated by ensuring a large non-terrace region.

[0197] In the susceptor 21, which is the basic configuration of embodiment 2, the terrace portion 12t is supported from below on the surface of the peripheral portion 13p of the satellite disk 13, but as long as there is no problem with strength, multiple partial terrace portions may be provided discretely instead of the continuously formed terrace portion 12t, as in embodiment 1.

[0198] <Third Embodiment> (Basic configuration) Fig. 18 is an explanatory diagram schematically showing the planar configuration of susceptor 31, which is the basic configuration of embodiment 3 of the present disclosure. Fig. 19 is an explanatory diagram schematically showing the configuration of the A3-A3 cross section of Fig. 18, Fig. 20 is an explanatory diagram schematically showing the configuration of the B3-B3 cross section of Fig. 18, and Fig. 21 is an explanatory diagram schematically showing the configuration of the C3-C3 cross section of Fig. 18. Fig. 18 schematically shows the planar structures of ring 12, which is a main component of susceptor 31, and SiC wafer 34 to be mounted, in an easily recognizable manner.

[0199] The susceptor 31, which is the basic configuration of the wafer loading device of the third embodiment, is intended to load a SiC wafer 34. In Fig. 18, the SiC wafer 34 is formally illustrated as a circle in a plan view, but the SiC wafer 34 represents either the SiC wafer 14 or the SiC wafer 24. That is, the susceptor 31 of the third embodiment is intended to load a SiC wafer 14 having an orientation flat portion 14k or a SiC wafer 24 having a notch portion 24n.

[0200] Hereinafter, the same reference numerals will be used to designate components similar to those of the susceptor 11 having the basic configuration of the first embodiment shown in Figures 1 to 5, and explanations will be omitted as appropriate. The following description will focus on the features of the susceptor 31 having the basic configuration of the third embodiment.

[0201] 18 to 21 show the ring 12 assuming that the SiC wafer 34 is the SiC wafer 14. Therefore, when the SiC wafer 34 is the SiC wafer 24, the ring 122 shown in FIGS. 14 to 16 is used instead of the ring 12.

[0202] For convenience of explanation, the susceptor 31 of the third embodiment will be described below assuming that the SiC wafer 34 is the SiC wafer 14.

[0203] As shown in FIGS. 18 to 21, the susceptor 31 includes, as its main components, a combination of a ring 12 and satellite disks 13, which are disks that are circular and have a convex cross section when viewed from above.

[0204] The satellite disk 13, which is a disk of the basic configuration, has an upper layer portion 13u that is a convex portion, and has a peripheral portion 13p around the upper layer portion 13u.

[0205] Three lift-up pins 25, which are multiple lift-up members each having the same height, are placed on the front surface 13s of the upper layer 13u of the satellite disk 13. The three lift-up pins 25 support the SiC wafer 34 from the back surface, thereby holding the SiC wafer 34.

[0206] In the susceptor 31 of the third embodiment, the surface 13s of the upper layer 13u of the satellite disk 13 serves as a lift-up region.

[0207] Furthermore, a support member 17 having a circular ring shape in plan view is disposed under the outer periphery of the rear surface of the satellite disk 13, and the support member 17 supports the satellite disk 13.

[0208] As described above, the susceptor 31, which is the basic configuration of the third embodiment, includes the ring 12, the satellite disks 13, the three lift-up pins 25, and the support member 17 as main components.

[0209] In the susceptor 31 of the third embodiment having such a configuration, the SiC wafer 34 can be held by placing the SiC wafer 34 on the three lift-up pins 25 so that the SiC wafer 34 fits within the opening O12 in plan view without coming into contact with the ring 12. This state is the semiconductor wafer-mounted state for the SiC wafer 34.

[0210] When the SiC wafer 34 is placed on the three lift-up pins 25, a space S13 above the disk is formed between the surface 13s of the upper layer 13u of the satellite disk 13 and the back surface of the SiC wafer 34, except for the area where the three lift-up pins 25 are formed.

[0211] Furthermore, between the upper layer 13u of the satellite disk 13 on the rear surface side of the SiC wafer 34 and the ring 12, a groove 2 is formed, which is an annular groove that is annular along the outer periphery of the opening O12 in plan view.

[0212] One side of the annular groove 2 is the side of the upper layer 13u, and the other side is the wall 12a. The groove 2 formed in the region where the terrace 12t is formed serves as the space above the terrace 12t, with the terrace 12t as its bottom.

[0213] On the other hand, as shown in Figure 19, in the area where the terrace portion 12t is not formed, the groove 2 directly below the wall portion 12b becomes groove 2k, and as shown in Figure 21, the groove 2 located directly below the peripheral areas at both ends of the wall portion 12b becomes groove 2m.

[0214] The terrace portion 12t of the ring 12 is provided so as not to come into contact with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2X that communicates with the groove 2 in the depth direction can be provided between the tip of the terrace portion 12t and the side surface of the upper layer portion 13u.

[0215] When the susceptor 31 of embodiment 3 is applied to the semiconductor manufacturing apparatus 50 shown in Figure 25, the satellite disk 183 is replaced with a susceptor 31 including a ring 12, a satellite disk 13, three lift-up pins 25, and a support material 17, and the SiC wafer 184 is replaced with a SiC wafer 34.

[0216] The susceptor 31, which is the basic configuration of the wafer loading device according to the third embodiment of the present disclosure, places a semiconductor wafer, i.e., an SiC wafer 34, on three lift-up pins 25, which are a plurality of lift-up members, thereby realizing a semiconductor wafer loading state for the SiC wafer 34. Therefore, a space S13 above the disk can be provided between the back surface of the SiC wafer 34 and the front surface 13s of the satellite disk 13.

[0217] Furthermore, in the susceptor 31 of the third embodiment, when the semiconductor wafer is mounted, a groove 2, which is an annular groove, is formed between the upper layer 13u of the satellite disk 13 and the ring 12 on the back side of the SiC wafer .

[0218] As a result, the susceptor 31 of the third embodiment, like the first and second embodiments, has the effect of being able to form an epitaxial layer with excellent in-plane uniformity on the surface of the SiC wafer 34 with the semiconductor wafer mounted thereon. Note that the in-plane uniformity indexes include the epitaxial thickness and the carrier concentration (impurity concentration).

[0219] Thus, the susceptor 31, which is the basic configuration of the third embodiment, has the same effects as the susceptors 11 and 21, which are the basic configurations of the first and second embodiments, and further has the following unique effects.

[0220] The susceptor 31 of the third embodiment has the surface 13s of the upper layer 13u of the satellite disk 13 as a lift-up region, and can stably support the SiC wafer 34 by three lift-up pins 25 placed on the surface 13s.

[0221] Furthermore, the susceptor 31 of the third embodiment can suppress the phenomenon of warping of the satellite disk 13 carrying the SiC wafer 34 via the three lift-up pins 25 by using the support material 17 that supports the satellite disk 13 from the backside.

[0222] Also in the third embodiment, modifications similar to the first and second modifications of the first embodiment can be configured.

[0223] That is, as a first modification, the surface 13s of the upper layer 13u of the satellite disk 13 may be modified to have a concave shape with a recessed center. However, in order to stably support the SiC wafer 34, it is desirable to make the area of ​​the surface 13s of the upper layer 13u on which the three lift-up pins 25 are placed flat.

[0224] As a second modified example, two auxiliary terraces may be provided between the terrace 12t and the wall 12b (wall 12c) in plan view.

[0225] <Fourth Embodiment> (Basic configuration) Fig. 22 is an explanatory diagram schematically showing the planar configuration of susceptor 41, which is the basic configuration of embodiment 4 of the present disclosure. Fig. 23 is an explanatory diagram schematically showing the configuration of the A4-A4 cross section of Fig. 22, and Fig. 24 is an explanatory diagram schematically showing the configuration of the B4-B4 cross section of Fig. 22. Note that Fig. 22 schematically illustrates the planar structures of ring 22 and satellite disks 23, which are main components of susceptor 41, in an easily recognizable manner.

[0226] Susceptor 41, which is the basic configuration of the wafer mounting device of embodiment 4, is intended to mount SiC wafer 14 having orientation flat portion 14k. That is, susceptor 41 of embodiment 4 is a wafer mounting device that mounts SiC wafer 14 having orientation flat portion 14k.

[0227] Hereinafter, the same reference symbols will be used to designate components similar to those of the susceptor 11 of the basic configuration of embodiment 1 shown in Figures 1 to 5, and explanations will be omitted as appropriate. The description will focus on the features of the susceptor 41 of the basic configuration of embodiment 4.

[0228] As shown in FIGS. 22 to 24, the susceptor 41 includes, as its main components, a combination of satellite disks 23, which are disks that are circular and have a convex cross section in plan view, and a ring 22.

[0229] Walls 22a and 22b that form the inner peripheral surface are provided on ring 22. That is, in ring 22, wall 22b is selectively provided as part of the inner peripheral surface of ring 22, and wall 22a that forms a uniform inner peripheral surface is provided in the area where wall 22b cannot be provided.

[0230] The ring 22 has an opening O22 whose outer periphery is defined by the wall portions 22a and 22b. The opening O22 has a shape similar to the wafer shape of the SiC wafer 14, includes the SiC wafer 14 in plan view, and has a planar shape slightly wider than the SiC wafer 14.

[0231] Wall 22b of ring 22 functions as a notch-side protruding wall that protrudes toward opening O22 in correspondence with orientation flat 14k, which is a notch in SiC wafer 14. As shown in Fig. 22, wall 22b is arranged parallel to orientation flat 14k in plan view, and a gap space S22 with a constant length in the short direction exists between wall 22b and orientation flat 14k.

[0232] Satellite disk 23, which is a disk with a basic configuration, has upper layer portion 23u, which is a convex portion, intermediate peripheral portion 23m, which is a first peripheral portion, around upper layer portion 23u, and outermost peripheral portion 23p, which is a second peripheral portion, around intermediate peripheral portion 23m. In satellite disk 23, the formation height decreases in the order of surface 23s of upper layer portion 23u, intermediate peripheral surface 23d of intermediate peripheral portion 23m, and outermost peripheral surface 23e of outermost peripheral portion 23p.

[0233] The ring 22 is placed on the satellite disk 23 in such a manner that the bottom surface of the ring 22 is supported on the outermost peripheral surface 23e of the outermost peripheral portion 23p, which is the second peripheral portion of the satellite disk 23, along the entire circumference of the opening O22.

[0234] As shown in FIG. 23, the wall portion 22b serving as the notch-side protruding wall portion is not in contact with the intermediate peripheral surface 23d of the intermediate peripheral portion 23m of the satellite disk 23.

[0235] In the susceptor 41 having the mechanical configuration of the fourth embodiment, the surface 23s of the upper layer 23u serves as a lift-up region for the three lift-up pins 25.

[0236] Three lift-up pins 25, each having the same height, are placed on the front surface 23s of the upper layer 23u of the satellite disk 23. The three lift-up pins 25 support the SiC wafer 14 from the back surface, thereby holding the SiC wafer 14.

[0237] Furthermore, a support member 27 having a circular ring shape in plan view is disposed under the outer periphery of the rear surface of the satellite disk 23, and the support member 27 supports the satellite disk 23.

[0238] Thus, the susceptor 41, which is the basic configuration of the fourth embodiment, includes the ring 22, the satellite disk 23, the three lift-up pins 25, and the support member 27 as main components.

[0239] In the susceptor 41 of the fourth embodiment having such a configuration, the SiC wafer 14 can be held by placing the SiC wafer 14 on the three lift-up pins 25 so that the SiC wafer 14 fits within the opening O22 in plan view without coming into contact with the ring 22. This state is the semiconductor wafer-mounted state for the SiC wafer 14.

[0240] When the SiC wafer 14 is in the semiconductor wafer loaded state, the wall portion 22b, which is the notch-side protruding wall portion, and the orientation flat portion 14k are positioned opposite each other with a gap space S22 at a fixed interval therebetween.

[0241] When the SiC wafer 14 is placed on the three lift-up pins 25, a space S23 above the disk is formed between the surface 23s of the upper layer 23u of the satellite disk 23 and the back surface of the SiC wafer 14, except for the area where the three lift-up pins 25 are formed.

[0242] Furthermore, between the upper layer 23u of the satellite disk 23 on the rear surface side of the SiC wafer 14 and the ring 12, a groove 2 is formed, which is an annular groove that is annular in shape along the outer periphery of the opening O22 in plan view.

[0243] One side of the annular groove 2 is the side of the upper layer 23u, and the other side is the wall 12a. As shown in Fig. 23, the groove 2 directly below the wall 12b is a groove 2k.

[0244] When the susceptor 41 of the fourth embodiment is applied to the semiconductor manufacturing apparatus 50 shown in FIG. 25, the satellite disk 183 is replaced with a susceptor 41 including a ring 22, a satellite disk 23, three lift-up pins 25, and a support material 27, and the SiC wafer 184 is replaced with the SiC wafer 14.

[0245] The susceptor 41, which is the basic configuration of the wafer loading device according to the fourth embodiment of the present disclosure, places the SiC wafer 14 on three lift-up pins 25, thereby realizing a semiconductor wafer loading state for the SiC wafer 14. This allows a space S23 above the disk to be provided between the back surface of the SiC wafer 14 and the front surface 23s of the satellite disk 23.

[0246] Furthermore, in the susceptor 41 of the fourth embodiment, groove 2, which is an annular groove, is formed between the upper layer 23u of the satellite disk 23 and the ring 22 on the back surface side of the SiC wafer 14 when the semiconductor wafer is mounted thereon.

[0247] As a result, the susceptor 41 of the fourth embodiment, like the first to third embodiments, has the effect of being able to form an epitaxial layer with excellent in-plane uniformity on the surface of the SiC wafer 14 with the semiconductor wafer mounted thereon. Note that the in-plane uniformity indexes include the epitaxial thickness and the carrier concentration (impurity concentration).

[0248] Thus, the susceptor 41, which is the basic configuration of the fourth embodiment, has the same effects as the susceptors 11, 21 and 31, which are the basic configurations of the first to third embodiments, and further has the following unique effects.

[0249] In the susceptor 41 of the fourth embodiment, the ring 22 is placed on the satellite disk 23 in such a manner that the bottom surface of the ring 22 is supported along the entire circumference of the opening O22 on the outermost peripheral surface 23e of the outermost peripheral portion 23p, which is the second peripheral portion of the satellite disk 23. Therefore, in the susceptor 41 of the fourth embodiment, a combined structure of the satellite disk 23 and the ring 22 can be realized without affecting the SiC wafer 14.

[0250] Also in the fourth embodiment, a modification similar to the first modification of the first embodiment can be configured.

[0251] That is, as a first modification, the surface 23s of the upper layer 23u of the satellite disk 23 may be changed to a concave shape with a recessed center. However, in order to stably support the SiC wafer 14, it is desirable to make the area on the surface 23s of the upper layer 23u where the three lift-up pins 25 are placed flat.

[0252] Although the susceptor 41 of the fourth embodiment is designed to carry the SiC wafer 14, it may also be designed to carry the SiC wafer 24, as in the susceptor 21 of the second embodiment. In this case, the ring 22 is provided with a wall portion having a structure similar to the wall portion 12c, instead of the wall portion 22b.

[0253] <Application to semiconductor manufacturing equipment> As described above, the semiconductor manufacturing apparatus 50 shown in FIG. 25 can be configured using the wafer mounting devices shown in the first to fourth embodiments as components.

[0254] When the susceptor 11 of the first embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced with the susceptor 11 including the ring 12, the satellite disk 13, and the three lift-up pins 15, and the SiC wafer 184 is replaced with the SiC wafer .

[0255] 26 is an explanatory diagram schematically showing the planar configuration of semiconductor manufacturing equipment 51. Semiconductor manufacturing equipment 51 is a novel semiconductor manufacturing equipment in which semiconductor manufacturing equipment 50 shown in FIG. 25 is applied to susceptor 11 of the first embodiment.

[0256] As shown in the figure, the planetary susceptor 182 accommodates eight susceptors 11, each having a ring 12, a satellite disk 13, and three lift-up pins 15 as its main components. That is, in the upper layer of the planetary susceptor 182, eight susceptors 11 are arranged as eight satellite disks 183 around a center part 187.

[0257] Each of the eight susceptors 11 carries a SiC wafer 14 and rotates along a disk rotation direction R183. The planetary susceptor 182 itself also rotates along a susceptor rotation direction R182.

[0258] When the susceptor 21 of the second embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced with a susceptor 21 including the ring 122, the satellite disk 13, and the three lift-up pins 15, and the SiC wafer 184 is replaced with the SiC wafer 24.

[0259] When the susceptor 31 of embodiment 3 is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced with a susceptor 31 including a ring 12, a satellite disk 13, three lift-up pins 25, and a support material 17, and the SiC wafer 184 is replaced with a SiC wafer 34.

[0260] When the susceptor 41 of embodiment 4 is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced with a susceptor 41 including a ring 22, a satellite disk 23, three lift-up pins 25, and a support material 27, and the SiC wafer 184 is replaced with the SiC wafer 14.

[0261] Semiconductor manufacturing apparatus 51, which includes any one of the wafer mounting apparatuses according to the first to fourth embodiments as a constituent element, is a novel semiconductor manufacturing apparatus. Both SiC wafer 14 and SiC wafer 24 are semiconductor wafers made of silicon carbide.

[0262] The semiconductor manufacturing equipment 51 has an induction heating coil 188 as a heating mechanism for heating the semiconductor wafer mounted thereon.

[0263] The novel semiconductor manufacturing apparatus 51 heats the SiC wafer 14 with the semiconductor wafer mounted thereon by the induction heating coil 188, which is a heating mechanism, and supplies a source gas G1 for epitaxial growth above the surface of the SiC wafer 14, thereby forming an epitaxial layer containing silicon carbide with good in-plane uniformity on the surface of the SiC wafer 14. Note that the epitaxial thickness and carrier concentration (impurity concentration) are included as indicators of in-plane uniformity.

[0264] <Method for manufacturing a semiconductor device and a semiconductor device manufactured by the manufacturing method> 27 is a flowchart showing the procedure of a method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51. The method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus 51 to which the susceptor 11 of the first embodiment is applied will be described below.

[0265] In step ST1, a SiC wafer 14 serving as a silicon carbide semiconductor substrate is placed on three lift-up pins 15, whereby the SiC wafer 14 is mounted by the susceptor 11.

[0266] That is, in step ST1, the SiC wafer 14 is placed on the three lift-up pins 15 so that the SiC wafer 14 fits within the opening O12 in a planar view without coming into contact with the ring 12, thereby realizing a semiconductor wafer-mounted state for the SiC wafer 14.

[0267] In step ST2, epitaxial growth processing is performed on the surface of the SiC wafer 14 with the semiconductor wafer mounted thereon. That is, a source gas G1 for epitaxial growth is supplied to the surface of the SiC wafer 14, and the SiC wafer 14 is heated by an induction heating coil 188, which is a heating mechanism.

[0268] As a result, an epitaxial layer is formed on the surface of the SiC wafer 14 in the semiconductor wafer-mounted state.

[0269] Thereafter, in step ST3, a semiconductor layer for element formation is formed in the epitaxial layer, and then in step ST4, a surface structure for element formation is formed on the semiconductor layer for element formation.

[0270] As a result, semiconductor devices can be fabricated with device-forming semiconductor layers and surface structures.

[0271] FIG. 28 is a cross-sectional view showing the cross-sectional structure of a semiconductor device 100, which is an example of a semiconductor device manufactured by the semiconductor device manufacturing method shown in FIG.

[0272] As shown in the figure, an epitaxial layer of N is formed on the surface of a SiC substrate 61 corresponding to the SiC wafer 14. - An epitaxial layer 62 is provided. - A P base layer 63 is selectively provided on the upper layer of the epitaxial layer 62, and an N source layer 64 is selectively provided in the surface of the P base layer 63. A P source layer 64 is formed between the N source layers 64, 64 in the surface of the P base layer 63. + A contact layer 65 is provided.

[0273] A gate electrode 67 is formed between a pair of N source layers 64, 64 that are formed in different P base layers 63 and adjacent to each other, with a gate oxide film 66 interposed therebetween. The gate electrode 67 extends from above the N source layer 64 provided in the surface of one of the P base layers 63 to above the one of the P base layers 63, -It is formed above the epitaxial layer 62, above the other P base layer 63, and above the N source layer 64 provided in the surface of the other P base layer 63. An interlayer insulating film 68 is provided to cover the gate oxide film 66 and the gate electrode 67.

[0274] Such combinations of gate oxide films 66, gate electrodes 67, and interlayer insulating films 68 are formed in multiple locations. Therefore, the semiconductor device 100 has multiple gate oxide films 66, multiple gate electrodes 67, and multiple interlayer insulating films 68. The N-type insulating film including the multiple interlayer insulating films 68 is - A source electrode 69 is provided on the entire surface of the epitaxial layer 62 , and a drain electrode 70 is provided on the rear surface of the SiC substrate 61 .

[0275] Hereinafter, a process for manufacturing the semiconductor device 100 shown in FIG. 28 by the semiconductor device manufacturing method shown in FIG. 27 will be described.

[0276] The process of step ST1 is a process of mounting the SiC wafer 14, which will eventually become the SiC substrate 61, on the susceptor 11.

[0277] The process of step ST2 is a process of supplying a source gas G1 for epitaxial growth onto the surface of the SiC wafer 14 mounted in the semiconductor manufacturing equipment 51, and heating the SiC wafer 14 by the induction heating coil 188.

[0278] As a result, epitaxial growth processing is performed on the surface of the SiC substrate 61, and N - An epitaxial layer 62 is formed. Here, the SiC substrate 61 and the N - The concentration of the n-type impurity contained in the epitaxial layer 62 is appropriately selected depending on the breakdown voltage of the semiconductor device to be fabricated.

[0279] Next, N - A semiconductor layer for forming elements is formed in the epitaxial layer 62. -P-type impurity and n-type impurity ions are implanted into the epitaxial layer 62, and the implanted ions are converted into N - Diffusion within the epitaxial layer 62 forms a P base layer 63, an N source layer 64, and a P + A contact layer 65 can be formed on each.

[0280] P base layer 63, N source layer 64, and P + The contact layer 65 is a semiconductor layer for forming an element. + This is the process for forming the contact layer 65.

[0281] Next, the P base layer 63, the N source layer 64 and the P + N containing contact layer 65 - On the surface of the epitaxial layer 62, a gate oxide film 66, a gate electrode 67 and an interlayer insulating film 68 are selectively formed.

[0282] First, the SiC wafer 14 is heated in an oxygen-containing atmosphere to form a gate oxide film 66 made of SiO2 on the upper surface of the semiconductor layer for element formation. Then, polysilicon doped with n-type or p-type impurities is deposited on the gate oxide film 66 using a CVD (Chemical Vapor Deposition) method or the like to form a gate electrode 67.

[0283] Thereafter, an interlayer insulating film 68 is formed on the gate electrode 67. The interlayer insulating film 68 is made of, for example, SiO2 or TEOS (Tetraethyl Orthosilicate). Through these steps, a plurality of gate oxide films 66, a plurality of gate electrodes 67, and a plurality of source electrodes 69 are selectively formed.

[0284] Then, a mask is applied to the upper surface of the interlayer insulating film 68, and a part of the interlayer insulating film 68 is etched through the opening in the resist to form a contact hole 59 penetrating the interlayer insulating film 68. The contact hole 59 is connected to the N source layer 64 and the P +It is formed on the surface of the contact layer 65 .

[0285] Next, a barrier metal (not shown) is formed in the contact hole 59 of the interlayer insulating film 68 and on the interlayer insulating film 68. The barrier metal is formed by depositing Ti, TiN, or the like using a PVD (Physical Vapor Deposition) method or a CVD method.

[0286] Next, a source electrode 69 is formed on the barrier metal. The source electrode 69 can be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal using a PVD method such as sputtering or vapor deposition.

[0287] Next, a drain electrode 70 is formed on the rear surface of the SiC substrate 61. The drain electrode 70 is formed by depositing an aluminum silicon alloy, titanium, or the like using a PVD method such as sputtering or vapor deposition. Alternatively, the drain electrode 70 may be formed by stacking multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold.

[0288] The surface structure for element formation is a gate oxide film 66, a gate electrode 67, an interlayer insulating film 68, a source electrode 69, and a drain electrode 70. That is, the processing of step ST4 is processing for forming the gate oxide film 66, the gate electrode 67, the interlayer insulating film 68, the source electrode 69, and the drain electrode 70.

[0289] Since multiple semiconductor devices 100, which are silicon carbide semiconductor devices, are fabricated in a matrix on a single SiC wafer 14, the single SiC wafer 14 is cut into individual semiconductor devices 100 by laser dicing or blade dicing to form chips, thereby completing the semiconductor device 100 shown in Figure 28.

[0290] As a result, it is possible to manufacture a semiconductor device 100 having an NMOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) as a semiconductor element constituted by the semiconductor layer and surface structure for element formation.

[0291] In this way, in the semiconductor device 100 manufactured by the semiconductor manufacturing method using the semiconductor manufacturing apparatus 51 having the planetary susceptor 182, N - The epitaxial layer 62 has high in-plane uniformity in epitaxial thickness, etc., and N - In the process after the formation of the epitaxial layer 62, a structure that results in poor electrical characteristics can be suppressed, thereby improving productivity.

[0292] Furthermore, since it is possible to prevent the electrical characteristics from becoming poor when forming a semiconductor layer for forming elements by ion implantation or the like, it is possible to obtain the semiconductor device 100 having a highly reliable NMOSFET.

[0293] The method for manufacturing the semiconductor device shown in FIG. 27 includes at least the following steps (a) to (c).

[0294] Step (a) is a step of mounting the SiC wafer 14 (SiC substrate 61) on three lift-up pins 15 so that the SiC wafer 14 fits within the opening O12 in a planar view without coming into contact with the ring 12, thereby realizing a semiconductor wafer mounting state for the SiC wafer 14.

[0295] Step (b) is a step of supplying a source gas G1 for epitaxial growth onto the surface of the SiC wafer 14 in the state where the semiconductor wafer is mounted.

[0296] Step (c) is a step of heating the SiC wafer 14 with the semiconductor wafer mounted thereon by the induction heating coil 188, which is a heating mechanism.

[0297] Step (a) corresponds to step ST1 shown in FIG. 27, and steps (b) and (c) correspond to step ST2 shown in FIG.

[0298] Therefore, after the above steps (a) to (c) are performed, the N - An epitaxial layer 62 is formed.

[0299] The method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51 performs steps (a) to (c) to form an epitaxial layer containing silicon carbide on the surface of the SiC wafer 14 in a semiconductor wafer mounting state. - The epitaxial layer 62 can be formed with good in-plane uniformity. Note that the epitaxial thickness and carrier concentration (impurity concentration) are included as indicators of in-plane uniformity.

[0300] That is, by the method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51, N formed on the SiC wafer 14 in a semiconductor wafer-mounted state - The in-plane uniformity of the epitaxial layer 62 can be improved.

[0301] The semiconductor device 100, which is a semiconductor device manufactured by the semiconductor device manufacturing method using the novel semiconductor manufacturing apparatus 51, has high in-plane uniformity of N - Since the semiconductor layer for element formation is formed in the epitaxial layer 62, it is possible to improve the reliability of the NMOSFET, which is a semiconductor element configured including the semiconductor layer for element formation.

[0302] It should be noted that, within the scope of the present disclosure, it is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0303] Various aspects of the present disclosure are summarized below as appendices.

[0304] (Appendix 1) A wafer mounting device for mounting a semiconductor wafer having a notch, a disk having a convex upper layer; a ring disposed on the disk and having a central opening; a plurality of lift-up members disposed on a lift-up region provided on the disk or the ring for supporting the semiconductor wafer from the backside; The ring has a notch-side protruding wall portion that protrudes toward the opening, In a semiconductor wafer loaded state in which the semiconductor wafer is placed on the plurality of lift-up members so that the semiconductor wafer fits within the opening in a plan view without coming into contact with the ring, the notch-side protruding wall portion faces the notch portion of the semiconductor wafer, and a space above the disk is formed between the surface of the upper layer portion of the disk and the back surface of the semiconductor wafer, except for an area where the plurality of lift-up members are formed, and an annular groove is formed along the outer periphery of the opening in a plan view between the upper layer portion of the disk on the back surface side of the semiconductor wafer and the ring, a side surface of the upper layer of the disk that forms a side surface of the annular groove; Wafer mounting equipment.

[0305] (Appendix 2) 2. The wafer loading device according to claim 1, the disk has a peripheral portion around the upper layer portion, the surface of the peripheral portion is lower in height than the surface of the upper layer portion, and a step exists between the surface of the peripheral portion and the surface of the upper layer; the ring has a terrace portion protruding toward the opening, the terrace portion not overlapping the notch-side protruding wall portion in a plan view, the ring is placed on the disk with the terraces supported on the peripheral surface of the disk; a thickness in a height direction of the terrace portion is thinner than the step in the disk; Wafer mounting equipment.

[0306] (Appendix 3) 3. The wafer loading device according to claim 2, the plurality of lift-up members are placed on the surface of the terrace portion of the ring; the lift-up region includes a surface region of the terrace portion, Wafer mounting equipment.

[0307] (Appendix 4) 4. The wafer mounting device according to claim 2, the terrace portion is not in contact with the side surface of the upper layer portion; Wafer mounting equipment.

[0308] (Appendix 5) 5. A wafer mounting device according to any one of Supplementary Note 2 to Supplementary Note 4, the opening includes the semiconductor wafer and has a formation area larger than the semiconductor wafer; the notch-side protruding wall portion does not contact the surface of the peripheral portion of the disk; Wafer mounting equipment.

[0309] (Appendix 6) 6. The wafer loading device according to claim 5, a formation height of the lower surface of the notch-side protruding wall portion is set to be equal to or greater than a formation height of the upper surfaces of the plurality of lift-up members; Wafer mounting equipment.

[0310] (Appendix 7) 10. The wafer mounting device according to claim 5 or 6, The upper surface of the notch-side protruding wall portion forms part of the upper surface of the ring. Wafer mounting equipment.

[0311] (Appendix 8) 10. A wafer mounting device according to any one of Supplementary Note 1 to Supplementary Note 7, The upper layer of the disk has a concave shape with a concave central portion. Wafer mounting equipment.

[0312] (Appendix 9) 4. The wafer loading device according to claim 3, the ring further has, in addition to the terrace portion, an auxiliary terrace portion protruding toward the opening portion, the auxiliary terrace portion being provided between the terrace portion and the notch-side protruding wall portion in a plan view, and having a thickness in a height direction smaller than that of the terrace portion; the ring is placed on the disk in such a manner that the terrace portion and the auxiliary terrace portion are supported on the peripheral surface of the disk; Wafer mounting equipment.

[0313] (Appendix 10) 3. The wafer loading device according to claim 2, the plurality of lift-up members are placed on the upper layer of the disk; the lift-up region includes a surface region of the upper layer; Wafer mounting equipment.

[0314] (Appendix 11) 11. The wafer loading device of claim 10, Further provided is a support member that supports the disk from the rear surface. Wafer mounting equipment.

[0315] (Appendix 12) 2. The wafer loading device according to claim 1, the disk has a first peripheral portion around the periphery of the upper layer portion, and a second peripheral portion around the periphery of the first peripheral portion, and the formation height decreases in the order of the surface of the upper layer portion, the surface of the first peripheral portion, and the surface of the second peripheral portion; the ring is placed on the disk such that a bottom surface of the ring rests on the second peripheral surface of the disk along the entire circumference of the opening; Wafer mounting equipment.

[0316] (Appendix 13) A wafer loading device according to any one of Supplementary Note 1 to Supplementary Note 12. the cutout portion includes an orientation flat portion, the notch-side protruding wall portion is disposed so as to face the orientation flat portion with a fixed gap therebetween when the semiconductor wafer is mounted. Wafer mounting equipment.

[0317] (Appendix 14) A wafer loading device according to any one of Supplementary Note 1 to Supplementary Note 12. the cutout portion includes a notch portion, the notch-side protruding wall portion is disposed so as to fill a part of the notch portion without coming into contact with the semiconductor wafer when the semiconductor wafer is mounted. Wafer mounting equipment.

[0318] (Appendix 15) A semiconductor manufacturing apparatus having a wafer mounting device according to any one of Supplementary Note 1 to Supplementary Note 14, the semiconductor wafer is made of silicon carbide, The wafer mounting device is a heating mechanism for heating the semiconductor wafer mounted on the support; Semiconductor manufacturing equipment.

[0319] (Appendix 16) A semiconductor device manufacturing method using the wafer mounting apparatus according to any one of Supplementary Note 1 to Supplementary Note 14, the semiconductor wafer is made of silicon carbide, the wafer mounting device further includes a heating mechanism for heating the semiconductor wafer; (a) placing the semiconductor wafer on the plurality of lift-up members so that the semiconductor wafer fits within the opening in a plan view without contacting the ring, thereby realizing the semiconductor wafer mounted state; (b) supplying a source gas for epitaxial growth onto the surface of the semiconductor wafer in the mounted state; (c) heating the semiconductor wafer mounted on the semiconductor wafer by the heating mechanism; After the steps (a) to (c) are performed, an epitaxial layer is formed on the surface of the semiconductor wafer in the semiconductor wafer-mounted state. A method for manufacturing a semiconductor device.

[0320] (Appendix 17) the epitaxial layer formed by the method for manufacturing a semiconductor device according to Supplementary Note 16; a semiconductor layer for forming an element formed in the epitaxial layer, Semiconductor device. [Explanation of symbols]

[0321] 2, 2k, 2m, 2m2, 2n groove, 2X auxiliary groove, 11, 11B, 11C, 21, 31, 41 susceptor, 12, 121, 122, 22 ring, 12a to 12c, 22a, 22b wall portion, 12t, 121t terrace portion, 13, 13B, 23, 183 satellite disk, 13u, 23u upper layer portion, 13p peripheral portion, 14, 24, 34, 73, 184 SiC wafer, 14k, 73k orientation flat portion, 15, 25 lift-up pin, 17, 27 support material, 23m middle peripheral portion, 23p outermost peripheral portion, 50, 51 semiconductor manufacturing equipment, 61 SiC substrate, 62 N - Epitaxial layer, 100 semiconductor device, 182 planetary susceptor, 188 induction heating coil, O12, O22, O122 opening.

Claims

1. A wafer mounting device for mounting a semiconductor wafer having a notch, a disk having a convex upper layer; a ring disposed on the disk and having a central opening; a plurality of lift-up members disposed on a lift-up region provided on the disk or the ring for supporting the semiconductor wafer from the backside; The ring has a notch-side protruding wall portion that protrudes toward the opening, In a semiconductor wafer loaded state in which the semiconductor wafer is placed on the plurality of lift-up members so that the semiconductor wafer fits within the opening in a plan view without coming into contact with the ring, the notch-side protruding wall portion faces the notch portion of the semiconductor wafer, and a space above the disk is formed between the surface of the upper layer portion of the disk and the back surface of the semiconductor wafer, except for an area where the plurality of lift-up members are formed, and an annular groove is formed along the outer periphery of the opening in a plan view between the upper layer portion of the disk on the back surface side of the semiconductor wafer and the ring, a side surface of the upper layer of the disk that forms a side surface of the annular groove; Wafer mounting equipment.

2. 2. The wafer loading device according to claim 1, the disk has a peripheral portion around the upper layer portion, the surface of the peripheral portion is lower in height than the surface of the upper layer portion, and a step exists between the surface of the peripheral portion and the surface of the upper layer; the ring has a terrace portion protruding toward the opening, the terrace portion not overlapping the notch-side protruding wall portion in a plan view, the ring is placed on the disk with the terraces supported on the peripheral surface of the disk; a thickness in a height direction of the terrace portion is thinner than the step in the disk; Wafer mounting equipment.

3. 3. The wafer loading device according to claim 2, the plurality of lift-up members are placed on the surface of the terrace portion of the ring; the lift-up region includes a surface region of the terrace portion, Wafer mounting equipment.

4. 4. The wafer loading device according to claim 2 or 3, the terrace portion is not in contact with the side surface of the upper layer portion; Wafer mounting equipment.

5. 4. The wafer loading device according to claim 2 or 3, the opening includes the semiconductor wafer and has a formation area larger than the semiconductor wafer; the notch-side protruding wall portion does not contact the surface of the peripheral portion of the disk; Wafer mounting equipment.

6. 6. The wafer loading device according to claim 5, a formation height of the lower surface of the notch-side protruding wall portion is set to be equal to or greater than a formation height of the upper surfaces of the plurality of lift-up members; Wafer mounting equipment.

7. 6. The wafer loading device according to claim 5, The upper surface of the notch-side protruding wall portion forms part of the upper surface of the ring. Wafer mounting equipment.

8. 4. The wafer loading device according to claim 1, wherein: The upper layer of the disk has a concave shape with a concave central portion. Wafer mounting equipment.

9. 4. The wafer loading device according to claim 3, the ring further has, in addition to the terrace portion, an auxiliary terrace portion protruding toward the opening portion, the auxiliary terrace portion being provided between the terrace portion and the notch-side protruding wall portion in a plan view, and having a thickness in a height direction smaller than that of the terrace portion; the ring is placed on the disk in such a manner that the terrace portion and the auxiliary terrace portion are supported on the peripheral surface of the disk; Wafer mounting equipment.

10. 3. The wafer loading device according to claim 2, the plurality of lift-up members are placed on the upper layer of the disk; the lift-up region includes a surface region of the upper layer; Wafer mounting equipment.

11. 11. The wafer loading device according to claim 10, Further provided is a support member that supports the disk from the rear surface. Wafer mounting equipment.

12. 2. The wafer loading device according to claim 1, the disk has a first peripheral portion around the periphery of the upper layer portion and a second peripheral portion around the periphery of the first peripheral portion, and the formation heights of the surface of the upper layer portion, the surface of the first peripheral portion, and the surface of the second peripheral portion decrease in this order; the ring is placed on the disk such that a bottom surface of the ring is supported on the surface of the second peripheral portion of the disk along the entire circumference of the opening; Wafer mounting equipment.

13. The wafer loading device according to any one of claims 1 to 3, the cutout portion includes an orientation flat portion, the notch-side protruding wall portion is disposed so as to face the orientation flat portion with a fixed gap therebetween when the semiconductor wafer is mounted. Wafer mounting equipment.

14. The wafer loading device according to any one of claims 1 to 3, the cutout portion includes a notch portion, the notch-side protruding wall portion is disposed so as to fill a part of the notch portion without coming into contact with the semiconductor wafer when the semiconductor wafer is mounted. Wafer mounting equipment.

15. A semiconductor manufacturing apparatus having the wafer mounting device according to any one of claims 1 to 3, the semiconductor wafer is made of silicon carbide, The wafer mounting device is a heating mechanism for heating the semiconductor wafer mounted on the support; Semiconductor manufacturing equipment.

16. A method of manufacturing a semiconductor device using the wafer mounting device according to any one of claims 1 to 3, comprising: the semiconductor wafer is made of silicon carbide, the wafer mounting device further includes a heating mechanism for heating the semiconductor wafer; (a) placing the semiconductor wafer on the plurality of lift-up members so that the semiconductor wafer fits within the opening in a plan view without contacting the ring, thereby realizing the semiconductor wafer mounted state; (b) supplying a source gas for epitaxial growth onto the surface of the semiconductor wafer in the mounted state; (c) heating the semiconductor wafer mounted on the semiconductor wafer by the heating mechanism; After performing steps (a) to (c), an epitaxial layer is formed on the surface of the semiconductor wafer in the mounted state. A method for manufacturing a semiconductor device.

17. the epitaxial layer formed by the method for manufacturing a semiconductor device according to claim 16; a semiconductor layer for forming an element formed in the epitaxial layer, Semiconductor device.

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