Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device and a semiconductor module with high reliability.SOLUTION: In a semiconductor device 100, each of a first chip 101 and a second chip 102 stacked in a first direction Z includes: semiconductor parts 11 and 12; a first electrode 21; a second electrode 22; and a protective film 40. A first bonding member 51 electrically connects the second electrode of a first chip and the first electrode of a second chip in an opening part of the protective film of the first chip. The protective film of the first chip has a first concave part 41 on a surface facing the first electrode of the second chip. A part of the first bonding member is disposed in the first concave part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a semiconductor module. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors) are widely used as power semiconductor devices that have high breakdown voltages and control large currents. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-210540 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a highly reliable semiconductor device and semiconductor module. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first chip and a second chip stacked in a first direction, and a first bonding member provided between the first chip and the second chip in the first direction, wherein each of the first chip and the second chip has a semiconductor portion having a first surface and a second surface located opposite the first surface in the first direction, a first electrode provided on the first surface, a second electrode provided on a portion of the second surface, and a protective film covering the second surface, the protective film having an opening through which the second electrode is exposed, the first bonding member being provided between the first electrode of the second chip and the second electrode of the first chip, and between the first electrode of the second chip and the protective film of the first chip in the first direction, the first bonding member electrically connecting the second electrode of the first chip and the first electrode of the second chip at the opening of the protective film of the first chip, the protective film of the first chip having a first recess on a surface facing the first electrode of the second chip, and a portion of the first bonding member being disposed in the first recess. [Brief explanation of the drawings]

[0006] [Figure 1] 2 is a schematic cross-sectional view of a first chip and a second chip in the semiconductor device of the embodiment. FIG. [Figure 2] FIG. 2 is a schematic plan view of a first chip and a second chip according to the embodiment. [Figure 3] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment; [Figure 4] FIG. 1 is a schematic plan view of a semiconductor module according to an embodiment. [Figure 5] 1 is a schematic cross-sectional view of a semiconductor module according to an embodiment; [Figure 6] FIG. 10 is a schematic cross-sectional view of a first chip and a second chip according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.

[0008] A semiconductor device 100 according to an embodiment will be described with reference to FIGS.

[0009] The semiconductor device 100 includes a first chip 101, a second chip 102, and a first bonding member 51. As shown in Fig. 1, the first chip 101 and the second chip 102 are stacked in a first direction Z. The second electrode 22 of the first chip 101 and the second electrode 22 of the second chip 102 are positioned so as to overlap in the first direction Z. The first bonding member 51 is provided between the first chip 101 and the second chip 102 in the first direction Z.

[0010] The first chip 101 and the second chip 102 have the same configuration. Each of the first chip 101 and the second chip 102 has a semiconductor portion 10, a first electrode 21, a second electrode 22, and a protective film 40.

[0011] The semiconductor part 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in the first direction Z. The first electrode 21 is provided on the first surface 10A. The second electrode 22 is provided on a part of the second surface 10B.

[0012] The semiconductor portion 10 is made of, for example, silicon carbide (SiC). In this specification, the first conductivity type is described as n-type and the second conductivity type is described as p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0013] The semiconductor section 10 has an n-type first semiconductor layer 11 provided on a first electrode 21, an n-type second semiconductor layer 12 provided on the first semiconductor layer 11, and a p-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the second semiconductor layer 12 is lower than the n-type impurity concentration of the first semiconductor layer 11. Conversely, the n-type impurity concentration of the first semiconductor layer 11 is higher than the n-type impurity concentration of the second semiconductor layer 12. The thickness of the second semiconductor layer 12 in the first direction Z is thicker than the thickness of the first semiconductor layer 11 in the first direction Z. The first semiconductor layer 11 is electrically connected to the first electrode 21. The second electrode 22 is provided on the third semiconductor layer 13, and the third semiconductor layer 13 is electrically connected to the second electrode 22.

[0014] Each of the first chip 101 and the second chip 102 is, for example, a diode chip. The first electrode 21 functions as a cathode electrode, and the second electrode 22 functions as an anode electrode. In each of the first chip 101 and the second chip 102, a current flows between the second electrode 22 and the first electrode 21 in the first direction Z.

[0015] The protective film 40 covers the second surface 10B of the semiconductor portion 10. The protective film 40 has an opening 43 that exposes the second electrode 22. The protective film 40 is an insulating film, such as a resin film. The protective film 40 mainly contains, for example, polyimide.

[0016] The first bonding member 51 is electrically conductive. The first bonding member 51 is provided in the first direction Z between the first electrode 21 of the second chip 102 and the second electrode 22 of the first chip 101, and between the first electrode 21 of the second chip 102 and the protective film 40 of the first chip 101. The first bonding member 51 electrically connects the second electrode 22 of the first chip 101 and the first electrode 21 of the second chip 102 at the opening 43 of the protective film 40 of the first chip 101. The first chip 101 and the second chip 102 are connected in series via the first bonding member 51. The first bonding member 51 can be made of, for example, solder or silver.

[0017] The protective film 40 of the first chip 101 has a first recess 41 on a surface facing the first electrode 21 of the second chip 102. A part of the first bonding member 51 is disposed in the first recess 41. The presence of the first recess 41 increases the volume for accommodating the first bonding member 51 between the first chip 101 and the second chip 102 stacked in the first direction Z, making it difficult for the first bonding member 51 to flow out onto the side surfaces of the first chip 101 and the second chip 102. This makes it possible to suppress unintended short-circuit defects and provide a highly reliable semiconductor device.

[0018] 2, the first recess 41 is preferably a groove that continuously surrounds the second electrode 22 in a plan view of the second surface 10B. This makes it difficult for the first bonding member 51 to flow onto the side surfaces of the first chip 101 and the second chip 102 in all directions around the second electrode 22. The protective film 40 of the first chip 101 contacts the first bonding member 51 in at least a part of the region inside the first recess 41. The protective film 40 of the first chip 101 may also contact the first bonding member 51 in the region outside the first recess 41.

[0019] 2, the second surface 10B of the semiconductor portion 10 can have an element region R1 in which the p-type third semiconductor layer 13 is located, and a termination region R2 located outside the element region R1. The termination region R2 continuously surrounds the element region R1. In FIG. 2, an outer edge 13A of the third semiconductor layer 13 can be the boundary between the element region R1 and the termination region R2.

[0020] In the termination region R2, as shown in FIG. 1 , a p-type fourth semiconductor layer 14 having a lower p-type impurity concentration than the third semiconductor layer 13 is located on the second semiconductor layer 12. The fourth semiconductor layer 14 continuously surrounds the third semiconductor layer 13 in a plan view. An inner peripheral portion of the fourth semiconductor layer 14 contacts an outer peripheral portion of the third semiconductor layer 13. A pn ​​junction between the third semiconductor layer 13 and the second semiconductor layer 12 is located inside the inner edge of the fourth semiconductor layer 14. The potential of the second electrode 22 is applied to the fourth semiconductor layer 14 via the third semiconductor layer 13. The fourth semiconductor layer 14 having a lower p-type impurity concentration than the third semiconductor layer 13 makes it easier for a depletion layer to extend into the termination region R2, thereby increasing the breakdown voltage of the first chip 101 and the second chip 102.

[0021] The depth of first recess 41 is smaller than the thickness of protective film 40 on termination region R2, thereby preventing a decrease in reliability due to a partial decrease in the thickness of protective film 40 on termination region R2. The depth and thickness are lengths in first direction Z. First recess 41 has a depth of 100 nm or more and 20,000 nm or less, and a width of 100 nm or more.

[0022] 1, each of the first chip 101 and the second chip 102 may further include an insulating film 30 provided between the second surface 10B of the semiconductor portion 10 and the protective film 40. The insulating film 30 is, for example, an inorganic film. The insulating film 30 is, for example, a silicon oxide film. The thickness of the protective film 40 is, for example, several tens to several hundreds times the thickness of the insulating film 30.

[0023] As shown in FIG. 3, the semiconductor device 100 of the embodiment may further include a third chip 103 connected in parallel to the first chip 101 and the second chip 102.

[0024] The third chip 103 is a transistor chip having a third electrode 103C electrically connected to the first electrode 21 of the first chip 101 and a fourth electrode 103E electrically connected to the second electrode 22 of the second chip 102. The third chip 103 is, for example, an IGBT (Insulated Gate Bipolar Transistor) chip. In the IGBT chip, the third electrode 103C is a collector electrode and the fourth electrode 103E is an emitter electrode. The third chip 103 further has a gate electrode 103G. The third chip 103 is, for example, an IGBT chip made of silicon material.

[0025] The first chip 101 and the second chip 102 function as freewheeling diodes that pass a reverse current generated when the third chip 103 (IGBT chip) is switched in applications such as inverters and motor drives. The withstand voltage of the third chip 103 (IGBT chip) is, for example, 4.5 kV. In the freewheeling diode of this embodiment, for example, the first chip 101 (or the second chip 102) with a withstand voltage of 1.2 kV and the second chip 102 (or the first chip 101) with a withstand voltage of 3.3 kV are connected in series, thereby realizing a freewheeling diode with a withstand voltage of 4.5 kV. This allows for lower costs and higher reliability than using a single diode chip with a withstand voltage of 4.5 kV.

[0026] A semiconductor module 200 according to an embodiment will be described with reference to FIGS.

[0027] As shown in FIG. 5 , the semiconductor module 200 includes a first conductive member 201, a second conductive member 202, and the plurality of semiconductor devices 100 arranged between the first conductive member 201 and the second conductive member 202 in the first direction Z. Each of the plurality of semiconductor devices 100 includes a first chip 101, a second chip 102, and a third chip 103. That is, the semiconductor module 200 includes a plurality of first chips 101, a plurality of second chips 102, and a plurality of third chips 103. The plurality of first chips 101 and the plurality of third chips 103 are spaced apart from each other in a plane intersecting the first direction Z. As described above, the first chip 101 and the second chip 102 are stacked and connected in series via the first bonding member 51. In FIG. 4 , the stacked chips of the first chip 101 and the second chip 102 are indicated by shading.

[0028] The first electrode 21 (cathode electrode) of the first chip 101 and the third electrode 103C (collector electrode) of the third chip 103 are electrically connected to the first conductive member 201. A first metal plate 205 is disposed between the first chip 101 and the first conductive member 201, and the first electrode 21 of the first chip 101 and the first conductive member 201 are electrically connected via the first metal plate 205. A third metal plate 203 is disposed between the third chip 103 and the first conductive member 201, and the third electrode 103C of the third chip 103 and the first conductive member 201 are electrically connected via the third metal plate 203.

[0029] The second electrode 22 (anode electrode) of the second tip 102 and the fourth electrode 103E (emitter electrode) of the third tip 103 are electrically connected to the second conductive member 202. A second metal plate 206 is disposed between the second tip 102 and the second conductive member 202, and the second electrode 22 of the second tip 102 and the second conductive member 202 are electrically connected via the second metal plate 206. A fourth metal plate 204 is disposed between the third tip 103 and the second conductive member 202, and the fourth electrode 103E of the third tip 103 and the second conductive member 202 are electrically connected via the fourth metal plate 204.

[0030] The first conductive member 201 and the second conductive member 202 may be made of, for example, copper. The first conductive member 201 and the second conductive member 202 extend along a plane intersecting with the first direction Z. The first conductive member 201 and the second conductive member 202 have a plurality of protrusions extending along the first direction Z. The plurality of protrusions are in contact with the first metal plate 205, the second metal plate 206, the third metal plate 203, and the fourth metal plate 204. The first metal plate 205, the second metal plate 206, the third metal plate 203, and the fourth metal plate 204 may be made of, for example, molybdenum.

[0031] The semiconductor module 200 may further include a wiring member 207 disposed between the first conductive member 201 and the second conductive member 202 in the first direction Z and electrically connected to the gate electrode 103G of the third chip 103. The gate electrode 103G of the third chip 103 is electrically connected to a wiring layer formed on the wiring member 207 via a connecting member 208. For example, a spring pin may be used as the connecting member 208. The third chip 103 is turned on and off by a gate voltage applied to the gate electrode 103G via the wiring member 207.

[0032] For example, the fastening force of the screws coupled to the first conductive member 201 and the second conductive member 202 maintains the first chip 101, the second chip 102, and the third chip 103 sandwiched between the first conductive member 201 and the second conductive member 202. Pressure is applied to the first chip 101, the second chip 102, and the third chip 103 along the first direction Z.

[0033] The semiconductor module 200 further includes a second bonding member 52 (shown in FIG. 1) that is provided between the second conductive member 202 and the second chip 102 and electrically connects the second conductive member 202 to the second electrode 22 of the second chip 102. The second bonding member 52 can be made of the same material as the first bonding member 51.

[0034] The protective film 40 of the second chip 102 has a second recess 42 on the surface facing the second conductive member 202 (the upper surface in FIG. 1), and a part of the second bonding member 52 is disposed in the second recess 42.

[0035] As the third chip 103 repeatedly turns on and off, the first bonding member 51 tends to flow due to repeated thermal expansion and contraction between the first chip 101 and the second chip 102. Similarly, the second bonding member 52 tends to flow due to repeated thermal expansion and contraction between the second conductive member 202 and the second chip 102.

[0036] According to this embodiment, as described above, the presence of the first recess 41 makes it difficult for the first bonding material 51 to flow onto the side surfaces of the first chip 101 and the second chip 102, even if the first bonding material 51 is prone to flow. Similarly, the presence of the second recess 42 makes it difficult for the second bonding material 52 to flow onto the side surfaces of the second chip 102 and the first chip 101. This makes it possible to suppress unintended short-circuit defects and provide a highly reliable semiconductor module.

[0037] Similar to the first recess 41 in the first chip 101, the second recess 42 is preferably a groove that continuously surrounds the second electrode 22 of the second chip 102 when the second surface 10B of the second chip 102 is seen in a plan view.

[0038] As in the modified example of the first chip 101 (or the second chip 102) shown in FIG. 6, the second surface 10B of the semiconductor portion 10 may be flat. Also, a plurality of third semiconductor layers 13 may be provided that are spaced apart from each other in a plane intersecting with the first direction Z. Also, the second electrode 22 may have a stacked structure of a first layer 22A, a second layer 22B, and a third layer 22C. The first layer 22A is provided on the second surface 10B of the semiconductor portion 10 and is in contact with the third semiconductor layer 13. The first layer 22A contains, for example, Ni. The second layer 22B is provided on the first layer 22A and contains, for example, Ti. The third layer 22C is provided on the second layer 22B and contains, for example, Au.

[0039] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0040] 10...semiconductor portion, 10A...first surface, 10B...second surface, 11...first semiconductor layer, 12...second semiconductor layer, 13...third semiconductor layer, 14...fourth semiconductor layer, 21...first electrode, 22...second electrode, 30...insulating film, 40...protective film, 41...first recess, 42...second recess, 51...first bonding member, 52...second bonding member, 100...semiconductor device, 101...first chip, 102...second chip, 103...third chip, 103C...third electrode, 103E...fourth electrode, 103G...gate electrode, 200...semiconductor module, 201...first conductive member, 202...second conductive member, 207...wiring member, R1...element region, R2...termination region

Claims

1. a first chip and a second chip stacked in a first direction; a first bonding member provided between the first tip and the second tip in the first direction; Equipped with Each of the first chip and the second chip includes: a semiconductor portion having a first surface and a second surface located opposite to the first surface in the first direction; a first electrode provided on the first surface; a second electrode provided on a portion of the second surface; a protective film covering the second surface, the protective film having an opening through which the second electrode is exposed; and the first bonding member is provided between the first electrode of the second chip and the second electrode of the first chip, and between the first electrode of the second chip and the protective film of the first chip, in the first direction; the first bonding member electrically connects the second electrode of the first chip to the first electrode of the second chip at the opening of the protective film of the first chip; the protective film of the first chip has a first recess on a surface facing the first electrode of the second chip; A semiconductor device, wherein a portion of the first bonding member is disposed in the first recess.

2. The semiconductor device according to claim 1 , wherein the first recess is a groove that continuously surrounds the second electrode in a plan view of the second surface.

3. each of the first chip and the second chip is a diode chip; The semiconductor portion is a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having a lower first conductivity type impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer and electrically connected to the second electrode; The semiconductor device according to claim 1 , comprising:

4. further comprising a third chip connected in parallel to the first chip and the second chip; 4. The semiconductor device according to claim 3, wherein the third chip is a transistor chip having a third electrode electrically connected to the first electrode of the first chip and a fourth electrode electrically connected to the second electrode of the second chip.

5. 5. The semiconductor device according to claim 4, wherein the third chip is an IGBT (Insulated Gate Bipolar Transistor) chip.

6. The second surface of the semiconductor portion is an element region in which the third semiconductor layer is located; a termination region located outside the element region; and 4. The semiconductor device according to claim 3, wherein a fourth semiconductor layer of the second conductivity type having a lower second conductivity type impurity concentration than the third semiconductor layer is located on the second semiconductor layer in the termination region.

7. 7. The semiconductor device according to claim 1, wherein said semiconductor portion is made of silicon carbide.

8. a first conductive member; A second conductive member; a plurality of semiconductor devices according to claim 4 , which are arranged between the first conductive member and the second conductive member in the first direction; Equipped with the first electrode of the first chip and the third electrode of the third chip are electrically connected to the first conductive member; the second electrode of the second chip and the fourth electrode of the third chip are electrically connected to the second conductive member.

9. 9. The semiconductor module according to claim 8, further comprising a second bonding member provided between the second conductive member and the second chip, the second bonding member electrically connecting the second conductive member and the second electrode of the second chip.

10. the protective film of the second chip has a second recess on a surface facing the second conductive member; The semiconductor module according to claim 9 , wherein a portion of the second joint member is disposed in the second recess.

11. The semiconductor module according to claim 10 , wherein the second recess is a groove that continuously surrounds the second electrode of the second chip in a plan view of the second surface of the second chip.

12. 12. The semiconductor module according to claim 8, further comprising a wiring member arranged between the first conductive member and the second conductive member in the first direction and electrically connected to a gate electrode of the third chip.

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