Inverter, photovoltaic and storage system, and inverter control method

Abstract

To provide an inverter, a photovoltaic and storage system, and an inverter control method.SOLUTION: An inverter includes an inverter circuit 310, a filter circuit 320, and a balanced circuit 330. The filter circuit 320 is configured to filter alternating current, and the filtered alternating current is used to supply power to a load. The inverter further includes a controller 340. The controller 340 is configured to: when the inverter runs in an off-grid mode and an absolute value of a voltage difference between two loads R1 and R2 that are connected in series is greater than a voltage threshold, control a switching transistor in two switching transistors G5 and G6 to be turned on, to enable the voltage difference to be less than the voltage threshold, where a series connection point of the two loads R1 and R2 that are connected in series is connected to a series connection point of two capacitors that are connected in series.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present application relates to the field of power technology, and in particular to inverters, photovoltaic and storage systems, and inverter control methods. [Background technology]

[0002] Inverters can convert the direct current (DC) of photovoltaic modules into alternating current (AC) and are currently widely used in photovoltaic power generation systems. Coupled inductors are generally selected as the inductors in the inverter's filter circuit to reduce costs. Because the inductors are coupled inductors, the driving signals of the two sets of switching transistors in the inverter must be identical. When the inverter is off-grid and supplies power to two loads connected in series, if the two loads have different rated powers, a two-phase output voltage imbalance problem will occur during the inverter's operation. This will affect the normal operation of the inverter and may even cause the inverter to stop working. Summary of the Invention

[0003] The present application provides an inverter, a photovoltaic and storage system, and an inverter control method to solve the problem of two-phase output voltage imbalance in the operation process of the inverter, thereby ensuring the normal operation of the inverter.

[0004] According to a first aspect, there is provided an inverter including an inverter circuit, a filter circuit, and a balance circuit. The inverter circuit is configured to convert direct current into alternating current. The filter circuit is configured to filter the alternating current, and the filtered alternating current is used to supply power to a load. The filter circuit includes a coupled inductor and two capacitors connected in series, where two input ports of the coupled inductor are connected to the inverter circuit, and the two capacitors connected in series are connected between two output ports of the coupled inductor. The balance circuit includes two switching transistors and a first inductor, where the two switching transistors are connected in series and then connected between a positive bus and a negative bus, one end of the first inductor is connected to the series connection point of the two switching transistors, and the other end of the first inductor is connected to the series connection point of the two capacitors connected in series. The inverter further includes a controller. The controller is configured to control the switching transistors in the two switching transistors to be turned on when the inverter operates in an off-grid mode and the absolute value of the voltage difference between the two loads connected in series is greater than a voltage threshold, so that the voltage difference becomes smaller than the voltage threshold, and wherein the series connection point of the two loads connected in series is connected to the series connection point of the two capacitors connected in series.

[0005] The inverter in this embodiment of the present application includes a balancing circuit. When the inverter operates in off-grid mode and the absolute value of the voltage difference between two series-connected loads is greater than a voltage threshold, the controller can control the switching transistors in the balancing circuit to turn on. The two switching transistors in the balancing circuit are connected in series and then connected between the positive bus and the negative bus, i.e., one switching transistor is directly connected to the positive bus and the other switching transistor is directly connected to the negative bus. Therefore, when the switching transistors in the two switching transistors are turned on, the positive voltage of the positive bus can increase the voltage at the series-connection point of the two loads, and the negative voltage of the negative bus can decrease the voltage at the series-connection point of the two loads, thereby reducing the voltage difference between the two loads. This can solve the problem of two-phase output voltage imbalance during the operation of the inverter, thereby ensuring the normal operation of the inverter.

[0006] In addition, in this embodiment of the present application, the balancing circuit of the inverter only includes two switching transistors and one inductor, so as to solve the problem of two-phase output voltage imbalance in the inverter operation process, with a small number of components, low cost, and easy implementation.

[0007] Referring to the first aspect, in one possible design, the inverter circuit includes a first bridge arm and a second bridge arm, each of which includes two switching transistors connected in series, each of which includes a parallel freewheel diode, and all of the freewheel diodes have the same freewheel direction. One switching transistor of the first bridge arm and one switching transistor of the second bridge arm form an upper half bridge arm, and the other switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form a lower half bridge arm. The one switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form one set of switching transistors, and the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm form the other set of switching transistors. The two loads include a first load and a second load. One end of the first load is connected to the series connection point of the two switching transistors of the second bridge arm through a filter circuit, and one end of the second load is connected to the series connection point of the two switching transistors of the first bridge arm through a filter circuit. The series connection point of the first load and the second load is connected to the series connection point of the two capacitors connected in series, and the controller is configured to: control the switching transistors in the balancing circuit that are directly connected to the negative bus to turn on when the voltage of the first load is greater than the voltage of the second load and one set of switching transistors is turned on, or when the voltage of the first load is less than the voltage of the second load and the other set of switching transistors is turned on; or control the switching transistors in the balancing circuit that are directly connected to the positive bus to turn on when the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors is turned on, or when the voltage of the first load is less than the voltage of the second load and one set of switching transistors is turned on.

[0008] In this embodiment of the present application, the controller can control the switching transistors in the balancing circuit to be turned on according to a specific case. Specifically, when the voltage of the first load is greater than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, the voltage at the connection point between the two loads is high, and the controller controls the switching transistor in the balancing circuit, which is directly connected to the negative bus, to be turned on, and the negative voltage of the negative bus can reduce the voltage at the series connection point of the two loads, thereby reducing the voltage difference between the two loads. When the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors is turned on, or when the voltage of the first load is smaller than the voltage of the second load and one set of switching transistors is turned on, the voltage at the connection point between the two loads is low, and the controller controls to turn on the switching transistor in the balance circuit directly connected to the positive bus, and the positive voltage of the positive bus can improve the voltage at the series connection point of the two loads, thereby reducing the voltage difference between the two loads.

[0009] Referring to the first aspect, in one possible design, the inverter further includes a voltage loop regulator, a current loop regulator, and an amplitude limiter, where the amplitude limiter is configured to limit a maximum current value in the balancing circuit. The voltage loop regulator is configured to output a first current value based on a voltage difference. The amplitude limiter is configured to output a second current value based on the first current value. The current loop regulator is configured to generate a duty cycle of a switching transistor in the balancing circuit based on a current difference between the second current value and a current value on the first inductor to reduce the voltage difference below a voltage threshold. The second current value is less than or equal to the first current value.

[0010] In this embodiment of the present application, the amplitude limiter outputs a second current value based on the first current value output by the voltage loop regulator, and the current loop regulator generates a duty cycle of the switching transistor in the balancing circuit based on the current difference between the second current value and the current value on the first inductor, so that the voltage difference between the two loads can be reduced until the voltage difference is smaller than the voltage threshold, thus solving the problem of two-phase output voltage imbalance in the inverter operation process.

[0011] Referring to the first aspect, in a possible design, if the first current value is less than or equal to the absolute value of the maximum current value, the second current value is equal to the first current value; or if the first current value is greater than the absolute value of the maximum current value, the second current value is equal to the maximum current value.

[0012] In this embodiment of the present application, the amplitude limiter is configured to limit the maximum current value in the balancing circuit, and the second current value output by the amplitude limiter is less than or equal to the absolute value of the maximum current value, so as to avoid damage to the switching transistor in the balancing circuit caused by a large current flowing through the switching transistor, and to protect the circuit topology.

[0013] Referring to the first aspect, in a possible design, the controller is further configured to reduce dead time of a switching transistor in the inverter circuit.

[0014] In this embodiment of the present application, when one set of switching transistors in the inverter circuit is turned on and then turned off, the current in the coupled inductor flows through the freewheeling diode of the other set of switching transistors in the inverter circuit, forming a freewheeling loop. When the one set of switching transistors is turned on again, the current preferentially flows through the freewheeling diode of one of the switching transistors in the one set of switching transistors, which exacerbates the problem of two-phase output voltage imbalance. Therefore, the controller can further reduce the voltage difference between the two loads by reducing the dead time of the switching transistors in the inverter circuit. In this way, the case of two-phase output voltage imbalance can be improved.

[0015] Referring to the first aspect, in one possible design, the inverter further includes two other capacitors connected in series, the other two capacitors connected between the positive bus and the negative bus, and the series junction of the other two capacitors connected in series to one end of the first inductor.

[0016] In this embodiment of the present application, the switching transistor in the balancing circuit may not be able to reduce the voltage difference between the two phases without limitation, and two additional capacitors connected in series can further improve the two-phase output voltage imbalance. In addition, the two capacitors connected in series can reduce the maximum current that the switching transistor in the balancing circuit can withstand, thereby reducing the selection specifications of the switching transistor in the balancing circuit and reducing the cost of the switching transistor.

[0017] According to a second aspect, there is provided a photovoltaic and storage system comprising a photovoltaic module according to any one of the possible designs of the first aspect, an energy storage device, and an inverter, wherein the energy storage device is configured to store direct current from the photovoltaic module, and the inverter is configured to convert the direct current from the photovoltaic module to alternating current.

[0018] For technical effects that can be achieved by the second aspect, please refer to the description of technical effects that can be achieved in any possible implementation of the first aspect, and the details will not be described again here.

[0019] According to a third aspect, there is provided an inverter control method, comprising: when the inverter operates in an off-grid mode and an absolute value of a voltage difference between two loads connected in series is greater than a voltage threshold, controlling two switching transistors in a balancing circuit of the inverter to be turned on, thereby making the voltage difference smaller than the voltage threshold, and wherein a series connection point of the two loads connected in series is connected to a series connection point of two capacitors connected in series in a filter circuit of the inverter. The filter circuit includes a coupled inductor and two capacitors connected in series, two input ports of the coupled inductor are connected to an inverter circuit of the inverter, and the two capacitors connected in series are connected between two output ports of the coupled inductor. The balancing circuit includes two switching transistors and a first inductor, the two switching transistors are connected in series and then connected between a positive bus and a negative bus, one end of the first inductor is connected to the series connection point of the two switching transistors, and the other end of the first inductor is connected to the series connection point of the two capacitors connected in series.

[0020] Referring to the third aspect, in a possible design, the step of controlling to turn on the switching transistors of two switching transistors in the balancing circuit of the inverter includes the step of controlling to turn on the switching transistors directly connected to the negative bus in the balancing circuit when the voltage of the first load is greater than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on; or the step of controlling to turn on the switching transistors directly connected to the positive bus in the balancing circuit when the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on.

[0021] The inverter circuit includes a first bridge arm and a second bridge arm, each of which includes two switching transistors connected in series. Each switching transistor includes a freewheel diode connected in parallel, and all freewheel diodes have the same freewheel direction. One switching transistor of the first bridge arm and one switching transistor of the second bridge arm form an upper half bridge arm, and the other switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form a lower half bridge arm. The one switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form one set of switching transistors, and the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm form the other set of switching transistors. One end of the first load is connected to the series connection point of the two switching transistors of the second bridge arm through a filter circuit, and one end of the second load is connected to the series connection point of the two switching transistors of the first bridge arm through a filter circuit. The series connection point of the first load and the second load is connected to the series connection point of two capacitors connected in series.

[0022] Referring to the third aspect, in a possible design, the method further comprises: reducing dead time of a switching transistor in the inverter circuit.

[0023] For technical effects that can be achieved in the third aspect, please refer to the description of the technical effects that can be achieved in any possible implementation of the first aspect, and the details will not be described again here. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a diagram of a scenario in which the present application is applicable. [Figure 2] FIG. [Figure 3]1 is a diagram of an inverter according to an embodiment of the present application; [Figure 4] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 5] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 6] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 7] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 8] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 9] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 10] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 11] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 12] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 13] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 14] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 15] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 16] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 17] 1 is a diagram of an inverter according to an embodiment of the present application; [Figure 18] FIG. 1 is a diagram of an inverter control method according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0025] The technical solutions of the present application are described below with reference to the accompanying drawings.

[0026] To facilitate understanding, the following first provides a brief explanation of the terms used in this application.

[0027] On-grid: The direct current generated by the generator set is converted by an inverter into alternating current that meets the requirements of the grid, and then the alternating current is input into the grid. Thus, on-grid can be understood as the power generation system being connected to the grid.

[0028] Off-grid: The direct current generated by the generator set is converted to alternating current by an inverter, and the alternating current cannot be transmitted to the grid. Therefore, off-grid can be understood as the power generation system not being connected to the grid.

[0029] Figure 1 is a diagram of a possible scenario in which the present application is applicable. Please refer to Figure 1. Photovoltaic modules convert solar energy into direct current through the photovoltaic effect; inverters convert the direct current into alternating current, which is then sent to the grid or supplied to a load. Alternatively, inverters can convert direct current from an energy storage device into alternating current, which is then sent to the grid or supplied to a load.

[0030] FIG. 2 is a diagram of the inverter. To reduce costs, a coupled inductor is generally selected as inductor L1. Because inductor L1 is a coupled inductor, the drive signals of the two sets of switching transistors in the inverter need to be the same. In other words, the drive signals of switching transistors G1 and G4 are the same, and the drive signals of switching transistors G2 and G3 are the same. When the inverter is in an off-grid state, if it supplies power to two loads connected in series and the two loads have different rated powers, a two-phase output voltage imbalance problem will occur in the inverter's operation process, i.e., an imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase. This will affect the normal operation of the inverter and may even cause the inverter to stop working.

[0031] Therefore, the present application provides an inverter that solves the problem of two-phase output voltage imbalance in the operation process of the inverter, thereby ensuring the normal operation of the inverter.

[0032] 3, the inverter includes an inverter circuit 310, a filter circuit 320, and a balance circuit 330. The inverter circuit 310 is configured to convert direct current into alternating current. The filter circuit 320 is configured to filter the alternating current, which is used to supply power to a load.

[0033] The filter circuit 320 includes a coupled inductor L1 and two capacitors C1 and C2 connected in series, where the two input ports of the coupled inductor L1 are connected to the inverter circuit 310, and the two capacitors C1 and C2 connected in series are connected between the two output ports of the coupled inductor L1.

[0034] The balance circuit 330 includes two switching transistors G5 and G6 and a first inductor L2, where the two switching transistors G5 and G6 are connected in series and then connected between the positive bus and the negative bus, one end of the first inductor L2 is connected to the series connection point of the two switching transistors G5 and G6, and the other end of the first inductor L2 is connected to the series connection point of the two capacitors C1 and C2 connected in series.

[0035] The switching transistor in this embodiment of the present application may specifically be a giant transistor (GTR), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a gallium nitride (GaN) high electron mobility transistor (HEMT), or the like. A GTR is used as an example in FIG. 3 .

[0036] The inverter further includes a controller 340. The controller 340 is configured to: control the switching transistors in the two switching transistors G5 and G6 to turn on when the inverter operates in an off-grid mode and the absolute value of the voltage difference between the two loads R1 and R2 connected in series is greater than a voltage threshold, allowing the voltage difference to be smaller than the voltage threshold, wherein the series connection point of the two loads R1 and R2 connected in series is connected to the series connection point of the two capacitors C1 and C2 connected in series.

[0037] In this embodiment of the present application, the inverter operates in off-grid mode. In other words, the AC current output by the inverter is not used to power a load on the power grid, but is used to supply power to a separate load. When the AC current output by the inverter is used to power two loads connected in series, if the two loads have different rated powers, the voltages of the two loads will be different, resulting in an imbalance between the voltages between the U and O phases and the voltages between the O and W phases. In other words, the voltage of the O phase is non-zero. In this case, the controller can control the switching transistors G5 and G6 in the balancing circuit to turn on. The switching transistor G5 is directly connected to the positive bus. When the switching transistor G5 is turned on, the positive voltage of the positive bus can increase the voltage of the O phase. The switching transistor G6 is directly connected to the negative bus. When the switching transistor G6 is turned on, the negative voltage of the negative bus can decrease the voltage of the O phase. This can solve the problem of imbalance between the voltages between the U and O phases and the voltages between the O and W phases.

[0038] The inverter in this embodiment of the present application includes a balancing circuit. When the inverter operates in off-grid mode and the absolute value of the voltage difference between two series-connected loads is greater than a voltage threshold, the controller can control the switching transistors in the balancing circuit to turn on. The two switching transistors in the balancing circuit are connected in series and then connected between the positive bus and the negative bus, i.e., one switching transistor is directly connected to the positive bus and the other switching transistor is directly connected to the negative bus. Therefore, when the switching transistors in the two switching transistors are turned on, the positive voltage of the positive bus can increase the voltage at the series-connection point of the two loads, and the negative voltage of the negative bus can decrease the voltage at the series-connection point of the two loads, thereby reducing the voltage difference between the two loads. This can solve the problem of two-phase output voltage imbalance during the operation of the inverter, thereby ensuring the normal operation of the inverter.

[0039] In addition, in this embodiment of the present application, the balancing circuit of the inverter only includes two switching transistors and one inductor, so as to solve the problem of two-phase output voltage imbalance in the inverter operation process, with a small number of components, low cost, and easy implementation.

[0040] The following describes in detail the case where the controller 340 controls the switching transistors G5 and G6 to be turned on.

[0041] 4, the inverter circuit 310 includes a first bridge arm and a second bridge arm, each of which includes two switching transistors connected in series. Each switching transistor includes a parallel freewheel diode, and all the freewheel diodes have the same freewheel direction. One switching transistor G1 of the first bridge arm and one switching transistor G3 of the second bridge arm form an upper half bridge arm, and the other switching transistor G2 of the first bridge arm and the other switching transistor G4 of the second bridge arm form a lower half bridge arm. The one switching transistor G1 of the first bridge arm and the other switching transistor G4 of the second bridge arm constitute one set of switching transistors, and the other switching transistor G2 of the first bridge arm and one switching transistor G3 of the second bridge arm constitute the other set of switching transistors.

[0042] In this embodiment of the present application, each switching transistor in the inverter circuit includes a parallel freewheel diode, which may be referred to as a body-diode.

[0043] The two loads include a first load R1 and a second load R2. One end of the first load R1 is connected to the series connection point of the two switching transistors of the second bridge arm through a filter circuit, and one end of the second load R2 is connected to the series connection point of the two switching transistors of the first bridge arm through a filter circuit. The series connection point of the first load R1 and the second load R2 is connected to the series connection point of two capacitors C1 and C2 connected in series.

[0044] The controller 340 is configured to control the switching transistor G6, which is directly connected to the negative bus in the balancing circuit, to turn on when: the voltage of the first load R1 is greater than the voltage of the second load R2 and one set of switching transistors G1 and G4 is turned on; or when the voltage of the first load R1 is smaller than the voltage of the second load R2 and the other set of switching transistors G2 and G3 is turned on.

[0045] The controller 340 is configured to control the switching transistor G5, which is directly connected to the positive bus in the balancing circuit, to turn on when the voltage of the first load R1 is greater than the voltage of the second load R2 and the other set of switching transistors G2 and G3 is turned on, or when the voltage of the first load R1 is smaller than the voltage of the second load R2 and one set of switching transistors G1 and G4 is turned on.

[0046] In this embodiment of the present application, the rated power of the load R1 may or may not be equal to the rated power of the load R2. When the rated power of the load R1 is equal to the rated power of the load R2, the voltages of the load R1 and the load R2 are generally equal, and the controller does not need to control the switching transistors G5 and G6 to turn on. When the rated power of the load R1 is not equal to the rated power of the load R2, the voltage of the load R1 is generally not equal to the voltage of the load R2, and the controller can control the switching transistors G5 and G6 to turn on.

[0047] Case 1: The rated power of the load R1 is equal to the rated power of the load R2. Because the rated power of the load R1 is equal to the rated power of the load R2, the voltages of the load R1 and the load R2 are equal. In this case, the controller 340 does not need to control the switching transistor G5 or the switching transistor G6 to turn on.

[0048] Specifically, when the switching transistors G2 and G3 are turned on, the current direction is shown in Figure 5. See Figure 5. The direct current output by the photovoltaic module flows through the switching transistor G3, inductor L1, load R1, load R2, inductor L1, and switching transistor G2, forming a current loop. In other words, the current flowing out from the positive electrode of the photovoltaic module flows through the switching transistor G3, inductor L1, load R1, load R2, inductor L1, and switching transistor G2, and returns to the negative electrode of the photovoltaic module.

[0049] When the switching transistors G1 and G4 are turned on, the current direction is shown in Figure 6. Please refer to Figure 6. The direct current output by the photovoltaic module flows through the switching transistor G1, inductor L1, load R2, load R1, inductor L1, and switching transistor G4, forming a current loop. In other words, the current flowing out from the positive electrode of the photovoltaic module flows through the switching transistor G1, inductor L1, load R2, load R1, inductor L1, and switching transistor G4, and returns to the negative electrode of the photovoltaic module.

[0050] In this case, the voltage of load R1 is equal to the voltage of load R2. In other words, the voltage between phases U and O is equal to the voltage between phases W and O. For example, when the voltage between phases U and W is 202 V, both the voltage between phases U and O and the voltage between phases O and W must be at their rated values, where the rated value is half the voltage between phases U and W, i.e., 101 V. In this case, the voltage between phases U and O and the voltage between phases W and O are in equilibrium.

[0051] Case 2: The rated power of the load R1 is not equal to the rated power of the load R2. Because the rated power of the load R1 is different from the rated power of the load R2, the voltage of the load R1 is not equal to the voltage of the load R2. When the voltage difference between the load R1 and the load R2 is greater than the voltage threshold, the controller can control the switching transistor G5 or the switching transistor G6 to turn on so as to make the voltage difference between the load R1 and the load R2 smaller than the voltage threshold.

[0052] The following describes in detail the case where the controller controls the switching transistor G5 or the switching transistor G6 to be turned on.

[0053] 1. The controller controls the switching transistor G6 to be turned on. (1) When the rated power of the load R1 is smaller than the rated power of the load R2, the voltage of the load R1 is larger than the voltage of the load R2. When the switching transistors G1 and G4 are turned on, the current direction is shown in Figure 7. Please refer to Figure 7. When a part of the direct current output by the photovoltaic module flows through the switching transistor G1, inductor L1, load R2, inductor L1, and switching transistor G4 to form a current loop, another part of the direct current flows through the switching transistor G1, inductor L1, load R2, inductor L2, and switching transistor G6 to form a current loop.

[0054] In this embodiment of the present application, when the switching transistors G1 and G4 are turned on, the U phase is connected to the negative bus and the W phase is connected to the positive bus. When the rated power of the load R1 is smaller than the rated power of the load R2, the voltage of the load R1 is larger than the voltage of the load R2, and the voltage of the O phase is no longer 0 V but is a value deviating from 0 V. Because the U phase is connected to the negative bus and the W phase is connected to the positive bus, the voltage of the O phase is a value greater than 0 V. Therefore, both the voltage between the U phase and the O phase and the voltage between the O phase and the W phase deviate from their rated values.

[0055] Specifically, for example, the voltage threshold is 2 V. When the voltage between the U phase and the W phase is 202 V, if the voltage of the O phase is 3 V, the voltage between the U phase and the O phase is 104 V, and the voltage between the O phase and the W phase is 98 V. In other words, the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase is 6 V, which is greater than the voltage threshold. The controller may control the switching transistor G6 in the balancing circuit to turn on.

[0056] To reduce the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase, it may be considered to reduce the voltage of the O phase. Because the switching transistor G6 is connected to the negative bus, the controller controls the switching transistor G6 to turn on. When the switching transistor G6 is turned on, the DC negative voltage output on the negative bus may reduce the voltage of the O phase, resulting in a decrease in the voltage between the U phase and the O phase and an increase in the voltage between the O phase and the W phase. When the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase is less than or equal to a voltage threshold, the controller turns off the switching transistor G6 to reduce the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase, thereby solving the imbalance problem between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0057] (2) When the rated power of the load R1 is greater than the rated power of the load R2, the voltage of the load R1 is smaller than the voltage of the load R2. When the switching transistors G2 and G3 are turned on, the current direction is shown in Figure 8. Please refer to Figure 8. When a part of the DC output by the photovoltaic module flows through the switching transistor G3, inductor L1, load R1, load R2, inductor L1, and switching transistor G2 to form a current loop, another part of the DC flows through the switching transistor G3, inductor L1, load R1, inductor L2, and switching transistor G6 to be connected to the negative bus.

[0058] In this embodiment of the present application, when switching transistors G2 and G3 are turned on, phase U is connected to the positive bus and phase W is connected to the negative bus. When the rated power of load R1 is greater than the rated power of load R2, the voltage of load R1 is smaller than the voltage of load R2, and the voltage of phase O is no longer 0 V but is a value deviating from 0 V. Because phase U is connected to the positive bus and phase W is connected to the negative bus, the voltage of phase O is a value greater than 0 V. Therefore, both the voltage between phase U and phase O and the voltage between phase O and phase W deviate from their rated values.

[0059] Specifically, for example, the voltage threshold is still 2 V. When the voltage between the U phase and the W phase is 202 V, if the voltage of the O phase is 3 V, the voltage between the U phase and the O phase is 98 V, and the voltage between the O phase and the W phase is 104 V. In other words, the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase is 6 V, which is greater than the voltage threshold. The controller can control the switching transistor G6 in the balancing circuit to turn on.

[0060] To reduce the voltage difference between the voltages between the U and O phases and the voltages between the O and W phases, it may be considered to reduce the voltage of the O phase. Because the switching transistor G6 is connected to the negative bus, the controller controls the switching transistor G6 to turn on. When the switching transistor G6 is turned on, the negative voltage on the negative bus may reduce the voltage of the O phase, resulting in an increase in the voltage between the U and O phases and a decrease in the voltage between the O and W phases. When the voltage difference between the voltages between the U and O phases and the voltages between the O and W phases is less than or equal to a voltage threshold, the controller turns off the switching transistor G6 to reduce the voltage difference between the voltages between the U and O phases and the voltages between the O and W phases, thereby solving the imbalance problem between the voltages between the U and O phases and the voltages between the O and W phases.

[0061] 2. The controller controls the switching transistor G5 to be turned on. (1) When the rated power of the load R1 is smaller than the rated power of the load R2, the voltage of the load R1 is larger than the voltage of the load R2. When the switching transistors G2 and G3 are turned on, the current direction is shown in Figure 9. Please refer to Figure 9. When a part of the DC output by the photovoltaic module flows through the switching transistor G3, inductor L1, load R1, load R2, inductor L1, and switching transistor G2 to form a current loop, another part of the DC flows through the switching transistor G5, inductor L2, load R2, inductor L1, and switching transistor G2 to form a current loop.

[0062] In this embodiment of the present application, when switching transistors G2 and G3 are turned on, phase U is connected to the positive bus and phase W is connected to the negative bus. When the rated power of load R1 is smaller than the rated power of load R2, the voltage of load R1 is larger than the voltage of load R2, and the voltage of phase O is no longer 0 V but is a value deviating from 0 V. Because phase U is connected to the positive bus and phase W is connected to the negative bus, the voltage of phase O is a value less than 0 V. Therefore, both the voltage between phase U and phase O and the voltage between phase O and phase W deviate from their rated values.

[0063] Specifically, for example, the voltage threshold is 2 V. When the voltage between the U phase and the W phase is 202 V, if the voltage of the O phase is −3 V, the voltage between the U phase and the O phase is 104 V, and the voltage between the O phase and the W phase is 98 V. In other words, the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase is 6 V, which is greater than the voltage threshold. The controller may control the switching transistor G5 in the balancing circuit to turn on.

[0064] To reduce the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase, it may be considered to increase the voltage of the O phase. Since the switching transistor G5 is connected to the positive bus, the controller controls the switching transistor G5 to turn on. When the switching transistor G5 is turned on, the DC positive voltage output on the positive bus may increase the voltage of the O phase, resulting in a decrease in the voltage between the U phase and the O phase and an increase in the voltage between the O phase and the W phase. When the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase is less than or equal to a voltage threshold, the controller turns off the switching transistor G5 to reduce the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase, thereby solving the imbalance problem between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0065] (2) When the rated power of the load R1 is greater than the rated power of the load R2, the voltage of the load R1 is smaller than the voltage of the load R2. When the switching transistors G1 and G4 are turned on, the current direction is shown in Figure 10. Please refer to Figure 10. When a part of the DC output by the photovoltaic module flows through the switching transistor G1, inductor L1, load R2, load R1, inductor L1, and switching transistor G4 to form a current loop, another part of the DC flows through the switching transistor G5, inductor L2, load R1, inductor L1, and switching transistor G4 to form a current loop.

[0066] In this embodiment of the present application, when the switching transistors G1 and G4 are turned on, the U phase is connected to the negative bus and the W phase is connected to the positive bus. When the rated power of the load R1 is greater than the rated power of the load R2, the voltage of the load R1 is smaller than the voltage of the load R2, and the voltage of the O phase is no longer 0 V but is a value deviating from 0 V. Because the U phase is connected to the negative bus and the W phase is connected to the positive bus, the voltage of the O phase is a value less than 0 V. Therefore, both the voltage between the U phase and the O phase and the voltage between the O phase and the W phase deviate from their rated values.

[0067] Specifically, for example, the voltage threshold is 2 V. When the voltage between the U phase and the W phase is 202 V, if the voltage of the O phase is −3 V, the voltage between the U phase and the O phase is 98 V, and the voltage between the O phase and the W phase is 104 V. In other words, the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase is 6 V, which is greater than the voltage threshold. The controller may control the switching transistor G5 in the balancing circuit to turn on.

[0068] To allow the voltage between the U phase and the O phase and the voltage between the O phase and the W phase to reach their rated values, it may be considered to increase the voltage of the O phase. Since the switching transistor G5 is connected to the positive bus, the controller controls the switching transistor G5 to turn on. When the switching transistor G5 is turned on, the positive voltage on the positive bus may increase the voltage of the O phase, resulting in an increase in the voltage between the U phase and the O phase and a decrease in the voltage between the O phase and the W phase. When the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase is less than or equal to the voltage threshold, the controller turns off the switching transistor G5 to reduce the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase, thereby solving the imbalance problem between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase.

[0069] It should be noted that in this embodiment of the present application, when the switching transistors G2 and G3 are turned on, the freewheeling diodes of the switching transistors G1 and G4 perform freewheeling. Because the current in the inductor L1 cannot change suddenly, the direction of the current flowing through the loads R1 and R2 also does not change suddenly, as shown by the current direction in FIG. 7 or FIG. 8. When the switching transistors G1 and G4 are turned on, the freewheeling diodes of the switching transistors G2 and G3 perform freewheeling. Because the current in the inductor L1 cannot change suddenly, the direction of the current flowing through the loads R1 and R2 also does not change suddenly, as shown by the current direction in FIG. 6 or FIG. 9.

[0070] In this embodiment of the present application, the controller can control the switching transistors in the balancing circuit to be turned on according to a specific case. Specifically, when the voltage of the first load is greater than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, the voltage at the connection point between the two loads is high, and the controller controls the switching transistor in the balancing circuit, which is directly connected to the negative bus, to be turned on, and the negative voltage of the negative bus can reduce the voltage at the series connection point of the two loads, thereby reducing the voltage difference between the two loads. When the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors is turned on, or when the voltage of the first load is smaller than the voltage of the second load and one set of switching transistors is turned on, the voltage at the connection point between the two loads is low, and the controller controls to turn on the switching transistor in the balance circuit directly connected to the positive bus, and the positive voltage of the positive bus can improve the voltage at the series connection point of the two loads, thereby reducing the voltage difference between the two loads.

[0071] It has been described above that the controller 340 controls the switching transistor G5 or the switching transistor G6 to be turned on in different cases. The following describes the duty cycle of the switching transistor G5 or the switching transistor G6 that is specifically controlled by the controller 340.

[0072] In an embodiment, the inverter further includes a voltage loop regulator, a current loop regulator, and an amplitude limiter, the amplitude limiter configured to limit a maximum current value in the balancing circuit.

[0073] 11, the voltage loop regulator is configured to output a first current value based on the voltage difference. The amplitude limiter is configured to output a second current value based on the first current value. The current loop regulator is configured to generate a duty cycle of a switching transistor in the balancing circuit based on a current difference between the second current value and the current value in the first inductor L2 to reduce the voltage difference below a voltage threshold. The second current value is less than or equal to the first current value.

[0074] In this embodiment of the present application, the voltage difference between the load R1 and the load R2 is used as the input of the voltage loop regulator. When the voltage loop regulator is stable, a corresponding current value is output, and the amplitude limiter outputs a second current value based on the current value. The current difference between the second current value and the current flowing through the first inductor L2 is used as the input of the current loop regulator, and the current loop regulator outputs the duty cycle of the switching transistor G5 or G6 so that the current difference is less than the current threshold and the voltage difference is less than the voltage threshold.

[0075] Specifically, when the voltage difference between load R1 and load R2 is 6V, the 6V voltage is used as the input of the voltage loop regulator. When the voltage loop regulator is stable, a corresponding current value is output. Assume that the current value is 5A, and the amplitude limiter outputs a second current value based on the current value. For example, the second current value is also 5A. The current difference between the 5A current value and the current flowing through the first inductor is used as the input of the current loop regulator, which outputs the duty cycle of the switching transistor G5, for example, the duty cycle is 0.5. When the controller controls the switching transistor G5 to be turned on and the duty cycle is 0.5, the voltage difference between load R1 and load R2 gradually decreases until the voltage difference is smaller than the voltage threshold.

[0076] In an embodiment, if the first current value is less than or equal to the absolute value of the maximum current value, the second current value is equal to the first current value, and if the first current value is greater than the absolute value of the maximum current value, the second current value is equal to the maximum current value.

[0077] In this embodiment of the present application, the amplitude limiter is configured to limit the maximum current value in the balancing circuit, and the second current value output by the amplitude limiter is less than or equal to the absolute value of the maximum current value, thereby avoiding damage to the switching transistor in the balancing circuit caused by a large current flowing through it and protecting the circuit topology. The maximum current value includes a maximum forward current value and a maximum reverse current value. When the first current value is less than or equal to the absolute value of the maximum current value, i.e., when the first current value is less than or equal to the maximum forward current value or when the first current value is greater than or equal to the maximum reverse current value, the current value output by the amplitude limiter is equal to the current value input by the amplitude limiter. When the first current value is greater than the maximum forward current value, the current value output by the amplitude limiter is the maximum forward current value used by the amplitude limiter to limit the balancing circuit. When the first current value is less than the maximum reverse current value, the current value output by the amplitude limiter is the maximum reverse current value used by the amplitude limiter to limit the balancing circuit.

[0078] For example, the absolute value of the maximum current value in the balancing circuit is 10 A. If the current value output by the voltage loop regulator is 5 A and the current value is smaller than the absolute value of the maximum current value in the balancing circuit, the current value output by the amplitude limiter is 5 A. If the current value output by the voltage loop regulator is 12 A and the current value is larger than the absolute value of the maximum current value in the balancing circuit, the current value output by the amplitude limiter is 10 A.

[0079] For ease of understanding, the dead time of the switching transistor will be briefly explained below.

[0080] Two switching transistors on the same bridge arm in an inverter circuit cannot be turned on at the same time. Otherwise, current will flow directly through the two switching transistors, resulting in a short circuit between the positive and negative electrodes of the power supply. To prevent two switching transistors on the same bridge arm from being turned on at the same time, there is a period during which the switching transistors on the upper and lower bridge arms are turned off, which is called dead time.

[0081] Continuing to refer to Figure 3, from time 0 to time t1, the switching transistors G1 and G4 are turned on, and the current direction is shown in Figure 12(a), where the current flows through the switching transistor G1, inductor L1, load R1, load R2, inductor L1, and switching transistor G4, forming a current loop.

[0082] At time t1, the controller controls the base signals of the switching transistors G1 and G2 to be inverted and the base signals of the switching transistors G3 and G4 to be inverted, so that the switching transistors G1 and G4 are turned off. Because the current in the inductor L1 cannot change suddenly, the switching transistors G2 and G3 cannot be turned on immediately, and the freewheeling diodes of the switching transistors G2 and G3 are turned on for freewheeling. The current direction is shown in Figure 12(b).

[0083] At time t2, the freewheeling diodes of the switching transistors G2 and G3 are cut off, and the switching transistors G2 and G3 begin to turn on, with the current direction shown in FIG.

[0084] In conclusion, in any one of the above stages, there is no case where the switching transistors G1 and G2 are turned on at the same time, or the switching transistors G3 and G4 are turned on at the same time, so that a short circuit between the positive and negative electrodes of the power supply is avoided. The period from t1 to t2 can be referred to as dead time.

[0085] As explained above, when the switching transistors G2 and G3 are turned on, the freewheel diodes of the switching transistors G1 and G4 perform freewheeling, and when the switching transistors G1 and G4 are turned on, the freewheel diodes of the switching transistors G2 and G3 perform freewheeling. Since the current in the inductor L1 cannot change suddenly, the direction of the current flowing through the loads R1 and R2 cannot change suddenly.

[0086] Assume that the direction of current flowing through the loads R1 and R2 when the switching transistors G2 and G3 are turned on is a positive half-cycle, and the direction of current flowing through the loads R1 and R2 when the switching transistors G1 and G4 are turned on is a negative half-cycle. In this embodiment of the present application, both the positive and negative half-cycles of each period include multiple dead times.

[0087] In some possible cases, even when switching transistor G5 or switching transistor G6 is turned on, the voltage difference between the voltages between the U and O phases and the voltages between the O and W phases is still large. Therefore, other measures can be taken to further improve performance. See below for more details.

[0088] In an embodiment, the controller 340 is further configured to reduce the dead time of the switching transistors in the inverter circuit 310 .

[0089] In this embodiment of the present application, by reducing the dead time of the switching transistors in the inverter circuit, the controller can further reduce the voltage difference between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase, thereby ameliorating the case of imbalance between the two voltages.

[0090] 1. Refer to FIG. 7. When the rated power of the load R1 is smaller than the rated power of the load R2 and the switching transistors G1 and G4 are turned on, a current flows through the switching transistor G1, the inductor L1, the load R2, the load R1, the inductor L1, and the switching transistor G4 to form a current loop, where the current loop can be referred to as the main power loop of G1 and G4. When the switching transistors G1 and G4 are turned off, the current in the inductor L1 cannot suddenly change, so the current in the inductor L1 is freewheeled through the freewheel diode of the switching transistor G2 and the freewheel diode of the switching transistor G3. The current loop can be referred to as the freewheel loop of G2 and G3. A specific freewheel loop is shown in FIG. 13.

[0091] When the switching transistors are switched from the freewheeling loop of G2 and G3 to the main power loop of G1 and G4, the rated power of the load R1 is smaller than that of the load R2, and the current flowing through the load R1 is smaller than that flowing through the load R2. Therefore, the current preferentially flows through the freewheeling diode of the switching transistor G4. This phenomenon is particularly evident when the rated power of the load R1 is much smaller than that of the load R2. When the current preferentially flows through the freewheeling diode of the switching transistor G4 and the U phase is connected to the negative bus, the voltage of the U phase decreases. This causes the voltage between the U phase and the O phase to further increase, worsening the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase. In other words, during the dead time of switching from the freewheeling loop of G2 and G3 to the main power loop of G1 and G4, current flows preferentially through the freewheeling diode of the switching transistor G4, which does not contribute to reducing the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0092] For example, when the switching transistors are switched from the freewheeling loop of G2 and G3 to the main power loop of G1 and G4, if current does not preferentially flow through the freewheeling diode of the switching transistor G4, the corresponding pulse width modulation (PWM) wave is shown in FIG. 14(a). When the switching transistors are switched from the freewheeling loop of G2 and G3 to the main power loop of G1 and G4, if current preferentially flows through the freewheeling diode of the switching transistor G4, the corresponding PWM wave is shown in FIG. 14(b). Referring to FIGS. 14(a) and 14(b), it can be seen that the width of the PWM wave shown in FIG. 14(b) is wider. This is because current preferentially flows through the freewheeling diode of the switching transistor G4, which results in the U phase being pre-connected to the negative bus, and the width of all pulses in the entire sinusoidal period is wider. After being filtered by the capacitor, the effective value of the equivalent sinusoidal signal increases, which worsens the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase. Therefore, in this embodiment of the present application, the controller may control to reduce the dead time, thereby improving the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase.

[0093] 2. Refer to FIG. 8. When the rated power of the load R1 is greater than the rated power of the load R2 and the switching transistors G2 and G3 are turned on, a current flows through the switching transistor G3, the inductor L1, the load R1, the load R2, the inductor L1, and the switching transistor G2 to form a current loop, which may be referred to as the main power loop of G2 and G3. When the switching transistors G2 and G3 are turned off, the current in the inductor L1 cannot change suddenly, so the current in the inductor L1 is freewheeled through the freewheel diode of the switching transistor G1 and the freewheel diode of the switching transistor G4. The current loop may be referred to as the freewheel loop of G1 and G4. A specific freewheel loop is shown in FIG. 15.

[0094] When the switching transistors are switched from the freewheeling loop of G1 and G4 to the main power loop of G2 and G3, the rated power of the load R1 is greater than the rated power of the load R2, and the current flowing through the load R1 is greater than the current flowing through the load R2. This phenomenon of the current preferentially flowing through the freewheeling diode of the switching transistor G2 is particularly evident when the rated power of the load R1 is much greater than the rated power of the load R2. When the current preferentially flows through the freewheeling diode of the switching transistor G2 and the W phase is connected to the negative bus, the voltage of the W phase decreases. This causes a further increase in the voltage between the W phase and the O phase, worsening the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase. In other words, during the dead time of switching from the freewheeling loop of G1 and G4 to the main power loop of G2 and G3, current flows preferentially through the freewheeling diode of the switching transistor G2, which does not contribute to reducing the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0095] For example, when the switching transistors are switched from the freewheeling loop of G1 and G4 to the main power loop of G2 and G3, if the current does not preferentially flow through the freewheeling diode of the switching transistor G2, the corresponding PWM wave is shown in FIG. 16(a). When the switching transistors are switched from the freewheeling loop of G1 and G4 to the main power loop of G2 and G3, if the current preferentially flows through the freewheeling diode of the switching transistor G2, the corresponding PWM wave is shown in FIG. 16(b). Referring to FIGS. 16(a) and 16(b), it can be seen that the width of the PWM wave shown in FIG. 16(b) is wider. This is because the current preferentially flows through the freewheeling diode of the switching transistor G2, which results in the W phase being connected to the negative bus in advance, widening the width of all pulses throughout the entire sine period. After being filtered by the capacitor, the effective value of the equivalent sine signal increases, which exacerbates the imbalance between the voltages between the U phase and the O phase and between the O phase and the W phase. Therefore, in this embodiment of the present application, the controller may control to reduce the dead time, thereby improving the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase.

[0096] 3. Refer to FIG. 9. When the rated power of the load R1 is smaller than the rated power of the load R2 and the switching transistors G2 and G3 are turned on, a current flows through the switching transistor G3, the inductor L1, the load R1, the load R2, the inductor L1, and the switching transistor G2 to form a current loop, which may be referred to as the main power loop of G2 and G3. When the switching transistors G2 and G3 are turned off, the current in the inductor L1 cannot change suddenly, so the current in the inductor L1 is freewheeled through the freewheel diode of the switching transistor G1 and the freewheel diode of the switching transistor G4. The current loop may be referred to as the freewheel loop of G1 and G4. A specific current loop is shown in FIG. 15.

[0097] When the switching transistors are switched from the freewheeling loop of G1 and G4 to the main power loop of G2 and G3, the rated power of the load R1 is smaller than that of the load R2, and the current flowing through the load R1 is smaller than that flowing through the load R2. Therefore, the current preferentially flows through the freewheeling diode of the switching transistor G3. This phenomenon is particularly evident when the rated power of the load R1 is much smaller than that of the load R2. When the current preferentially flows through the freewheeling diode of the switching transistor G3 and the U phase is connected to the positive bus, the voltage of the U phase rises. This causes a further increase in the voltage between the U phase and the O phase, worsening the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase. In other words, during the dead time of switching from the freewheel loop of G1 and G4 to the main power loop of G2 and G3, current preferentially flows through the freewheel diode of the switching transistor G3, which does not contribute to reducing the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase. Therefore, in this embodiment of the present application, the controller can control to reduce the dead time, thereby improving the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0098] 4. Refer to FIG. 10. When the rated power of the load R1 is greater than the rated power of the load R2 and the switching transistors G1 and G4 are turned on, a current flows through the switching transistor G1, the inductor L1, the load R2, the load R1, the inductor L1, and the switching transistor G4 to form a current loop, where the current loop can be referred to as the main loop of G1 and G4. When the switching transistors G1 and G4 are turned off, the current in the inductor L1 cannot suddenly change, so the current in the inductor L1 is freewheeled through the freewheel diode of the switching transistor G2 and the freewheel diode of the switching transistor G3. The current loop can be referred to as the freewheel loop of G2 and G3. A specific current loop is shown in FIG. 13.

[0099] When the switching transistors are switched from the freewheeling loop of G2 and G3 to the main power loop of G1 and G4, the rated power of the load R1 is greater than the rated power of the load R2, and the current flowing through the load R1 is greater than the current flowing through the load R2. This phenomenon of the current preferentially flowing through the freewheeling diode of the switching transistor G1 is particularly evident when the rated power of the load R1 is much greater than the rated power of the load R2. When the current preferentially flows through the freewheeling diode of the switching transistor G1 and the W phase is connected to the positive bus, the voltage of the W phase rises. This causes a further increase in the voltage between the W phase and the O phase, worsening the imbalance between the voltage between the U phase and the O phase and the voltage between the O phase and the W phase. In other words, during the dead time of switching from the freewheel loops of G2 and G3 to the main power loops of G1 and G4, current preferentially flows through the freewheel diode of the switching transistor G1, which does not contribute to reducing the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase. Therefore, in this embodiment of the present application, the controller can control to reduce the dead time, thereby improving the imbalance between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase.

[0100] In conclusion, when one set of switching transistors in the inverter circuit is turned on and then turned off, the current in the coupled inductor flows through the freewheeling diode of the other set of switching transistors in the inverter circuit, forming a freewheeling loop. When one set of switching transistors is turned on again, the current preferentially flows through the freewheeling diode of one of the switching transistors in the first set of switching transistors, thereby exacerbating the two-phase output voltage imbalance problem. Therefore, the controller can further reduce the voltage difference between the two loads by reducing the dead time of the switching transistors in the inverter circuit. In this way, the two-phase output voltage imbalance case can be improved.

[0101] In this embodiment, as shown in Fig. 17, the inverter further includes two other series-connected capacitors C3 and C4. The two other series-connected capacitors C3 and C4 are connected between the positive bus and the negative bus, and the series connection point of the two other series-connected capacitors C3 and C4 is connected to one end of the first inductor L2.

[0102] In this embodiment of the present application, two capacitors C3 and C4 connected in series can improve the ability to improve two-phase output voltage imbalance. Specifically, FIG. 3 is used as an example. In some possible cases, the switching transistors G5 and G6 in the balancing circuit may not be able to reduce the voltage difference between the U phase and the O phase and the O phase and the W phase indefinitely. Two additional capacitors C3 and C4 connected in series can further improve the imbalance between the U phase and the O phase and the O phase and the W phase.

[0103] For example, assume that the switching transistors G5 and G6 in the balancing circuit can reduce the voltage difference to a maximum of 20 V. When series-connected capacitors C3 and C4 are further added, the switching transistors G5 and G6 and the capacitors C3 and C4 in the balancing circuit can reduce the voltage difference to a maximum of 50 V.

[0104] In addition, the two series-connected capacitors C3 and C4 can reduce the selection specifications of the switching transistors G5 and G6, thereby reducing costs. Specifically, FIG. 3 is still used as an example. The switching transistors G5 and G6 in the balancing circuit may have a large overcurrent capability; for example, the maximum current that the switching transistors G5 and G6 can withstand reaches 60 A. When the series-connected capacitors C3 and C4 are further added, the capacitors C3 and C4 can reduce the voltage difference between the voltages between the U phase and the O phase and the voltages between the O phase and the W phase, so that the current flowing through the switching transistors G5 and G6 due to the voltage difference decreases. Therefore, the overcurrent capability of the switching transistors G5 and G6 is reduced. In other words, the selection specifications of the switching transistors G5 and G6 are reduced, thereby reducing costs for the switching transistors G5 and G6.

[0105] Additionally, the present application further provides a photovoltaic and storage system, comprising a photovoltaic module, an energy storage device, and an inverter according to any one of the above embodiments, wherein the energy storage device is configured to store direct current from the photovoltaic module, and the inverter is configured to convert the direct current from the photovoltaic module to alternating current.

[0106] For the inverter in the energy storage system, please refer to the relevant description in the above embodiment, and the details will not be described again.

[0107] In addition, the present application further provides an inverter control method. As shown in Figure 18, the method includes step S180.

[0108] S180: When the inverter operates in off-grid mode and the absolute value of the voltage difference between the two loads connected in series is greater than a voltage threshold, control the switching transistors in two switching transistors in the balancing circuit of the inverter to be turned on, thereby making the voltage difference smaller than the voltage threshold, and wherein the series connection point of the two loads connected in series is connected to the series connection point of the two capacitors connected in series in the filter circuit of the inverter.

[0109] The filter circuit includes a coupled inductor and two capacitors connected in series, the two input ports of the coupled inductor are connected to the inverter circuit of the inverter, and the two capacitors connected in series are connected between the two output ports of the coupled inductor; the balance circuit includes two switching transistors and a first inductor, the two switching transistors are connected in series and then connected between the positive bus and the negative bus, one end of the first inductor is connected to the series connection point of the two switching transistors, and the other end of the first inductor is connected to the series connection point of the two capacitors connected in series.

[0110] In an embodiment, the step of controlling to turn on the switching transistors of two switching transistors in the balancing circuit of the inverter includes the step of controlling to turn on the switching transistors directly connected to the negative bus in the balancing circuit when the voltage of the first load is greater than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on; or the step of controlling to turn on the switching transistors directly connected to the positive bus in the balancing circuit when the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is smaller than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on.

[0111] The inverter circuit includes a first bridge arm and a second bridge arm, each of which includes two switching transistors connected in series. Each switching transistor includes a freewheel diode connected in parallel, and all freewheel diodes have the same freewheel direction. One switching transistor of the first bridge arm and one switching transistor of the second bridge arm form an upper half bridge arm, and the other switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form a lower half bridge arm. The one switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form one set of switching transistors, and the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm form the other set of switching transistors. One end of the first load is connected to the series connection point of the two switching transistors of the second bridge arm through a filter circuit, and one end of the second load is connected to the series connection point of the two switching transistors of the first bridge arm through a filter circuit. The series connection point of the first load and the second load is connected to the series connection point of two capacitors connected in series.

[0112] In an embodiment, the method further comprises reducing a dead time of a switching transistor in the inverter circuit.

[0113] For the inverter control method, please refer to the above related content, and the details will not be described again.

[0114] The above description is merely a specific implementation of the present application, but is not intended to limit the scope of protection of the present application. Any modifications or substitutions that are easily understood by those skilled in the art within the technical scope disclosed in the present application shall fall within the scope of protection of the present application. Therefore, the scope of protection of the present application is subject to the scope of protection of the claims.

Claims

1. An inverter including an inverter circuit, a filter circuit, and a balance circuit, The inverter circuit is configured to convert direct current to alternating current, the filter circuit is configured to filter the alternating current, and the filtered alternating current is used to supply power to a load; the filter circuit includes a coupled inductor and two capacitors connected in series, two input ports of the coupled inductor are connected to the inverter circuit, and the two capacitors connected in series are connected between two output ports of the coupled inductor; The balance circuit includes two switching transistors and a first inductor, wherein the two switching transistors are connected in series and then connected between a positive bus and a negative bus, one end of the first inductor is connected to the series connection point of the two switching transistors, and the other end of the first inductor is connected to the series connection point of the two capacitors connected in series; The inverter further includes a controller, the controller comprising: When the inverter operates in an off-grid mode and an absolute value of a voltage difference between two loads connected in series is greater than a voltage threshold, controlling the switching transistors in the two switching transistors to be turned on, thereby allowing the voltage difference to be smaller than the voltage threshold, wherein a series connection point of the two loads connected in series is connected to the series connection point of the two capacitors connected in series. It is configured as follows: Inverter.

2. the inverter circuit includes a first bridge arm and a second bridge arm, each of the first bridge arm and the second bridge arm including two switching transistors connected in series, each switching transistor including a parallel freewheel diode, the freewheel directions of all the freewheel diodes being the same, one switching transistor of the first bridge arm and one switching transistor of the second bridge arm forming an upper half bridge arm, the other switching transistor of the first bridge arm and the other switching transistor of the second bridge arm forming a lower half bridge arm, the one switching transistor of the first bridge arm and the other switching transistor of the second bridge arm being one set of switching transistors, and the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm being another set of switching transistors; the two loads include a first load and a second load, one end of the first load is connected to the series connection point of the two switching transistors of the second bridge arm through the filter circuit, one end of the second load is connected to the series connection point of the two switching transistors of the first bridge arm through the filter circuit, and the series connection point of the first load and the second load is connected to the series connection point of the two capacitors connected in series; The controller: When the voltage of the first load is greater than the voltage of the second load and the one set of switching transistors is turned on, or when the voltage of the first load is less than the voltage of the second load and the other set of switching transistors is turned on, controlling the switching transistor in the balancing circuit that is directly connected to the negative bus to be turned on; or When the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors is turned on, or when the voltage of the first load is smaller than the voltage of the second load and the one set of switching transistors is turned on, the switching transistor in the balancing circuit that is directly connected to the positive bus is controlled to be turned on. It is configured as follows: The inverter according to claim 1 .

3. the inverter further comprising a voltage loop regulator, a current loop regulator, and an amplitude limiter, wherein the amplitude limiter is configured to limit a maximum current value in the balancing circuit; the voltage loop regulator is configured to output a first current value based on the voltage difference, the amplitude limiter is configured to output a second current value based on the first current value, and the current loop regulator is configured to generate a duty cycle of the switching transistor in the balancing circuit based on a current difference between the second current value and a current value on the first inductor, thereby allowing the voltage difference to be less than the voltage threshold, wherein the second current value is less than or equal to the first current value; The inverter according to claim 2 .

4. if the first current value is less than or equal to the absolute value of the maximum current value, the second current value is equal to the first current value; or If the first current value is greater than the absolute value of the maximum current value, the second current value is equal to the maximum current value. The inverter according to claim 3 .

5. The controller may further: configured to reduce a dead time of the switching transistor in the inverter circuit; The inverter according to any one of claims 2 to 4.

6. 5. The inverter according to claim 1, further comprising: another two capacitors connected in series; the another two capacitors connected in series are connected between the positive bus and the negative bus; and a series connection point of the another two capacitors connected in series is connected to one end of the first inductor.

7. 5. A photovoltaic and storage system comprising a photovoltaic module, an energy storage device, and the inverter of claim 1, wherein the energy storage device is configured to store direct current from the photovoltaic module, and the inverter is configured to convert the direct current from the photovoltaic module to alternating current.

8. When the inverter operates in an off-grid mode and the absolute value of the voltage difference between two loads connected in series is greater than a voltage threshold, controlling two switching transistors in a balancing circuit of the inverter to be turned on, thereby allowing the voltage difference to be smaller than the voltage threshold, wherein a series connection point of the two loads connected in series is connected to a series connection point of two capacitors connected in series in a filter circuit of the inverter, wherein: the filter circuit includes a coupled inductor and the two capacitors connected in series, two input ports of the coupled inductor are connected to an inverter circuit of the inverter, and the two capacitors connected in series are connected between two output ports of the coupled inductor; the balance circuit includes the two switching transistors and a first inductor, the two switching transistors are connected in series and then connected between a positive bus and a negative bus, one end of the first inductor is connected to the series connection point of the two switching transistors, and the other end of the first inductor is connected to the series connection point of the two capacitors connected in series; An inverter control method comprising:

9. The step of controlling to turn on the switching transistors in two switching transistors in the balancing circuit of the inverter includes: When the voltage of the first load is greater than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is less than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, controlling the switching transistors in the balancing circuit that are directly connected to the negative bus to be turned on; or controlling the switching transistor in the balancing circuit, which is directly connected to the positive bus, to be turned on when the voltage of the first load is greater than the voltage of the second load and the other set of switching transistors in the inverter circuit is turned on, or when the voltage of the first load is less than the voltage of the second load and one set of switching transistors in the inverter circuit is turned on, wherein: The inverter circuit includes a first bridge arm and a second bridge arm, each of the first bridge arm and the second bridge arm includes two switching transistors connected in series, each switching transistor includes a parallel freewheel diode, and the freewheel directions of all the freewheel diodes are the same. One switching transistor of the first bridge arm and one switching transistor of the second bridge arm form an upper half bridge arm, the other switching transistor of the first bridge arm and the other switching transistor of the second bridge arm form a lower half bridge arm, and the one switching transistor of the first bridge arm the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm are the one set of switching transistors, the other switching transistor of the first bridge arm and the one switching transistor of the second bridge arm are the other set of switching transistors, one end of the first load is connected to the series connection point of the two switching transistors of the second bridge arm through the filter circuit, one end of the second load is connected to the series connection point of the two switching transistors of the first bridge arm through the filter circuit, and the series connection point of the first load and the second load is connected to the series connection point of the two capacitors connected in series. The inverter control method according to claim 8, comprising:

10. The inverter control method further comprises: reducing the dead time of the switching transistor in the inverter circuit; The inverter control method according to claim 9, comprising:

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