Method for manufacturing semiconductor device and device for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device and a device for manufacturing the semiconductor device capable of reducing costs compared to conventional ones.SOLUTION: A method for manufacturing the semiconductor device includes steps of: applying a viscous material 8 to a surface 1 of a semiconductor wafer 3 on which an unevenness 4 is formed; curing the viscous material 8; and grinding a back surface 2 of the semiconductor wafer 3 provided with the cured viscous material 8. The surface 1 has the unevenness 4 formed by a reference surface 5 and a convex portion 6, and a variation in distance D between a surface 9 and the reference surface 5 in the cured viscous material 8 is 15% or less of an in-plane average A of the distance D on the surface 1 of the semiconductor wafer 3. This allows a fractured layer 19 on the back surface 2 to be made thinner after grinding, thereby enhancing the fracture strength of the semiconductor wafer 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method and an apparatus for manufacturing a semiconductor device, and in particular to a method and an apparatus for thinning a semiconductor wafer. [Background technology]

[0002] In the fields of memory and microprocessors, the packaging density of semiconductor devices is increasing through three-dimensional packaging, etc. This is accompanied by a demand for thinner semiconductor wafers.

[0003] Furthermore, power semiconductor devices that handle relatively large amounts of power, mainly from several hundred kilowatts to several megawatts, are sometimes used in inverter circuits mounted on air conditioner compressor motors, automobile motors, etc., and in undersea DC power transmission, etc. Power semiconductor devices include, for example, semiconductor switches such as diodes, metal-oxide-semiconductor field-effect transistors ("MOSFETs"), and insulated gate bipolar transistors ("IGBTs").

[0004] In the manufacture of these power semiconductor devices, semiconductor wafers are thinned to improve electrical properties such as on-resistance, which generally involves mechanical grinding (polishing) such as backgrinding and polishing, and chemical surface treatment such as wet etching and dry etching to remove any process-affected layers resulting from the mechanical grinding.

[0005] Among these, mechanical grinding (polishing) can cause cracks in the semiconductor wafer when grinding the backside of the semiconductor wafer due to the unevenness formed on the front side of the semiconductor wafer. In recent years, semiconductor devices have become thinner, and the proportion of the height difference of the unevenness to the overall thickness of the semiconductor device has increased. Therefore, in mechanical grinding (polishing), planarizing the front side of the semiconductor wafer has become increasingly important. There are various methods for planarizing the front side, one of which is to apply a resin to the uneven surface of the semiconductor wafer.

[0006] As an example, Patent Document 1 discloses a method in which a resin is applied to the surface side of a semiconductor wafer using a dispenser, a support substrate is then laminated on the surface of the uncured resin, and the resin is cured while maintaining the laminated state to flatten the surface of the resin layer. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2022-190916 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the method disclosed in Patent Document 1 requires laminating a support substrate on the surface of the uncured resin, which raises the problem of increased costs in manufacturing the semiconductor device.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device manufacturing method and semiconductor device manufacturing apparatus that can reduce costs compared to conventional methods. [Means for solving the problem]

[0010] The method for manufacturing a semiconductor device according to the present disclosure includes a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface behind the first main surface, a curing step of hardening the viscous material, and a grinding step of grinding the second main surface of the wafer having the hardened viscous material on the first main surface, wherein irregularities are formed on the first main surface by a reference surface corresponding to the surface of the wafer perpendicular to the thickness direction of the wafer and convex portions formed on the reference surface, and the variation in the distance between the surface of the hardened viscous material and the reference surface is 15% or less of the in-plane average of the distance on the first main surface.

[0011] In addition, the method for manufacturing a semiconductor device according to the present disclosure includes a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface behind the first main surface, a curing step of curing the viscous material, and a grinding step of grinding the second main surface of the wafer, wherein the coating step includes a first coating step of coating the viscous material into the recesses of the irregularities, and a second coating step of applying the viscous material to the first main surface after the first coating step.

[0012] In addition, the semiconductor device manufacturing apparatus according to the present disclosure includes a stage on which the second main surface of a wafer having a first main surface with irregularities formed thereon and a second main surface behind the first main surface is placed, a dispenser disposed opposite the stage and applying a viscous material to the first main surface with the wafer placed on the stage, and a housing covering the discharge portion of the dispenser and the stage, having an opening formed opposite the stage through which the discharge portion is inserted, and further having an exhaust port formed at a location different from the opening. [Effects of the Invention]

[0013] According to the semiconductor device manufacturing method and semiconductor device manufacturing apparatus according to the present disclosure, the cost of manufacturing a semiconductor device can be reduced compared to conventional methods. [Brief explanation of the drawings]

[0014] [Figure 1] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 2]FIG. 2 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S1. [Figure 3] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S4. [Figure 4] 10 is a scanning electron microscope image showing a cross section of a semiconductor wafer in step S4. [Figure 5] 1 is a schematic perspective view of a coating device according to a first embodiment. [Figure 6] 10(a) is a schematic cross-sectional view showing the state of the semiconductor wafer in step S4, and FIG. 10(b) is a schematic cross-sectional view showing the state of the semiconductor wafer in step S4 of another example. [Figure 7] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S5. [Figure 8] FIG. 10 is a diagram showing the relationship between the thickness of the fracture layer, the variation in the predetermined distance in the viscous material, and the fracture strength of the semiconductor wafer. [Figure 9] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S5. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S6. [Figure 11] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S8. [Figure 13] FIG. 10 is a schematic cross-sectional view showing the state of the semiconductor wafer in step S10. DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiment 1 FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. The manufacturing method is outlined as follows: a first main surface (hereinafter referred to as the "front surface") of a semiconductor wafer is formed with irregularities due to a transistor structure or the like; a viscous material is applied to the irregular surface; and the viscous material is then hardened. After the viscous material has hardened, a second main surface (hereinafter referred to as the "back surface") of the semiconductor wafer, which is located behind the first main surface, is thinned. During the thinning process, the viscous material protects the front surface of the semiconductor wafer. After the thinning process, a diffusion layer is formed on the back surface, and the viscous material on the front surface is removed. FIG. 2 shows a cross section of a semiconductor wafer 3 having irregularities 4 due to a transistor structure or the like formed on the front surface 1. FIG. 3 shows a cross section of the semiconductor wafer 3 after the viscous material 1 has hardened.

[0016] Next, a method for manufacturing a semiconductor device according to this embodiment will be described in detail with reference to the flowchart shown in FIG. 1 and the cross-sectional views shown in FIGS.

[0017] 2, a semiconductor wafer 3 having a front surface 1 and a rear surface 2 on the rear side thereof is prepared, and irregularities 4 are formed on the front surface 1 by transistor structures, electrodes, etc., completing the front surface wafer process. The irregularities 4 are formed by a reference surface 5 corresponding to the front surface 1 of the semiconductor wafer 3, which is perpendicular to the thickness direction of the front surface 1, and protrusions 6 such as transistor structures and electrodes formed on the reference surface 5, and recesses 7 are formed between the protrusions 6.

[0018] In step S2, as shown in Fig. 3, a viscous material 8 is directly applied to the surface 1 of the semiconductor wafer 3. The viscous material 8 is, for example, a thermosetting resin such as polyimide resin or an ultraviolet-curable resin such as epoxy resin, and is a fluid material that hardens when heated or exposed to ultraviolet light. In this embodiment, an example using a thermosetting resin will be described.

[0019] In step S3, the semiconductor wafer 3 is heated from the backside using a heating means such as a hot plate (not shown) to volatilize the solvent contained in the viscous material 8. The heating conditions are, for example, 150° C. for 3 minutes.

[0020] In step S4, the semiconductor wafer 3 is placed in a heating furnace (not shown) to harden the viscous material 8. The heating conditions are, for example, 300° C. for 60 minutes. This hardens the viscous material 8.

[0021] FIG. 4 shows a scanning electron microscope image of the cross section of the semiconductor wafer 3 after the viscous material 8 has hardened. The amount of viscous material 8 applied is such that the distance D between the reference surface 5 and the surface 9 of the viscous material 8 is greater than the height difference H of the irregularities 4 (the height of the convex portions 6 from the reference surface 5). In the semiconductor wafer 3 shown in FIG. 4, the distance D between the reference surface 5 and the surface 9 of the viscous material 8 is 23.7 μm, the height H of the convex portions 6 from the reference surface 5 is 23.7 μm - 17.7 μm = 6.0 μm, and the ratio D / H is approximately 3.9. The hardness of the hardened viscous material 8 is preferably an elastic modulus of 2 GPa or more so that it will not deform under pressure applied to the semiconductor wafer 3 during the grinding process of the back surface 2, which will be described later. Note that the distance D is measured, for example, from cross-sectional images (e.g., scanning electron microscope images) of multiple locations on the semiconductor wafer 3 after the viscous material 8 has hardened.

[0022] Here, an example of an apparatus for applying a viscous material 8 to the surface 1 of a semiconductor wafer 3 is shown. FIG. 5 is a schematic perspective view of the exterior of a coating apparatus 10. In FIG. 5, to make it easier to understand the interior of the coating apparatus 10, a housing 11 of the coating apparatus 10 is shown by a dashed line, and the internal configuration is shown by a solid line. The coating apparatus 10 has the housing 11, a coating stage 12 provided within the housing 11, a coating unit 13 arranged opposite the coating stage 12, and an exhaust port 14 for exhausting air from within the housing 11 to the outside.

[0023] The coating stage 12 is arranged horizontally, and the semiconductor wafer 3 is placed on the coating stage 12 with the surface 1 of the semiconductor wafer 3 facing upward. The coating stage 12 is configured to be movable horizontally by an actuator (not shown) or the like. An opening 15 is formed in the top surface of the housing 11 at a position opposite the coating stage 12, and an exhaust port 14 is formed on one side of the housing 11.

[0024] Coating unit 13 is a dispenser-type coating device that discharges a fixed amount using gas pressure or the like, and extends from the top of housing 11 through opening 15, with its lower end located inside housing 11. Discharge section 16 that discharges viscous material 8 filled in a syringe is provided at the lower end of coating unit 13. Discharge section 16 discharges viscous material 8 onto surface 1 of semiconductor wafer 3 placed on coating stage 12.

[0025] The operation of the coating unit 13 will now be described. With the semiconductor wafer 3 placed on the coating stage 12, a fixed amount of viscous material 8 is discharged from the discharge section 16, and then the coating stage 12 moves horizontally, and when an uncoated portion of the surface 1 of the semiconductor wafer 3 reaches directly below the discharge section 16, the viscous material 8 is discharged from the discharge section 16. By repeatedly performing these operations, the viscous material 8 is coated on the surface 1 of the semiconductor wafer 3.

[0026] By using a dispenser system that can adjust the discharge pressure according to the viscosity of the viscous material 8 in this way, the viscous material 8 can be applied with high precision according to the pattern of the unevenness 4. As a result, the flatness of the surface 9 of the viscous material 8 can be improved, and the amount of viscous material 8 used can be controlled. In addition, the coating stage 12 and the discharge part 16 of the coating unit 13 are covered by the housing 11, and an airflow is formed from the opening 15 to the exhaust port 14 by exhausting air from the exhaust port 14, so that turbulence of the airflow that occurs when the coating stage 12 is driven can be reduced. As a result, variation in the thickness (distance D) of the viscous material 8 can be suppressed.

[0027] 6 is a schematic cross-sectional view showing the entire semiconductor wafer 3 after application of the viscous material 8 has been completed. The surface 1 of the semiconductor wafer 3 includes an uneven region 17 where the unevenness 4 is formed, and a non-uneven region 18 located at the outer peripheral edge of the semiconductor wafer 3 where the unevenness 4 is not formed. As shown in FIG. 6(a), the viscous material 8 may be applied to the entire surface 1 of the semiconductor wafer 3, i.e., to the uneven region 17 and the non-uneven region 18, or as shown in FIG. 6(b), the viscous material 8 may be applied to the uneven region 17 but not to the non-uneven region 18.

[0028] When the viscous material 8 is applied to the entire surface 1 of the semiconductor wafer 3, the outer peripheral edge of the semiconductor wafer 3 can be protected, and cracks or chips at the outer peripheral edge of the semiconductor wafer 3 can be suppressed.

[0029] When the viscous material 8 is not applied to the non-relief region 18, the amount of viscous material 8 used can be reduced while the relieving region 17 is protected by the viscous material 8. In addition, it is not necessary to remove the viscous material 8 from the non-relief region 18, and it is possible to prevent the generation of foreign matter due to the falling off of the hardened viscous material 8 during transportation of the semiconductor wafer 3 and other processing steps.

[0030] In step S5, the back surface 2 of the semiconductor wafer 3 is thinned by mechanical grinding. FIG. 7 shows a cross section of the semiconductor wafer 3 after being thinned in step S5. As a result of the above-described thinning, a fractured layer 19 is formed on the back surface 2 of the semiconductor wafer 3, as shown in FIG. 7. The fractured layer 19 may be chemically removed by wet etching using a mixed acid containing hydrofluoric acid and acetic acid, if necessary.

[0031] FIG. 8 shows the relationship between the thickness of the fracture layer 19, the variation in the distance D between the surface 9 of the viscous material 8 and the reference plane 5, and the fracture strength of the semiconductor wafer 3. The inventors have found that, as shown in FIG. 8, when the variation in the distance D is 15% or less of the in-plane average A of the distance D on the surface 9 of the viscous material 8, in other words, when the difference between the distance D and the in-plane average A is 15% or less of the in-plane average A, a decrease in the fracture strength of the semiconductor wafer 3 can be suppressed. Here, the in-plane average A is the average value of the distance D measured at multiple points at random positions on the surface 9 of the viscous material 8. Specifically, when the distance D is 15% or less of the in-plane average A, the fracture strength of the semiconductor wafer 3 gradually decreases as the variation in the distance D increases, but a fracture strength sufficient to suppress cracks and breakage of the semiconductor wafer 3 during semiconductor device manufacturing is maintained. On the other hand, if the variation in the distance D exceeds 15% of the in-plane average A, the thickness of the fractured layer 19 increases, and the fracture strength of the semiconductor wafer 3 decreases.

[0032] Based on the above findings, the presently disclosed invention aims to improve the fracture strength of the semiconductor wafer 3 by reducing the variation in the distance D between the surface 9 of the hardened viscous material 8 and the reference surface 5 to 15% or less of the in-plane average A of the distance D.

[0033] By applying the viscous material 8 by controlling the gas pressure of the application unit 13 so that the variation in the distance D between the surface 9 of the viscous material 8 and the reference plane 5 is 15% or less of the in-plane average A of the distance D, the thickness of the fracture layer 19 can be reduced, thereby increasing the fracture strength of the semiconductor wafer 3. Therefore, the conventional stacking of support substrates and cutting of the resin surface are unnecessary. In particular, when stacking support substrates, the support substrates must be stacked parallel to the semiconductor wafer, which requires time and effort to position and hold the support substrates. Furthermore, it is possible to reduce the grinding time of the fracture layer 19 and the amount of chemical solution used in chemical grinding. As described above, the semiconductor device manufacturing method according to this embodiment can reduce the cost of semiconductor device manufacturing compared to conventional methods.

[0034] 9 shows a cross section of the semiconductor wafer 3 after the diffusion layer 20 has been formed in step S6. In step S6, as shown in FIG. 9, the diffusion layer 20 is formed on the rear surface 2 of the semiconductor wafer 3 by ion implantation or the like, and an electrode is formed by sputtering.

[0035] FIG. 10 shows a cross section of the semiconductor wafer 3 after the viscous material 8 has been removed in step S7. In step S7, as shown in FIG. 10, the viscous material 8 is removed from the surface 1 of the semiconductor wafer 3. The viscous material 8 can be removed by the following methods. For example, an organic solvent is dropped onto the surface 9 of the viscous material 8 to dissolve and remove the viscous material 8. Alternatively, the viscous material 8 can be removed by ashing, which involves irradiating the viscous material 8 with oxygen-containing plasma to carbonize and remove the viscous material 8. Alternatively, the viscous material 8 can be removed by using a mixed solution containing sulfuric acid and hydrogen peroxide. When using a mixed solution to perform the removal method, the above-mentioned plasma irradiation may be used in combination. There are various methods for removing the viscous material 8, but in this embodiment, the viscous material 8 is removed using an organic solvent.

[0036] As described above, according to the method for manufacturing a semiconductor device of this embodiment, the thickness of the fracture layer 19 can be reduced to increase the fracture strength of the semiconductor wafer 3, thereby reducing the cost of manufacturing a semiconductor device compared to conventional methods.

[0037] Embodiment 2 11 is a flowchart showing a method for manufacturing a semiconductor device according to embodiment 2. In the method for manufacturing a semiconductor device according to this embodiment, components and steps similar to those in the manufacturing method according to embodiment 1 are denoted by the same reference numerals, and the following description will focus on differences from embodiment 1.

[0038] 11, in the manufacturing method according to the present embodiment, steps S8 to S11 are performed between the front surface wafer process (step S1) and the back surface grinding and wet etching process (step S5) in the manufacturing flow (FIG. 1) according to the first embodiment. Specifically, a first viscous material application process (step S8), a first viscous material hardening process (step S9), a second viscous material application process (step S10), and a second viscous material hardening process (step S11) are performed. Each process will be described below.

[0039] FIG. 12 shows a cross section of the semiconductor wafer 3 after the first viscous material 21 has been applied in step S8. In step S8, as shown in FIG. 12, the first viscous material 21 is applied to the surface 1 of the semiconductor wafer 3, primarily to the recesses 7 of the irregularities 4. This fills the recesses 7 with the first viscous material 21, smoothing the surface of the irregularities 4 and improving flatness. Furthermore, using a dispenser-type application unit 13 allows the first viscous material 21 to be applied to the recesses 7 with high positioning accuracy, thereby contributing to improving the flatness of the surface of the irregularities 4. Furthermore, the amount of the first viscous material 21 applied can be controlled, thereby reducing the amount of the first viscous material 21 used. The application of the first viscous material 21 is not limited to the application unit 13, and may be performed using, for example, a spin coater (not shown). However, since the first viscous material 21 is applied to the recesses 7 of the irregularities 4, which are relatively small areas, it is preferable to use a dispenser method with high positioning accuracy.

[0040] The first viscous material 21 is a thermosetting resin, similar to the viscous material 8 of embodiment 1. The first viscous material 21 is not limited to a thermosetting resin, and may be, for example, an ultraviolet curable resin.

[0041] In step S9, the first viscous material 21 is hardened. Specifically, the first viscous material 21 is thermally hardened in the same manner as in steps S3 and S4 of the first embodiment.

[0042] 13 shows a cross section of the semiconductor wafer 3 after the second viscous material 22 has been applied in step S10. In step S10, as shown in FIG. 13, a second viscous material 22 different from the first viscous material 21 is applied to the surface 1 of the semiconductor wafer 3 after the first viscous material 21 has hardened. The method for applying the second viscous material 22 is not particularly limited, but it is preferable to use a spin coater. By using a spin coater, the second viscous material 22 spreads smoothly from the center to the periphery of the semiconductor wafer 3 over the smoothed surface of the unevenness 4, thereby reducing the application time and improving production efficiency.

[0043] The second viscous material 22 is a thermosetting resin, similar to the viscous material 8 of embodiment 1. The second viscous material 22 is not limited to a thermosetting resin, and may be, for example, an ultraviolet curable resin.

[0044] It is preferable that the viscosity of the first viscous material 21 is higher than the viscosity of the second viscous material 22. In this case, the high-viscosity first viscous material 21 is less likely to spread within the recesses 7 of the irregularities 4 and is more likely to remain within the recesses 7, thereby increasing the flatness of the irregularities 4, and the low-viscosity second viscous material 22 spreads, thereby increasing the flatness of the surface 23 of the second viscous material 22.

[0045] In step S11, the first viscous material 21 is hardened. Specifically, the first viscous material 21 is thermally hardened in the same manner as in steps S3 and S4 of the first embodiment.

[0046] As described above, the second viscous material 22 can be applied to the surface whose irregularities 4 have been smoothed by the first viscous material 21, thereby forming a highly flat surface of the second viscous material 22. As a result, the variation in the distance D between the surface 23 of the second viscous material 22 and the reference surface 5 can be suppressed to 15% or less of the in-plane average A of the distance D on the surface 1 of the semiconductor wafer 3.

[0047] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0048] In embodiment 1, the viscous material 8 was not applied to the non-rough region 18 on the surface 1 of the semiconductor wafer 3, but this is not limited to this, and the viscous material may be applied to the non-rough region 18, and the applied thickness of the viscous material in the non-rough region 18 may be smaller than the applied thickness in the rough region 17.

[0049] In the second embodiment, the first viscous material and the second viscous material are materials with different viscosities, but they may be materials with the same viscosity.

[0050] In the second embodiment, the first viscous material 21 and the second viscous material 22 have different viscosities, but are not limited to this. For example, the first viscous material 21 and the second viscous material 22 may have different curing shrinkage rates, hardness after curing, and chemical resistance. If the curing shrinkage rates are different, it is preferable that the curing shrinkage rate of the first viscous material 21 is greater than that of the second viscous material 22. If the hardness after curing is different, it is preferable that the hardness of the first viscous material 21 is greater than that of the second viscous material 22.

[0051] In addition, in embodiment 2, the first viscous material and the second viscous material are hardened separately, but this is not limited to this. For example, the second viscous material may be applied after the first viscous material is applied, and both may be hardened in one step.

[0052] Furthermore, in the first and second embodiments, the viscous material is applied once or twice, but this is not limitative and it may be applied three or more times.

[0053] Various aspects of the present disclosure are summarized below as appendices.

[0054] (Appendix 1) a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface on the back side of the first main surface; a curing step of curing the viscous material; a grinding step of grinding the second main surface of the wafer, the first main surface has a reference surface corresponding to a surface of the wafer perpendicular to a thickness direction of the wafer and a protrusion formed on the reference surface, a variation in the distance between the surface of the hardened viscous material and the reference surface is 15% or less of the in-plane average of the distance on the first main surface; 10. A method for manufacturing a semiconductor device comprising the steps of:

[0055] (Appendix 2) a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface on the back side of the first main surface; a curing step of curing the viscous material; a grinding step of grinding the second main surface of the wafer, The application step includes a first application step of applying the viscous material to the recesses of the unevenness, and a second application step of applying the viscous material to the first main surface after the first application step. 10. A method for manufacturing a semiconductor device comprising the steps of:

[0056] (Appendix 3) the first main surface has a reference surface corresponding to a surface of the wafer perpendicular to a thickness direction of the wafer and a protrusion formed on the reference surface, a variation in the distance between the surface of the hardened viscous material and the reference surface is 15% or less of the in-plane average of the distance on the first main surface; 3. A method for manufacturing a semiconductor device according to claim 2.

[0057] (Appendix 4) The viscosity of the viscous material applied in the first application step is higher than the viscosity of the viscous material applied in the second application step. 4. A method for manufacturing a semiconductor device according to claim 2 or 3.

[0058] (Appendix 5) In the first application step, the viscous material is applied using a dispenser; In the second coating step, the viscous material is coated using a spin coater. 5. A method for manufacturing a semiconductor device according to any one of claims 2 to 4.

[0059] (Appendix 6) the first main surface has the uneven region and a non-uneven region located outside the uneven region, In the application step, the viscous material is applied to the uneven region and the viscous material is not applied to the non-uneven region, or the viscous material is applied so that the thickness of the viscous material applied to the non-uneven region is smaller than the thickness of the viscous material applied to the uneven region. 6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

[0060] (Appendix 7) a stage on which the second main surface of a wafer having a first main surface on which projections and depressions are formed and a second main surface on the back side of the first main surface is placed; a dispenser disposed opposite the stage and configured to apply the viscous material to the first main surface while the wafer is placed on the stage; a housing that covers the discharge portion of the dispenser and the stage, has an opening formed therein through which the discharge portion is inserted so as to face the stage, and has an exhaust port formed at a position different from the opening; 1. A semiconductor device manufacturing apparatus comprising: [Explanation of symbols]

[0061] 1 First principal surface (front surface), 2 Second principal surface (rear surface), 3 Semiconductor wafer, 4 Concave and convex portions, 5 Reference surface, 6 Convex portions, 7 Concave portions, 8 Viscous material, 9 Surface of viscous material, 10 Coating device, 11 Housing, 12 Coating stage, 13 Coating unit, 14 Exhaust port, 15 Opening, 16 Discharge portion, 17 Concave and convex portions, 18 Non-concave and convex portions, 19 Crushed layer, 20 Diffusion layer, 21 First viscous material, 22 Second viscous material, 23 Surface of second viscous material

Claims

1. a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface on the back side of the first main surface; a curing step of curing the viscous material; a grinding step of grinding the second main surface of the wafer, the first main surface has a reference surface corresponding to a surface of the wafer perpendicular to a thickness direction of the wafer and a protrusion formed on the reference surface, a variation in the distance between the surface of the hardened viscous material and the reference surface is 15% or less of the in-plane average of the distance on the first main surface; 10. A method for manufacturing a semiconductor device comprising the steps of:

2. a coating step of coating a viscous material onto a first main surface of a wafer having a first main surface on which irregularities are formed and a second main surface on the back side of the first main surface; a curing step of curing the viscous material; a grinding step of grinding the second main surface of the wafer, The application step includes a first application step of applying the viscous material to the recesses of the unevenness, and a second application step of applying the viscous material to the first main surface after the first application step.

10. A method for manufacturing a semiconductor device comprising the steps of:

3. the first main surface has a reference surface corresponding to a surface of the wafer perpendicular to a thickness direction of the wafer and a protrusion formed on the reference surface, a variation in the distance between the surface of the hardened viscous material and the reference surface is 15% or less of the in-plane average of the distance on the first main surface; 3. The method for manufacturing a semiconductor device according to claim 2.

4. The viscosity of the viscous material applied in the first application step is higher than the viscosity of the viscous material applied in the second application step.

3. The method for manufacturing a semiconductor device according to claim 2.

5. In the first application step, the viscous material is applied using a dispenser; In the second coating step, the viscous material is coated using a spin coater.

3. The method for manufacturing a semiconductor device according to claim 2.

6. the first main surface has the uneven region and a non-uneven region located outside the uneven region, In the application step, the viscous material is applied to the uneven region and the viscous material is not applied to the non-uneven region, or the viscous material is applied so that the thickness of the viscous material applied to the non-uneven region is smaller than the thickness of the viscous material applied to the uneven region.

6. The method for manufacturing a semiconductor device according to claim 1,

7. a stage on which the second main surface of a wafer having a first main surface on which projections and depressions are formed and a second main surface on the back side of the first main surface is placed; a dispenser disposed opposite the stage and configured to apply a viscous material to the first main surface while the wafer is placed on the stage; a housing that covers the discharge portion of the dispenser and the stage, has an opening formed therein through which the discharge portion is inserted so as to face the stage, and has an exhaust port formed at a position different from the opening; 1. A semiconductor device manufacturing apparatus comprising:

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