Mask, vapor deposition apparatus, and manufacturing method of mask

Abstract

To provide a mask with an improved reliability such that a vapor deposit material is deposited only in a predetermined vapor deposit region when the vapor deposit material injected from a vapor deposition source is vapor deposited on a target substrate through a mask.SOLUTION: A mask (100) includes a first layer (110) defining a first opening (OP1), and a second layer (120) that is arranged on the first layer, defines a second opening (OP2) overlapped on the first opening (OP1) on a plane, has a vapor deposition pattern (DP) with a reverse tapered profile in a cross section, and includes a silicon with a [100] crystal orientation.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a mask, a deposition apparatus including the mask, and a method for manufacturing the mask. [Background technology]

[0002] A display device is formed by stacking multiple layers, such as a light-emitting layer and a metal layer. A deposition process is performed to form the multiple layers of the display device. The deposition process is performed by closely contacting a target substrate on which deposition is performed with a mask having the same pattern as the light-emitting layer, the metal layer, etc. Here, a deposition material sprayed from a deposition source is deposited on the target substrate through the mask. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 2021-0096891 (KR10-2021-0096891A) [Patent Document 2] Korean Patent Publication No. 2023-0089374 (KR10-2023-0089374A) Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide a mask with improved reliability.

[0005] Another object of the present invention is to provide a deposition apparatus including the mask.

[0006] Another object of the present invention is to provide a method for manufacturing the mask.

[0007] However, the object of the present invention is not limited to the above object, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object of the present invention, a mask according to the present invention includes a first layer defining a first opening, and a deposition pattern disposed on the first layer defining a second opening overlapping the first opening in a planar view, the deposition pattern having an inverse tapered shape in cross section, and a crystal orientation of <100> and a second layer comprising silicon in which

[0009] The angle formed between one surface of the vapor deposition pattern that is separated from the first layer and a side surface of the vapor deposition pattern is 45° or more and 75° or less.

[0010] The width of each of the second openings is equal to or greater than the thickness of the deposition pattern.

[0011] The first layer includes silicon.

[0012] The mask further includes an insulating layer disposed between the first layer and the second layer.

[0013] In order to achieve the above-mentioned object of the present invention, a deposition apparatus according to the present invention includes a deposition source that contains a deposition material, a mask that is disposed on the deposition source and through which the deposition material passes, and a stage that is disposed on the mask and on which a target substrate onto which the deposition material is deposited is fixed, the mask including: (1) a first layer that defines a first opening; and (2) a deposition pattern that is disposed on the first layer and defines a second opening that overlaps the first opening in a planar view, the deposition pattern having an inverse tapered shape in a cross section, and a crystal orientation of <100> and a second layer comprising silicon in which

[0014] The angle formed between one surface of the vapor deposition pattern that is separated from the first layer and a side surface of the vapor deposition pattern is 45° or more and 75° or less.

[0015] The width of each of the second openings is greater than or equal to the thickness of the deposition pattern.

[0016] The first layer includes silicon.

[0017] The mask further includes an insulating layer disposed between the first layer and the second layer.

[0018] In order to achieve the above-mentioned object of the present invention, a method for manufacturing a mask according to the present invention includes the steps of: etching a preliminary first layer to form a first layer defining a first opening; and etching a first layer disposed below the preliminary first layer, the first layer having a crystal orientation of <100> and etching a preliminary second layer comprising silicon having a thickness of 1000 nm to define a second opening that overlaps the first opening on a plane, thereby forming a second layer having a deposition pattern that has an inverse tapered shape on a cross section.

[0019] In the step of forming the second layer, the deposition pattern is formed such that one surface of the deposition pattern that is separated from the first layer and a side surface of the deposition pattern form an angle of 45° to 75°.

[0020] In the step of forming the second layer, the width of each of the second openings is formed to be greater than or equal to the thickness of the deposition pattern.

[0021] In the step of forming the second layer, the preliminary second layer is etched using an etching solution containing potassium hydroxide (KOH).

[0022] The concentration of the potassium hydroxide is 15 wt % or more and 70 wt % or less.

[0023] The temperature of the etching solution containing potassium hydroxide is 50°C or higher and 100°C or lower.

[0024] The step of forming the first layer includes the step of etching the preliminary first layer to form an auxiliary pattern that defines an auxiliary opening.

[0025] The step of forming the auxiliary pattern includes the steps of etching the preliminary first layer to form a first sub-opening, and etching the preliminary first layer to form a second sub-opening connected to the first sub-opening.

[0026] In the step of forming the second layer, the auxiliary pattern of the preliminary first layer and the preliminary second layer are etched simultaneously.

[0027] The method for manufacturing the mask further includes the step of etching a preliminary insulating layer disposed between the preliminary first layer and the preliminary second layer to form an insulating layer. [Effects of the Invention]

[0028] The deposition apparatus according to the present invention includes a mask having silicon. The mask defines an opening, has an inverted tapered cross section, and includes a deposition pattern. This prevents deposition material deposited on a target substrate through the opening in the mask from being deposited in areas outside the deposition area of ​​the target substrate. Therefore, in a display device manufactured using the mask, stains and color mixing on the display device, which occur when deposition material is deposited in areas outside the deposition area of ​​the target substrate, can be minimized.

[0029] In addition, in the mask manufacturing method according to the present invention, the wafer etching process is performed sequentially in one direction, which eliminates the need to turn the wafer over during the wafer etching process, thereby minimizing problems such as foreign particles that may occur when the wafer is turned over during the mask manufacturing process.

[0030] However, the effects of the present invention are not limited to the above-described effects, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0031] [Figure 1]FIG. 1 is a cross-sectional view schematically showing a vapor deposition apparatus according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing a mask included in the deposition apparatus of FIG. [Figure 3] 3A to 3C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 4] 4A to 4C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 5] 5A to 5C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 6] 6A to 6C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 7] 7A to 7C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 8] 8A to 8C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 9] 9A to 9C are cross-sectional views showing a method for manufacturing the mask of FIG. [Figure 10] FIG. 10 is a cross-sectional view schematically showing a display device manufactured using the vapor deposition apparatus of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to denote the same components in the drawings, and redundant description of the same components will be omitted.

[0033] FIG. 1 is a cross-sectional view schematically showing a vapor deposition apparatus according to one embodiment of the present invention.

[0034] As shown in FIG. 1, the deposition apparatus 1000 includes a chamber (CB), a mask 100 , a deposition source 200 , and a stage 300 .

[0035] The deposition apparatus 1000 deposits a deposition material on a target substrate 10. The target substrate 10 is a substrate for manufacturing a display device. For example, the target substrate 10 refers to a display device under manufacture. The target substrate 10 may include a plastic substrate, a glass substrate, a silicon substrate, or the like, and may further include at least one layer included in the display device. For example, the target substrate 10 may further include at least one inorganic layer, an organic layer, or a metal layer.

[0036] That is, the deposition apparatus 1000 is used in the manufacturing process of the display device. For example, the deposition apparatus 1000 is used in the process of depositing a light-emitting layer on a target substrate 10 in the manufacturing process of the display device. However, the present invention is not limited thereto, and the deposition apparatus 1000 can be used in various deposition processes in the manufacturing process of the display device.

[0037] In one embodiment, the display device is a micro LED display device (or a micro LED display device) including a micro LED (or a micro LED) as a light-emitting element. However, the present invention is not limited thereto. In another embodiment, the display device is an organic LED display device including an organic light-emitting diode as a light-emitting element.

[0038] The chamber (CB) provides an internal space for performing a deposition process. In one embodiment, the chamber (CB) is used for evaporation, in which a deposition material is evaporated and deposited on the target substrate 10. In this case, the interior of the chamber (CB) is maintained at a vacuum.

[0039] Various components used in the deposition process are disposed in the chamber (CB), such as the mask 100, the deposition source 200, and the stage 300.

[0040] The mask 100 is parallel to a plane defined by a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the first direction (DR1) and the second direction (DR2) are perpendicular to each other. The mask 100 has a pattern, and the deposition material is deposited on the target substrate 10 in a pattern corresponding to the pattern. For example, the mask 100 includes a deposition membrane that defines a plurality of openings, each of which corresponds to a deposition region on the target substrate 10.

[0041] In one embodiment, the mask 100 includes silicon, such as a silicon wafer (Si wafer), a silicon carbide wafer (SiC wafer), or a single crystal silicon wafer (single crystal Si wafer).

[0042] 1, the mask 100 is shown spaced a predetermined distance from the target substrate 10, but is not limited thereto. For example, the mask 100 may be disposed in contact with the target substrate 10.

[0043] The deposition source 200 is disposed opposite the mask 100. For example, the deposition source 200 is disposed below the mask 100 and faces the target substrate 10 across the mask 100.

[0044] The deposition source 200 accommodates the deposition material. The deposition source 200 provides the deposition material to the target substrate 10. For example, the deposition source 200 vaporizes the deposition material, and the vaporized deposition material is provided toward the target substrate 10. For example, the deposition material is provided in a third direction (DR3) intersecting the first direction (DR1) and the second direction (DR2). For example, the third direction (DR3) is perpendicular to the first direction (DR1) and the second direction (DR2). Here, the vaporized deposition material is deposited on the target substrate 10 through the mask 100. That is, the deposition material is deposited in the deposition region on the target substrate 10 through the openings in the mask 100. For example, the deposition source 200 provides an organic material that forms an emission layer included in the display device, but is not limited thereto.

[0045] The stage 300 is disposed opposite the deposition source 200 and facing the mask 100. For example, the stage 300 is disposed above the mask 100 and faces the deposition source 200 across the mask 100. The target substrate 10 is fixed to the stage 300. The target substrate 10 is fixed to the stage 300 and disposed between the stage 300 and the mask 100.

[0046] Fig. 2 is a cross-sectional view showing a mask included in the deposition apparatus of Fig. 1. For example, Fig. 2 is a cross-sectional view showing a schematic portion of the mask 100.

[0047] As shown in FIGS. 1 and 2, the mask 100 includes a first layer 110, a second layer 120, and an insulating layer .

[0048] In one embodiment, the first layer 110 includes silicon. The first layer 110 includes crystalline silicon. For example, the first layer 110 includes monocrystalline silicon.

[0049] The first layer 110 defines a first opening (OP1), which penetrates the first layer 110 in the third direction (DR3).

[0050] The second layer 120 is disposed on the first layer 110. In one embodiment, the second layer 120 comprises silicon. The second layer 120 comprises silicon crystals. For example, the second layer 120 comprises single crystal silicon. In one embodiment, the second layer 120 has a crystal orientation <100> Here, the crystal orientation of the silicon contained in the second layer 120 is different from or the same as the crystal orientation of the silicon contained in the first layer 110.

[0051] The second layer 120 defines a plurality of second openings (OP2). The second layer 120 includes a deposition pattern (DP) that defines the second openings (OP2). Each of the second openings (OP2) penetrates the second layer 120 in the third direction (DR3). The second openings (OP2) are repeatedly arranged along the first direction (DR1) or the second direction (DR2) and are spaced apart from each other. For example, the second openings (OP2) are arranged in a matrix along the first direction (DR1) and the second direction (DR2). For example, the second openings (OP2) are arranged along either the first direction (DR1) or the second direction (DR2). The deposition pattern (DP) is disposed between adjacent second openings (OP2). For example, the deposition pattern (DP) has a net-like shape in a plan view.

[0052] The second opening (OP2) overlaps with the first opening (OP1) in a plane. The second opening (OP2) is connected to the first opening (OP1). The first opening (OP1) and the second opening (OP2) penetrate the mask 100 in the third direction (DR3).

[0053] In one embodiment, the deposition pattern (DP) has an inversely tapered cross section. That is, the width of the deposition pattern (DP) gradually increases in the third direction (DR3), and the side surface (SS) of the deposition pattern (DP) is inclined. Here, the width of the deposition pattern (DP) is the length of the deposition pattern (DP) in the first direction (DR1). The side surface (SS) of the deposition pattern (DP) is inclined at a certain angle as it extends along the thickness direction of the deposition pattern (DP) (i.e., the third direction (DR3) or the direction opposite to the third direction (DR3)). This limits the angle at which the deposition material provided in the third direction (DR3) toward the target substrate 10 passes through the mask 100.

[0054] In one embodiment, the angle (θ) between a surface (SF) of the deposition pattern (DP) that is separated from the first layer 110 and the side surface (SS) of the deposition pattern (DP) is 45° to 75°. Preferably, the angle (θ) is 50° to 60°. More preferably, the angle (θ) is 53° to 57°. The angle (θ) is adjusted so that the deposition material passing through the mask 100 is not deposited in areas outside the deposition area of ​​the target substrate 10.

[0055] In one embodiment, the width (WD) of the second opening (OP2) is greater than or equal to the thickness (TH) of the deposition pattern (DP). Here, the width (WD) of the second opening (OP2) is the length of the second opening (OP2) in the first direction (DR1), and the thickness (TH) of the deposition pattern (DP) is the length of the deposition pattern (DP) in the third direction (DR3). That is, on the cross section, the separation distance of the deposition pattern (DP) defining the second opening (OP2) in the first direction (DR1) is greater than or equal to the thickness (TH) of the deposition pattern (DP). For example, the width (WD) of the second opening (OP2) is 4 μm or more and 5 μm or less, and the thickness (TH) of the deposition pattern (DP) is 1 μm or more and approximately 4 μm or less, but is not limited thereto.

[0056] If the thickness (TH) of the deposition pattern (DP) is greater than the width (WD) of the second opening (OP2), an area where the deposition material is not sufficiently deposited will occur in the deposition area on the target substrate 10. Therefore, by forming the width (WD) of the second opening (OP2) to be greater than or equal to the thickness (TH) of the deposition pattern (DP), it is possible to minimize the area where the deposition material is not sufficiently deposited in the deposition area on the target substrate 10.

[0057] The insulating layer 130 is disposed between the first layer 110 and the second layer 120. The insulating layer 130 includes an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), etc. The insulating layer 130 defines an opening corresponding to the first opening (OP1) of the first layer 110. The opening penetrates the insulating layer 130 in the third direction (DR3), such that the first opening (OP1) and the second opening (OP2) penetrate the mask 100.

[0058] The deposition apparatus 1000 according to an embodiment of the present invention includes the mask 100 having the first layer 110 and the second layer 120. The mask 100 includes silicon, and the second layer 120 includes a deposition pattern (DP) having an inversely tapered cross section. The angle at which the deposition material provided toward the target substrate 10 passes through the mask 100 is limited by the cross-sectional shape of the deposition pattern (DP). As a result, the deposition material deposited on the target substrate 10 through the mask 100 is not deposited on regions outside the deposition region of the target substrate 10. This prevents staining and color mixing on a display device that may occur due to the deposition material being deposited on regions outside the deposition region of the target substrate 10, thereby improving the display quality of the display device manufactured using the mask 100.

[0059] 3 to 9 are cross-sectional views showing a method for manufacturing the mask of FIG.

[0060] As shown in FIGS. 3 and 4, a spare second layer P#120 and a spare insulating layer P#130 are formed on the spare first layer P#110.

[0061] In one embodiment, the preliminary first layer P#110 includes silicon. The preliminary first layer P#110 includes crystalline silicon. For example, the preliminary first layer P#110 includes single-crystal silicon.

[0062] The spare second layer P#120 is disposed on the spare first layer P#110. In one embodiment, the spare second layer P#120 includes silicon. The spare second layer P#120 includes silicon crystals. For example, the spare second layer P#120 includes single crystal silicon. In one embodiment, the spare second layer P#120 has a crystal orientation of <100> Here, the crystal orientation of the silicon contained in the spare second layer P#120 is different from or the same as the crystal orientation of the silicon contained in the spare first layer P#110.

[0063] The preliminary insulating layer P#130 is disposed between the preliminary first layer P#110 and the preliminary second layer P#120. The preliminary insulating layer P#130 includes an inorganic material such as silicon oxide or silicon nitride.

[0064] The preliminary first layer P#110, the preliminary second layer P#120, and the preliminary insulating layer P#130 are each parallel to the plane defined by the first direction (DR1) and the second direction (DR2). The preliminary first layer P#110, the preliminary insulating layer P#130, and the preliminary second layer P#120 are sequentially provided along the third direction (DR3). For example, a wafer including the preliminary first layer P#110, the preliminary insulating layer P#130, and the preliminary second layer P#120 is provided. For example, the wafer is an SOI (silicon on insulator) wafer.

[0065] The wafer including the spare first layer P#110, the spare insulating layer P#130, and the spare second layer P#120 is then flipped over. That is, the wafer in FIG. 3 is flipped over like the wafer in FIG. 4. As a result, the spare second layer P#120, the spare insulating layer P#130, and the spare first layer P#110 are arranged sequentially along the third direction (DR3). However, the present invention is not limited to this, and the wafer including the spare first layer P#110, the spare insulating layer P#130, and the spare second layer P#120 is provided in an upside-down state like the wafer in FIG. 4.

[0066] 4 and 5, a portion of the preliminary first layer P#110 is removed to form a first sub-opening (SOP1). The first sub-opening (SOP1) is formed so as not to penetrate the preliminary first layer P#110.

[0067] The first sub-opening (SOP1) is formed by etching a surface of the preliminary first layer P#110 that is spaced apart from the preliminary second layer P#120 in a direction opposite to the third direction (DR3). For example, the first sub-opening (SOP1) is formed by a wet etching process, but the present invention is not limited thereto.

[0068] 5 and 6, a portion of the preliminary first layer P#110 is further removed to form a plurality of second sub-openings (SOP2), and the portion of the preliminary first layer P#110 is also removed to form a first auxiliary pattern (AP1) that defines the second sub-openings (SOP2).

[0069] The second sub-openings (SOP2) are repeatedly arranged along the first direction (DR1) or the second direction (DR2) and are spaced apart from each other. For example, the second sub-openings (SOP2) are arranged in a matrix along the first direction (DR1) and the second direction (DR2). For example, the second sub-openings (SOP2) are arranged along either the first direction (DR1) or the second direction (DR2). The first auxiliary patterns (AP1) are arranged between adjacent second sub-openings (SOP2). For example, the first auxiliary patterns (AP1) are formed in a net-like pattern on a plane.

[0070] The second sub-openings (SOP2) are formed by etching the first sub-openings (SOP1) of the preliminary first layer P#110 in a direction opposite to the third direction (DR3). For example, the second sub-openings (SOP2) and the first auxiliary patterns (AP1) are formed by a dry etching process, but are not limited thereto.

[0071] The second sub-opening (SOP2) is connected to the first sub-opening (SOP1), and the first sub-opening (SOP1) and the second sub-opening (SOP2) form a first auxiliary opening (AOP1). The first auxiliary opening (AOP1) defines the first auxiliary pattern (AP1) and penetrates the preliminary first layer P#110 in the third direction (DR3). That is, the first auxiliary opening (AOP1) and the first auxiliary pattern (AP1) are formed in the preliminary first layer P#110 by an etching process.

[0072] 6 and 7, a portion of the preliminary insulating layer P#130 is removed to form a plurality of second auxiliary openings (AOP2). The portion of the preliminary insulating layer P#130 is also removed to form second auxiliary patterns (AP2) that define the second auxiliary openings (AOP2). Each of the second auxiliary openings (AOP2) is formed to penetrate the preliminary insulating layer P#130 in the third direction (DR3).

[0073] The second auxiliary openings (AOP2) are repeatedly arranged along the first direction (DR1) or the second direction (DR2) and are spaced apart from each other. For example, the second auxiliary openings (AOP2) are arranged in a matrix along the first direction (DR1) and the second direction (DR2). For example, the second auxiliary openings (AOP2) are arranged along either the first direction (DR1) or the second direction (DR2). The second auxiliary patterns (AP2) are arranged between adjacent second auxiliary openings (AOP2). For example, the second auxiliary patterns (AP2) are formed in a net-like pattern on a plane.

[0074] The second auxiliary openings (AOP2) are formed by etching from the first auxiliary opening (AOP1) of the preliminary first layer P#110 in the direction opposite to the third direction (DR3). The second auxiliary pattern (AP2) is formed by etching in the direction opposite to the third direction (DR3) using the first auxiliary pattern (AP1) of the preliminary first layer P#110 as a mask. As a result, the second auxiliary opening (AOP2) is connected to the first auxiliary opening (AOP1), and the second auxiliary pattern (AP2) overlaps the first auxiliary pattern (AP1) in a plan view. For example, the second auxiliary opening (AOP2) and the second auxiliary pattern (AP2) are formed by a dry etching process, but the method is not limited to this.

[0075] 7 and 8, the first auxiliary pattern (AP1) of the preliminary first layer P#110 is removed to form the first opening (OP1), a portion of the preliminary second layer P#120 is removed to form the second opening (OP2), and the portion of the preliminary second layer P#120 is removed to form the deposition pattern (DP) that defines the second opening (OP2).

[0076] The second openings (OP2) are formed by etching from the second auxiliary openings (AOP2) of the preliminary insulating layer P#130 in the direction opposite to the third direction (DR3). The deposition patterns (DP) are formed by etching in the direction opposite to the third direction (DR3) using the second auxiliary patterns (AP2) of the preliminary insulating layer P#130 as a mask. As a result, the second openings (OP2) are connected to the second auxiliary openings (AOP2), respectively, and the deposition patterns (DP) overlap the second auxiliary patterns (AP2) in a plan view. For example, the second openings (OP2) and the deposition patterns (DP) are formed by a wet etching process, but are not limited to this.

[0077] This forms the first layer 110 that defines the first opening (OP1), and the second layer 120 that includes the deposition pattern (DP) that defines the second opening (OP2). The first opening (OP1) is formed to penetrate the first layer 110 in the third direction (DR3), and the second openings (OP2) are each formed to penetrate the second layer 120 in the third direction (DR3). The first opening (OP1) and the second opening (OP2) are connected via the second auxiliary opening (AOP2).

[0078] In one embodiment, the first auxiliary pattern (AP1) of the preliminary first layer P#110 and the portion of the preliminary second layer P#120 are removed by the same wet etching process, i.e., the first layer 110 and the second layer 120 are formed by the same wet etching process.

[0079] In one embodiment, the wet etching process is performed using an etching solution containing potassium hydroxide (KOH), for example, the etching solution contains potassium hydroxide, water, and isopropyl alcohol.

[0080] In one embodiment, the concentration of potassium hydroxide in the etching solution is 15 wt% to 70 wt%. Preferably, the concentration of potassium hydroxide is 30 wt% to 45 wt%. If the concentration of potassium hydroxide is less than 30 wt%, the deposition pattern (DP) of the second layer 120 becomes relatively rough.

[0081] In one embodiment, the temperature of the etching solution containing potassium hydroxide is 50° C. or more and 100° C. or less. Preferably, the temperature of the etching solution is 70° C. or more and 90° C. or less.

[0082] Here, the time for which the wet etching process is performed varies depending on the concentration of potassium hydroxide in the etching solution and the temperature of the etching solution.

[0083] By the wet etching process, the deposition pattern (DP) of the second layer 120 is formed to have an inversely tapered (or tapered) cross section. That is, the side surface (SS) of the deposition pattern (DP) is formed to be inclined at a certain angle when extending along the thickness direction of the deposition pattern (DP) (i.e., the third direction (DR3) or the direction opposite to the third direction (DR3)).

[0084] In one embodiment, the deposition pattern (DP) is formed such that the side surface (SF) of the deposition pattern (DP) away from the first layer 110 and the side surface (SS) of the deposition pattern (DP) form an angle (θ) of 45° to 75°. Preferably, the angle (θ) is 50° to 60°. More preferably, the angle (θ) is 53° to 57°.

[0085] In one embodiment, the preliminary first layer P#110 has a crystal orientation of <100> Since the preliminary first layer P#110 contains silicon, when the preliminary first layer P#110 is etched with the etching solution containing potassium hydroxide, the first layer 110 is formed including the deposition pattern (DP) in which the one surface (SF) and the side surface (SS) form the angle (θ). In one embodiment, the width (WD) of the second opening (OP2) is formed to be greater than or equal to the thickness (TH) of the deposition pattern (DP).

[0086] 8 shows that the first auxiliary pattern (AP1) of the preliminary first layer P#110 is completely removed in the wet etching process that removes a portion of the preliminary first layer P#110 and a portion of the preliminary second layer P#120 to form the first layer 110 and the second layer 120, respectively. However, the present invention is not limited to this. For example, in the wet etching process, a portion of the first auxiliary pattern (AP1) of the preliminary first layer P#110 may remain unremoved. In this case, an etching process is further performed to remove the portion. For example, the portion of the first auxiliary pattern (AP1) that remains unremoved is removed by a dry etching process.

[0087] 2, 8, and 9, the second auxiliary pattern (AP2) of the preliminary insulating layer P#130 is removed to form the insulating layer 130. The second auxiliary pattern (AP2) is removed to form the opening corresponding to the first opening (OP1), and the first opening (OP1) and the second opening (OP2) penetrate the mask 100. For example, the second auxiliary pattern (AP2) is removed by a dry etching process, but is not limited thereto.

[0088] This results in the mask 100 including the first layer 110 defining the first opening (OP1), the second layer 120 including the deposition pattern (DP) defining the second opening (OP2), and the insulating layer 130 disposed between the first layer 110 and the second layer 120. For example, the mask in Fig. 9 is used in a deposition process upside down like the mask 100 in Fig. 2.

[0089] In the method for manufacturing the mask 100 according to one embodiment of the present invention, the wafer etching process is performed sequentially in one direction (e.g., from the first layer 110 to the second layer 120). This eliminates the need to turn the wafer over during the etching process, thereby minimizing problems caused by foreign particles that may occur when the wafer is turned over and improving process reliability.

[0090] The wafer has a crystal orientation <100> The mask 100 includes the preliminary second layer P#120 having silicon, and the preliminary second layer P#120 is etched with the etching solution containing potassium hydroxide to form the mask 100 including the deposition pattern (DP) having an inverse tapered shape on a cross section.

[0091] Fig. 10 is a cross-sectional view schematically illustrating a display device manufactured using the deposition apparatus of Fig. 1. For example, Fig. 10 is a cross-sectional view schematically illustrating a portion of a display device (DD) manufactured using the deposition apparatus 1000. For example, the display device (DD) is formed by cutting the target substrate 10 into a plurality of display devices after the target substrate 10 is manufactured into a plurality of display devices.

[0092] As shown in Figures 1 and 10, the display device (DD) includes a base substrate (SUB), a buffer layer (BFR), a transistor (TR), a gate insulating layer (GI), an interlayer insulating layer (ILD), a via insulating layer (VIA), a light emitting element (LE), a pixel defining layer (PDL), and an encapsulation layer (TFE).

[0093] Here, the transistor (TR) includes an active pattern (ACT), a gate electrode (GE), a first electrode (SD1), and a second electrode (SD2), and the light-emitting element (LE) includes a pixel electrode (PE), an emitting layer (EL), and a common electrode (CE).

[0094] The base substrate (SUB) may include a transparent material or an opaque material. For example, the base substrate (SUB) may include plastic, glass, quartz, silicon, etc. For example, the base substrate (SUB) may include a silicon wafer, a silicon carbide wafer, a single crystal silicon wafer, etc. These may be used alone or in combination with each other.

[0095] The buffer layer (BFR) is disposed on the base substrate (SUB). The buffer layer (BFR) prevents metal atoms, impurities, etc. from diffusing into the transistor (TR). In addition, the buffer layer (BFR) can improve the flatness of the surface of the base substrate (SUB) if the surface of the base substrate (SUB) is not uniform. The buffer layer (BFR) includes an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc. These may be used alone or in combination with each other.

[0096] The active pattern (ACT) is disposed on the buffer layer (BFR). The active pattern (ACT) includes a source region, a drain region, and a channel region located between the source region and the drain region. The active pattern (ACT) includes a silicon semiconductor material or an oxide semiconductor material. Examples of the silicon semiconductor material include amorphous silicon and polycrystalline silicon. Examples of the oxide semiconductor material include indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). These materials can be used alone or in combination with each other.

[0097] The gate insulating layer (GI) is disposed on the active pattern (ACT) and covers the active pattern (ACT). The gate insulating layer (GI) may include an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., which may be used alone or in combination with each other.

[0098] The gate electrode (GE) is disposed on the gate insulating layer (GI). The gate electrode (GE) overlaps the channel region of the active pattern (ACT). The gate electrode (GE) may be made of a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like, which may be used alone or in combination with each other.

[0099] The interlayer dielectric layer (ILD) is disposed on the gate electrode (GE) and covers the gate electrode (GE). The interlayer dielectric layer (ILD) may comprise an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc., which may be used alone or in combination with each other.

[0100] The first electrode (SD1) and the second electrode (SD2) are disposed on the interlayer insulating layer (ILD). The first electrode (SD1) is connected to the source region of the active pattern (ACT) through a first contact hole that penetrates the gate insulating layer (GI) and the interlayer insulating layer (ILD). The second electrode (SD2) is connected to the drain region of the active pattern (ACT) through a second contact hole that penetrates the gate insulating layer (GI) and the interlayer insulating layer (ILD). For example, each of the first electrode (SD1) and the second electrode (SD2) may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other.

[0101] As a result, the transistor (TR) including the active pattern (ACT), the gate electrode (GE), the first electrode (SD1), and the second electrode (SD2) is disposed on the base substrate (SUB).

[0102] The via insulating layer (VIA) is disposed on the interlayer insulating layer (ILD) and covers the first electrode (SD1) and the second electrode (SD2). The via insulating layer (VIA) may include an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin, etc. These may be used alone or in combination with each other.

[0103] The pixel electrode (PE) is disposed on the via insulating layer (VIA). The pixel electrode (PE) is connected to the second electrode (SD2) through a contact hole penetrating the via insulating layer (VIA). The pixel electrode (PE) may be made of a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like, which may be used alone or in combination with each other. For example, the pixel electrode (PE) may function as an anode.

[0104] The pixel definition layer (PDL) is disposed on the via insulating layer (VIA) and covers at least a portion of the pixel electrode (PE). An opening that exposes at least a portion of the upper surface of the pixel electrode (PE) is defined in the pixel definition layer (PDL). The pixel definition layer (PDL) includes an inorganic or organic material. For example, the pixel definition layer (PDL) includes an organic material such as an epoxy resin or a siloxane resin. The pixel definition layer (PDL) also includes an inorganic or organic material having a black light-shielding material.

[0105] The light-emitting layer (EL) is disposed on the pixel electrode (PE). The light-emitting layer (EL) is disposed on the pixel electrode (PE) exposed by the pixel defining layer (PDL). The light-emitting layer (EL) includes an organic material that emits light of a predetermined color.

[0106] In one embodiment, the EL is formed using the deposition apparatus 1000. For example, the EL is formed by passing the target substrate 10 on which the pixel defining layer (PDL) is formed through the deposition apparatus 1000. However, the present invention is not limited thereto, and various thin films included in the display device (DD) may be formed using the deposition apparatus 1000.

[0107] The common electrode (CE) is disposed on the light-emitting layer (EL). For example, the common electrode (CE) is a solid electrode extending over the entire display area or a portion thereof. The common electrode (CE) may be made of a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. For example, the common electrode (CE) may act as a cathode.

[0108] Thus, the light-emitting element (LE), which includes the pixel electrode (PE), the light-emitting layer (EL), and the common electrode (CE), is disposed on the base substrate (SUB), and the light-emitting element (LE) is electrically connected to the transistor (TR).

[0109] The encapsulation layer (TFE) is disposed on the common electrode (CE). The encapsulation layer (TFE) can protect the light emitting element (LE) from external oxygen, moisture, etc. The encapsulation layer (TFE) includes at least one inorganic layer and at least one organic layer. For example, the encapsulation layer (TFE) has a structure in which inorganic layers and organic layers are alternately stacked. [Industrial Applicability]

[0110] The present invention can be applied to manufacturing processes of display devices and electronic devices including the same, such as high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and notebook computers.

[0111] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will recognize that various modifications and variations can be made thereto without departing from the spirit and scope of the invention as set forth in the following claims.

[0112] According to a preferred specific embodiment, it is as follows:

[0113] The background to this case is as follows (i) to (vii). (i) When forming the light-emitting element for each sub-pixel in an organic light-emitting display panel in which organic light-emitting elements (OLEDs) are arranged, a deposition mask with openings corresponding to the sub-pixels is used. Organic light-emitting display panels are widely used in mobile devices such as smartphones, tablet PCs, and smartwatches.

[0114] (ii) On the other hand, micro LED display panels in which micro LEDs are arranged are being considered as next-generation display panels, and the use of deposition masks is also being considered when forming the semiconductor active layer for each sub-pixel in micro LED display panels. (iii) These display panels are also being considered for use in next-generation displays, such as eyeglass displays, which require high definition.

[0115] (iii) In manufacturing such a deposition mask, it has been considered to use a laminated substrate in which silicon layers are formed above and below a silicon oxide layer, and to manufacture a deposition mask made of a silicon layer and having mesh-like openings by appropriately performing wet etching or dry etching (Patent Document 1).

[0116] (iv) Patent Document 1 discloses the following method. - Remove the lower silicon layer (40') and silicon oxide layer (30') except for the frame (Figure 5(e)). - Next, a "pattern insulating portion (M2)" is formed as a photoresist by printing or the like (Fig. 5(f)). - The upper silicon layer (20') is etched to form a predetermined mask pattern (P), and then the "pattern insulating portion (M2)" is removed (FIG. 5(g) to FIG. 5(h)).

[0117] (v) On the other hand, Patent Document 2 discloses a method for producing a metal deposition mask from a laminated substrate similar to that of Patent Document 1, by the following procedure. - An etch mask pattern is formed on the upper silicon layer (Fig. 2(4)), and a tapered hole is formed by anisotropic wet etching (Fig. 2(5)). - Fill the tapered hole with metal, then remove all but the metal part (Figure 2 (6) to (7)).

[0118] (vi) Patent Document 2 describes minimizing the "shadow effect" by tapering the side surfaces of the openings appropriately. However, it does not disclose or suggest a method for efficiently manufacturing a deposition mask of a similar shape made of silicon. (vii) On the other hand, Patent Document 1 does not specifically describe the procedure for making the side surface of the opening appropriately tapered or the effect of doing so.

[0119] Therefore, according to a particularly preferred embodiment, any combination of A1 to A3 or A1 to A9 below is used.

[0120] A1 A laminate is manufactured in which a lower silicon layer (first layer 110), an inorganic insulating layer (insulating layer 130), and an upper silicon layer (second layer 120) are deposited in this order. Here, the inorganic insulating layer (insulating layer 130) is made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide-nitride, or the like.

[0121] A2 When the upper silicon layer (second layer 120) is formed on the inorganic insulating layer (insulating layer 130) by epitaxial growth or the like, a diamond structure crystal with a "(100)" crystal face is formed.

[0122] The formation of such a predetermined crystal structure can be easily confirmed by X-ray diffraction analysis, for example, by confirming that the area of ​​the "(100)" peak in X-ray diffraction analysis is, for example, 90% or more, 95% or more, 98% or more, or 99% or more of the total area of ​​the sharp peaks. https: / / www.universitywafer.com / silicon-wafer-orientation.html https: / / semi-journal.jp / basics / si-chem / crystal-structure.html https: / / semi-journal.jp / basics / si-chem / epitaxial.html

[0123] A3: With the lower silicon layer (first layer 110) facing upward, a photoresist pattern is formed and then wet etching is performed from above to form recesses (first sub-openings SOP1) corresponding to the respective display panels (Fig. 5).

[0124] A4: In the recesses (first sub-openings SOP1) in the lower silicon layer (first layer 110), the upper silicon layer (first layer 110) is further dry-etched, for example after forming a photoresist pattern, to form multiple recesses (second sub-openings SOP2) corresponding to the mesh-like deposition masking pattern, and a lattice-like remaining portion (first auxiliary pattern AP1) (Fig. 6 of the present application).

[0125] A5: Dry etching is performed using the remaining portion (first auxiliary pattern AP1) as a mask to form an opening (second auxiliary opening AOP2) in the inorganic insulating layer (insulating layer 130) corresponding to the recessed portion (second sub-opening SOP2) and a remaining portion (second auxiliary pattern AP2) corresponding to the remaining portion (first auxiliary pattern AP1) (FIG. 7 of the present application).

[0126] A6: Using the remaining portions (second auxiliary pattern AP2) of the inorganic insulating layer (insulating layer 130) as masks, wet etching is performed to form a number of openings (second openings OP2) corresponding to the mesh-like vapor deposition masking pattern and a lattice-like remaining portion (vapor deposition pattern DP) in the upper silicon layer (second layer 120) (Fig. 8 of the present application).

[0127] A7 After the wet etching for patterning the upper silicon layer (second layer 120), if any inorganic insulating layer (insulating layer 130) remains in the area overlapping the remaining portion (deposition pattern DP), it is removed by dry etching or the like (Fig. 9 of the present application).

[0128] A8: In the wet etching for patterning the upper silicon layer (second layer 120), an etching solution made of potassium hydroxide, water, and a low molecular weight alcohol solvent (propanol or butanol, particularly isopropanol) is used. A8-1 The concentration of potassium hydroxide in the etching solution is 15 to 70% by weight, 20 to 60% by weight, or 25 to 50% by weight, preferably 30 to 45% by weight, or 33 to 42% by weight. A8-2 The temperature of the etching solution is 50°C or higher and 100°C or lower, 60°C or higher and 95°C or lower, 70°C or higher and 90°C or lower, or 75°C or higher and 85°C or lower. A8-3 The ratio of the alcohol solvent to the total of water and the alcohol solvent in the etching solution can be, for example, 10 to 70% by weight or 20 to 60% by weight.

[0129] A9 The inclination angle (inclination angle with respect to the direction perpendicular to the deposition mask; reverse tapering angle) of the side surface of the mask opening of the deposition mask (side surface SS of the deposition pattern DP) shall be 45° or more and 75° or less, 50° or more and 60° or less, or 53° or more and 57° or less. [Explanation of symbols]

[0130] 1000: Vapor deposition equipment 100: Mask 110: First layer 120: Second layer 130: Insulating layer OP1: First opening OP2: Second opening DP: Deposition pattern SF: One side of the deposition pattern SS: Side of deposition pattern WD: Width of second opening TH: Thickness of the deposition pattern

Claims

1. a first layer defining a first opening; a second layer disposed on the first layer, defining a second opening overlapping the first opening in a plan view, the second layer having a deposition pattern with an inverse tapered cross section, and comprising silicon with a <100> crystal orientation.

2. 2. The mask according to claim 1, wherein an angle formed between a surface of the deposition pattern that is separated from the first layer and a side surface of the deposition pattern is 45 degrees or more and 75 degrees or less.

3. 2. The mask according to claim 1, wherein the width of each of the second openings is greater than or equal to the thickness of the deposition pattern.

4. 2. The mask of claim 1, wherein the first layer comprises silicon.

5. 2. The mask of claim 1, further comprising an insulating layer disposed between said first layer and said second layer.

6. a deposition source containing a deposition material; a mask disposed on the deposition source and through which the deposition material passes; a stage disposed on the mask and on which a target substrate onto which the deposition material is to be deposited is fixed; The mask is a first layer defining a first opening; a second layer disposed on the first layer, defining a second opening overlapping the first opening in a plan view, having a deposition pattern with an inverse tapered cross section, and comprising silicon with a <100> crystal orientation.

7. The deposition apparatus according to claim 6 , wherein an angle formed between a surface of the deposition pattern that is separated from the first layer and a side surface of the deposition pattern is in the range of 45° to 75°.

8. The deposition apparatus according to claim 6 , wherein the width of each of the second openings is equal to or greater than the thickness of the deposition pattern.

9. The deposition apparatus of claim 6 , wherein the first layer includes silicon.

10. 7. The deposition apparatus of claim 6, wherein the mask further comprises an insulating layer disposed between the first layer and the second layer.

11. Etching the preliminary first layer to form a first layer defining a first opening; and etching a preliminary second layer disposed below the preliminary first layer and comprising silicon with a <100> crystal orientation to define a second opening overlapping the first opening in a plan view, thereby forming a second layer having a deposition pattern with an inverse tapered shape in a cross section.

12. In the step of forming the second layer, 12. The method of claim 11, wherein the deposition pattern is formed such that a surface of the deposition pattern that is separated from the first layer forms an angle of 45° to 75° with a side surface of the deposition pattern.

13. In the step of forming the second layer, The method of claim 11, wherein the width of each of the second openings is greater than or equal to the thickness of the deposition pattern.

14. In the step of forming the second layer, 12. The method for manufacturing a mask according to claim 11, wherein the preliminary second layer is etched using an etching solution containing potassium hydroxide (KOH).

15. 15. The method for manufacturing a mask according to claim 14, wherein the concentration of the potassium hydroxide is 15 wt % or more and 70 wt % or less.

16. 15. The method for manufacturing a mask according to claim 14, wherein the temperature of the etching solution containing potassium hydroxide is 50° C. or more and 100° C. or less.

17. 12. The method of manufacturing a mask according to claim 11, wherein the step of forming the first layer includes the step of etching the preliminary first layer to form an auxiliary pattern that defines an auxiliary opening.

18. The step of forming the auxiliary pattern includes: Etching the preliminary first layer to form a first sub-opening; 20. The method of claim 17, further comprising the step of: etching the preliminary first layer to form a second sub-opening connected to the first sub-opening.

19. In the step of forming the second layer, 18. The method for manufacturing a mask according to claim 17, wherein the auxiliary pattern of the preliminary first layer and the preliminary second layer are etched simultaneously.

20. 12. The method for manufacturing a mask according to claim 11, further comprising the step of forming an insulating layer by etching a preliminary insulating layer disposed between the preliminary first layer and the preliminary second layer.

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