Electrostatic chuck with improved temperature control

Abstract

To provide a method and apparatus for enhanced temperature control across the entire radial profile of a substrate during processing using an electrostatic chuck for holding the substrate, and a method and apparatus for controlling hydrogen concentration in a processed film during a high-density plasma (HDP) process.SOLUTION: An electrostatic chuck 100 has a top surface 102 and a bottom surface 104, and the top surface has a central region 110 comprising a plurality of substrate support mesas 115, an inner channel (IC) 120 surrounding the central region, an inner band (IB) 130 surrounding the inner channel, an outer channel (OC) 140 surrounding the inner band, and an outer band (OB) 150 surrounding the outer channel. The electrostatic chuck further has a controller 160 that controls the temperature across the entire surface of a wafer fixed to the top surface of the electrostatic chuck during processing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to an apparatus for clamping a substrate during processing. In particular, embodiments of the present disclosure relate to an apparatus and method for clamping a substrate during high density plasma (HDP) processing. [Background technology]

[0002] Negative-bias temperature instability (NBTI) is a major reliability issue in metal-oxide-semiconductor field-effect transistors (MOSFETs). NBTI manifests as an increase in the MOSFET's threshold voltage and a resulting decrease in drain current and transconductance. In general, more stable dynamic random access memory (DRAM) refresh speeds and NBTI performance are desirable because they result in improved device yields.

[0003] Gate-induced drain leakage (GIDL) is leakage current caused by a high electric field between the gate and the drain. GIDL occurs when a MOSFET is biased in the accumulation region and when the drain bias is much lower than the breakdown voltage.

[0004] Gate-induced drain leakage is an undesirable short-channel effect that occurs at higher drain biases during the overdriven off-state of a transistor. GIDL is the result of a deep depletion region forming at the drain at high off-bias (negative for NFETs and positive for PFETs). The depletion region causes band bending, which allows conductive band-to-band tunneling, creating excessive current. GIDL can be detrimental to integrated circuits, particularly nonvolatile memory circuits such as flash EEPROMs.

[0005] A higher temperature at the edge of the substrate during the MOSFET formation process leads to a lower concentration of hydrogen (H%) in the processed layer of the substrate. Conversely, a lower temperature results in a higher H% and a higher wet etch rate (WER) for the processed film.

[0006] The adjustability or control of substrate temperature, especially at the edge, is also limited by the design of the electrostatic chuck (ESC). Current designs limit the maximum gas pressure edge cooling channels between the wafer and the ESC before gas leakage becomes an issue. This design capacity limits the available parameters between the inner and outer channels for adjusting the temperature and H% at the edge of the wafer.

[0007] Thus, there is a need in the art for an apparatus that allows increased adjustability of the temperature and H % of HDP processed films at the edge of the wafer. Summary of the Invention

[0008] One or more embodiments of the present disclosure are directed to an electrostatic chuck including a top surface, a bottom surface, and a controller. The top surface includes a central region including a plurality of substrate support mesas, an inner channel (IC) surrounding the central region and having an IC width, an inner band (IB) surrounding the inner channel and having an IB width, an outer channel (OC) surrounding the inner band and having an OC width, and an outer band (OB) surrounding the outer channel and having an OB width. The controller is configured to control the temperature across a wafer secured to the top surface of the electrostatic chuck during processing.

[0009] An additional embodiment of the present disclosure is directed to an electrostatic chuck having a top surface and a bottom surface. The top surface includes a central region including a plurality of substrate support mesas, an inner channel (IC) surrounding the central region and having an IC width, an inner band (IB) surrounding the inner channel and having an IB width, an outer channel (OC) surrounding the inner band and having an OC width, and an outer band (OB) surrounding the outer channel and having an OB width. The electrostatic chuck is configured to provide an H% with a range divided by two (R / 2) of about 2% or less across the wafer during processing.

[0010] A further embodiment of the present disclosure is directed to a method of modifying an electrostatic chuck to improve temperature control across a surface of a wafer secured to the top surface of the electrostatic chuck, the method comprising one or more of reducing the surface roughness of the top surface of the electrostatic chuck, varying the shape of a plurality of substrate support mesas, decreasing the contact area for the plurality of substrate support mesas, increasing the width of an inner band of the electrostatic chuck, increasing the width of an outer band of the electrostatic chuck, increasing the pressure in an outer channel, and decreasing the pressure in the inner channel.

[0011] So that the manner in which the above-described features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered limiting with respect to the scope of the present disclosure, since the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates an orthographic view of an electrostatic chuck in accordance with one or more embodiments of the present disclosure. [Figure 2] FIG. 1 illustrates a partial cross-sectional view of an outer peripheral edge of an electrostatic chuck in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates a partial cross-sectional view of an outer peripheral edge of an electrostatic chuck in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Before describing various exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps discussed in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface upon which a process acts. It will also be understood by those skilled in the art that a reference to a substrate may refer to only a portion of the substrate, unless the context clearly dictates otherwise. Additionally, a reference to a deposition on a substrate can refer to both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0015] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include, depending on the application, materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, aluminum gallium arsenide, aluminum gallium nitride, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, without limitation, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include the underlying layer as the context dictates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] One or more embodiments of the present disclosure are directed to an electrostatic chuck. Some embodiments of the present disclosure advantageously provide an electrostatic chuck configured to adjust the concentration of hydrogen (H%) across the surface of a wafer secured to the electrostatic chuck. Some embodiments of the present disclosure advantageously provide an electrostatic chuck with a range of variability in H% (range divided by 2; R / 2) of about 2% or less.

[0017] Many variability plots provide the average value of measurements across the wafer, along with the standard variation and range of values ​​present on the wafer. The range of variability is sometimes expressed as a range around the mean value + / -. Because the range of variability extends both above and below the mean value, the range of variability is sometimes simply expressed as R / 2, i.e., the variability from the mean value in only one direction.

[0018] 1 and 2, one or more embodiments of the present disclosure are directed to an electrostatic chuck 100. FIG. 1 illustrates an orthogonal projection view of the electrostatic chuck 100 according to one or more embodiments. FIG. 2 illustrates a partial cross-sectional view of the electrostatic chuck 100 according to one or more embodiments. The illustrated electrostatic chuck 100 is a generally disk-shaped body 101 comprising an upper coating layer 101A and a lower body 101B. The upper coating layer 101A has a thickness T ESC The upper coating layer 101A contacts the lower body 101B such that the top surface of the lower body is adjacent to the bottom surface 104 of the upper coating layer 101A. The lower body 101B has a bottom surface 105. The thickness of the body 101, including the upper coating layer 101A and the lower body 101B, ranges from about 1.5 inches to about 2.5 inches. In some embodiments, the thickness of the body 101 is about 2 inches.

[0019] In some embodiments, the thickness T of the upper coating layer 101A ESC In some embodiments, the thickness T of the upper coating layer 101A ranges from about 7 mils to about 15 mils, or from about 8 mils to about 12 mils. ESC is approximately 10 mils.

[0020] An outer peripheral edge 106 forms the outer boundary of the body 101. The top surface 102 is configured to support a substrate during processing.

[0021] The top surface 102 of the electrostatic chuck 100 comprises a central region 110, an inner channel 120, an inner band 130, an outer channel 140, and an outer band 150. The central region 110, also referred to as the field of the electrostatic chuck 100, is adjacent to the inner channel 120 at the outer peripheral edge of the central region 110. The intersection 114 of the inner wall 121 of the inner channel 120 with the top surface 112 is the outer peripheral edge of the central region 110.

[0022] The diameter of the central region 110 relative to the total diameter of the upper coating layer 101A can vary. The diameter of the central region 110 is measured from the intersection 114 of the inner wall 121 of the inner channel 120 with the top surface 112 of the central region 110 through the center of the body 101. In some embodiments, the ratio of the diameter of the central region 110 to the diameter of the body 101 is in the range of 80% to 95%, or in the range of 85% to 95%, or in the range of 85% to 92%, or in the range of 86% to 90%.

[0023] The inner channel 120 adjacent to the central region 110 has a width W IC and a depth D IC It extends over a width W IC is measured as the distance between the inner wall 121 and the outer wall 123 of the inner channel 120. IC is measured from the top surface 102 of the upper coating layer 101A to the bottom surface 122 of the inner channel 120. The thickness T of the upper coating layer 101A at the inner channel 120 IC is measured from the bottom surface 122 of the inner channel 120 to the bottom surface 104 of the upper coating layer 101A. In the embodiment illustrated in FIG. 2, the depth of the inner channel 120 adjacent the inner wall 121 is the inner channel depth D IC The depth D close to the field in the central region 110 is smaller than IF is shallower in this embodiment due to the top surface 112 being lower than the support surface which is the top surface 102 .

[0024] Width W of inner channel 120 IC is in the range of 0.5 mm to 5 mm, or in the range of 1 mm to 5 mm, or in the range of 1.5 mm to 5 mm, or in the range of 2 mm to 5 mm, or in the range of 2 mm to 4.5 mm, according to some embodiments.

[0025] Depth D of inner channel 120 ICis equal to or less than 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm, according to one or more embodiments. In some embodiments, the depth D of the inner channel 120 IC is the thickness T of the upper coating layer 101A. ESC ranges from 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60% of the

[0026] Inner channel 120 is separated from outer channel 140 by inner band 130. Inner band 130 has a top surface 132 that is substantially coplanar with top surface 102 of upper coating layer 101A. As used in this manner, the term "substantially coplanar" means that the major plane formed by top surface 102 of upper coating layer 101A is within ±0.025 mm of the major plane formed by top surface 132 of inner band 130.

[0027] Width of inner band 130 IB can be varied to change the spacing between the inner channel 120 and the outer channel 140. A typical electrostatic chuck may have an IB width of about 2 mm to about 3 mm, more specifically, about 2.3 mm to about 2.7 mm. In some embodiments, the width W of the inner band IB (IB width) is increased by a percentage in the range of about 50% to about 60%, in the range of about 90% to about 110%, or in the range of about 50% to about 110%. In some embodiments, the IB width is increased by an amount in the range of about 1.2 mm to about 1.6 mm, in the range of about 2.0 mm to about 3.0 mm, or in the range of about 1.2 mm to about 3.0 mm.

[0028] The outer channel 140 adjacent to the inner band 130 has a width W OC and a depth D OC It extends over a width W OC is measured as the distance between the inner wall 141 and the outer wall 143 of the outer channel 140. OCis measured from the top surface 102 of the upper coating layer 101A to the bottom surface 142 of the outer channel 140. The thickness T of the upper coating layer 101A at the outer channel 140 OC is measured from the bottom surface 142 of the outer channel 140 to the bottom surface 104 of the upper coating layer 101A.

[0029] Outer channel 140 width W OC is in the range of 0.5 mm to 10 mm, or in the range of 1 mm to 8 mm, or in the range of 2 mm to 6 mm, or in the range of 2.5 mm to 5.5 mm, according to some embodiments.

[0030] Depth D of outer channel 140 OC is equal to or less than 1 mm, 0.75 mm, 0.5 mm, 0.3 mm, or 0.2 mm, according to one or more embodiments. In some embodiments, the depth D of the outer channel 140 OC is the thickness T of the upper coating layer 101A. ESC ranges from 10% to 90%, 20% to 80%, 30% to 70%, or 40% to 60% of the

[0031] The outer band 150 is the region of the electrostatic chuck 100 between the outer wall 143 of the outer channel 140 and the outer peripheral edge 106 of the body 101. In some embodiments, the width W of the outer band 150 is in the range of 2 mm to 5.5 mm, in the range of 2.2 mm to 5.2 mm, in the range of 3.5 mm to 4 mm, in the range of 4 mm to 4.5 mm, or in the range of 4.75 mm to 5.25 mm. OB A typical electrostatic chuck has an outer band width W of about 1.7 mm to about 2.7 mm, more specifically about 2.0 mm to about 2.4 mm. OBIn some embodiments, the OB width is increased by a percentage in the range of about 45% to about 55%, about 65% to about 70%, about 45% to about 70%, about 90% to about 110%, about 110% to about 150%, about 120% to about 140%, or about 45% to about 150%. In some embodiments, the OB width is increased by an amount in the range of about 1.3 mm to about 1.7 mm, about 2.8 mm to about 3.1 mm, or about 1.3 mm to about 3.1 mm.

[0032] 1 and 2, the central region 110 includes a plurality of substrate support mesas 115. The substrate support mesas 115 extend from the top surface 112 of the central region 110 to the top surface 116 of the substrate support mesas 115. In some embodiments, the top surfaces 116 of the plurality of substrate support mesas 115 are substantially coplanar with each other. In some embodiments, the top surface 116 of the substrate support mesas 115 is substantially coplanar with the top surface 102 of the upper coating layer 101A. The height of the substrate support mesas 115 depends on the height difference between the top surface 112 of the central region 110 and the top surface 102 of the upper coating layer 101A.

[0033] The substrate support mesa 115 may be any suitable shape. While a rectangular mesa is shown in FIG. 1 , those skilled in the art will recognize that this is for illustrative purposes only and that the present disclosure is not limited to rectangular or square mesas. In some embodiments, the substrate support mesa 115 has a shape selected from one or more of a square, rectangular, round, oval, triangular, polygonal (e.g., pentagonal, hexagonal, etc.), star, diamond, trapezoid, cross, flower, semicircular, or crescent.

[0034] 3 illustrates a partial cross-sectional view of an electrostatic chuck 100 in accordance with one or more embodiments of the present disclosure. The illustrated electrostatic chuck 100 includes a substrate 250 shown on a top surface 102. In some embodiments, the substrate 250 is in contact with the substrate support mesa 115, the inner band 130, and the outer band 150. Although the substrate support mesa 115 is shown with a different shading than the main body 101 of the electrostatic chuck 100, those skilled in the art will recognize that this is for illustrative purposes only. In some embodiments, the substrate support mesa 115 is made of the same material as the rest of the electrostatic chuck 100. The shading is provided to easily distinguish contact areas.

[0035] The electrostatic chuck 100 further comprises a controller 160. In some embodiments, the controller 160 is coupled to the electrostatic chuck 100. In some embodiments, the controller 160 is coupled to one or more of the inner channel 120 or the outer channel 140. In some embodiments, there are two or more controllers 160 connected to individual channels, and a primary control processor is coupled to each of the separate processors to control the electrostatic chuck 100.

[0036] Controller 160 may be one of any type of general-purpose computer processor, microcontroller, microprocessor, etc. that may be used in an industrial environment for controlling various channels and sub-processors.

[0037] The controller 160 may have a processor 162, a memory 164 coupled to the processor 162, an output device 166 coupled to the processor 162, and support circuits 168 for communication between different electronic components. The memory 164 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0038] The memory 164 or computer-readable medium of the processor 162 may be one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The memory 164 may hold a set of instructions operable by the processor 162 to control parameters and components of the electrostatic chuck 100.

[0039] The support circuits 168 are coupled to the processor 162 for supporting the processor 162 in a conventional manner. The circuits may include, for example, cache, power supplies, clock circuits, input / output circuitry, subsystems, and the like.

[0040] The processes may generally be stored in memory as software routines that, when executed by the processor 162, cause the electrostatic chuck to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. As such, the processes may be implemented in software and executed using a computer system, may be implemented in hardware, for example, as an application-specific integrated circuit or other type of hardware implementation, or may be implemented as a combination of software and hardware. The software routines, when executed by the processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation so that processes are performed.

[0041] In some embodiments, controller 160 has one or more configurations for executing individual processes or subprocesses to perform a method. Controller 160 may be connected to and configured to operate intermediate components to perform the functions of a method. For example, controller 160 may be connected to and configured to control one or more of gas valves, heaters, mass flow controllers, etc.

[0042] In some embodiments, the controller 160 has one or more configurations selected from a configuration for chucking and / or dechucking a substrate on an electrostatic chuck, a configuration for monitoring the concentration of hydrogen across the wafer, a configuration for monitoring the surface temperature across the wafer, a configuration for controlling the pressure in the inner channel, or a configuration for controlling the pressure in the outer channel.

[0043] As previously discussed, current electrostatic chuck designs limit the maximum gas pressure in the outer cooling channels before leakage becomes a problem. Thus, this disclosure identifies various methods for modifying current electrostatic chucks to allow better control of temperature, and therefore hydrogen (H) concentration, across the wafer.

[0044] One or more embodiments of the present disclosure advantageously provide an electrostatic chuck with improved outer zone cooling. Some embodiments provide an electrostatic chuck with improved cooling fluid leakage rates. Some embodiments provide an ESC with improved cooling at the ESC / wafer edge resulting in a higher radial tuning range of hydrogen percentage, an improved wet etch rate (WER), and / or an ESC that minimizes or eliminates gate-induced drain leakage.

[0045] In some embodiments, the cooling fluid comprises one or more of helium, neon, argon, krypton, or xenon, hi some embodiments, the cooling fluid consists essentially of helium.

[0046] Current ESC designs are capable of having a pressure of approximately 20 Torr in each of the inner and outer channels. It has been observed that a conventional ESC with pressures of 4 Torr and 10 Torr in the inner and outer channels, respectively, results in a hydrogen non-uniformity of approximately 8.7%. The inventors surprisingly found that an inner channel:outer channel pressure ratio of 6:14 Torr results in a hydrogen non-uniformity of 0.5%. Without being bound by any particular theory of operation, it is believed that GIDL is eliminated or minimized by varying the inner and outer channel backside pressure. Some embodiments advantageously result in hydrogen percentage non-uniformities of less than approximately 5%, 4%, 3%, or 2% for processes at 315°C. Some embodiments result in improved wafer cooling efficiency. Some embodiments allow for higher outer channel setpoints, lower inner channel setpoints, and higher outer:inner channel ratios for process tuning. Some embodiments reduce ESC / substrate helium leak rates. Some embodiments provide improved substrate temperature control.

[0047] One embodiment of the present disclosure provides an electrostatic chuck with reduced surface roughness. Without being bound by theory, reducing the surface roughness of the top surface of the electrostatic chuck allows for more efficient heat transfer between the substrate support mesa and the wafer. Furthermore, reducing the surface roughness of the top surface of the electrostatic chuck provides a larger surface area and a stronger chucking force in the inner and outer bands, thereby reducing gas leakage from the inner and / or outer channels.

[0048] In some embodiments, the surface roughness of one or more of the plurality of substrate support mesas 115, the inner band 130, or the outer band 150 is reduced relative to a standard electrostatic chuck. In some embodiments, the surface roughness is reduced by soft polishing one or more of the plurality of substrate support mesas 115, the inner band 130, or the outer band 150. In some embodiments, the surface roughness of the outer band is reduced by an amount in a range from about 70% to about 90% relative to a standard electrostatic chuck.

[0049] For example, a standard electrostatic chuck may have a surface roughness ranging from about 25 Ra to about 40 Ra. In some embodiments, the surface roughness of the outer band is reduced to about 25 Ra or less, about 20 Ra or less, about 15 Ra or less, about 10 Ra or less, or about 7 Ra or less. In some embodiments, the surface roughness is reduced to about 6 Ra. In some embodiments, the surface roughness ranges from about 10 Ra to about 25 Ra, or about 15 Ra to about 20 Ra. In some embodiments, the surface roughness is measured by a surface profilometer.

[0050] Another embodiment of the present disclosure provides an electrostatic chuck with reduced substrate support mesas. In some embodiments, the number of substrate support mesas is reduced. In some embodiments, the contact area of ​​the substrate support mesas is reduced. In some embodiments, the percentage of the central area covered by the substrate support mesas is reduced. In some embodiments, the ratio between the perimeter and area of ​​each substrate support mesa is reduced.

[0051] Without being bound by theory, it is believed that each of the above proposed modifications reduces conductive heat transfer through the substrate support mesa. Convective heat transfer will still occur, but a relatively greater amount of heat transfer is expected to occur through the inner and outer bands, where it can be more easily controlled using the inner and outer channels.

[0052] For example, a typical electrostatic chuck may have square substrate support mesas, where each mesa is approximately 11 mm 2 For the number of mesas on a typical electrostatic chuck, the contact coverage can be about 12% or more, or about 15% or more of the total area of ​​the top surface of the electrostatic chuck.

[0053] In some embodiments, the substrate support mesas are circular in shape. In some embodiments, each mesa is approximately 10 mm 2 In some embodiments, the number of mesas results in contact coverage of about 10% or less, about 7% or less, or about 5% or less of the total area of ​​the electrostatic chuck.

[0054] Further embodiments of the present disclosure enable electrostatic chucks with wider inner and / or outer bands. Without being bound by theory, it is believed that wider inner and / or outer bands enable increased heat transfer between the electrostatic chuck and the wafer. It is also believed that wider outer bands may help prevent leakage of cooling gas from the outer channels. It is also believed that wider inner bands may enable greater pressure fluctuations between the inner and outer channels.

[0055] Additional embodiments of the present disclosure enable electrostatic chucks with increased pressure in the outer channel and / or decreased pressure in the inner channel. Without being bound by theory, it is believed that the increased pressure differential between the outer and inner channels provides greater control over wafer temperature uniformity. It is also believed that the physical modifications to standard electrostatic chucks outlined in this disclosure allow for a larger pressure differential.

[0056] In some embodiments, the maximum pressure of the coolant in the inner and outer channels is about 20 Torr. In some embodiments, the minimum pressure in the inner and outer channels is about 2 Torr.

[0057] In some embodiments, the pressure in the inner channel (IC pressure) is lower than the pressure in the outer channel (OC pressure). In some embodiments, the IC pressure is about 6 Torr or less, about 5.5 Torr or less, or about 5 Torr or less. In some embodiments, the OC pressure is about 14 Torr or more, about 15 Torr or more, about 17 Torr or more, or about 19 Torr or more.

[0058] In some embodiments, the difference between the IC pressure and the OC pressure is about 8 Torr or greater, about 10 Torr or greater, about 12 Torr or greater, or about 14 Torr or greater. In some embodiments, the ratio of the OC pressure to the IC pressure is about 2.5 or greater, about 3 or greater, about 4 or greater, or about 4 or greater. In some embodiments, the ratio of the OC pressure to the IC pressure is in the range of about 2.5 to about 4, about 3 to about 4, or about 3.5 to about 4.

[0059] Without being bound by theory, various embodiments of the present disclosure improve wafer temperature control (temperature uniformity) across the wafer. Temperature is believed to correlate with the concentration of hydrogen (H%) in films produced by high-density plasma (HDP) deposition processes. Increased H% also correlates with the wet etch rate (WER) and wet etch rate ratio (WERR) of the deposited films.

[0060] Given that the improved temperature control of some embodiments enables increased temperature uniformity across the surface of a wafer during HDP processing, some embodiments of the present disclosure also enable increased H% uniformity and increased WERR uniformity across the wafer. In some embodiments, the electrostatic chuck is configured to have an H% across the wafer with an (R / 2) range of about 2% or less, about 1% or less, or about 0.5% or less.

[0061] Example Five electrostatic chuck samples, approximately 300 mm in diameter, were prepared with different dimensions and properties as displayed in Table 1. Unless otherwise stated, all dimensions are normalized to Sample 1. TIFF2025138688000002.tif83170

[0062] Evaluation of the average wafer temperature during processing was performed for Samples 1-4 at various set points for IC and OC pressures. Temperature was measured with an infrared optical thermometer at a wavelength of approximately 1 μm. Temperature was measured on the backside of the wafer through a small hole in the center region of the electrostatic chuck. The thermometer was unable to measure temperatures below 193°C. Temperatures of 193°C (or lower) are presented as "Low" in Tables 2A-2D.

[0063] The data are grouped by IC pressure in Tables 2A-2D. In some instances, the higher OC pressure could not be maintained due to leaks. These situations are marked with a dash. TIFF2025138688000003.tif74170TIFF2025138688000004.tif74170TIFF2025138688000005.tif73170TIFF2025138688000006.tif75170

[0064] To vary the pressure in the inner and outer channels, SiO samples were prepared on each of the electrostatic chuck samples using the HDP method. The substrate temperature was set at 315°C, but temperature variations across the substrate surface were evident due to the inner and outer channel cooling.

[0065] The prepared SiO2 films were evaluated for wet etch rate across the wafer surface and normalized to form a radial profile for each sample. To evaluate the wet etch rate, the oxide film thickness on the wafer surface was measured both before and after the wafer was immersed in a 1% HF solution for a controlled period of time. A summary of the results for Samples 1-4 is provided in Table 3. All pressures are given in Torr. For each combination of IC pressure and OC pressure, the average wet etch rate across the wafer is normalized to 1. The standard deviation, listed as 1Sig / R / 2, and R / 2 are provided as an indication of the variance of the wet etch rate across the wafer. For Samples 1-3, higher OC pressures could not be maintained due to leakage. These situations are marked with a dash. TIFF2025138688000007.tif94170

[0066] References throughout this specification to "one embodiment," "an embodiment," "one or more embodiments," or "one embodiment" mean that the individual feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "an embodiment," "in one embodiment," or "in one embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the individual features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067] While the present disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Thus, the present disclosure may include modifications and variations that come within the scope of the appended claims and equivalents of those claims.

Claims

1. An electrostatic chuck, A top surface and a bottom surface, wherein the top surface is: a central region comprising a plurality of substrate support mesas; an inner channel (IC) having an IC width surrounding the central region; an inner band (IB) having a width IB surrounding the inner channel; an outer channel (OC) having an OC width surrounding the inner band; and an outer band (OB) having an OB width surrounding the outer channel; a top surface and a bottom surface comprising: a controller configured to control the temperature across a wafer secured to the top surface of the electrostatic chuck during processing; and An electrostatic chuck comprising:

2. 10. The electrostatic chuck of claim 1, wherein a maximum pressure of coolant in said IC and said OC is about 20 Torr.

3. 10. The electrostatic chuck of claim 1, wherein a pressure in said inner channel (IC pressure) is less than a pressure in said outer channel (OC pressure).

4. 4. The electrostatic chuck of claim 3, wherein the difference between the IC pressure and the OC pressure is greater than or equal to about 8 Torr.

5. 4. The electrostatic chuck of claim 3, wherein the OC pressure is greater than or equal to about 14 Torr.

6. 4. The electrostatic chuck of claim 3, wherein the ratio of the OC pressure to the IC pressure is in the range of about 2.5 to about 4.

7. An electrostatic chuck, A top surface and a bottom surface, wherein the top surface is: a central region comprising a plurality of substrate support mesas; an inner channel (IC) having an IC width surrounding the central region; an inner band (IB) having an IB width surrounding the inner channel; an outer channel (OC) having an OC width surrounding the inner band; an outer band (OB) having an OB width surrounding the outer channel; a top surface and a bottom surface, The electrostatic chuck is configured to have an H% with an R / 2 of about 2% or less across the wafer during processing.

8. 8. The electrostatic chuck of claim 7, wherein R / 2 is less than or equal to about 0.5% across the wafer.

9. 8. The electrostatic chuck of claim 7, wherein a surface roughness of one or more of the plurality of substrate support mesas, the inner band, and the outer band is reduced relative to a standard electrostatic chuck.

10. 10. The electrostatic chuck of claim 9, wherein the surface roughness of the outer band is reduced by an amount in the range of about 70% to about 90%.

11. 8. The electrostatic chuck of claim 7, wherein the plurality of substrate support mesas are circular in shape.

12. 8. The electrostatic chuck of claim 7, wherein the contact area size of the plurality of substrate support mesas is reduced relative to a standard electrostatic chuck.

13. 8. The electrostatic chuck of claim 7, wherein an area of ​​the plurality of substrate support mesas is less than about 10% of a total area of ​​the top surface.

14. 8. The electrostatic chuck of claim 7, wherein the OB width is increased by a percentage in the range of about 65% to about 70% relative to a standard electrostatic chuck.

15. 8. The electrostatic chuck of claim 7, wherein the OB width is increased by an amount ranging from about 1.3 mm to about 1.7 mm.

16. 8. The electrostatic chuck of claim 7, wherein the OB width is increased by a percentage in the range of about 110% to about 150% relative to a standard electrostatic chuck.

17. 8. The electrostatic chuck of claim 7, wherein the OB width is increased by an amount ranging from about 2.8 mm to about 3.1 mm.

18. 8. The electrostatic chuck of claim 7, wherein the IB width is increased by a percentage in the range of about 50% to about 60% relative to a standard electrostatic chuck.

19. 8. The electrostatic chuck of claim 7, wherein the IB width is increased by an amount in the range of about 1.2 mm to about 1.6 mm.

20. 1. A method of modifying a standard electrostatic chuck to improve control of the concentration of hydrogen across the surface of a wafer secured to the top surface of the electrostatic chuck, comprising: reducing the surface roughness of the top surface of the electrostatic chuck; Varying the shape of the plurality of substrate support mesas; reducing the contact area for the plurality of substrate support mesas; increasing a width of an inner band of the electrostatic chuck; increasing the width of the outer band of the electrostatic chuck; increasing the pressure in the outer channel; and Reducing the pressure in the inner channel A method comprising one or more of:

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