Wiring board

Abstract

To cause cracks to be less likely to occur in a glass core layer in a wiring board having the glass core layer.SOLUTION: A semiconductor device includes a glass core layer, a first wiring layer provided on one surface of the glass core layer, a first insulating layer covering the first wiring layer, a second wiring layer provided on the other surface of the glass core layer, a second insulating layer covering the second wiring layer, a plurality of first dummy pads arranged at each corner of one surface of the glass core layer and electrically independent of other parts of the first wiring layer, a plurality of second dummy pads that are part of the second wiring layer and arranged at each corner of the other surface of the glass core layer and electrically independent of other parts of the second wiring layer, and a dummy through wire connecting the first dummy pads and the second dummy pads, and the distance from the vertex of each corner of one surface of the glass core layer to the center of the nearest dummy through wire in a planar view is 17 times or less the maximum width of the dummy through wire on one surface of the glass core layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] In recent years, wiring boards with glass core layers have been attracting attention. In some cases, inexpensive organic materials are used as interlayer insulating materials in such wiring boards. However, because the thermal expansion coefficients of organic materials and copper wiring are larger than that of the glass core layer, there is a concern that cracks may occur in the glass core layer due to a mismatch in the thermal expansion coefficients. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-219683 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above points, and has as its object to make it difficult for cracks to occur in a glass core layer in a wiring board having a glass core layer. [Means for solving the problem]

[0005] This wiring board has a glass core layer, a first wiring layer provided on one surface of the glass core layer, a first insulating layer covering the first wiring layer, a second wiring layer provided on the other surface of the glass core layer, a second insulating layer covering the second wiring layer, a plurality of first dummy pads that are part of the first wiring layer and are arranged at each corner of the one surface of the glass core layer and are electrically independent of other parts of the first wiring layer, a plurality of second dummy pads that are part of the second wiring layer and are arranged at each corner of the other surface of the glass core layer and are electrically independent of other parts of the second wiring layer, and a dummy through wire that penetrates the glass core layer and connects the first dummy pads and the second dummy pads, wherein the first insulating layer and the second insulating layer are mainly composed of an organic material, and in a planar view, the distance from the vertex of each of the corners on one surface of the glass core layer to the center of the nearest dummy through wire is 17 times or less the maximum width of the dummy through wire on one surface of the glass core layer. [Effects of the Invention]

[0006] According to the disclosed technology, in a wiring board having a glass core layer, cracks can be made less likely to occur in the glass core layer. [Brief explanation of the drawings]

[0007] [Figure 1] 1A and 1B are diagrams illustrating a wiring substrate according to a first embodiment. [Figure 2] 2A and 2B are diagrams illustrating a portion of a glass core layer of the wiring substrate according to the first embodiment. [Figure 3] 1A to 1C are views (part 1) illustrating a manufacturing process of a wiring board according to the first embodiment. [Figure 4] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 5] FIG. 10 is a plan view partially illustrating a glass core layer of a wiring substrate according to a modified example of the first embodiment. [Figure 6] FIG. 10 is a diagram illustrating a simulation. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] First Embodiment [Overall structure of wiring board] 1A and 1B are diagrams illustrating a wiring board according to a first embodiment, in which FIG. 1A is a plan view and FIG. 1B is a partial cross-sectional view taken along line AA in FIG. 1A.

[0010] 1, wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of glass core layer 10. Wiring board 1 has, for example, a laminated structure in which the glass core layer 10 is symmetrical above and below.

[0011] Specifically, in the wiring board 1, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17 are sequentially stacked on one surface 10a of the glass core layer 10. Furthermore, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially stacked on the other surface 10b of the glass core layer 10. The number of stacked wiring layers and insulating layers is not limited to the example in Fig. 1 and can be determined arbitrarily.

[0012] In the first embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side is referred to as the lower side or the other side. Furthermore, the surface of each part facing the solder resist layer 17 is referred to as one side or the upper side, and the surface facing the solder resist layer 27 is referred to as the other side or the lower side. However, the wiring board 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one surface 10a of the glass core layer 10, and a planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the glass core layer 10.

[0013] A general-purpose glass substrate can be used as the glass core layer 10. The general-purpose glass substrate can be made of any glass material, including, for example, soda-lime glass, borosilicate glass, quartz glass, etc., without any particular limitations. The thickness of the glass core layer 10 is, for example, approximately 300 to 2000 μm. The glass core layer 10 is provided with through holes 10x penetrating the glass core layer 10 in the thickness direction. The planar shape of the through holes 10x is, for example, circular. The cross-sectional shape of the through holes 10x is, for example, an hourglass shape, gradually narrowing from wide portions located on both surfaces of the glass core layer 10 toward narrow portions located in the center in the thickness direction. The cross-sectional shape of the through holes 10x may be rectangular, etc.

[0014] The wiring layer 12 is formed on one surface 10a of the glass core layer 10. The wiring layer 22 is formed on the other surface 10b of the glass core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by through-holes 10x formed in the through-holes 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. The wiring layers 12 and 22 and the through-holes 11 may be made of a material such as copper (Cu). The thickness of the wiring layers 12 and 22 is, for example, approximately 10 to 40 μm. The wiring layer 12, the wiring layer 22, and the through-holes 11 may be integrally formed. The wiring layer 12 is a typical example of a first wiring layer according to the present invention. The wiring layer 22 is a typical example of a second wiring layer according to the present invention.

[0015] The insulating layer 13 is an interlayer insulating layer formed on one surface 10a of the glass core layer 10 so as to cover the wiring layer 12. The insulating layer 13 may be made of a non-photosensitive thermosetting resin whose main component is an organic material such as an epoxy resin or a polyimide resin. The insulating layer 13 may also be made of a photosensitive thermosetting resin whose main component is an organic material such as an acrylic resin. The insulating layer 13 may contain a filler such as silica (SiO2). The insulating layer 13 has a thickness of, for example, about 20 to 40 μm.

[0016] The insulating layer 13 has a via hole 13x which is an opening. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The via hole 13x is, for example, a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening on the insulating layer 15 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 12. The insulating layer 13 is a representative example of a first insulating layer according to the present invention.

[0017] The wiring layer 14 fills the via holes 13x and is electrically connected to the wiring layer 12, and extends from the via holes 13x to the upper surface of the insulating layer 13. In detail, the wiring layer 14 includes via wirings filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 through the via wirings. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0018] The insulating layer 15 is an interlayer insulating layer formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. The insulating layer 15 may contain a filler such as silica (SiO2). The insulating layer 15 has a via hole 15x which is an opening. The via hole 15x penetrates the insulating layer 15 and exposes the upper surface of the wiring layer 14. The via hole 15x is, for example, an inverted truncated cone-shaped recess in which the diameter of the opening on the solder resist layer 17 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14.

[0019] The wiring layer 16 fills the via holes 15x and is electrically connected to the wiring layer 14, and extends from the via holes 15x to the upper surface of the insulating layer 15. In detail, the wiring layer 16 includes via wirings filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 through the via wirings. The material of the wiring layer 16 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0020] The solder resist layer 17 is a protective insulating layer located at the outermost position on one side of the wiring board 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 has openings 17x, and a portion of the upper surface of the wiring layer 16 is exposed in the openings 17x. The planar shape of the openings 17x is, for example, circular. The wiring layer 16 exposed in the openings 17x can be used as a pad for electrical connection to a semiconductor chip or the like. The material of the solder resist layer 17 can be, for example, a photosensitive insulating resin containing, as a main component, a phenolic resin or a polyimide resin. The solder resist layer 17 may contain a filler such as silica (SiO2). The thickness of the solder resist layer 17 is, for example, approximately 20 to 40 μm.

[0021] A surface treatment layer (not shown) may be formed on the upper surface of the wiring layer 16 exposed in the opening 17x. Examples of the surface treatment layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). Alternatively, the surface treatment layer may be formed by applying an anti-oxidation treatment such as an OSP (organic solderability preservative) treatment to the upper surface of the wiring layer 16 exposed in the opening 17x. The OSP treatment can form an organic coating made of an azole compound, an imidazole compound, or the like as the surface treatment layer. Alternatively, a protruding electrode (not shown), such as a metal post, may be formed on the upper surface of the wiring layer 16 exposed in the opening 17x.

[0022] The insulating layer 23 is an interlayer insulating layer formed on the other surface 10b of the glass core layer 10 so as to cover the wiring layer 22. The material and thickness of the insulating layer 23 are, for example, the same as those of the insulating layer 13. The insulating layer 23 may contain a filler such as silica (SiO2). The insulating layer 23 has a via hole 23x which is an opening. The via hole 23x penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22. The via hole 23x is, for example, a truncated cone-shaped recess in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 22. The insulating layer 23 is a representative example of a second insulating layer according to the present invention.

[0023] The wiring layer 24 fills the via holes 23x and is electrically connected to the wiring layer 22, and extends from the via holes 23x to the lower surface of the insulating layer 23. In detail, the wiring layer 24 includes via wirings filled in the via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring pattern of the wiring layer 24 is electrically connected to the wiring layer 22 through the via wirings. The material of the wiring layer 24 and the thickness of the wiring pattern are similar to those of the wiring layer 12, for example.

[0024] The insulating layer 25 is an interlayer insulating layer formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. The insulating layer 25 may contain a filler such as silica (SiO2). The insulating layer 25 has a via hole 25x which is an opening. The via hole 25x penetrates the insulating layer 25 and exposes the lower surface of the wiring layer 24. The via hole 25x is, for example, a truncated cone-shaped recess in which the diameter of the opening on the solder resist layer 27 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 24.

[0025] The wiring layer 26 fills the via holes 25x and is electrically connected to the wiring layer 24, and extends from the via holes 25x to the lower surface of the insulating layer 25. In detail, the wiring layer 26 includes via wiring filled in the via holes 25x, and pads and wiring formed on the lower surface of the insulating layer 25. The pads and wiring of the wiring layer 26 are electrically connected to the wiring layer 24 through the via wiring. The material of the wiring layer 26 and the thickness of the pads and wiring are the same as, for example, the wiring layer 12.

[0026] The solder resist layer 27 is a protective insulating layer located at the outermost position on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 27 has openings 27x, in which a portion of the lower surface of the wiring layer 26 is exposed. The planar shape of the openings 27x is, for example, circular. The wiring layer 26 exposed in the openings 27x can be used as a pad for electrical connection to a mounting substrate such as a motherboard. If necessary, the aforementioned metal layer may be formed on the lower surface of the wiring layer 26 exposed in the openings 27x, or an organic coating may be formed by performing an anti-oxidation treatment such as OSP treatment. The material and thickness of the solder resist layer 27 are, for example, the same as those of the solder resist layer 17. The solder resist layer 27 may contain a filler such as silica (SiO2).

[0027] [Dummy pads, dummy through-wiring] Fig. 2 is a diagram partially illustrating the glass core layer of the wiring board according to the first embodiment, with Fig. 2(a) being a plan view of the glass core layer at the corner R in Fig. 1(a) and Fig. 2(b) being a cross-sectional view taken along line BB in Fig. 2(a). Note that one surface 10a and the other surface 10b of the glass core layer 10 have four corners R, and all four corners R have a structure corresponding to that shown in Fig. 2.

[0028] 2, 12P denotes a part of the wiring layer 12, a plurality of first dummy pads arranged at each corner R of one surface 10a of the glass core layer 10, and electrically isolated from other parts of the wiring layer 12. 22P denotes a part of the wiring layer 22, a plurality of second dummy pads arranged at each corner R of the other surface 10b of the glass core layer 10, and electrically isolated from other parts of the wiring layer 22. 11V denotes a dummy through wiring that penetrates the glass core layer 10 and connects the first dummy pad 12P and the second dummy pad 22P.

[0029] The first dummy pad 12P and the second dummy pad 22P are, for example, located at overlapping positions in a plan view. In the example of Fig. 2, the first dummy pad 12P and the second dummy pad 22P are rectangular in a plan view, but are not limited to this and may be triangular, circular, or the like in a plan view. The diameter of the dummy through wiring 11V at the positions of the one surface 10a and the other surface 10b can be, for example, approximately 20µm to 200µm. The pitch of the dummy through wiring 11V can be, for example, approximately 1.5 to 5 times the diameter.

[0030] The diameter of the dummy through wiring 11V at the positions of the one surface 10a and the other surface 10b may or may not be the same as the diameter of the signal through wiring 11 at the positions of the one surface 10a and the other surface 10b. The first dummy pad 12P, the second dummy pad 22P, and the dummy through wiring 11V may be integrally formed.

[0031] The thermal expansion coefficients of the wiring layers and insulating layers constituting the wiring substrate 1 are greater than that of the glass core layer 10. The thermal expansion coefficients of the wiring layers and insulating layers are, for example, 1.5 times or more that of the glass core layer 10. Due to this mismatch in thermal expansion coefficients, there is a concern that cracks may occur in the glass core layer 10 due to temperature changes. Cracks are particularly likely to occur at the four corners R where thermal stress is concentrated. Therefore, in the wiring substrate 1, a first dummy pad 12P, a second dummy pad 22P, and a dummy through-wire 11V are arranged at each of the four corners R.

[0032] In plan view, the distance L from the vertex of each corner R on one surface 10a of the glass core layer 10 to the center of the nearest dummy through wiring 11V is 17 times or less the maximum width of the dummy through wiring 11V on one surface of the glass core layer 10. Arranging the dummy through wiring 11V in such a range can make it difficult for cracks to occur in the glass core layer 10.

[0033] The maximum width of the dummy through wiring 11V is the diameter when the shape of the dummy through wiring 11V at the position of one surface 10a of the glass core layer 10 is circular, the major axis when the shape is elliptical, and the length of the diagonal when the shape is rectangular or square. When the shape of the dummy through wiring 11V at the position of one surface 10a of the glass core layer 10 is other than these, the maximum width is defined as the length of the longest straight line that can be drawn continuously within the shape of the dummy through wiring 11V at the position of one surface 10a of the glass core layer 10.

[0034] In plan view, the distance L from the vertex of each corner R on one surface 10a of the glass core layer 10 to the center of the nearest dummy through wire 11V is preferably 8 times or less the maximum width of the dummy through wire 11V on one surface of the glass core layer 10. Arranging the dummy through wire 11V in such a range can make it more difficult for cracks to occur in the glass core layer 10.

[0035] Furthermore, in plan view, the distance L from the vertex of each corner R on one surface 10a of the glass core layer 10 to the center of the nearest dummy through wire 11V is preferably three times or more the maximum width of the dummy through wire 11V on one surface of the glass core layer 10. By arranging the dummy through wire 11V in such a range, the through hole 10x and the dummy through wire 11V can be stably formed at the corner R.

[0036] From the viewpoint of enhancing the effect of suppressing cracks occurring in the glass core layer 10, the number of dummy through wirings 11V at one corner is preferably 40 or more, and more preferably 100 or more. Furthermore, from the viewpoint of enhancing the effect of suppressing cracks occurring in the glass core layer 10, the diameter of the dummy through wirings 11V at the positions of the one surface 10a and the other surface 10b is preferably 50 μm or more, and more preferably about 100 μm.

[0037] In this way, by arranging the first dummy pad 12P, the second dummy pad 22P and the dummy through wiring 11V at each of the four corners of the glass core layer 10, the anchor effect can make it less likely for cracks to occur in the glass core layer 10.

[0038] [Method of manufacturing wiring board] 3 and 4 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment, showing a cross section corresponding to FIG. 1(b).

[0039] As shown in Figures 3 and 4, the wiring board 1 shown in Figure 1 can be manufactured by sequentially stacking wiring layers and insulating layers on one surface 10a and the other surface 10b of the glass core layer 10, for example, by a well-known build-up method.

[0040] 3(a), a through hole 10x is formed in the glass core layer 10. The through hole 10x can be formed, for example, by irradiating the glass core layer 10 with laser light from one surface 10a to form a recess, and then irradiating the glass core layer 10 with laser light from the other surface 10b to form a recess, and connecting the two recesses near the center in the thickness direction of the glass core layer 10. A CO2 laser, for example, can be used to form the through hole 10x.

[0041] Next, in the step shown in FIG. 3(b), the through wiring 11 and the wiring layers 12 and 22 are formed in the glass core layer 10, for example, by a well-known semi-additive method. Specifically, for example, a seed layer (copper or the like) is formed by electroless plating, sputtering, or the like to cover the one surface 10a and the other surface 10b of the glass core layer 10 and the inner wall surfaces of the through holes 10x. Then, a resist layer with openings is formed on the seed layer on the one surface 10a and the other surface 10b of the glass core layer 10. Then, an electrolytic plating method using the seed layer as a power supply layer is used to form an electrolytic plated layer (copper or the like) on the seed layer exposed in the openings of the resist layer. Next, after removing the resist layer, etching is performed using the electrolytic plated layer as a mask to remove the seed layer exposed from the electrolytic plated layer. As a result, the through holes 10x are filled with the electrolytic plating layer formed on the seed layer to form the through wiring 11, and wiring layers 12 and 22, in which the seed layer and the electrolytic plating layer are stacked, are formed on one surface 10a and the other surface 10b of the glass core layer 10. In this process, dummy through wirings 11V, first dummy pads 12P, and second dummy pads 22P are formed at the four corners of the glass core layer 10, along with the through wiring 11 and the wiring layers 12 and 22.

[0042] 3(c), a semi-cured film-like non-photosensitive thermosetting resin mainly composed of an organic material such as an epoxy resin is laminated on one surface 10a of the glass core layer 10 so as to cover the wiring layer 12, and then cured to form the insulating layer 13. A semi-cured film-like non-photosensitive thermosetting resin mainly composed of an organic material such as an epoxy resin is laminated on the other surface 10b of the glass core layer 10 so as to cover the wiring layer 22, and then cured to form the insulating layer 23. Alternatively, instead of laminating a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layers 13 and 23.

[0043] 3(d), via holes 13x are formed in the insulating layer 13 as openings that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. Also, via holes 23x are formed in the insulating layer 23 as openings that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The via holes 13x and 23x can be formed by, for example, a laser processing method using a CO2 laser or the like. After the via holes 13x and 23x are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surfaces of the wiring layers 12 and 22 that are exposed at the bottoms of the via holes 13x and 23x.

[0044] 4(a), the via holes 13x are filled to form a wiring layer 14 that is electrically connected to the wiring layer 12 and extends from within the via holes 13x to the upper surface of the insulating layer 13. The wiring layer 14 includes via wirings filled within the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The via holes 23x are also filled to form a wiring layer 24 that is electrically connected to the wiring layer 22 and extends from within the via holes 23x to the lower surface of the insulating layer 23. The wiring layer 24 includes via wirings filled within the via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring layers 14 and 24 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0045] Next, in the step shown in FIG. 4(b), an insulating layer 15, a via hole 15x, a wiring layer 16, an insulating layer 25, a via hole 25x, and a wiring layer 26 are formed by the same method as in FIGS. 3(c) to 4(a).

[0046] 4(c), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. In addition, a solder resist layer 27 is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of the insulating layer 15 so as to cover the wiring layer 16 by screen printing, roll coating, spin coating, or the like. Alternatively, the solder resist layer 17 may be formed, for example, by laminating a film-like photosensitive epoxy insulating resin on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as that for the solder resist layer 17.

[0047] Next, the solder resist layers 17 and 27 are exposed and developed to form an opening 17x in the solder resist layer 17, exposing a portion of the upper surface of the wiring layer 16. Furthermore, an opening 27x is formed in the solder resist layer 27, exposing a portion of the lower surface of the wiring layer 26. If necessary, the upper surface of the wiring layer 16 exposed in the opening 17x or the lower surface of the wiring layer 26 exposed in the opening 27x may be formed with the aforementioned metal layer by electroless plating or the like, or an organic coating may be formed by performing an anti-oxidation treatment such as OSP treatment. Thus, the wiring board 1 is obtained.

[0048] <Modification of the first embodiment> In the modified example of the first embodiment, an example in which alignment marks are formed on dummy pads is shown. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0049] 5 is a plan view partially illustrating an example of a glass core layer of a wiring substrate according to a modified example of the first embodiment. In the modified example shown in FIG. 5, an alignment mark 12A is provided in a formation region of a first dummy pad 12P in a plan view. The alignment mark 12A is, for example, circular, with one surface 10a exposed in a ring shape around the circle. The alignment mark 12A may also be rectangular, cross-shaped, or the like.

[0050] The alignment marks 12A can be provided, for example, at all four corners of one surface 10a of the glass core layer 10. The alignment marks 12A may also be provided, for example, at two diagonally opposing corners of one surface 10a of the glass core layer 10. Providing the alignment marks 12A facilitates alignment in each manufacturing process of the wiring substrate 1. In plan view, an alignment mark similar to the alignment mark 12A may be provided in the formation region of the second dummy pad 22P.

[0051] [simulation] A linear static analysis was performed using ABAQUS2023 on a wiring board with the structure shown in Figure 1. The external dimensions of the wiring board were assumed to be 75 mm square, and a laminated structure in which the glass core layer was symmetrical above and below was assumed. Copper was also assumed for the wiring layer. Then, for conditions 1 to 8 shown in Figure 6, the temperature of the wiring board was lowered from 180°C to 25°C, and the extent to which the maximum stress value generated at the corners of the glass core layer changed depending on the presence or absence of dummy through-holes was confirmed. The physical properties of each layer at room temperature were as shown in Table 1. The planar shape of the through-holes was assumed to be circular. For simplicity, the through-holes will be referred to as TGVs below.

[0052] [Table 1] In all of conditions 1 to 8, a 50 mm square wiring pattern was placed in the center of the upper and lower surfaces of the glass core layer in a planar view, and 4 mm square or 2.8 mm square dummy pads were placed at the four corners. Condition 1 is a case where no TGVs or dummy TGVs are placed on the glass core layer. Condition 2 is a case where a TGV is placed in the center of the glass core layer in a planar view, and no dummy TGVs are placed at the corners. Conditions 3 to 8 are cases where a TGV is placed in the center of the glass core layer in a planar view, and dummy TGVs are placed at each corner.

[0053] The diameter, pitch, and number of TGVs, as well as the distance L (see Figure 2) under each condition, are shown in Figure 6 along with the simulation results. Note that in Figure 6, "Maximum stress value at the corner of the glass core layer," the perspective view shows the entire glass core layer, and the area within the dashed line shows an enlarged view of one corner. The value below the dashed line is the maximum stress value generated at the corner of the glass core layer, as determined by this simulation. The following results can be read from Figure 6.

[0054] Even if a TGV is placed in the center as in condition 2, if dummy TGVs are not placed in the corners, the maximum stress value generated in the corners of the glass core layer is the same as in condition 1, where no TGVs are placed at all. In other words, the structure of condition 2 is not effective in suppressing cracks in the glass core layer.

[0055] Even if dummy TGVs are placed at the corners, as in Conditions 5 and 6, when "distance L / diameter of dummy TGV at corner" is relatively large, the maximum stress value generated at the corners of the glass core layer is the same as in Condition 1, where no TGVs are placed. In other words, "distance L / diameter of dummy TGV at corner" is important for suppressing cracking in the glass core layer.

[0056] According to conditions 3 and 7, when dummy TGVs are placed at the corners and the "distance L / diameter of dummy TGV at corner" is 17.3, the maximum stress value generated at the corners of the glass core layer is reduced compared to condition 1, where no TGVs are placed. Also, according to conditions 4 and 8, when dummy TGVs are placed at the corners and the "distance L / diameter of dummy TGV at corner" is 8.7, the maximum stress value generated at the corners of the glass core layer is further reduced compared to conditions 3 and 7.

[0057] According to conditions 3 and 4, and conditions 7 and 8, when the distance L is the same, the larger the diameter of the dummy TGV placed at the corner, the smaller the maximum stress value generated at the corner of the glass core layer. Also, the size of the dummy pad does not have a significant effect on the maximum stress value generated at the corner of the glass core layer.

[0058] In this structure in which dummy pads are arranged at the corners of both sides of the glass core layer and the dummy pads on each side are connected by multiple dummy TGVs, it is preferable that the distance from the apex of each corner on one side of the glass core layer to the center of the nearest dummy TGV in plan view is 17 times or less the diameter of the dummy TGV on one side of the glass core layer, thereby reducing the maximum stress value generated at the corners of the glass core layer.

[0059] It is more preferable that the distance from the apex of each corner on one surface of the glass core layer to the center of the nearest dummy TGV in plan view is 8 times or less the diameter of the dummy TGV on one surface of the glass core layer, which further reduces the maximum stress value generated at the corner of the glass core layer.

[0060] When the temperature of the wiring board is lowered from 180°C to 25°C, the dummy TGVs, which have a larger thermal expansion coefficient than the glass core layer, tend to shrink more than the glass core layer 10. At that time, the dummy pads arranged on both sides of the glass core layer apply a force in a direction that compresses the glass core layer from both sides of the glass core layer. Generally, a glass core layer is pulled in the vertical direction, causing cracks, but the force of the dummy pads in the direction that compresses the glass core layer makes it difficult for the glass core layer to be pulled in the vertical direction, which is thought to suppress the occurrence of cracks.

[0061] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0062] For example, the present invention may be applied to a wiring board having a structure in which a wiring layer and an insulating layer are laminated on one side of a glass core layer, and in this case too, cracks are less likely to occur in the glass core layer. [Explanation of symbols]

[0063] 1. Wiring board 10 Glass core layer 10a One side 10b The other side 10x through holes 11 Through wiring 11V dummy through wiring 12, 14, 16, 22, 24, 26 wiring layer 12P 1st dummy pad 13, 15, 23, 25 Insulation layers 13x, 15x, 23x, 25x via holes 17, 27 Solder resist layer 22P Second dummy pad

Claims

1. a glass core layer; a first wiring layer provided on one surface of the glass core layer; a first insulating layer covering the first wiring layer; a second wiring layer provided on the other surface of the glass core layer; a second insulating layer covering the second wiring layer; a plurality of first dummy pads that are part of the first wiring layer, that are arranged at each corner of one surface of the glass core layer, and that are electrically independent from other parts of the first wiring layer; a plurality of second dummy pads that are part of the second wiring layer, that are arranged at each corner of the other surface of the glass core layer, and that are electrically independent from other parts of the second wiring layer; a dummy through-wiring that penetrates the glass core layer and connects the first dummy pad and the second dummy pad; the first insulating layer and the second insulating layer are mainly composed of an organic material, A wiring board, wherein, in a planar view, the distance from the vertex of each corner of one surface of the glass core layer to the center of the nearest dummy through wiring is 17 times or less the maximum width of the dummy through wiring on one surface of the glass core layer.

2. The wiring board according to claim 1 , wherein the distance is equal to or less than eight times the maximum width.

3. The wiring board according to claim 1 , wherein the distance is at least three times the maximum width.

4. 3. The wiring board according to claim 1, wherein the thermal expansion coefficients of the first wiring layer, the second wiring layer, the first insulating layer, and the second insulating layer are each 1.5 times or more the thermal expansion coefficient of the glass core layer.

5. 3. The wiring board according to claim 1, wherein an alignment mark is provided in each of the first dummy pad formation region and the second dummy pad formation region.

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