Memory device

Abstract

To suppress the manufacturing cost of a memory device.SOLUTION: A memory device includes a substrate, a plurality of first conductor layers 22, a plurality of memory pillars MP, a plurality of first pillars HR, and a plurality of second pillars DMP. The substrate includes a first region MA, a second region BA, and a third region HA which are arranged in order in a first direction. The first conductor layers are arranged in a second direction above the substrate. The plurality of memory pillars are provided in the first region. Each of the plurality of memory pillars has a portion intersecting the plurality of first conductor layers, and each includes a laminated film 42. The plurality of first pillars are provided in the second region and the third region. Each of the plurality of first pillars has a portion intersecting at least part of the plurality of first conductor layers, and each has a composition different from that of the memory pillars. The plurality of second pillars are provided in the second region. Each of the plurality of second pillars has a portion intersecting at least one of the plurality of first conductor layers, and each includes the laminated film.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-090170 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce manufacturing costs of memory devices. [Means for solving the problem]

[0005] The memory device of the embodiment includes a substrate, a plurality of first conductive layers, a plurality of memory pillars, a plurality of first pillars, and a plurality of second pillars. The substrate includes a first region, a second region, and a third region aligned in order in a first direction. The first conductive layers are aligned above the substrate in a second direction intersecting the first direction. The plurality of memory pillars MP are provided in the first region. Each of the plurality of memory pillars has a portion intersecting with the plurality of first conductive layers and includes a stacked film. The plurality of first pillars are provided in the second region and the third region. Each of the plurality of first pillars has a portion intersecting with at least a portion of the plurality of first conductive layers and has a different configuration from the memory pillars. The plurality of second pillars are provided in the second region. Each of the plurality of second pillars has a portion intersecting with at least one first conductive layer of the plurality of first conductive layers and includes a stacked film. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 3] FIG. 1 is a perspective view showing an example of the appearance of a memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of a memory area of ​​a memory cell array included in the memory device according to the first embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure in a memory region of a memory cell array included in the memory device according to the first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment. [Figure 8] FIG. 2 is a plan view showing an example of a planar layout in the vicinity of a boundary region of a memory cell array included in the memory device according to the first embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of a cross-sectional structure in the vicinity of a boundary region of a memory cell array included in the memory device according to the first embodiment. [Figure 10] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 11] FIG. 2 is a plan view showing an example of a planar layout in a manufacturing process of a memory cell array included in the memory device according to the first embodiment. [Figure 12] 12 is a cross-sectional view taken along line XII-XII in FIG. 11, showing an example of a cross-sectional structure during the manufacturing process of the memory cell array included in the memory device according to the first embodiment. [Figure 13] FIG. 2 is a plan view showing an example of a planar layout in a manufacturing process of a memory cell array included in the memory device according to the first embodiment. [Figure 14] 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13, showing an example of a cross-sectional structure during the manufacturing process of the memory cell array included in the memory device according to the first embodiment. [Figure 15] FIG. 2 is a plan view showing an example of a planar layout in a manufacturing process of a memory cell array included in the memory device according to the first embodiment. [Figure 16] 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15, showing an example of a cross-sectional structure during the manufacturing process of the memory cell array included in the memory device according to the first embodiment. [Figure 17] FIG. 2 is a plan view showing an example of a planar layout in a manufacturing process of a memory cell array included in the memory device according to the first embodiment. [Figure 18] 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17, showing an example of a cross-sectional structure during the manufacturing process of the memory cell array included in the memory device according to the first embodiment. [Figure 19] FIG. 2 is a plan view showing an example of a planar layout in a manufacturing process of a memory cell array included in the memory device according to the first embodiment. [Figure 20] 20 is a cross-sectional view taken along line XX-XX in FIG. 19, showing an example of a cross-sectional structure during the manufacturing process of the memory cell array included in the memory device according to the first embodiment. [Figure 21] FIG. 1 is a plan view showing an example of a planar layout of a memory cell array according to a first comparative example. [Figure 22] 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21, showing an example of the cross-sectional structure of the memory cell array according to the first comparative example. [Figure 23] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array according to a second comparative example. [Figure 24] 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23, showing an example of the cross-sectional structure of the memory cell array according to the second comparative example. [Figure 25] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a second embodiment. [Figure 26]FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in the vicinity of a boundary region of a memory cell array included in a memory device according to a second embodiment. [Figure 27] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 28] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 29] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 30] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 31] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 32] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 33] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to a second embodiment during a manufacturing process. [Figure 34] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array according to a first modification. [Figure 35] 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 34, showing an example of the cross-sectional structure of the memory cell array according to the first modification. [Figure 36] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array according to a second modification. [Figure 37] 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG. 36, showing an example of the cross-sectional structure of a memory cell array according to a second modification. [Figure 38] FIG. 10 is a cross-sectional view showing an example of a detailed cross-sectional structure in the vicinity of two opposing bond pads. [Figure 39]FIG. 10 is a cross-sectional view showing an example of a detailed cross-sectional structure of a boundary portion between a first layer and a second layer of a memory pillar included in a memory device according to a second embodiment. [Figure 40] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array according to a third modification. [Figure 41] FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fourth modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components are omitted as appropriate. Hatching added to plan views does not necessarily relate to the material or characteristics of the components. In this specification, components having approximately the same function and configuration are assigned the same reference numerals. Numbers and letters added to reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] <1> First embodiment The memory device 1 according to the first embodiment has a structure in which memory cells are stacked three-dimensionally and manufactured using a manufacturing method in which two semiconductor substrates are bonded together. A pattern for assisting the opening of the memory holes at the ends and a pattern for maintaining the stacked wiring structure in the lead-out region are arranged so as to overlap in the boundary region. Details of the memory device 1 according to the first embodiment are described below.

[0009] <1-1> Configuration First, the configuration of the memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Overall configuration of memory device 1 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device 1 according to a first embodiment. As shown in FIG. 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and a plurality of word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0012] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals to and from the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, commands, etc. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated under the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes a block address, a page address, a column address, etc. The commands include instructions for various operations of the memory device 1.

[0015] The sequencer 14 controls the overall operation of the memory device 1. Based on the command and address information stored in the register circuit 13, the sequencer 14 executes read operations, write operations, erase operations, and the like.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc.

[0017] The row decoder module 16 is a circuit used to select a block BLK to be operated and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0018] The sense amplifier module 17 is a circuit used to transfer voltages to each bit line BL and to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0019] The combination of the memory device 1 and the memory controller 2 may constitute one semiconductor device. TM Examples include memory cards and solid state drives (SSDs).

[0020] <1-1-2> Circuit configuration of memory cell array 10 FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in the memory device 1 according to the first embodiment. FIG. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. As shown in FIG. 2, select gate lines SGD0 to SGD4, word lines WL0 to WL(N-1) (N is an integer of 2 or more), select gate line SGS, bit lines BL0 to BLm, and source line SL are connected to the block BLK. The select gate lines SGD0 to SGD4, word lines WL0 to WL(N-1), and select gate line SGS are provided for each block BLK. The bit lines BL0 to BLm and source line SL can be shared by multiple blocks BLK.

[0021] A block BLK includes, for example, five string units SU0 to SU4. Each string unit SU includes NAND strings NS0 to NSm. The NAND strings NS0 to NSm are associated with bit lines BL0 to BLm, respectively. Each NAND string NS is connected between the associated bit line BL and a source line SL. Each bit line BL is shared by NAND strings NS that are assigned the same column address across multiple blocks BLK.

[0022] Each NAND string NS includes, for example, a select transistor ST1, N memory cell transistors MT0 to MT(N-1), and a select transistor ST2. In each NAND string NS, the select transistor ST1, memory cell transistors MT(N-1) to MT0, and select transistor ST2 are connected in series in this order. The drain of the select transistor ST1 is connected to an associated bit line BL, and the source of the select transistor ST2 is connected to a source line SL. Each memory cell transistor MT has a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. The select transistors ST1 and ST2 are used to select a string unit SU.

[0023] The select gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each select gate line SGD is connected to the gates of the select transistors ST1 included in the associated string unit SU. The select gate line SGS is connected to the gates of the select transistors ST2 included in the block BLK. The word lines WL0 to WL(N-1) are connected to the control gates of the memory cell transistors MT0 to MT(N-1) included in the block BLK, respectively.

[0024] A set of multiple memory cell transistors MT connected to a common word line WL in one string unit SU corresponds to a “page.” A set of multiple memory cell transistors MT connected to a common word line WL in one string unit SU can have a storage capacity of two or more pages depending on the number of bits stored in the memory cell transistors MT.

[0025] The memory cell array 10 may have other circuit configurations. For example, the number of string units SU included in a block BLK and the number of memory cell transistors MT and select transistors ST1 and ST2 included in a NAND string NS may be designed to be any number. Below, the memory device 1 according to the first embodiment will be described using an example in which each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7, respectively.

[0026] <1-1-3> Structure of memory device 1 The structure of the memory device 1 according to the first embodiment will be described below.

[0027] In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the front surface of the reference semiconductor substrate. "Up and down" are defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the front surface of the reference semiconductor substrate. The XY plane (cross section) corresponds to a plane (cross section) parallel to each of the X and Y directions. The YZ cross section corresponds to a cross section parallel to each of the Y and Z directions. The XZ cross section corresponds to a cross section parallel to each of the X and Z directions. The "front surface of the semiconductor substrate" corresponds to the surface on which the semiconductor circuit is formed. The "back surface of the semiconductor substrate" corresponds to the surface opposite the front surface of the semiconductor substrate.

[0028] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the first embodiment will be described. The memory device 1 according to the first embodiment is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. Specifically, the memory device 1 according to the first embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is a silicon substrate. Below, a case will be described in which the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after the semiconductor substrates W1 and W2 are bonded together.

[0029] Fig. 3 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. As shown in Fig. 3, the memory device 1 has a structure in which, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300 are stacked in this order from the bottom.

[0030] The CMOS layer 100 includes a CMOS circuit (control circuit) formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions and the like according to the design of the CMOS circuit. The CMOS layer 100 includes control circuits such as an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0031] The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a CMOS circuit provided in the CMOS layer 100 and form part of the semiconductor circuit. The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to a memory cell array 10 provided in the memory layer 200 and form part of the semiconductor circuit. The plurality of bonding pads included in the bonding layer B1 are respectively connected to a plurality of bonding pads BP included in the bonding layer B2. The space between the bonding layers B1 and B2 corresponds to the boundary between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2 (not shown).

[0032] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2 together. The wiring layer 300 includes wiring connected to a semiconductor circuit provided in the memory layer 200 and a plurality of pads PD. The plurality of pads PD are exposed on the surface of the memory device 1. The plurality of pads PD are used to connect the memory device 1 to a memory controller 2, etc.

[0033] (2: Planar layout of memory cell array 10) 4 is a plan view showing an example of a planar layout of the memory cell array 10 included in the memory device 1 according to the first embodiment. As shown in FIG. 4, the memory cell array 10 includes a plurality of slits SLT. The memory cell array 10 also has a memory region MA and a lead-out region HA aligned in the X direction.

[0034] Each slit SLT corresponds to a plate-like member extending along the X direction. Each slit SLT has a portion extending along the X direction, and crosses the memory area MA and the lead-out area HA along the X direction. A plurality of slits SLT are aligned in the Y direction. Each slit SLT separates adjacent wirings (for example, word lines WL0 to WL7 and select gate lines SGD and SGS) via the slit SLT. In the memory cell array 10, each of the areas partitioned along the Y direction by the slits SLT corresponds to one block BLK.

[0035] The memory region MA is an area used for storing data. The memory region MA includes a plurality of memory pillars configured to be able to store data. The lead-out region HA is an area used, for example, for connection between stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) and the row decoder module 16. The lead-out region HA includes a plurality of support pillars for maintaining the structure of the stacked wiring when it is formed. Hereinafter, the area sandwiched between the memory region MA and the lead-out region HA is referred to as the boundary region BA. The boundary region BA includes a pattern for assisting in the formation of memory pillars arranged at the end of the memory region MA.

[0036] (3: Planar layout of memory area MA of memory cell array 10) 5 is a plan view showing an example of a planar layout of a memory region of the memory cell array 10 included in the memory device 1 according to the first embodiment. Fig. 5 shows a region including one block BLK sandwiched between two adjacent slits SLT. As shown in Fig. 5, the memory device 1 includes, in the memory region MA, for example, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL.

[0037] Each slit SHE has a portion extending along the X direction and crosses the memory area MA along the X direction. A plurality of slits SHE are arranged in the Y direction. In this example, four slits SHE are arranged between two slits SLT adjacent to each other in the Y direction. Each slit SHE has a structure in which an insulator is embedded, for example. Each slit SHE separates adjacent wirings (at least the select gate lines SGD) via the slit SHE. In the memory cell array 10, each of the areas separated by the slits SLT and SHE corresponds to one string unit SU. In this example, string units SU0 to SU4 are arranged between two adjacent slits SLT.

[0038] Each memory pillar MP is, for example, a columnar member corresponding to one NAND string NS. The multiple memory pillars MP are arranged in a staggered pattern (grid pattern) for each block BLK. For example, the multiple memory pillars MP are arranged in a staggered pattern of 24 rows in the area between two adjacent slits SLT. In this example, counting from the top of the page, one slit SHE is arranged to overlap the memory pillar MP in the fifth row, the memory pillar MP in the tenth row, the memory pillar MP in the fifteenth row, and the memory pillar MP in the twentieth row.

[0039] Each bit line BL has a portion extending in the Y direction. The multiple bit lines BL are spaced apart from stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) in the Z direction and are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CV. Furthermore, the contact CV between the memory pillar MP and the bit line BL in contact with two different select gate lines SGD may be omitted.

[0040] The planar layout of the memory area MA may be other layouts. For example, the number and arrangement of memory pillars MP and slits SHE arranged between two adjacent slits SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0041] (4: Cross-sectional structure of memory area MA of memory cell array 10) 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory region MA of the memory cell array 10 included in the memory device 1 according to the first embodiment. Fig. 6 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in Fig. 6, the memory cell array 10 includes, in the memory region MA, for example, conductor layers 21-26, insulator layers 30-36, an insulating member 37, and contacts V0 and V1.

[0042] An insulating layer 30 is provided on a semiconductor substrate W2. A conductor layer 21 is provided on the insulating layer 30. Insulating layers 31 and conductor layers 22 are alternately provided on the conductor layer 21. An insulating layer 32, a conductor layer 23, an insulating layer 33, an insulating layer 34, and a conductor layer 24 are provided in this order on the uppermost conductor layer 22. Each of the conductor layers 21, 22, and 23 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 24 has, for example, a portion formed in a line shape extending in the Y direction. The conductor layer 21 is used as a select gate line SGS. The multiple conductor layers 22 are used, in order from the bottom, as word lines WL0 to WL7, respectively. The conductor layer 23 is used as a select gate line SGD. The conductor layer 24 is used as a bit line BL.

[0043] A conductive layer 25 is provided above the conductive layer 24. The conductive layer 24 and the conductive layer 25 are connected via a contact V0. A conductive layer 26 is provided above the conductive layer 25. The conductive layer 25 and the conductive layer 26 are connected via a contact V1. The side surfaces of the conductive layer 25 and the contacts V0 and V1 are covered with an insulator layer 35. The insulator layer 35 may be composed of multiple insulating films. The side surfaces of the conductive layer 26 are covered with an insulator layer 36. The insulator layer 36 and the conductive layer 26 are included in the bonding layer B2. The conductive layer 26 corresponds to the bonding pad BP. The conductive layer 26 includes, for example, copper.

[0044] The slits SLT separate the insulating layers 30 to 33 and the conductive layers 21 to 23. For example, an insulating member 37 is embedded in the slits SLT. The insulating member 37 has a plate-like portion extending along the XZ plane. A conductive material having an insulating spacer on its side wall may be arranged in the slits SLT so as to be insulated from these wirings.

[0045] Each memory pillar MP extends along the Z direction and penetrates the insulator layers 30 to 33 and the conductor layers 21 to 23. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator extending along the Z direction. The semiconductor layer 41 covers the core member 40. The lower part of the semiconductor layer 41 is in contact with, for example, the semiconductor substrate W2. The stacked film 42 covers the side and bottom surfaces of the semiconductor layer 41. The semiconductor layer 41 and the conductor layer 24 are connected via contacts CV.

[0046] The portion where the memory pillar MP intersects with the conductive layer 21 functions as a select transistor ST2. The portion where the memory pillar MP intersects with the conductive layer 22 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 23 functions as a select transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0047] (5: Cross-sectional structure of memory pillar MP) FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar MP included in the memory device 1 according to the first embodiment. FIG. 7 illustrates a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. As shown in FIG. 7, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 contains, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 contains, for example, silicon nitride.

[0048] (6: Planar layout in the vicinity of the boundary area BA of the memory cell array 10) 8 is a plan view showing an example of a planar layout near the boundary area BA of the memory cell array 10 included in the memory device 1 according to the first embodiment. Fig. 8 shows the boundary area BA and a portion of the memory area MA and lead-out area HA adjacent to the boundary area BA. As shown in Fig. 8, each of the lead-out area HA and the boundary area BA includes a plurality of support pillars HR. The boundary area BA further includes a plurality of dummy pillars DMP.

[0049] Each support pillar HR is a columnar member for maintaining the structure of stacked wiring in the memory cell array 10. At the same height, the diameter of the support pillar HR is larger than the diameter of the memory pillar MP. The multiple support pillars HR are arranged in a staggered pattern (grid pattern) for each block BLK in each of the lead-out region HA and the boundary region BA.

[0050] Each dummy pillar DMP corresponds to a pattern for assisting the formation of memory pillars MP arranged at the end of the memory region MA. At the same height, the diameter of the dummy pillar DMP is smaller than the diameter of the support pillars HR. Furthermore, the diameter of the dummy pillar DMP tends to become smaller, for example, the closer it is to the lead-out region HA. Each dummy pillar DMP has the same layer structure as the memory pillar MP. Depending on its position, each dummy pillar DMP may have a structure in which some of the components included in the memory pillar MP are omitted.

[0051] The multiple dummy pillars DMP are arranged in a staggered pattern for each block BLK in the boundary area BA. It is preferable that the number of rows and columns of the support pillars HR arranged in a staggered pattern within the boundary area BA and between two adjacent slits SLT are designed to be the same as the number of rows and columns of the dummy pillars DMP arranged in a staggered pattern. It is more preferable that the multiple dummy pillars DMP provided in the boundary area BA completely overlap in the Z direction with the multiple support pillars HR provided in the boundary area BA.

[0052] (7: Cross-sectional structure in the vicinity of the boundary area BA of the memory cell array 10) 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of a cross-sectional structure near the boundary region BA of the memory cell array 10 included in the memory device 1 according to the first embodiment. Fig. 9 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and shows coordinate axes based on the semiconductor substrate W2. As shown in Fig. 9, the memory cell array 10 includes, in the lead-out region HA and the boundary region BA, a plurality of insulating members 50 corresponding to the plurality of support columns HR, respectively.

[0053] Each insulating member 50 has a shape extending in the Z direction from the insulator layer 33 to the insulator layer 30. Each support pillar HR penetrates the insulator layers 30 and 33, the insulator layers 31 and 32, and at least some of the conductive layers 21 to 23 sandwiched between the insulator layer 33 and the insulator layer 30. The bottom of the insulating member 50 contacts the semiconductor substrate W2. The structure of each insulating member 50 is the same between the lead region HA and the boundary region BA. The insulating member 50 contains, for example, silicon oxide (SiO2). That is, the insulating member 50 contains, for example, oxygen and silicon. In this way, the configuration of the support pillar HR is different from the configuration of the memory pillar MP.

[0054] The top surfaces of the dummy pillars DMP are aligned with the top surfaces of the memory pillars MP. The top surfaces of the dummy pillars DMP may or may not be aligned with the top surfaces of the support pillars HR. The side surfaces and bottom of each dummy pillar DMP are covered by the insulating members 50 (support pillars HR) overlapping in the Z direction. Therefore, the length of each dummy pillar DMP in the Z direction is shorter than the length of the support pillars HR in the Z direction. In this example, the dummy pillars DMP arranged on the memory region MA side have the same layer structure (core member 40, semiconductor layer 41, and stacked film 42) as the memory pillars MP. For example, the film thickness of the stacked film 42 included in the dummy pillars DMP is approximately the same as the film thickness of the stacked film 42 included in the memory pillars MP. In this example, the dummy pillars DMP arranged on the lead-out region HA side have a smaller diameter than the dummy pillars DMP on the memory region MA side, and therefore only have the semiconductor layer 41 and stacked film 42 of the layer structure of the memory pillars MP. The dummy pillars DMP are not connected to the stacked wiring of the memory cell array 10 and conductive layers (for example, bit lines BL) spaced apart in the Z direction.

[0055] In the lead-out region HA, each of the stacked wirings included in the memory cell array 10 may have a terrace portion. The terrace portion corresponds to a portion that does not overlap with the wiring (conductor layer) in the upper layer (opposite the semiconductor substrate W2) in a top view. The structure formed by the multiple terrace portions is similar to a step, terrace, rimstone, or the like. In this example, only the terrace portions of the two conductor layers 22 are illustrated. In addition, in this example, the step formed by the terrace portions is filled with an insulating layer 33. Contacts (not shown) provided in the lead-out region HA are connected to the terrace portion of the corresponding wiring among the stacked wirings. The wiring and the row decoder module 16 are electrically connected via the contacts and wiring (not shown).

[0056] (8: Cross-sectional structure of memory device 1) FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. FIG. 10 shows coordinate axes based on the semiconductor substrate W1. As shown in FIG. 10, the CMOS layer 100 includes an insulator layer 60, a plurality of conductor layers 62, and a plurality of contacts 63. The junction layer B1 includes an insulator layer 61 and a conductor layer 64. The memory layer 200 includes insulator layers 30 to 36, conductor layers 21 to 27, a plurality of memory pillars MP, a slit SLT, and contacts CV, V0, and V1. The wiring layer 300 includes an insulator layer 38. A transistor TR is provided on the semiconductor substrate W1. The transistor TR corresponds to an element included in the sense amplifier module 17.

[0057] In the CMOS layer 100, an insulator layer 60 is provided on a semiconductor substrate W1. Within the insulator layer 60, at least one contact 63 and at least one conductor layer 62 are connected in series on the transistor TR. The insulator layer 60 may be composed of multiple insulating films. An insulator layer 61 is provided on the insulator layer 60. A conductor layer 64 is in contact with the upper part of the uppermost contact 63, which is indirectly connected to the transistor TR. The conductor layer 64 corresponds to a bond pad BP formed using the semiconductor substrate W1. The conductor layer 64 is in contact with the conductor layer 26 arranged opposite to it in the Z direction.

[0058] The memory layer 200 includes a structure in which the structure in the memory region MA of the memory cell array 10 described with reference to FIG. 6 is inverted vertically. In this example, the semiconductor substrate W2 is removed, and a part of the insulator layer 30, a part of the insulating member 37 in the slit SLT, and the stacked film 42 on the upper part of the memory pillar MP are also removed. The conductor layer 27 is provided on the insulator layer 30. The conductor layer 27 is formed in a plate shape extending along the XY plane. The conductor layer 27 is in contact with the semiconductor layer 41 on the upper part of the memory pillar MP. The conductor layer 27 is used as the source line SL. The insulator layer 38 is provided on the conductor layer 27. The insulator layer 38 includes the pad PD described with reference to FIG. 3, wiring for connecting the pad PD to the input / output circuit 11, and the like (not shown).

[0059] In this example, although not shown, the height of the upper surface of the support pillar HR is flush with the upper surface of the memory pillar MP due to the process of removing the semiconductor substrate W2 and the stacked film 42 on the upper part of the memory pillar MP. Also, although not shown, the upper part of the support pillar HR may be in contact with the conductor layer 27 (source line SL) like the memory pillar MP, or may be in contact with an insulator layer (not shown). The number of wiring layers included in the memory device 1 is not limited to the number of wiring layers shown in FIG. 10.

[0060] <1-2> Manufacturing method Next, a manufacturing method of the memory device 1 according to the first embodiment will be described with reference to FIGS. 11 to 20. FIGS. 11, 13, 15, 17, and 19 are plan views showing an example of a planar layout during the manufacturing process of the memory cell array 10 included in the memory device 1 according to the first embodiment. The planar layout referred to in this section corresponds to the area near the boundary area BA of the memory cell array 10 shown in FIG. 8. FIGS. 12, 14, 16, 18, and 20 are cross-sectional views showing an example of a cross-sectional structure during the manufacturing process of the memory cell array 10 included in the memory device 1 according to the first embodiment. FIG. 12 corresponds to a cross-section taken along line XII-XII in FIG. 11. FIG. 14 corresponds to a cross-section taken along line XIV-XIV in FIG. 13. FIG. 16 corresponds to a cross-section taken along line XVI-XVI in FIG. 15. FIG. 18 corresponds to a cross-section taken along line XVIII-XVIII in FIG. 17. FIG. 20 corresponds to a cross-section taken along line XX-XX in FIG. 19. In this specification, the term "laminated wiring section" refers to a structure used to form laminated wiring including a plurality of word lines WL aligned in the Z direction.

[0061] First, although not shown in the figure, sacrificial members 70-72 of the stacked wiring section are formed. Specifically, first, the sacrificial member 70 is formed on the insulator layer 30. On the sacrificial member 70, insulator layers 31 and sacrificial members 71 are alternately stacked. On the uppermost sacrificial member 71, an insulator layer 32 and a sacrificial member 72 are formed in this order. Then, by slimming or etching, a staircase structure of the sacrificial members 70-72 is formed in the lead-out region HA. Then, the steps of the staircase structure are filled with the insulator layer 33, and the upper surface of the insulator layer 33 is planarized. The sacrificial members 70-72 are, for example, silicon nitride (SiN). Depending on the design of the memory cell array 10, the formation of the staircase structure of the sacrificial members 70-72 may be omitted.

[0062] Next, as shown in FIG. 11, a mask REG1 is formed. Specifically, first, a mask member (e.g., carbon) to be used as a mask for the deep hole etching process is formed on the insulator layer 33. Then, a resist material is applied to the mask member. The resist material is then processed into a shape having a plurality of holes H1 by a photolithography process. The plurality of holes H1 are provided corresponding to the positions where the plurality of support pillars HR will be formed. Thereafter, the mask member is processed by an anisotropic etching process using the resist material as a mask. As a result, the shape of the resist material is transferred to the mask member, and a mask REG1 having a plurality of holes H1 is formed.

[0063] Next, an anisotropic etching process is performed using the mask REG1 as a mask. Then, etching proceeds through the holes H1, forming holes HH as shown in FIG. 12. Note that FIG. 12 shows the cross-sectional structure after the mask used at this time is removed. Each hole HH penetrates the insulator layers 30 and 33, the sacrificial members 70-72, and the portions of the insulator layers 31-32 sandwiched between the insulator layers 30 and 33. The surface of the semiconductor substrate W2 is exposed at the bottom of each hole HH. That is, in this process, the semiconductor substrate W2 is used as an etching stopper. Note that, for example, RIE (Reactive Ion Etching) is used in this process.

[0064] Next, as shown in Fig. 13, each of the holes HH is filled with an insulating member 50. At this time, as shown in Fig. 14, the bottom of each insulating member 50 is in contact with the semiconductor substrate W2. Furthermore, the side surface of each insulating member 50 is in contact with the insulator layer 33 and at least one of the insulator layers 30 to 32. After the holes HH are filled with the insulating member 50, an insulating film may be formed on the insulating member 50 and the stacked wiring portion, and the insulator layer 33 may be stacked.

[0065] Next, as shown in FIG. 15, a mask REG2 is formed. Specifically, first, a mask member (e.g., carbon) to be used as a mask for the deep hole etching process is formed on the insulator layer 33. Then, a resist material is applied to the mask member. Then, the resist material is processed by photolithography into a shape having a plurality of holes H2 and a plurality of holes H3. The plurality of holes H2 are provided corresponding to the positions where the plurality of memory pillars MP will be formed. The plurality of holes H3 are provided corresponding to the positions where the plurality of dummy pillars DMP will be formed. Note that, at this time, the plurality of holes H3 tend to be formed with a smaller diameter the closer they are to the end row in the overall arrangement of the plurality of holes H2 and holes H3. Thereafter, the mask member is processed by an anisotropic etching process using the resist material as a mask. As a result, the shape of the resist material is transferred to the mask member, and a mask REG2 having a plurality of holes H2 and a plurality of holes H3 is formed.

[0066] Next, an anisotropic etching process is performed using the mask REG2 as a mask. Then, etching proceeds through the holes H2 and H3, forming a plurality of memory holes MH and a plurality of holes DMH as shown in FIG. 16. Note that FIG. 16 shows a cross-sectional structure after the mask used at this time is removed. Each memory hole MH is formed by penetrating the insulator layers 30-33 and the sacrificial members 70-72. The surface of the semiconductor substrate W2 is exposed at the bottom of each memory hole MH. That is, in this process, the semiconductor substrate W2 is used as an etching stopper. Each hole DMH is formed by removing a portion of the insulating member 50 constituting the support post HR. The surface of the insulating member 50 is exposed at the side and bottom of each hole DMH. The position (height) of the bottom of each hole DMH varies depending on the diameter of the corresponding hole H3. Note that this process uses, for example, RIE. In RIE, when holes H3 are formed at the same pitch on the mask REG2, the smaller the diameter of the holes H3, the more likely it is that etching will be suppressed in the height direction (Z direction).

[0067] Next, as shown in FIG. 17, a memory pillar MP is formed in each memory hole MH, and a dummy pillar DMP is formed in each hole DMH. Specifically, a stacked film 42 (i.e., a block insulating film 45, an insulating film 44, and a tunnel insulating film 43), a semiconductor layer 41, and a core member 40 are formed in this order on the side surface and bottom surface of the memory hole MH. At this time, the stacked film 42, the semiconductor layer 41, and the core member 40 are also formed in this order on the side surface and bottom surface of the hole DMH. Note that, depending on the diameter of the hole DMH, it is not necessary for a portion of the stacked film 42, the semiconductor layer 41, and the core member 40 to be formed in the hole DMH. Then, a portion of the core member 40 provided in the upper part of the memory hole MH is removed, and a semiconductor layer 41 is formed in the portion from which the core member 40 was removed. As a result, as shown in FIG. 18, a structure corresponding to the memory pillar MP is formed in the memory hole MH. Similarly, a structure corresponding to the dummy pillar DMP is formed in the hole DMH. Thereafter, the laminated film 42, the semiconductor layer 41, and the core member 40 above the insulating layer 33 are removed by CMP (Chemical Mechanical Polishing) or the like.

[0068] Next, as shown in Fig. 19, slits SLT are formed to separate each of the sacrificial members 70-72 into blocks BLK. Specifically, first, an insulating film (not shown) is formed on the insulator layer 33 so as to protect the memory pillars MP, dummy pillars DMP, and support columns HR. Thereafter, the slits SLT are formed by a combination of photolithography and anisotropic etching. Although not shown, the slits SLT separate the insulator layers 30-33 from the sacrificial members 70-72. This process exposes the surface of the semiconductor substrate W2 at the bottom of the slits SLT.

[0069] Next, a replacement process is performed. Specifically, as shown in FIG. 20, the sacrificial members 70-72 are selectively removed through the slits SLT by wet etching using hot phosphoric acid or the like. At this time, the spaces from which the sacrificial members 70-72 have been removed are maintained by the multiple memory pillars MP and the multiple support columns HR. Then, conductors are embedded in the spaces from which the sacrificial members 70-72 have been removed through the slits SLT. CVD, for example, is used to form the conductors in this process. Then, the conductors formed in the slits SLT are removed by an etch-back process or the like, and the conductors formed in adjacent spaces are separated into multiple layers. This forms a conductor layer 21 that functions as the select gate line SGS, multiple conductor layers 22 each functioning as the word line WL, and a conductor layer 23 that functions as the select gate line SGD. After that, an insulating member 37 is formed in the slits SLT, and the stacked wiring shown in FIGS. 6 and 9 is completed.

[0070] <1-3> Effects of the first embodiment The memory device 1 according to the first embodiment described above makes it possible to reduce the manufacturing cost of the memory device 1. The effects of the first embodiment will be described in detail below using a first comparative example and a second comparative example.

[0071] In a memory device having a structure in which memory cells are stacked three-dimensionally, a plurality of support pillars HR are provided to maintain the structure of the stacked wiring portion when the sacrificial members 70-72 are removed during replacement processing. In a manufacturing method in which the memory pillars MP and the support pillars HR are formed in separate processes, holes DMH are arranged in the boundary region BA to assist the opening of the memory holes MH in the edge row when processing the plurality of memory holes MH. However, it is difficult to control the depth of the holes DMH.

[0072] FIG. 21 is a plan view showing an example of the planar layout of a memory cell array 10A according to a first comparative example. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21, showing an example of the cross-sectional structure of the memory cell array 10A according to the first comparative example. The first comparative example corresponds to a case in which multiple support pillars HR are not formed in the boundary region BA, as shown in FIG. 21. In this example, as shown in FIG. 22, the diameter of the dummy pillars DMP is small in the boundary region BA, and the bottoms of the dummy pillars DMP do not reach the semiconductor substrate W2. With this design, there is a risk that the layer structure of the insulator layer 31 below the dummy pillars DMP will collapse during a replacement process in the formation of stacked wiring. Specifically, the insulator layer 31 will bend in the portions not reached by the dummy pillars DMP, which may result in poor filling of the conductor corresponding to the word line WL.

[0073] FIG. 23 is a plan view showing an example of the planar layout of a memory cell array 10B according to a second comparative example. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 23 , showing an example of the cross-sectional structure of the memory cell array 10B according to the second comparative example. The second comparative example corresponds to a case where the diameter of the dummy pillars DMP in the boundary region BA is larger than that of the first comparative example, as shown in FIG. 23 . In this case, as shown in FIG. 24 , the bottoms of the dummy pillars DMP may reach the semiconductor substrate W2 in the boundary region BA. As a result, deflection of the insulator layer 31 during the replacement process can be suppressed. On the other hand, if the diameter of the dummy pillars DMP is increased, over-etching of the semiconductor substrate W2 may occur when forming holes HH corresponding to the dummy pillars DMP. In this case, because the heights of the bottoms of the memory pillars MP and the dummy pillars DMP differ, a step may occur when removing the semiconductor substrate W2 after the bonding process for the semiconductor substrates W1 and W2. The resulting step may then cause defects.

[0074] In contrast, the memory device 1 according to the first embodiment has a structure in which the dummy pillars DMP and the support pillars HR overlap in the Z direction in the boundary region BA. For example, the multiple support pillars HR formed in the boundary region BA can suppress bending of the insulator layer 31 during replacement processing. Furthermore, the multiple support pillars HR formed in the boundary region BA can tolerate the dummy pillars DMP not reaching the semiconductor substrate W2 when forming the multiple memory holes MH. That is, in the memory device 1 according to the first embodiment, the diameter of the dummy pillars DMP is designed to be small, which can suppress over-etching of the semiconductor substrate W2 and the occurrence of defects caused by over-etching.

[0075] As described above, the memory device 1 according to the first embodiment can suppress the occurrence of defects in the replacement process and defects caused by over-etching of the dummy pillars DMP. Therefore, the memory device 1 according to the first embodiment can improve the yield and suppress the manufacturing cost of the memory device 1.

[0076] <2> Second embodiment In the second embodiment, a boundary area BA having the same planar layout as in the first embodiment is applied to a memory cell array 10C formed in multiple layers. The following describes the memory device 1 according to the second embodiment, focusing on the differences from the first embodiment.

[0077] <2-1> Configuration First, the configuration of the memory device 1 according to the second embodiment will be described. The configuration of the memory device 1 according to the second embodiment is the same as that of the memory device 1 according to the first embodiment, except that the structure of the memory cell array 10 is different. In the second embodiment, an example will be described in which each NAND string NS includes 16 memory cell transistors MT0 to MT15 connected to word lines WL0 to WL15, respectively. Hereinafter, the memory pillar MP of the memory device 1 according to the second embodiment will be referred to as a "memory pillar MPa."

[0078] (1: Cross-sectional structure of memory cell array 10C) 25 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 10C included in a memory device 1 according to the second embodiment. Fig. 25 shows an example of the structure of the memory cell array 10C formed on a semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in Fig. 25, the memory cell array 10C includes, for example, a semiconductor substrate W2, conductor layers 21, 22a, 22b, 23, and 24, insulator layers 30, 31a, 31b, 32 to 35, and 80, a memory pillar MPa, slits SLT and SHE, and contacts CV.

[0079] The memory cell array 10C differs from the memory cell array 10 of the first embodiment in the structure between the conductor layer 21 and the insulator layer 32. Specifically, insulator layers 31a and conductor layers 22a are alternately stacked on the conductor layer 21. An insulator layer 80 is provided on the uppermost conductor layer 22a. Conductor layers 22b and insulator layers 31b are alternately stacked on the insulator layer 80. An insulator layer 32 is provided on the uppermost conductor layer 22b.

[0080] Each of the conductive layers 22a and 22b is formed, for example, in the shape of a plate extending along the XY plane. The eight stacked conductive layers 22a are used as word lines WL0 to WL7, respectively, in order from the conductive layer 21 side. The eight stacked conductive layers 22b are used as word lines WL8 to WL15, respectively, in order from the conductive layer 21 side. Each of the conductive layers 22a and 22b contains, for example, tungsten. Hereinafter, a division unit in the process of forming holes for forming the memory pillars MPa is referred to as a tier TI. In this example, the memory cell array 10C includes tiers TI1 and TI2. Tier TI1 includes eight conductive layers 22a. Tier TI2 includes eight conductive layers 22b.

[0081] The memory pillar MPa has a structure in which multiple pillars, each extending along the Z direction, are connected to one another. In this example, the memory pillar MPa includes two pillars connected to one another in the Z direction. These two pillars will be referred to below as the lower pillar LMP and the upper pillar UMP. The lower pillar LMP corresponds to the level TI1. The lower pillar LMP is provided to penetrate the insulator layers 30, 31a, and 80 and the conductor layers 21 and 22a, respectively. The upper pillar UMP is provided above the lower pillar LMP and corresponds to the level TI2. The upper pillar UMP is provided to penetrate the insulator layers 31b, 32, and 33 and the conductor layers 22b and 23, respectively. The connection portion between the lower pillar LMP and the upper pillar UMP is included in the layer at the same height as the insulator layer 80.

[0082] The lower pillar LMP and the upper pillar UMP share the core member 40, the semiconductor layer 41, and the stacked film 42. That is, the core member 40, the semiconductor layer 41, and the stacked film 42 included in the memory pillar MPa are each continuously provided between the lower pillar LMP and the upper pillar UMP. In this example, the lower pillar LMP and the upper pillar UMP each have an inverse tapered shape. In this case, the XY cross-sectional area of ​​the upper end of the lower pillar LMP is larger than the XY cross-sectional area of ​​the lower end of the upper pillar UMP. The intersection of the lower pillar LMP and the conductor layer 21 functions as the select transistor ST2. The intersection of the lower pillar LMP and each of the eight conductor layers 22a functions as memory cell transistors MT0 to MT7, starting from the bottom. The intersection of the upper pillar UMP and each of the eight conductor layers 22b functions as memory cell transistors MT8 to MT15, starting from the bottom. The intersection of the upper pillar UMP and the conductive layer 23 functions as a select transistor ST1.

[0083] The slit SLT of the second embodiment separates the conductor layers 21, 22a, 22b, and 23 from the insulator layers 30, 31a, 80, 31b, 32, and 33. That is, the slit SLT separates the wirings provided in the levels TI1 and TI2. In the slit SLT of the second embodiment, a conductor having an insulating spacer on its sidewall may be arranged insulated from the wirings. The slit SHE of the second embodiment separates at least the conductor layer 23, as in the first embodiment.

[0084] (2: Cross-sectional structure of the memory cell array 10C in the vicinity of the boundary area BA) FIG. 26 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 10C in the memory device 1 according to the second embodiment near the boundary region. FIG. 26 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in FIG. 26, the support pillars HR of the second embodiment are provided to penetrate through the levels TI1 and TI2. Specifically, the insulating members 50 constituting the support pillars HR of the second embodiment penetrate, for example, the insulator layers 30, 31a, 80, 31b, 32, and 33 and the conductor layers 21, 22a, 22b, and 23. That is, the insulating members 50 are provided continuously between the levels TI1 and TI2. Furthermore, the side surfaces of the insulating members 50 constituting the support pillars HR have a continuous shape across the levels TI1 and TI2. The bottoms of the insulating members 50 of the second embodiment contact the semiconductor substrate W2. The structure of each insulating member 50 in the second embodiment is the same between the lead-out area HA and the boundary area BA.

[0085] The dummy pillars DMP in the second embodiment are included in, for example, the story TI2, but not in the story TI1. Specifically, in the boundary region BA, the top surface of each dummy pillar DMP is aligned with the top surface of the memory pillar MPa. The top surface of the dummy pillar DMP may or may not be aligned with the top surface of the support pillar HR. The side and bottom of each dummy pillar DMP are covered by the insulating member 50 (support pillar HR) overlapping in the Z direction. The length of each dummy pillar DMP in the Z direction is shorter than the height of the story TI2. However, without being limited to this, the boundary region BA may include dummy pillars DMP that extend from the top of the story TI2 to partway up the story TI1.

[0086] In the lead-out region HA of the second embodiment, the stacked wiring of the layer TI1 and the stacked wiring of the layer TI2 included in the memory cell array 10C may each have a terrace portion. In this example, the layer TI1 includes terrace portions of two conductor layers 22. In this example, the step formed by the terrace portion in the layer TI1 is filled with an insulating layer 80. The step formed by the terrace portion in the layer TI2 is filled with an insulating layer 33 (not shown).

[0087] <2-2> Manufacturing method Next, a manufacturing method of the memory device 1 according to the second embodiment will be described with reference to Figures 27 to 33. Each of Figures 27, 28, 29, 30, 31, 32, and 33 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing process of the memory cell array 10C included in the memory device 1 according to the second embodiment. The cross-sectional structure referred to in this section corresponds to the region near the boundary region BA of the memory cell array 10 shown in Figure 26.

[0088] First, although not shown in the figure, sacrificial members 70 and 71a of the stacked wiring section corresponding to tier TI1 are formed. Specifically, first, the sacrificial member 70 is formed on the insulator layer 30. Insulator layers 31a and sacrificial members 71a are alternately stacked on the sacrificial member 70. Then, a staircase structure of the sacrificial members 70 and 71a is formed in the lead-out region HA by slimming and etching. Then, the steps of the staircase structure are filled with an insulator layer 80, and the upper surface of the insulator layer 80 is flattened. The sacrificial members 70 and 71a are, for example, silicon nitride (SiN). Depending on the design of the memory cell array 10C, the formation of the staircase structure of the sacrificial members 70 and 71a may be omitted.

[0089] Next, a mask REG2 (not shown) similar to that of the first embodiment is formed, and an anisotropic etching process is performed using the mask REG2 as a mask. Then, etching proceeds through the holes H2 and H3, forming a plurality of memory holes LMH and a plurality of holes LDMH, as shown in FIG. 27. Each memory hole LMH penetrates the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. The surface of the semiconductor substrate W2 is exposed at the bottom of each memory hole LMH. That is, in this process, the semiconductor substrate W2 is used as an etching stopper. Each hole LDMH penetrates a portion of the stacked structure of the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. The bottom of each hole LDMH stops midway through the stacked structure (layer TI1) of the insulator layers 30, 31a, and 80 and the sacrificial members 70 and 71a. Note that this process uses, for example, RIE.

[0090] Next, as shown in Fig. 28, a sacrificial member 90 is formed in each memory hole LMH, and an insulating member 91 is formed in each hole LDMH. The material used for the sacrificial member 90 is different from the material used for the insulating member 91. Therefore, the formation of the sacrificial member 90 and the formation of the insulating member 91 are performed in separate steps. The sacrificial member 90 is, for example, carbon (C). The insulating member 91 is, for example, silicon oxide (SiO2).

[0091] Next, as shown in FIG. 29, sacrificial members 71b and 72 of the stacked wiring portion corresponding to tier TI2 are formed. Specifically, first, sacrificial members 71b and insulator layers 31b are alternately stacked on an insulator layer 80. Then, a staircase structure (not shown) of the sacrificial members 71b and 72 is formed in the lead-out region HA by slimming or etching. Then, the steps of the staircase structure are filled with an insulator layer 33, and the upper surface of the insulator layer 33 is flattened. The sacrificial members 71b and 72 are made of, for example, silicon nitride (SiN). Depending on the design of the memory cell array 10C, the formation of the staircase structure of the sacrificial members 71b and 72 may be omitted.

[0092] Next, a mask REG1 (not shown) similar to that of the first embodiment is formed, and an anisotropic etching process is performed using the mask REG1 as a mask. Then, etching proceeds through the multiple holes H1, forming multiple holes HH as shown in FIG. 30. Each hole HH in the second embodiment penetrates the insulator layers 30, 33, and 80, the sacrificial members 70, 71a, 71b, and 72, and the portions of the insulator layers 31, 31a, 31b, and 32 sandwiched between the insulator layers 30 and 33. The surface of the semiconductor substrate W2 is exposed at the bottom of each hole HH. In other words, the semiconductor substrate W2 is used as an etching stopper in this process. Thus, each hole HH in the second embodiment penetrates the stacked wiring portions of the levels TI1 and TI2. This process removes part or all of the insulating member 91 provided on the level TI1.

[0093] 31, an insulating member 50 is formed, and each of the holes HH is filled with the insulating member 50. At this time, the bottom of each insulating member 50 is in contact with the semiconductor substrate W2. In addition, the side surface of each insulating member 50 is in contact with the insulating layers 33 and 80 and at least one of the insulating layers 30, 31a, 31b, 32, and 33.

[0094] Next, a mask REG2 (not shown) similar to that of the first embodiment is formed, and an anisotropic etching process is performed using the mask REG2 as a mask. Then, etching proceeds through the plurality of holes H2 and the plurality of holes H3, forming a plurality of memory holes UMH and a plurality of holes UDMH, as shown in FIG. 32. Each memory hole UMH is formed penetrating the insulator layers 31b and 33 and the sacrificial members 71b and 72. At the bottom of each memory hole UMH, the upper surface of the sacrificial member 90 of the associated memory hole LMH is exposed. That is, in this process, the sacrificial member 90 of the memory hole LMH is used as an etching stopper when forming the memory hole UMH. Each hole UDMH is formed by removing a portion of the insulating member 50 constituting the support post HR. At the side and bottom of each hole UDMH, the surface of the insulating member 50 is exposed. The position (height) of the bottom of each hole UDMH varies depending on the diameter of the corresponding hole H3. Note that this process uses, for example, RIE.

[0095] Next, the sacrificial member 90 in the corresponding memory hole LMH is removed via each memory hole UMH, for example, by wet etching. Then, as shown in FIG. 33 , a memory pillar MPa is formed in the pair of connected memory holes LMH and UMH, and a dummy pillar DMP is formed in each hole UDMH. Specifically, a stacked film 42 (i.e., a block insulating film 45, an insulating film 44, and a tunnel insulating film 43), a semiconductor layer 41, and a core member 40 are formed in this order on the side and bottom surfaces of the connected memory holes LMH and UMH. At this time, the stacked film 42, the semiconductor layer 41, and the core member 40 are also formed in this order on the side and bottom surfaces of the hole UDMH. Note that depending on the diameter of the hole UDMH, it is possible that the stacked film 42, the semiconductor layer 41, and a portion of the core member 40 are not formed in the hole UDMH. Then, a portion of the core member 40 provided in the upper portion of the connected memory holes LMH and UMH is removed, and a semiconductor layer 41 is formed in the portion from which the core member 40 was removed. As a result, as shown in Fig. 33, a structure corresponding to the memory pillar MPa is formed in the connected memory holes LMH and UMH. Similarly, a structure corresponding to the dummy pillar DMP is formed in the hole UDMH. Thereafter, the stacked film 42, the semiconductor layer 41, and the core member 40 above the insulator layer 33 are removed by CMP or the like.

[0096] Next, although not shown in the figure, slits SLT are formed to separate each of the sacrificial members 70, 71a, 71b, and 72 into blocks BLK, and a replacement process is performed. Specifically, the sacrificial members 70, 71a, 71b, and 72 are selectively removed through the slits SLT by wet etching using hot phosphoric acid or the like. At this time, the spaces left by the removal of the sacrificial members 70, 71a, 71b, and 72 are maintained by the multiple memory pillars MPa and the multiple support columns HR. Then, conductors are embedded through the slits SLT into the spaces left by the removal of the sacrificial members 70, 71a, 71b, and 72. The conductors in this process are formed, for example, by CVD. Thereafter, the conductors formed in the slits SLT are removed by etch-back or the like, and the conductors formed in adjacent spaces are separated into multiple layers. This forms a conductive layer 21 that functions as a select gate line SGS, a plurality of conductive layers 22a and 22b that each function as a word line WL, and a conductive layer 23 that functions as a select gate line SGD. After that, an insulating member 37 is formed in the slit SLT, and the stacked wiring shown in FIGS. 25 and 26 is completed.

[0097] <2-3> Effects of the second embodiment As described above, the memory device 1 according to the second embodiment has memory pillars MPa formed in multiple layers, and has a structure in which multiple dummy pillars DMP and multiple support pillars HR overlap in the Z direction in the boundary region BA. Even in such a case, the memory device 1 according to the second embodiment can suppress the occurrence of defects in the replacement process and defects caused by over-etching of the dummy pillars DMP, as in the first embodiment. Therefore, the memory device 1 according to the second embodiment can improve yield and suppress the manufacturing cost of the memory device 1.

[0098] <3> Modifications etc. The memory device 1 described above can be modified in various ways.

[0099] FIG. 34 is a plan view showing an example of the planar layout of a memory cell array 10D according to a first modification. FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 34, showing an example of the cross-sectional structure of the memory cell array 10D according to the first modification. The first modification corresponds to a case where, as shown in FIG. 34, the positions of multiple dummy pillars DMP and multiple support pillars HR are misaligned in the boundary region BA. That is, it corresponds to a state where the dummy pillars DMP and the support pillars HR partially overlap. In this case, as shown in FIG. 35, a portion of the stacked film 42 of the dummy pillars DMP is in contact with at least one of the conductor layers 21 to 23. In this way, even when the positions of the dummy pillars DMP and the support pillars HR are misaligned in the boundary region BA, the same effects as those of the first embodiment can be achieved.

[0100] FIG. 36 is a plan view showing an example of the planar layout of a memory cell array 10E according to a second modification. FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG. 36, showing an example of the cross-sectional structure of the memory cell array 10E according to the second modification. The second modification corresponds to the case where, as shown in FIG. 36, a plurality of dummy pillars DMP and a plurality of support pillars HR are separated (do not overlap) in the boundary region BA. In this case, as shown in FIG. 37, the side surface of the dummy pillar DMP is in contact with at least one of the conductor layers 21 to 23. In this way, even when the dummy pillars DMP and the support pillars HR are separated in the boundary region BA, the same effects as those of the first embodiment can be achieved.

[0101] The structures described in the first and second modified examples can also be caused by misalignment during photolithography. The greater the overlap between the support pillars HR and the dummy pillars DMP in the boundary region BA, the more likely it is that an increase in wiring resistance will be suppressed due to the formation of the dummy pillars DMP. Therefore, the support pillars HR and dummy pillars DMP arranged in a staggered pattern within the boundary region BA and between two adjacent slits SLT may have different numbers of rows and columns and pitches, but it is more preferable that they be the same. Furthermore, in the second embodiment, if misalignment occurs between the formation of the memory holes LMH and holes LDMH in the layer TI1 and the formation of the holes HH in the layers TI1 and TI2, the insulating members 91 formed in the holes LDMH may remain in the memory device 1.

[0102] FIG. 38 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bond pads BP. FIG. 38 shows a conductive layer 64 (bond pad BP) formed using a semiconductor substrate W1 (not shown), a conductive layer 26 (bond pad BP) formed using a semiconductor substrate W2 (not shown), and some contacts 63, V1, and conductive layers 62 and 25 connected to these bond pads BP. As shown in FIG. 38, the two opposing bond pads BP may have different tapered shapes based on the etching direction during formation. Specifically, the conductive layer 64 formed using the semiconductor substrate W1 has, for example, an inverse tapered shape. The conductive layer 26 formed using the semiconductor substrate W2 has, for example, a tapered shape. Therefore, the cross-sectional shape along the Z direction at the bonded portion between the conductive layer 64 and the conductive layer 26 may have a non-rectangular shape rather than a linear sidewall. The shapes of the two opposing bond pads BP in other portions may also be formed similarly to the conductive layers 26 and 64. Furthermore, a pair of two opposing bond pads BP may be bonded with a misalignment depending on the alignment during the bonding process. This may result in a step between the upper surface of the conductive layer 64 and the lower surface of the conductive layer 26. The pair of opposing bond pads BP may have a boundary or may be integrated. The bond pads BP and the contacts 63, V1 connected to the bond pads BP may be integrally formed. A plurality of corresponding contacts 63, V1 may be connected to the bond pads BP. For example, the conductive layer 64 may be connected to the conductive layer 62 via a plurality of contacts 63. Similarly, the conductive layer 26 may be connected to the conductive layer 25 via a plurality of contacts V1.

[0103] FIG. 39 is a cross-sectional view showing an example of a detailed cross-sectional structure of a boundary portion between the first tier TI1 and the second tier TI2 of the memory pillar MPa included in the memory device 1 according to the second embodiment. As shown in FIG. 39 , for example, in a YZ cross-section, the upper end of the lower memory pillar LMP may have a rounded shape instead of an angular shape. In this case, the XY cross-sectional area of ​​the upper end of the lower memory pillar LMP is not clearly larger than the XY cross-sectional area of ​​the lower end of the upper memory pillar UMP. However, the shape of the side surface of the memory pillar MPa is discontinuous at the boundary portion between the lower memory pillar LMP and the upper memory pillar UMP. Specifically, for example, in a YZ cross-section, the side surface SLMP of the lower memory pillar LMP is offset from the extension line of the side surface SUMP of the upper memory pillar UMP, which is indicated by a dashed line in FIG. 39 . The offset between the two side surfaces SLMP and SUMP can occur in any cross-section including the Z direction, such as an XZ cross-section. In this specification, the boundary portion of the memory pillar MP in two adjacent layers TI in the Z direction can be identified based on the discontinuous portion in the shape of the side surface of the memory pillar MP. The memory pillar MPa may have a structure in which three or more pillars, each extending along the Z direction, are connected. Even in such a case, the memory pillar MPa may have a structure such as that shown in FIG. 39 at the boundary portion of the adjacent layers TI.

[0104] FIG. 40 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 10F according to a third modification. As shown in FIG. 40, the third modification corresponds to a case in which the support pillars HR and dummy pillars DMP described in the first embodiment are formed for each level TI. Specifically, the memory cell array 10F according to the third modification has a structure in which the support pillars HR in the second embodiment are replaced with support pillars HRa, and insulating members 91 corresponding to the holes LDMH remain. The support pillars HRa include insulating members 50a provided for the levels TI1 and TI2, respectively. The shape of the side surfaces of the insulating members 50a and 50b is discontinuous. The dummy pillars DMP overlap the support pillars HRa in the Z direction and are provided by removing a portion of the insulating member 50b. The insulating members 91 corresponding to the holes LDMH overlap the support pillars HRa in the Z direction and are provided by removing a portion of the insulating member 50a. Thus, even when the support pillars HR are provided for each level TI, the same effects as those of the second embodiment can be achieved. In the memory cell array 10F according to the third modification, a sacrificial member 90 may be formed in place of the insulating member 91 in the holes LDMH.

[0105] FIG. 41 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1A according to a fourth modification. As shown in FIG. 41, the fourth modification corresponds to a case where the memory device 1A is formed using a single semiconductor substrate SUB, and a CMOS circuit is disposed below the memory cell array 10. Even when the memory device 1A is not formed using multiple semiconductor substrates, the support pillars HR and dummy pillars DMP are formed in the boundary region BA as in the first embodiment, thereby preventing the dummy pillars DMP from penetrating through to the insulator layer 60. This prevents defects caused by the bottoms of the dummy pillars DMP interfering with the CMOS circuit formed below the memory cell array 10. As a result, the memory device 1A according to the fourth modification can improve yield and reduce the manufacturing cost of the memory device 1A.

[0106] In the above-described embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be modified as appropriate. The memory pillar MP may have a structure in which a pillar corresponding to the select gate line SGD and a pillar corresponding to the word line WL are connected to each other. The memory pillar MP and the bit line BL may be connected by multiple contacts connected in the Z direction. A conductive layer may be inserted at the connection portion of the multiple contacts. The number of wiring layers and contacts included in the memory device 1 may be modified as appropriate depending on the circuit design. The memory pillar MP may have a tapered shape, an inverse tapered shape, or a bowing shape. The slit SLT may have a tapered shape, an inverse tapered shape, or a bowing shape. The XY cross-sectional structure of the memory pillar MP and the support post HR may be circular or elliptical. In this specification, the "XY cross-sectional area" corresponds to the cross-sectional area of ​​a cross section parallel to the semiconductor substrate W1 or W2. Each wiring in the stacked wiring may include a metal oxide film surrounding a conductor such as tungsten. In a multilayer wiring, the conductive layers alternately stacked with the insulating layers may be considered to include such a metal oxide film.

[0107] The manufacturing processes described in the above embodiments are merely examples. For example, other processes may be inserted between each manufacturing process, and the order of manufacturing processes may be changed as long as no problems arise. In this specification, "connected" refers to being electrically connected and does not exclude, for example, the use of another element between them. "Electrically connected" may also refer to an insulator being used as long as it operates similarly to an electrically connected structure. "Tapered shape" refers to a shape that becomes thinner with increasing distance from a reference member. "Inverse tapered shape" refers to a shape that becomes thicker with increasing distance from a reference member. "Columnar" refers to a structure provided in a hole formed during the manufacturing process of the memory device 1. "Diameter" refers to the inner diameter of a hole or the outer diameter of a pillar in a cross section parallel to the surface of the substrate (XY cross section). A "semiconductor substrate" may simply be referred to as a "substrate." A "semiconductor layer" may also be referred to as a "conductor layer." A "region" may be considered a structure contained within a substrate. For example, if the semiconductor substrate W1 is defined to include a memory area MA and a lead-out area HA, the memory area MA and the lead-out area HA are respectively associated with different areas above the semiconductor substrate W1. "Height" corresponds to, for example, the distance in the Z direction between the structure to be measured and the semiconductor substrate W1. A structure other than the semiconductor substrate W1 may be used as the basis for "height." "Top (planar) view" corresponds, for example, to viewing the front surface of the semiconductor substrate W1 from the vertical direction of the semiconductor substrate W1.

[0108] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0109] 1, 1A... memory device, 2... memory controller, 10, 10A, 10B, 10C, 10D, 10E, 10F... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21 to 27, 22a, 22b, 62, 64... conductor layer, 30 to 36, 31a, 31b, 38, 60, 61, 80... insulating layer, 37, 50, 50a, 50b, 91... insulating member, 40... core member, 41... semiconductor layer, 42... stacked film, 43... tunnel insulating film, 44... insulating film, 45... block Insulating film, 63, CV, V0, V1...contacts, 70 to 72, 71a, 71b, 90...sacrificial member, W1, W2...semiconductor substrate, 100...CMOS layer, 200...memory layer, 300...wiring layer, B1, B2...junction layer, BLK...block, SU...string unit, NS...NAND string, BL...bit line, WL...word line, SGD, SGS...select gate line, MT...memory cell transistor, ST1, ST2...select transistor, H1 to H3...hole, LMP...lower pillar, UMP...upper pillar, REG1, REG2...mask, SAU...sense amplifier unit, RD...row decoder, TI1, TI2...hierarchy

Claims

1. a substrate including a first region, a second region, and a third region aligned in order in a first direction; a plurality of first conductive layers arranged above the substrate in a second direction intersecting the first direction; a plurality of memory pillars provided in the first region, each of which has a portion intersecting with the plurality of first conductive layers and includes a stacked film; a plurality of first pillars provided in the second region and the third region, each having a portion intersecting with at least a portion of the plurality of first conductor layers, and having a configuration different from that of the memory pillars; a plurality of second pillars provided in the second region, each having a portion intersecting with at least one of the plurality of first conductive layers, and including the stacked film; A memory device comprising:

2. In the second region, at least a portion of each of the plurality of second pillars overlaps with any of the plurality of first pillars in the second direction. The memory device of claim 1 .

3. each of the second pillars is spaced from the first conductive layers; The memory device of claim 1 .

4. At least one second pillar of the plurality of second pillars is shorter in the second direction than the plurality of memory pillars. The memory device of claim 1 .

5. the plurality of first pillars are made of a first insulating material containing oxygen and silicon; The memory device of claim 1 .

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