Semiconductor device, pwm device, method for manufacturing semiconductor device, and program

Abstract

To provide a semiconductor device including a circuit that enables a delay measurement for adjusting a delay amount of a delay circuit.SOLUTION: A semiconductor device 13 includes: a signal generation circuit 21; a signal propagation circuit 23; and an input / output circuit 25. The signal generation circuit 21 includes a delay circuit 27 that generates a delay signal having a trimmable delay time. The signal propagation circuit 23 includes a series connection 31 of a signal capture circuit 29, and the series connection 31 forms a propagation line 33 that propagates a signal from an input of the signal propagation circuit 23 as a propagation signal SPGT. Each of the signal acquisition circuits 29 acquires the propagation signal SPGT in synchronization with a clock signal CLK, and generates an acquisition signal SLAT from an acquisition value of the propagation signal SPGT. In the input / output circuit 25, an output circuit 35 generates an output signal SOUT from a specific signal SDET associated with a capture signal SLAT. An input circuit 37 receives a trimming code signal STRM specifying the delay time from the outside and provides the trimming code signal STRM to the signal generation circuit 21.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a PWM device, a method for manufacturing a semiconductor device, and a program. [Background technology]

[0002] Patent Document 1 discloses an analog-to-digital conversion circuit. This analog-to-digital conversion circuit includes a delay cell array through which an analog input signal propagates, and an encoder connected to the delay cell array. The delay cell array has a plurality of delay cells connected in series. Each of the delay cells operates in response to a reference clock signal. The encoder encodes the output signal of each stage of the delay cells to generate a digital output signal. The serially connected delay cells have a weighted delay amount for each delay cell. The encoder encodes the output signal of each stage of the delay cells with a weight corresponding to the number of stages of the delay cells. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-236225 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device controls an external device connected to the semiconductor device, and this control requires adjusting, i.e., fine-tuning, the edges of signal transitions in a time shorter than the period of a clock signal for synchronous operation in the semiconductor device.

[0005] For example, control based on pulse width modulation (PWM) requires high-resolution control. High-resolution PWM control requires fine adjustment of the rising or falling edge of a PWM signal. Specifically, fine adjustment of the rising and / or falling edge requires an adjustable delay circuit with a small delay amount. Furthermore, the measurement value of the delay amount of a delay circuit in a semiconductor device is sensitive not only to variations in the manufacturing process of the semiconductor device but also to the measurement environment and / or measurement method.

[0006] Generally, this delay is smaller than the clock period. It is not easy to measure pulse signals of semiconductor devices with a period of less than a microsecond using a test device such as a tester.

[0007] The present disclosure aims to provide a semiconductor device including a circuit that enables delay measurement for adjusting the delay amount of a delay circuit, a PWM device, a method for manufacturing the semiconductor device, and a program. [Means for solving the problem]

[0008] A semiconductor device according to a first aspect of the present disclosure is a semiconductor device including a signal generation circuit, a signal propagation circuit connected to the signal generation circuit, and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, wherein the signal generation circuit includes a signal input configured to receive a base signal for controlling a control target, a delay circuit configured to be able to generate delay signals with a plurality of trimmable delay times different from each other from the signal of the signal input, and a signal output for providing a signal from the delay circuit, and the signal propagation circuit includes an input configured to receive a clock signal and a signal different from the clock signal, a plurality of signal acquisition circuits, and one or more outputs connected to the input / output circuit, the signal acquisition circuits are connected in series to form at least one series connection, and the series connection of the signal acquisition circuits is configured to form a propagation line for propagating a signal from the input of the signal propagation circuit in a direction from the first stage to the last stage of the series connection. the signal propagation circuit is configured such that the signal acquisition circuit of the propagation line acquires a propagation signal propagating through the propagation line in synchronization with one of a rising edge and a falling edge of the clock signal to generate a plurality of acquisition signals for delay measurement on the propagation line, the signal propagation circuit is configured to generate one or more specific signals associated with the acquisition signals, the input / output circuit comprises one or more signal inputs configured to receive the specific signals, an output circuit configured to generate an output signal to be provided to the outside of the semiconductor device from at least a part of the specific signal, an input circuit configured to receive a trimming code signal from the outside of the semiconductor device that is specified based on a result of the delay measurement, and a trimming output configured to provide the trimming code signal, and the signal generation circuit has a trimming input connected to the input / output circuit via the trimming output.

[0009] A PWM device according to a second aspect of the present disclosure comprises a semiconductor device described in the above aspect and an external device controlled by the semiconductor device, wherein the semiconductor device further includes a drive circuit configured to generate a PWM drive signal in response to a signal from the signal generation circuit, and the external device is connected to the drive circuit.

[0010] A method for manufacturing a semiconductor device according to a third aspect of the present disclosure includes preparing an integrated circuit including a delay circuit configured to be capable of generating delay signals having a plurality of delay times that are trimmable and untrimmed and that are different from each other, and at least one propagation line including signal acquisition circuits connected in series, wherein the at least one propagation line forms an arrangement of the signal acquisition circuits from a first stage to a last stage in the series connection of the signal acquisition circuits; and inputting at least one reference signal to the propagation line, wherein the series connection of the signal acquisition circuits generates a propagation signal on the propagation line in response to the input of the reference signal. inputting a reference signal; acquiring a value of the propagation signal on the propagation line in the signal acquisition circuit in synchronization with a clock signal to generate a plurality of acquisition signals in the signal acquisition circuit; generating a trimming value for trimming the delay time of the delay circuit based on at least a portion of the acquired values ​​of the acquisition signals; specifying a delay value of the delay circuit using the trimming value; and manufacturing a semiconductor device including the delay circuit to which the trimming value has been applied, wherein applying the trimming value includes changing the memory contents of a rewritable non-volatile memory element.

[0011] A program according to a fourth aspect of the present disclosure is a program installed in a manufacturing apparatus including a connection device configured to be connected to a semiconductor device so as to be capable of bidirectional communication, and a test device connected to the connection device, wherein the semiconductor device includes a signal generation circuit including a delay circuit configured to generate delay signals having a plurality of trimmable delay times different from each other, a signal propagation circuit connected to the signal generation circuit, and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, the input / output circuit of the semiconductor device is configured to be connected to the test device via electrodes of the semiconductor device, the test device and the semiconductor device are operable in synchronization with a clock signal, the test device includes a processor and a memory coupled to the processor, the memory is configured to store program code executable by the processor, and the program code, when executed by the processor, causes the processor to perform the following process: controlling the signal propagation circuit to propagate at least one reference signal to the signal propagation circuit, and the signal propagation circuit propagates a signal between the signal propagation circuit and the signal propagation circuit connected in series. controlling an output circuit of the input / output circuit to provide from the semiconductor device to the test device one or more output signals generated by the input / output circuit to be associated with the specific signals; controlling the test device to receive the output signals; generating one or more trimming code signals based on the received output signals; and controlling an input circuit of the input / output circuit to provide the trimming code signals from the test device to the semiconductor device, the input circuit providing the trimming code signals to the delay circuit;configured to cause; [Effects of the Invention]

[0012] According to the above aspects, it is possible to provide a semiconductor device, a PWM device, a method for manufacturing a semiconductor device, and a program, which include a circuit that enables delay measurement for adjusting the delay amount of a delay circuit. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a diagram schematically showing a manufacturing apparatus and a semiconductor device according to this embodiment. [Figure 3] FIG. 3 is a diagram schematically illustrating a control device, for example a PWM device, according to this embodiment. [Figure 4] FIG. 4 is a diagram showing the relationship between a propagation signal propagating through a propagation line of an exemplary signal propagation circuit of the semiconductor device according to this embodiment and a signal acquisition circuit. [Figure 5] FIG. 5 is a diagram schematically showing a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 6] FIG. 6 is a diagram schematically showing how a propagation signal is received in a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 7] FIG. 7 is a diagram schematically showing a delay circuit of the semiconductor device according to this embodiment. [Figure 8] FIG. 8 is a diagram showing delay measurement in a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 9] FIG. 9 is a diagram showing delay measurement in a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 10] FIG. 10 is a diagram showing delay measurement in a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 11] FIG. 11 is a diagram showing delay measurement in a signal propagation circuit of the semiconductor device according to this embodiment. [Figure 12]FIG. 12 is a diagram showing delay measurement in the signal propagation circuit of the semiconductor device according to this embodiment. [Figure 13] FIG. 13 is a diagram showing the main steps in the method for manufacturing a semiconductor device and the method for adjusting a semiconductor device according to this embodiment. [Figure 14] FIG. 14 is a block diagram schematically showing exemplary hardware resources of the microcomputer of the manufacturing apparatus according to this embodiment. [Figure 15] FIG. 15 is a block diagram showing modules for a test device according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, the same parts will be designated by the same reference numerals and duplicated descriptions will be omitted.

[0015] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment.

[0016] The semiconductor device 13 may be in the form of a semiconductor chip CHP, or may be in the form of an assembly in which the semiconductor chip CHP is housed in a package PKG. The semiconductor device 13 may be in the form of a substrate to which a wafer process in a previous step has been applied.

[0017] FIG. 2 is a diagram schematically showing a manufacturing apparatus and a semiconductor device according to this embodiment.

[0018] The manufacturing apparatus 12 includes a connection device 14 (for example, a connector or a probe card) configured to be connected to the semiconductor device 13 so as to enable bidirectional communication, and a test device 16 connected to the connection device 14.

[0019] 1 and 2, the semiconductor device 13 will be described. The semiconductor device 13 includes a signal generation circuit 21, a signal propagation circuit 23, and an input / output circuit 25. The signal propagation circuit 23 is connected to the signal generation circuit 21, and the input / output circuit 25 is connected to the signal generation circuit 21 and the signal propagation circuit 23.

[0020] The semiconductor device 13 may include a plurality of electrodes 10 such as pad electrodes. The test device 16 is placed outside the semiconductor device 13.

[0021] The signal generating circuit 21 includes a signal input 21b, a delay circuit 27, and a signal output 21c.

[0022] The delay circuit 27 includes a signal input 21b and a signal output 21c, where the signal input 21b is configured to receive a control signal for controlling a controlled object. The signal output 21c provides a highly accurate control signal. Specifically, the delay circuit 27 can be configured to generate delay signals SDRY having multiple, trimmable delay times different from one another from the base signal SCNT of the signal input 21b. The delay circuit 27 is configured to receive the base signal SCNT at the input 27b and to provide a control signal SDCNT at the delay output 27c. The delay circuit 27 provides a highly accurate control signal at the delay output 27c.

[0023] FIG. 3 is a diagram schematically showing a control device according to this embodiment.

[0024] The control device 11 includes a semiconductor device 13 and an external device 18 controlled by the semiconductor device 13. The exemplary external device 18 is configured to be controlled by the semiconductor device 13 using a pulse width modulation method. The external device 18 can employ various modulation methods as the pulse width modulation method.

[0025] 1, 2, and 3, the exemplary semiconductor device 13 may further include a basic signal generating circuit such as a PWM control circuit 41, and may further include an external driving circuit such as a PWM driving circuit 43. The PWM control circuit 41 is connected to the signal input 21b of the signal generating circuit 21 and the signal input 23b of the signal propagation circuit 23. The basic signal generating circuit, for example, the PWM control circuit 41, generates a basic signal SCNT, for example, a PWM basic signal SPWMB, configured to control the external device 18 according to a driving method of the external device 18 as a controlled object.

[0026] The PWM basic signal SPWMB is provided to a signal generating circuit 21. The signal generating circuit 21 generates a high-resolution PWM signal SPWMH using a delay circuit 27 capable of generating a delay signal having a trimmable delay time. The high-resolution PWM signal SPWMH is provided to a PWM driving circuit 43, which generates a PWM driving signal SPWM. The PWM driving signal SPWM is provided to an external device 18 as a control target via an electrode 10 (10b) such as a pad electrode. An exemplary external device 18 can be controlled using the PWM driving method.

[0027] 1 and 2, the trimming of the delay circuit 27 will be described. The signal propagation circuit 23 and the input / output circuit 25 are used to specify a trimmable delay time of the delay circuit 27. Specifically, the signal propagation circuit 23 enables delay measurement for trimming the delay circuit 27.

[0028] The signal propagation circuit 23 includes a signal input 23b, multiple signal acquisition circuits 29, and one or more outputs 23c. The signal acquisition circuits 29 are connected in series. The signal input 23b is configured to receive a clock signal CLK and a signal different from the clock signal CLK. The output 23c is connected to the input / output circuit 25.

[0029] Specifically, the signal propagation circuit 23 has a series connection 31 of signal acquisition circuits 29, and the series connection 31 may include at least one propagation line 33. The propagation line 33 propagates a signal from the signal input 23b of the signal propagation circuit 23 in a direction from the first stage to the last stage of the series connection 31. Although the drawing depicts a single propagation line 33 within the signal propagation circuit 23, the signal propagation circuit 23 may include additional propagation lines. The additional propagation lines are configured to have the same function as the propagation line 33.

[0030] 1 and 2, the input / output circuit 25 includes one or more signal inputs 25b, an output circuit 35, an input circuit 37, and a trimming output 25c. The signal input 25b is connected to the output 23c of the signal propagation circuit 23. The signal input 25b also receives one or more specific signals SDET associated with the output signal of the signal acquisition circuit 29 (hereinafter referred to as "acquisition signal SLAT") from the output 23c of the signal propagation circuit 23. The specific signals SDET are provided to the output circuit 35 via the signal input 25b of the input / output circuit 25. The output circuit 35 is configured to generate an output signal SOUT to be provided to the outside of the semiconductor device 13 from at least a part of the specific signal SDET.

[0031] The output circuit 35 and the input circuit 37 are connected to the electrodes 10 (10c) of the semiconductor device 13 via conductive lines 40, and are configured to respectively output and input signals to and from outside the semiconductor device 13. The output circuit 35 and the input circuit 37 operate exclusively, and when the output circuit 35 provides an output signal SOUT to the conductive line 40, the input circuit 37 does not accept a signal on the conductive line 40. When the input circuit 37 receives an input signal on the conductive line 40 (for example, a "trimming code signal" described below), the output circuit 35 does not provide the output signal SOUT to the conductive line 40.

[0032] Accordingly, the input circuit 37 is configured to receive a trimming code signal STRM that specifies the trimmable delay time of the delay circuit 27. The output circuit 35 provides an output signal SOUT that is related to the captured value of the signal capture circuit 29 so as to be able to generate the trimming code signal STRM.

[0033] 2, the output signal SOUT is provided to a test device 16 external to the semiconductor device 13. The test device 16 generates a trimming code signal STRM from the output signal SOUT, which specifies the delay time of the delay circuit 27. The trimming code signal STRM can be generated using, for example, a look-up table based on circuit simulation of the signal propagation circuit 23 and the delay circuit 27, and measurements of the semiconductor device 13 can be taken into consideration when creating the look-up table.

[0034] The input circuit 37 receives a trimming code signal STRM specifying a delay time from outside the semiconductor device 13. The input circuit 37 provides the trimming code signal STRM from a trimming output 25c. The trimming output 25c is connected to a trimming input 21d of the signal generating circuit 21.

[0035] The signal generation circuit 21 receives the trimming code signal STRM at a trimming input 21d. The trimming code signal STRM is used to adjust the delay time of the delay circuit 27. Upon receiving the trimming code signal STRM, the signal generation circuit 21 stores the value of the trimming code signal STRM in the adjustment circuit 28. The adjustment circuit 28 includes one or more rewritable nonvolatile storage elements, and exemplary rewritable nonvolatile storage elements include nonvolatile storage elements such as flash memory elements and fuse elements. The adjustment circuit 28 writes the value of the trimming code signal STRM to the nonvolatile storage elements. Furthermore, the delay time of the delay circuit 27 is adjusted based on the value of the trimming code signal STRM in the adjustment circuit 28.

[0036] When a trimming code signal STRM is applied to the signal generation circuit 21, the exemplary signal generation circuit 21 can generate a high-resolution control signal SDCNT, such as a high-resolution PWM signal SPWMH.

[0037] FIG. 4 is a drawing showing the relationship between the propagation signal propagating through the propagation line of the signal propagation circuit of the semiconductor device according to the present embodiment and the signal capture circuit. On the upper side of FIG. 4, a propagation line 33 is shown, and two vertical coincidence chain lines indicate the start point and the end point of the propagation line 33. On the lower side of FIG. 4, a series connection 3__ of the signal capture circuit 29 is shown. Four propagation signals SPGT (SPGTa, SPGTb, SPGTc, SPGTd) are drawn between the propagation line 33 and the series connection 3__. The solid lines of these propagation signals SPGT (SPGTa, SPGTb, SPGTc, SPGTd) respectively show the waveforms of the propagation signal SPGT in the propagation line 33 at times (T1 < T2 < T3 < T4) from top to bottom.

[0038] At time (T1), the propagation signal SPGT (SPGTa) as a reference signal is input to the series connection 3__ of the signal capture circuit 29. At time (T2), the propagation signal SPGT (SPGTb) is propagating through the series connection 3__ of the signal capture circuit 29. At time (T3), while the propagation signal SPGT (SPGTc) is propagating through the series connection 3__ of the signal capture circuit 29, it is captured into the series connection 3__ of the signal capture circuit 29 at the rising edge of the clock signal CLK, for example, like a screenshot. At time (T4), the propagation signal SPGT (SPGTd) continues to propagate through the series connection 3__ of the signal capture circuit 29.

[0039] Note: There seems to be an error in the original text where "series connection 31" is repeatedly written as "series connection 3__" in the translation. It should be corrected according to the actual situation in the original text.Regarding the operation of the signal propagation circuit 23, as shown in part (a) of FIG. 4, the signal input 23b of the signal propagation circuit 23 can receive, for example, a reference signal, which has at least one transition. The reference signal is used to estimate the delay amount per stage of the signal acquisition circuit 29. Specifically, the reference signal is input to the first stage of the signal acquisition circuit 29, and the input reference signal propagates through the propagation line 33 as a propagating signal SPGT, as shown in part (b) of FIG. 4. Each of the signal acquisition circuits 29 acquires the reference signal propagating through the propagation line 33, i.e., the propagating signal SPGT, in response to one of the rising edge and falling edge of the clock signal CLK after the input point, i.e., the rising edge of the exemplary clock signal, as shown in part (c) of FIG. 4. Furthermore, the signal acquisition circuits 29 in the series connection 31 generate a series of acquisition signals SLAT associated with the acquired values ​​of the propagating signal SPGT. As shown in part (d) of FIG. 4, the reference signal continues to propagate in the propagation line 33.

[0040] As can be seen from FIG. 4, the propagation signal SPGT propagating through the propagation line 33 is delayed by accumulating the unit delay of the signal acquisition circuit 29 itself each time it passes through a signal acquisition circuit 29. Therefore, the arrangement of the signal acquisition circuits 29 in the series connection 31 at time T3 shown in FIG. 4(c) is an example of an arrangement of acquired values ​​in a series of acquired signals SLAT. In this arrangement, using a certain number of stages from the first stage of the series connection 31 as a reference (referred to as the "change point PCG"), the signal acquisition circuit 29 in the first half of two adjacent signal acquisition circuits 29 at the change point PCG stores a value that is different from the value stored in the signal acquisition circuit 29 in the second half. In the series connection 31 of signal acquisition circuits 29, the position of the signal acquisition circuit 29 related to this change point is associated with the cumulative delay amount that accumulates each time the signal acquisition circuit 29 passes through one stage. Calculating this cumulative delay amount is referred to as delay measurement. The delay measurement value is useful as an index representing the device characteristics of the semiconductor device 13.

[0041] Accordingly, the value change point PCG in the array of acquired values ​​in the series of acquired signals SLAT is associated with the cumulative delay amount (the cumulative delay amount resulting from the accumulation of delays at each pass through each stage of the signal acquisition circuit 29) that occurs as the transition position of the reference signal propagates through the propagation line 33.

[0042] Considering that the period of one cycle or half cycle of the clock signal CLK used for acquisition is known, the cumulative delay amount associated with the transition of the reference signal is related to the delay amount per stage of the signal acquisition circuit 29. This delay amount indicates the element characteristics of the semiconductor device 13 (for example, the delay characteristics of the signal acquisition circuit 29 of the propagation line 33), and when applied to trimming the delay time of the delay circuit 27, the delay time can be fine-tuned in relation to the element characteristics of the semiconductor device 13.

[0043] Therefore, one example of the usefulness of a measurement that specifies the delay time per stage of the signal acquisition circuit 29, ie, a delay measurement, is that the signal generation circuit 21 can generate a high-resolution control signal.

[0044] Each of the signal acquisition circuits 29 acquires the value of the propagation signal SPGT having a cumulative delay that is the delay up to the individual signal acquisition circuit 29 or the delay up to the preceding signal acquisition circuit 29. In the entire propagation line 33, the signal acquisition circuits 29 acquire the respective values ​​of the propagation signal SPGT in synchronization with, for example, the clock signal CLK.

[0045] The position of the adjacent signal acquisition circuit 29 (the number of stages from the first stage on the propagation line 33) indicated by the transition of the propagation signal SPGT propagated on the propagation line 33 is identified using a series of acquisition signals SLAT from the propagation line 33. The total number of stages of the signal acquisition circuits 29 on the propagation line 33 is known.

[0046] The exemplary signal propagation circuit 23 can generate a characteristic signal SDET associated with a series of unidirectional or reverse transitions of the propagation signal SPGT based on all or at least a portion of the signal acquisition circuit 29 of the propagation line 33. The characteristic signal SDET is provided to the input / output circuit 25.

[0047] The exemplary specific signal SDET is provided as an output signal SOUT to the test device 16 via the input / output circuit 25. The test device 16 (see FIG. 2) can estimate the delay time per stage of the signal acquisition circuit 29 in the semiconductor device 13.

[0048] Estimating the delay per stage of the signal acquiring circuit 29 makes it possible to estimate the delay time of the delay circuit 27 of the signal generating circuit 21. According to the delay time estimation of the delay circuit 27, it is possible to specify a trimming code for the delay circuit 27 so as to bring the delay time of the delay circuit 27 closer to a desired value.

[0049] The test device 16 can receive the output signal SOUT from the semiconductor device 13 via the connection device 14 and the electrode 10 (10b). The test device 16 can generate a trimming code signal STRM based on the output signal SOUT.

[0050] Referring again to Figures 1 and 2, the semiconductor device 13 may further include a control circuit 45, which is configured to generate control signals that control the signal generation circuit 21, the signal propagation circuit 23, and the input / output circuit 25.

[0051] As shown in FIG. 2, the semiconductor device 13 can be connected to a test device 16, for example, at the electrodes 10 (10c).

[0052] The exemplary control circuit 45 can be connected to the test device 16 via the input / output circuit 25, thereby enabling bidirectional communication with the test device 16. The control circuit 45 can receive requests from the test device 16 via the input / output circuit 25, and can also send requests to the test device 16 via the input / output circuit 25. Both of these communications enable control in the semiconductor device 13 related to the transmission of the output signal SOUT and the reception of the trimming code signal STRM, which will be described subsequently. Alternatively, both communications can be performed using a communication port (e.g., a serial port) separate from the electrode 10 (10c).

[0053] The test device 16 is configured so as to be connectable to the input / output 25d of the input / output circuit 25 via the connection device 14 and the electrode 10 (10c).

[0054] In response to control by the control circuit 45, the input / output circuit 25 provides the output signal SOUT via the output circuit 35 to the outside of the semiconductor device 13, for example, to the test device 16. The test device 16 can identify the trimming code signal STRM based on the output signal SOUT generated from the propagation of the reference signal. The semiconductor device 13 can generate a identification signal SDET associated with the capture signal SLAT from at least a part of the capture signal SLAT and provide the identification signal SDET to the test device 16.

[0055] In response to control from the control circuit 45, the signal generation circuit 21 can be configured to provide a reference signal to the signal propagation circuit. The signal propagation circuit 23 is configured to generate a propagation signal SPGT from the reference signal. In response to the propagation of the reference signal, the signal propagation circuit 23 generates a series of acquisition signals SLAT and provides an acquisition signal SLAT related to the acquisition signal SLAT to the input / output circuit 25.

[0056] In response to control by the control circuit 45, the input / output circuit 25 provides the output signal SOUT via the output circuit 35 to an external device of the semiconductor device 13, such as a test device 16. The test device 16 can identify the trimming code signal STRM based on the output signal SOUT generated from the reference signal. The test device 16 provides the trimming code signal STRM to the input / output circuit 25.

[0057] 1 and 2, the input / output circuit 25 may further include a shift register 49, which is connected to the electrode 10 (10b) via at least one of the output circuit 35 and the input circuit 37. The exemplary shift register 49 may also receive a specific signal SDET from the output 23c of the signal propagation circuit 23, and may also provide a trimming code signal STRM to the adjustment circuit 28. The shift register 49 is controlled by the control circuit 45.

[0058] The signal propagation circuit 23 further includes a conversion circuit 47. The conversion circuit 47 is configured to convert at least a portion of the one-dimensional array of the series of acquired signals SLAT from the output of the signal acquisition circuit 29 into a signal of another format, for example, a binary format signal.

[0059] The conversion circuit 47 converts this one-dimensional array into another format, for example, a binary signal. The binary signal is stored in the shift register 49 when it is provided from the signal propagation circuit 23 to the output circuit 35 of the input / output circuit 25. The shift register 49 stores, for example, the output signal SOUT and is used for serial transfer via the electrode 10 (10b). The shift register 49 can also receive the trimming code signal STRM from the test device 16 via the input circuit 37 of the input / output circuit 25.

[0060] In the signal propagation circuit 23, the number of signal acquisition circuits 29 connected in series can be set so that the total delay time of the signal acquisition circuits 29 on the propagation line 33 is greater than one period or half period of the clock signal CLK.

[0061] As can be seen from the above description, a series of acquisition signals SLAT are provided from the parallel-connected signal propagation circuits 23. In the exemplary signal propagation circuits 23, the parallel outputs from the serially connected signal acquisition circuits 29 form a bit string equal to the number of signal propagation circuits 23 (e.g., 128 or 256). The exemplary bit string is a one-dimensional array including a series of "0"s followed by a series of "1"s.

[0062] When the number of stages of the exemplary series connection 31 is 128, for example, the first to sixth signal acquisition circuits 29 of the propagation line 33 indicate a logic value [H], and the seventh to 128th signal acquisition circuits 29 indicate a logic value [L]. To represent the number of bits of the logic value [H] or the logic value [L] in binary format, for example, a 7-bit register is required.

[0063] The signal propagation circuit 23 can include a clock adjustment circuit 42, which provides the clock signal CLK and the inverted signal of the clock signal CLK required for the signal acquisition circuit 29 to acquire the propagation signal SPGT.

[0064] The signal propagation circuit 23 may include a signal switching circuit 44. The exemplary signal switching circuit 44 receives a base signal SCNT, such as a PWM base signal SPWMB, a control signal SDCNT, such as a high-resolution PWM signal SPWMH, and other signals, and provides any of these signals to the propagation line 33.

[0065] 1 and 2, the semiconductor device 13 may include a microcomputer 46. The exemplary microcomputer 46 may include a processor 46b, a memory 46c, and a clock generation circuit 46d, and may be connected to a control signal generation circuit such as the PWM control circuit 41. The clock generation circuit 46d generates a clock signal CLK.

[0066] 5 is a diagram schematically illustrating a signal propagation circuit of the semiconductor device according to this embodiment. An exemplary signal acquisition circuit 29 may include a gate circuit 51 and a data retention circuit 53.

[0067] The gate circuits 51 are connected in series to form the propagation line 33. In each of the signal acquisition circuits 29, a data retention circuit 53 is connected at the data input D to one of the input and output of the gate circuit 51, and an exemplary data retention circuit 53 can be connected to the output of the gate circuit 51, for example.

[0068] The data retention circuit 53 receives the clock signal CLK at a clock input CK and captures the value of the propagation signal SPGT on the propagation line 33 in response to one of a rising edge and a falling edge, for example the rising edge, of the clock signal CLK. The data retention circuit 53 receives a reset signal SRST at a reset input R. The data retention circuit 53 provides a capture signal SLAT at a data output Q.

[0069] Each of the exemplary gate circuits 51 may include an even number or odd number of stages of inversion logic circuits (e.g., inverters). Each of the exemplary data retention circuits 53 may include one or more flip-flop circuits or latch circuits.

[0070] FIG. 6 is a diagram schematically illustrating the waveform of a propagation signal in a series connection of signal propagation circuits in a semiconductor device according to this embodiment. FIG. 6 includes a circuit CIRCUIT6 and a graph GRAPH6. The circuit CIRCUIT6 illustrates three exemplary signal acquisition circuits 29. The graph GRAPH6 illustrates the waveform change of the propagation signal SPGT in the propagation line 33. The horizontal axis indicates the coordinate in the arrangement of the signal acquisition circuits 29 arranged from the first stage to the last stage of the series connection 31. The vertical axis indicates the time evolution of the propagation signal SPGT in the propagation line 33 from top to bottom of GRAPH6.

[0071] The exemplary signal propagation circuit 23 receives a base signal SCNT having a single transition TG at the first stage of the signal acquisition circuit 29 on the propagation line 33 as a reference signal for delay measurement. Propagation signals SPGT1, SPGT2, and SPGT3 indicate waveforms on the propagation line 33 at respective times. In this sense, the horizontal axis of graph GRAPH6 indicates the positions of the signal acquisition circuits 29a (29), 29b (29), and 29c (29) along the direction of the propagation line 33. In terms of time, moving from bottom to top of the vertical axis indicates the past.

[0072] Referring to the circuit CIRCUIT6, for example, at the rising edge TLAT of the clock signal CLK, the signal acquisition circuits 29a (29), 29b (29), and 29c (29) acquire acquisition signals (SLAT1, SLAT2, and SLAT3) from the propagation line 33, respectively.

[0073] FIG. 7 is a diagram schematically showing a delay circuit of the semiconductor device according to this embodiment.

[0074] The delay circuit 27 may include a plurality of delay stages 55. The delay time of the gate circuit 51 of the signal acquisition circuit 29 is shorter than the delay time of the delay stages 55. Furthermore, the delay time of each of the delay stages 55 is shorter than the time of a half cycle of the clock signal CLK.

[0075] In the delay circuit 27, some of the delay stages 55 are connected in series. At least some of the delay stages 55 are connected to an adjustment circuit 28 that stores the value of the trimming code signal STRM and are trimmable.

[0076] The delay circuit 27 includes a plurality of delay lines 30 (30a, 30b, 30c, 30d), each having a different number of delay stages 55. Accordingly, the delay lines 30 provide different delay times.

[0077] The exemplary delay line 30 (30a, 30b, 30c, 30d) receives a base signal SCNT, such as a PWM base signal SPWMB, from the signal input 21b.

[0078] Each of the delay stages 55 has one or more resistors and one or more capacitors connected to generate a delay time in each of the delay stages 55. In each of the delay stages 55, at least one of the resistor and the capacitor can be adjusted by a trimming code stored in the adjustment circuit 28.

[0079] The delay circuit 27 further includes a selector 57 configured to receive signals from the delay lines 30 (30a, 30b, 30c, 30d) and the no-delay line 30e, which is connected to the signal input 21b.

[0080] For example, the delay line 30 (30a) includes a series connection of four delay stages 55, and each of the outputs (tap outputs) of the delay stages 55 is connected to a selector 57. Accordingly, the exemplary selector 57 has eight inputs. The inputs of the selector 57 are selected in response to a selection signal SSEL from the control circuit 45, as shown in FIGS. 1 and 3. The signal generating circuit 21 receives the selection signal SSEL at a selection input 21f.

[0081] As can be understood from the above description, delay measurement makes it possible to estimate the delay amount of the series connection 31 of the signal acquisition circuits 29 in the signal propagation circuit 23, for example, the delay amount per stage. Various delay measurements in the signal propagation circuit 23 of the semiconductor device, specifically, exemplary delay measurements 1 to 6, will be described. The total delay time from the first stage to the last stage of the series connection of the signal acquisition circuits 29 is specified to be greater than the time of one cycle of the clock signal CLK. In response to control from the control circuit 45, the signal propagation circuit 23 can provide a reference signal for delay measurement in the signal propagation circuit 23 to the propagation line 33.

[0082] (Delay measurement 1) 8 is a diagram showing an exemplary delay measurement in a signal propagation circuit of a semiconductor device according to this embodiment. In FIG. 8, the horizontal axis represents the time course showing the waveform change of the propagation signal SPGT in each signal acquisition circuit 29. The vertical axis represents the time evolution of the propagation signal SPGT in the propagation line 33. "R", "H", and "L" in the series connection 31 of the propagation line 33 represent a reset value, a logic value [H], and a logic value [L], respectively.

[0083] 6, the exemplary signal propagation circuit 23 includes a series connection 31 of exemplary signal acquisition circuits 29 in response to control by the control circuit 45. The first stage of the signal acquisition circuit 29 in the propagation line 33 receives the signal SG0 as a reference signal. The signal SG0 propagates through the propagation line 33 and, over time, has a waveform similar to that of the propagation signals SPGT4, SPGT5, and SPGT6 within the propagation line 33.

[0084] At each edge of the clock signal CLK, each of the signal acquisition circuits 29 of the series connection 31 acquires the acquisition signal SLAT from the propagation line 33 .

[0085] At the first edge TLAT1 of the clock signal CLK, the signal acquisition circuit 29 of the series connection 31 acquires the waveform of the propagation signal SPGT5. The series of acquired values ​​indicates the switching position (first transition point PCG1) from the acquired value [L] to the acquired value [H].

[0086] At the second edge TLAT2 of the clock signal CLK, the signal acquisition circuit 29 of the series connection 31 acquires the waveform of the propagation signal SPGT6. The series of acquired values ​​indicates the switching position (second transition point PCG2) from the acquired value [L] to the acquired value [H].

[0087] The time interval between the first edge TLAT1 and the second edge TLAT2 of the clock signal CLK is one cycle of the clock signal CLK. Furthermore, the number of stages of the signal acquisition circuit 29 between the first transition point PCG1 and the second transition point PCG2 can be determined based on the series of first acquired values ​​and the series of second acquired values. These delay measurements make it possible to estimate the delay amount of the signal acquisition circuit 29. Furthermore, the delay amount per stage of the signal acquisition circuit 29 can be estimated from the delay measurement values.

[0088] (Delay measurement 2) 9 is a diagram illustrating a delay measurement in a signal propagation circuit of a semiconductor device according to this embodiment. The reference signal may include a first signal SG1 and a second signal SG2. In delay measurement 2, the first signal SG1 and the second signal SG2 may have substantially the same waveform.

[0089] In response to control by the control circuit 45, the signal propagation circuit 23 receives the first signal SG1 as the reference signal from, for example, the signal generation circuit 21. The signal propagation circuit 23 generates a propagation signal SPGT7 from the first signal SG1. The signal acquisition circuit 29 in the propagation line 33 acquires the propagation signal SPGT8 in synchronization with the rising edge TLATR of the clock signal CLK, and the series of acquired values ​​indicates the switching position (first transition point PCG1) from the acquired value [L] to the acquired value [H].

[0090] Furthermore, after capturing the propagation signal SPGT8, the signal propagation circuit 23 receives the second signal SG2 as the reference signal from, for example, the signal generation circuit 21 in response to control by the control circuit 45. The signal propagation circuit 23 generates a propagation signal SPGT9 from the second signal SG2. In synchronization with the falling edge TLATF of the clock signal CLK, the signal propagation circuit 23 captures the propagation signal SPGT10. The series of captured values ​​indicates the switching position (second transition point PCG2) from the captured value [L] to the captured value [H].

[0091] On the propagation line 33, the time interval between the rising edge TLATR and the falling edge TLATF is equal to a half period (or the sum of n periods and a half period) of the clock signal CLK. Furthermore, the number of stages of the signal acquisition circuit 29 between the first transition point PCG1 and the second transition point PCG2 can be determined based on a series of acquired values ​​of the first signal SG1 and a series of acquired values ​​of the second signal SG2. These delay measurements make it possible to estimate the delay of the signal acquisition circuit 29. Furthermore, the delay per stage of the signal acquisition circuit 29 can be estimated from the delay measurement values.

[0092] (Delay measurement 3) FIG. 10 is a diagram showing delay measurement in a signal propagation circuit of the semiconductor device according to this embodiment.

[0093] The propagation lines 33 of the signal generation circuit 21 may include a first propagation line for the series connection 31b and a second propagation line for the series connection 31c. In response to control from the control circuit 45, the signal propagation circuit 23 simultaneously receives the signal SG0 as a reference signal from the series connection 31b of the first propagation line and the series connection 31c of the second propagation line.

[0094] Specifically, the series connection 31b of the first propagation line generates a propagation signal SPGT11 from the signal SG0. The signal acquisition circuit 29 in the first propagation line acquires the propagation signal SPGT12 in synchronization with the rising edge TLATb of the clock signal CLK.

[0095] Furthermore, the series connection 31c of the second propagation line generates a propagation signal SPGT13 from the signal SG0. The signal capturing circuit 29 in the second propagation line captures the propagation signal SPGT14 in synchronization with the falling edge TLATc of the clock signal CLK.

[0096] In the first propagation line and the second propagation line, the time difference between the rising edge TLATb and the falling edge TLATc is equal to a half period (or the sum of n periods and a half period) of the clock signal CLK. Furthermore, the number of stages of the signal acquisition circuit 29 between the first transition point PCG1 and the second transition point PCG2 can be determined based on the respective series of acquired values ​​of the two signals SG0. These delay measurements make it possible to estimate the delay amount of the signal acquisition circuit 29. Furthermore, the delay amount per stage of the signal acquisition circuit 29 can be estimated from the measured delay measurements.

[0097] (Delay measurement 4) 11 is a diagram illustrating delay measurement in a signal propagation circuit of a semiconductor device according to this embodiment. The reference signal may include a first signal SG1 and a third signal SG3. The third signal SG3 may have an inverted waveform of the first signal SG1.

[0098] In response to control by the control circuit 45, the signal propagation circuit 23 receives the first signal SG1 from the signal generation circuit 21 as the reference signal. The signal propagation circuit 23 generates a propagation signal SPGT15 from the first signal SG1. The signal acquisition circuit 29 in the propagation line 33 acquires the propagation signal SPGT16 in synchronization with the rising edge TLATR of the clock signal CLK, and the series of acquired values ​​indicates the switching position (first transition point PCG1) from the acquired value [L] to the acquired value [H].

[0099] Furthermore, after capturing the propagation signal SPGT16, the signal propagation circuit 23 receives the third signal SG3 as a reference signal from the signal generation circuit 21 in response to control by the control circuit 45. The signal propagation circuit 23 generates a propagation signal SPGT17 from the third signal SG3. In synchronization with the falling edge TLATF of the clock signal CLK, the signal propagation circuit 23 captures the propagation signal SPGT18. The series of captured values ​​represents the switching position (second transition point PCG2) from the captured value [H] to the captured value [L].

[0100] On the propagation line 33, the time difference between the rising edge TLATR and the falling edge TLATF is equal to half the period of the clock signal CLK. The number of stages of the signal acquisition circuit 29 between the first transition point PCG1 and the second transition point PCG2 can be determined based on a series of acquired values ​​of the first signal SG1 and a series of acquired values ​​of the third signal SG3, and can be estimated, for example, as the number of consecutive identical acquired values. These delay measurements make it possible to estimate the delay per stage of the signal acquisition circuit 29. The delay per stage of the signal acquisition circuit 29 can also be estimated from the delay measurement values. (Delay measurement 5) FIG. 12 is a diagram showing delay measurement in the signal propagation circuit of the semiconductor device according to this embodiment.

[0101] The propagation lines 33 of the signal generating circuit 21 may include a first propagation line for the series connection 31b and a second propagation line for the series connection 31c. The reference signals may include a first signal SG1 and a third signal SG3. The third signal SG3 may have an inverted waveform of the first signal SG1. The first signal SG1 and the third signal SG3 may be simultaneously input to the series connection 31b of the first propagation line and the series connection 31c of the second propagation line, respectively.

[0102] In the signal propagation circuit 23, the series connection 31b of the first propagation line receives the first signal SG1 as a reference signal from, for example, the signal generation circuit 21 in response to control of the control circuit 45. The series connection 31b generates a propagation signal SPGT19 from the first signal SG1. At the same time, the series connection 31c of the second propagation line receives the third signal SG3 as a reference signal from, for example, the signal generation circuit 21 in response to control of the control circuit 45. The series connection 31c generates a propagation signal SPGT21 from the third signal SG3.

[0103] The signal acquisition circuit 29 in the series connection 31b acquires the propagation signal SPGT20 in synchronization with the rising edge TLATR of the clock signal CLK, and the series of acquired values ​​indicates the switching position (first transition point PCG1) from the acquired value [L] to the acquired value [H]. Also, the signal acquisition circuit 29 acquires the propagation signal SPGT22 in synchronization with the falling edge TLATF of the clock signal CLK. The series of acquired values ​​indicates the switching position (second transition point PCG2) from the acquired value [H] to the acquired value [L].

[0104] On the propagation line 33, the time difference between the rising edge TLATR and the falling edge TLATF is equal to a half period (or the sum of n periods and a half period) of the clock signal CLK. The number of stages of the signal acquisition circuit 29 between the first transition point PCG1 and the second transition point PCG2 can be determined based on a series of acquired values ​​of the first signal SG1 and a series of acquired values ​​of the third signal SG3, and is estimated, for example, as the number of consecutive identical acquired values. These delay measurements make it possible to estimate the delay of the signal acquisition circuit 29. The delay per stage of the signal acquisition circuit 29 can also be estimated from the delay measurement values.

[0105] (Delay measurement 6) The signal propagation circuit 23 receives a reference signal in response to control from the control circuit 45. An exemplary reference signal may be a signal having a first transition (e.g., a transition from a logic value [L] to [H]) and a second transition (e.g., a transition from a logic value [H] to [L]) with a known interval between the first and second transitions. The propagation line 33 can detect the first and second transitions associated with the first and second transitions, respectively. These delay measurements allow the delay of the signal acquisition circuit 29 to be estimated. Furthermore, the delay per stage of the signal acquisition circuit 29 can be estimated from the delay measurement values.

[0106] Although exemplary delay measurements have been described, delay measurements according to the present invention are not limited to the exemplary delay measurements.

[0107] 13 is a diagram showing the main steps in the method for manufacturing a semiconductor device and the method for adjusting a semiconductor device according to this embodiment. In the following description, where possible, reference numerals already described will be used to avoid redundant description.

[0108] The method 100 includes step ST1. In step ST1, an integrated circuit including a delay circuit and a plurality of signal acquisition circuits is prepared. Preparing the integrated circuit includes, for example, manufacturing the integrated circuit, obtaining the integrated circuit with or without payment, and the like. The integrated circuit can be manufactured using, for example, a CMOS semiconductor process.

[0109] The prepared integrated circuit includes a delay circuit (e.g., delay circuit 27) capable of generating delay signals with multiple delay times that are both trimmable and untrimmed. Multiple signal acquisition circuits (e.g., signal acquisition circuits 29) are connected in series to form a series connection 31. The series connection 31 of the signal acquisition circuits 29 forms at least one propagation line 33 from the first stage to the last stage in the series connection.

[0110] The method 100 includes step ST2, in which at least one reference signal is input to the propagation line 33. The series connection 31 of the signal acquisition circuits 29 generates a propagation signal SPGT on the propagation line 33 in response to the input of the reference signal.

[0111] Method 100 includes step ST3, in which, in response to one of a rising edge and a falling edge of clock signal CLK, series connection 31 of signal acquisition circuits 29 acquires the value of propagation signal SPGT to generate a series of acquisition signals SLAT.

[0112] Method 100 includes step ST4, in which steps ST2 and ST3 may be repeated to generate a series of additional acquisition signals SLAT.

[0113] The method 100 includes step ST5, in which a trimming value for trimming the delay time of the delay circuit 27 is generated based at least in part on the acquired values ​​of the series of acquired signals SLAT and the series of additional acquired signals SLA.

[0114] The method 100 includes step ST6, in which a delay value of the delay circuit 27 is specified using the trimming value, and a semiconductor device 13 including the specified delay circuit 27 is manufactured. Specifying the delay value includes, for example, writing the trimming value to a rewritable nonvolatile memory element.

[0115] In step ST3, the propagation line 33 may include a first propagation line. The value of the propagation signal SPGT is captured on the first propagation line in synchronization with one of the rising edge and the falling edge of the clock signal CLK. The value of the propagation signal SPGT is also captured on the first propagation line in response to the other of the rising edge and the falling edge of the clock signal CLK.

[0116] In step ST3, the propagation line 33 may include a first propagation line and a second propagation line. Capturing the value of the propagation signal SPGT includes performing the capture on the first propagation line in synchronization with one of the rising edge and the falling edge of the clock signal CLK to generate the capture signal SLAT. Capturing the value of the propagation signal SPGT includes performing the capture on the second propagation line in synchronization with the other of the rising edge and the falling edge of the clock signal CLK to generate the capture signal SLAT.

[0117] The method for manufacturing a semiconductor device and the method for adjusting a semiconductor device according to this embodiment can be performed using, for example, a manufacturing apparatus 12. As already described, the manufacturing apparatus 12 includes a connection device 14 configured to be connected to the semiconductor device 13 so as to enable bidirectional communication, and a test device 16 connected to the connection device 14. The input / output circuit 25 of the semiconductor device 13 is configured to be connected to the test device 16 via the electrodes 10 of the semiconductor device 13.

[0118] FIG. 14 is a block diagram that schematically shows exemplary hardware resources of the microcomputer of the manufacturing apparatus 12 according to this embodiment.

[0119] The microcomputer 20 uses hardware resources to generate trimming codes. The exemplary microcomputer 20 may include a processor 141 (central processing unit: CPU), a memory 142 (storage device), an input / output port 143, and a network port 144, and may also include an input device 145, a display 146, and peripheral circuits 148, as needed. The memory 142 is communicatively coupled to the processor 141. The input / output port 143 is communicatively coupled to the processor 141 and receives and transmits data from external sensors. The network port 144 is communicatively coupled to the processor 141 and is connected to an (external) network. The input device 145 is communicatively coupled to the processor 141. The display 146 is communicatively coupled to the processor 141 and the memory 142. Information for identifying the location of the short circuit is stored in the memory 142 or provided from the network via the network port 144. The processor 141 , memory 142 , input / output port 143 , network port 144 , input device 145 and display 146 are connected via a system bus 147 .

[0120] The semiconductor device 13 and the test device 16 can operate in synchronization with a clock signal CLK. The test device 16 includes a processor 141 and a memory 142 coupled to the processor 141. The memory 142 is configured to store program code 140b executable by the processor 141, as well as a look-up table and trimming code signals 140c based on circuit simulation.

[0121] The program code 140b, when executed by the processor 141, causes the processor 141 to process according to the modules subsequently described.

[0122] 15 is a block diagram showing modules for the test device 16 according to the present embodiment. The modules (see 140b in FIG. 13) can be stored in the memory 142 in the form of program code defining instructions. Specifically, the memory 142 is configured to store one or more instructions.

[0123] The instructions, when executed, can be configured to cause the processor (141) to perform the following exemplary operations of a module (140b, see FIG. 13):

[0124] Module MD1: Controlling the signal generation circuit 21 to cause the signal input 23b of the signal propagation circuit 23 to provide at least one reference signal from the signal generation circuit 21.

[0125] The series connection 31 of the signal acquisition circuits 29 is configured to form a propagation line 33 that propagates a signal from the signal input 23b of the signal propagation circuit 23 in the direction from the first stage of the series connection 31 to the last stage.

[0126] Module MD2: Controlling the series connection 31 of the signal acquisition circuits 29 so as to acquire the propagation signal SPGT propagating through the propagation line 33 in synchronization with one of the rising and falling edges of the clock signal CLK.

[0127] Each of the signal acquisition circuits 29 acquires the propagation signal SPGT propagating through the propagation line 33 in synchronization with one of the rising edge and falling edge of the clock signal CLK to generate an acquired value of the propagation signal SPGT. Also, each of the signal acquisition circuits 29 generates one or more acquired signals associated with the acquired value.

[0128] Module MD3: Repeated provision of a reference signal and acquisition of a propagated signal SPGT.

[0129] Module MD4: Controlling the input / output circuit 25 to generate one or more output signals SOUT based on the received signal.

[0130] Module MD5: controlling the input / output circuit 25 to provide the output signal SOUT to the test device 16, and controlling the test device 16 to receive the output signal SOUT from the semiconductor device 13.

[0131] Specifically, in response to the control of the test device 16, the semiconductor device 13 controls the output circuit 35 of the input / output circuit 25 to provide the output signal SOUT to the test device 16 via the output circuit 35 of the input / output circuit 25. The output signal SOUT is generated by the input / output circuit 25 so as to be associated with the capture signal SLAT.

[0132] Module MD6: in the test device 16, controlling the test device 16 to generate one or more trimming code signals STRM based on the output signal SOUT.

[0133] Module MD7: Controlling the test equipment 16 so that the test equipment 16 can provide the trimming code signal STRM to the semiconductor device 13.

[0134] The test device 16 controls the input / output circuit 25 so as to provide the trimming code signal STRM to the input circuit 37 of the input / output circuit 25 for the semiconductor device 13. Furthermore, the semiconductor device 13 controls the input circuit 37 of the input / output circuit 25 in response to the control of the test device 16. The input circuit 37 of the semiconductor device 13 provides the trimming code signal STRM to the signal generating circuit 21.

[0135] In the previously described embodiments, an exemplary semiconductor device includes a signal generating circuit including a delay circuit configured to generate delay signals with different trimmable delay times from an input signal. However, the signal generating circuit is not limited to including a delay circuit, and may include a circuit different from the delay circuit in addition to or instead of the delay circuit. This circuit may include one or more transistors, one or more resistors, and one or more capacitors, as well as one or more switches that enable connection and disconnection between the same and different types of these. The conduction and non-conduction of the switch is determined by a trimming code signal generated using a specific signal based on the delay measurement.

[0136] As described above, according to the present embodiment, it is possible to provide a semiconductor device including a circuit that enables delay measurement for adjusting the delay amount of a delay circuit, a PWM device, a method for manufacturing a semiconductor device, and a program.

[0137] This embodiment can have various aspects as shown below.

[0138] A semiconductor device according to a first aspect of this embodiment is a semiconductor device including a signal generation circuit, a signal propagation circuit connected to the signal generation circuit, and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, wherein the signal generation circuit includes a signal input configured to receive a base signal for controlling a control target, a delay circuit configured to be able to generate delay signals with a plurality of trimmable delay times different from each other from the signal of the signal input, and a signal output for providing a signal from the delay circuit, and the signal propagation circuit includes an input configured to receive a clock signal and a signal different from the clock signal, a plurality of signal acquisition circuits, and one or more outputs connected to the input / output circuit, and the signal acquisition circuits are connected in series to form at least one series connection, and the series connection of the signal acquisition circuits is configured to form a propagation line for propagating a signal from the input of the signal propagation circuit in a direction from the first stage to the last stage of the series connection. the signal propagation circuit is configured such that the signal acquisition circuit of the propagation line acquires a propagation signal propagating through the propagation line in synchronization with one of a rising edge and a falling edge of the clock signal to generate a plurality of acquisition signals for delay measurement on the propagation line, the signal propagation circuit is configured to generate one or more specific signals associated with the acquisition signals, the input / output circuit comprises one or more signal inputs configured to receive the specific signals, an output circuit configured to generate an output signal to be provided to the outside of the semiconductor device from at least a part of the specific signal, an input circuit configured to receive a trimming code signal from the outside of the semiconductor device that is specified based on a result of the delay measurement, and a trimming output configured to provide the trimming code signal, and the signal generation circuit has a trimming input connected to the input / output circuit via the trimming output.

[0139] A semiconductor device according to a second aspect of the first aspect of this embodiment further includes a control circuit, wherein the signal generation circuit is configured to provide a reference signal including at least one transition to the signal propagation circuit in response to control of the control circuit, the signal propagation circuit is configured to generate the propagation signal from the reference signal, the input / output circuit is configured to provide the output signal to the outside of the semiconductor device via the output circuit in response to control of the control circuit, and the trimming code signal can be determined based on the output signal.

[0140] In a semiconductor device according to a third aspect in accordance with the second aspect of this embodiment, the signal propagation circuit is configured to receive a first signal as the reference signal in response to control of the control circuit, and the signal propagation circuit is configured to generate a first capture signal as the capture signal at one of the rising edge and falling edge of the clock signal in response to propagation of the first signal, and to provide a first specific signal generated from the first capture signal to the input / output circuit as the specific signal, and the input / output circuit can be configured to generate a first output signal associated with the first specific signal as the output signal in response to control of the control circuit.

[0141] In a semiconductor device according to a fourth aspect in accordance with the third aspect of this embodiment, the signal propagation circuit is configured to receive a second signal as the reference signal in response to control of the control circuit, the signal propagation circuit is configured to generate a second capture signal as the capture signal at the other of the rising edge and the falling edge of the clock signal in response to propagation of the second signal, and to provide a second specified signal generated from the second capture signal as the specified signal to the input / output circuit, the input / output circuit is configured to generate a second output signal associated with the second specified signal as the output signal in response to control of the control circuit, the input / output circuit is configured to receive the trimming code signal specified based on the first output signal and the second output signal from outside the semiconductor device via the input circuit in response to control of the control circuit, the input / output circuit is configured to receive the trimming code signal from outside the semiconductor device via the input circuit in response to control of the control circuit, and the trimming code signal can be specified based on the first output signal and the second output signal.

[0142] In a semiconductor device according to a fifth aspect in accordance with the second aspect of this embodiment, the series connection of the signal acquisition circuits includes a second propagation line different from the propagation line, and the second propagation line is configured to propagate a signal from the input of the signal propagation circuit in a direction from a first stage to a last stage of the series connection of the second propagation line, each of the signal acquisition circuits of the second propagation line is configured to generate a second acquisition signal at the other of the rising edge and the falling edge of the clock signal and to generate a second specified signal from the second acquisition signal, the input / output circuit is configured to generate a second output signal associated with the second specified signal in response to control of the control circuit, the input / output circuit is configured to provide the second output signal to an external device of the semiconductor device via the output circuit in response to control of the control circuit, and the input / output circuit is configured to receive the trimming code signal from an external device of the semiconductor device via the input circuit in response to control of the control circuit, The trimming code signal can be determined based on the output signal and the second output signal.

[0143] In a semiconductor device according to a sixth aspect in accordance with the first, second, third, fourth, or fifth aspect of this embodiment, the signal propagation circuit may further include a conversion circuit configured to convert a sequence of signals from at least a portion of the output of the signal propagation circuit into a binary format signal, and the conversion circuit may be configured to provide the binary format signal to the output of the signal propagation circuit.

[0144] In a semiconductor device according to a seventh aspect that is in accordance with the first, second, third, fourth, fifth, or sixth aspect of this embodiment, each of the signal acquisition circuits includes a gate circuit and a data retention circuit, and in each of the signal acquisition circuits, the data retention circuit is connected to one of the input and output of the gate circuit, the gate circuits of the signal acquisition circuits are connected in series to form the propagation line, and the data retention circuit can be configured to acquire the value of the propagation signal on the propagation line in response to one of the rising edge and the falling edge of the clock signal.

[0145] In the semiconductor device according to an eighth aspect in accordance with the seventh aspect of this embodiment, each of the data holding circuits can include a flip-flop circuit or a latch circuit.

[0146] In a semiconductor device according to a ninth aspect in accordance with the seventh or eighth aspect of this embodiment, each of the gate circuits may include an even number of stages or an odd number of stages of inversion logic circuits.

[0147] In a semiconductor device according to a tenth aspect in accordance with the seventh, eighth or ninth aspect of this embodiment, the delay circuit may include a plurality of delay stages, and the delay time of the gate circuit may be smaller than the delay time of the delay stages.

[0148] A PWM device according to an eleventh aspect of this embodiment comprises a semiconductor device described in any one of the first to tenth aspects and an external device controlled by the semiconductor device, wherein the semiconductor device further includes a drive circuit configured to generate a PWM drive signal in response to a signal from the signal generation circuit, and the external device is connected to the drive circuit.

[0149] A method for manufacturing a semiconductor device according to a twelfth aspect of this embodiment includes preparing an integrated circuit including a delay circuit configured to be able to generate delay signals having a plurality of delay times that are trimmable and untrimmed and different from each other, and at least one propagation line including signal acquisition circuits connected in series, wherein the at least one propagation line forms an arrangement of the signal acquisition circuits from a first stage to a last stage in the series connection of the signal acquisition circuits; and inputting at least one reference signal to the propagation line, wherein the series connection of the signal acquisition circuits generates a propagation signal on the propagation line in response to the input of the reference signal. inputting a reference signal, acquiring a value of the propagation signal on the propagation line in synchronization with a clock signal in the signal acquisition circuit to generate a plurality of acquisition signals in the signal acquisition circuit, generating a trimming value for trimming the delay time of the delay circuit based on at least a portion of the acquired values ​​of the acquisition signals, specifying a delay value of the delay circuit using the trimming value, and manufacturing a semiconductor device including the delay circuit to which the trimming value has been applied, wherein applying the trimming value includes changing the memory content of a rewritable non-volatile memory element.

[0150] In the method according to the thirteenth aspect in accordance with the twelfth aspect of this embodiment, at least one of the propagation lines includes a first propagation line, and the value of the propagation signal can be captured on the first propagation line in response to one of a rising edge and a falling edge of the clock signal, and the value of the propagation signal can be captured on the first propagation line in response to the other of the rising edge and the falling edge of the clock signal.

[0151] In the method according to the fourteenth aspect in accordance with the twelfth aspect of this embodiment, at least one of the propagation lines may include a first propagation line and a second propagation line, and capturing the value of the propagation signal may occur on the first propagation line in response to one of a rising edge and a falling edge of the clock signal to generate the capture signal, and capturing the value of the propagation signal may occur on the second propagation line in response to the other of the rising edge and the falling edge of the clock signal.

[0152] A fifteenth aspect of the present embodiment provides a program installed in a manufacturing apparatus including a connection device configured to be connected to a semiconductor device so as to be capable of bidirectional communication, and a test device connected to the connection device, wherein the semiconductor device includes a signal generation circuit including a delay circuit configured to generate delay signals having a plurality of trimmable delay times different from each other, a signal propagation circuit connected to the signal generation circuit, and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, the input / output circuit of the semiconductor device is configured to be connected to the test device via electrodes of the semiconductor device, the test device and the semiconductor device are operable in synchronization with a clock signal, the test device includes a processor and a memory coupled to the processor, the memory is configured to store program code executable by the processor, and the program code, when executed by the processor, causes the processor to perform the following processes: controlling the signal propagation circuit to propagate a signal to a signal propagation circuit, the signal propagation circuit including at least one propagation line including signal acquisition circuits connected in series, the at least one propagation line forming an arrangement of the series connection of the signal acquisition circuits from the first stage to the last stage, each of the signal acquisition circuits acquiring a respective propagation signal propagating through the propagation line in response to one or the other of a rising edge and a falling edge of the clock signal to generate an acquired value of the propagation signal, the signal propagation circuit being configured to generate one or more specific signals associated with the acquired value; controlling an output circuit of the input / output circuit to provide one or more output signals generated by the input / output circuit from the semiconductor device to the test device so as to be associated with the specific signal; controlling the test device to receive the output signal; and generating one or more trimming code signals based on the received output signal;and controlling an input circuit of the input / output circuit to provide the trimming code signal from the test device to the semiconductor device, the input circuit controlling the input circuit to provide the trimming code signal to the delay circuit.

[0153] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the present disclosure, all of which are included in the technical concept of the present disclosure. [Explanation of symbols]

[0154] 10...electrode, 11. Control device, 12...manufacturing equipment, 13. Semiconductor device, 14. Connection device, 16···Test equipment, 18...external device, 20. Microcomputer, 21...signal generation circuit, 21b Signal input, 21c···Signal output, 21d...Trimming input, 21f···Selection input, 23···Signal propagation circuit, 23b Signal input, 23c···output, 25... Input / output circuit, 25b···Signal input, 25c···Trimming output, 25d···Input / output, 27... Delay circuit, 27b···input, 27c···Delayed output, 28...adjustment circuit, 29, 29a, 29b, 29c... Signal acquisition circuit, 30··· delay line, 30e···line, 31, 31b, 31c...Series connection, 33···Propagation line, 35...output circuit, 37···Input circuit, 40....conductive line, 41... control circuit, 42... Clock adjustment circuit, 43...Drive circuit, 44... Signal switching circuit, 45....Control circuit, 46. ​​Microcomputer, 46b... processor, 46c···memory, 46d... Clock generation circuit, 47...Conversion circuit, 49...shift register, 51... Gate circuit, 53...Data retention circuit, 55···delay stages, 57···Selector, CLK: Clock signal. MD1~MD7··· modules. PCG1, PCG2, PCG3, PCG4...transition point, PCG···change point, SCNT...Basic signal, SDCNT control signal, SDET...specific signal, SDRY delayed signal, SG0, SG1, SG2, SG3...signal, SLAT....acquired signal, SOUT: Output signal, SPGT, SPGT1 to SPGT22... propagation signal, SPWM drive signal, SPWMB...Basic signal, SPWMH...PWM signal, SRST Reset signal, SSEL: Selection signal, STRM: Trimming code signal, T1~T3...time, TLAT1, TLAT2, TLATF, TLATR, TLATb, TLATc···edge.

Claims

1. A semiconductor device comprising: a signal generation circuit; a signal propagation circuit connected to the signal generation circuit; and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, The signal generating circuit a signal input configured to receive a base signal for controlling a controlled object; a delay circuit configured to be able to generate delay signals with a plurality of delay times that are different from each other and that can be trimmed from the signal of the signal input; a signal output providing a signal from the delay circuit; Equipped with The signal propagation circuit includes: an input configured to receive a clock signal and a signal different from the clock signal; a plurality of signal acquisition circuits; one or more outputs connected to the input / output circuit; Equipped with the signal acquisition circuits are connected in series to form at least one series connection, and the series connection of the signal acquisition circuits is configured to form a propagation line that propagates a signal from the input of the signal propagation circuit in a direction from a first stage to a last stage of the series connection; the signal propagation circuit is configured such that the signal acquisition circuit of the propagation line acquires the propagation signal propagating through the propagation line in synchronization with one of a rising edge and a falling edge of the clock signal to generate a plurality of acquisition signals for delay measurement in the propagation line; the signal propagation circuitry is configured to generate one or more specific signals associated with the captured signal; The input / output circuit includes: one or more signal inputs configured to receive the particular signal; an output circuit configured to generate an output signal to be provided to an external device from at least a part of the specific signal; an input circuit configured to receive a trimming code signal specified based on the result of the delay measurement from outside the semiconductor device; a trimming output configured to provide the trimming code signal; Equipped with the signal generating circuit has a trimming input connected to the input / output circuit via the trimming output; Semiconductor device.

2. Further comprising a control circuit; the signal generating circuit is configured to provide a reference signal including at least one transition to the signal propagating circuit in response to control of the control circuit; the signal propagation circuit is configured to generate the propagation signal from the reference signal; the input / output circuit is configured to provide the output signal to an external device via the output circuit in response to control by the control circuit; The trimming code signal is determined based on the output signal.

2. The semiconductor device according to claim 1.

3. the signal propagation circuit is configured to receive a first signal as the reference signal in response to control by the control circuit; the signal propagation circuit is configured to generate a first capture signal as the capture signal at one of a rising edge and a falling edge of the clock signal in response to propagation of the first signal, and to provide a first specified signal generated from the first capture signal as the specified signal to the input / output circuit; the input / output circuit is configured to generate, as the output signal, a first output signal associated with the first particular signal in response to control by the control circuit; 3. The semiconductor device according to claim 2.

4. the signal propagation circuit is configured to receive a second signal as the reference signal in response to control by the control circuit; the signal propagation circuit is configured to generate a second capture signal as the capture signal at the other of the rising edge and the falling edge of the clock signal in response to propagation of the second signal, and to provide a second specified signal generated from the second capture signal as the specified signal to the input / output circuit; the input / output circuit is configured to generate, as the output signal, a second output signal associated with the second particular signal in response to control by the control circuit; the input / output circuit is configured to receive the trimming code signal specified based on the first output signal and the second output signal from outside the semiconductor device via the input circuit in response to control by the control circuit; the input / output circuit is configured to receive the trimming code signal from outside the semiconductor device via the input circuit in response to control by the control circuit; the trimming code signal is determined based on the first output signal and the second output signal.

4. The semiconductor device according to claim 3.

5. the series connection of the signal acquisition circuit includes a second propagation line different from the propagation line, and the second propagation line is configured to propagate a signal from the input of the signal propagation circuit in a direction from a first stage to a last stage of the series connection of the second propagation line; each of the signal acquisition circuits of the second propagation line is configured to generate a second acquisition signal at the other of the rising edge and the falling edge of the clock signal and to generate a second specified signal from the second acquisition signal; the input / output circuit is configured to generate a second output signal associated with the second specific signal in response to control by the control circuit; the input / output circuit is configured to provide the second output signal to an external device via the output circuit in response to control by the control circuit; the input / output circuit is configured to receive the trimming code signal from outside the semiconductor device via the input circuit in response to control by the control circuit; the trimming code signal is determined based on the output signal and the second output signal; 3. The semiconductor device according to claim 2.

6. the signal propagation circuit further includes a conversion circuit configured to convert a stream of signals from at least a portion of the outputs of the signal propagation circuit into a binary format signal; the conversion circuit is configured to provide the binary format signal to the output of the signal propagation circuit; 2. The semiconductor device according to claim 1.

7. each of the signal acquisition circuits includes a gate circuit and a data retention circuit; In each of the signal acquisition circuits, the data retention circuit is connected to one of the input and output of the gate circuit; the gate circuits of the signal acquisition circuit are connected in series to form the propagation line; the data retention circuit is configured to capture the value of the propagation signal on the propagation line in response to one of the rising edge and the falling edge of the clock signal.

2. The semiconductor device according to claim 1.

8. Each of the data retention circuits includes a flip-flop circuit or a latch circuit.

8. The semiconductor device according to claim 7.

9. Each of the gate circuits includes an even number of stages or an odd number of stages of inversion logic circuits.

8. The semiconductor device according to claim 7.

10. the delay circuit includes a plurality of delay stages; The delay time of the gate circuit is smaller than the delay time of the delay stage.

8. The semiconductor device according to claim 7.

11. A semiconductor device according to any one of claims 1 to 10; an external device controlled by the semiconductor device; Equipped with the semiconductor device further includes a drive circuit configured to generate a PWM drive signal in response to a signal from the signal generation circuit; the external device is connected to the drive circuit; PWM device.

12. An integrated circuit is provided, the integrated circuit including a delay circuit configured to be able to generate delay signals having a plurality of delay times that are trimmable and untrimmed, and at least one propagation line including signal acquisition circuits connected in series, the at least one propagation line forming an arrangement of the signal acquisition circuits from the first stage to the last stage in the series connection of the signal acquisition circuits; inputting at least one reference signal into the propagation line, the series connection of the signal acquisition circuits generating a propagation signal into the propagation line in response to inputting the reference signal; acquiring the value of the propagation signal on the propagation line in the signal acquisition circuit in synchronization with a clock signal, thereby generating a plurality of acquisition signals in the signal acquisition circuit; generating a trimming value for trimming the delay time of the delay circuit based on at least a portion of the acquired value of the acquired signal; Specifying a delay value of the delay circuit using the trimming value, and manufacturing a semiconductor device including the delay circuit to which the trimming value is applied, wherein applying the trimming value includes changing the memory content of a rewritable nonvolatile memory element; Equipped with A method for manufacturing a semiconductor device.

13. the at least one transmission line includes a first transmission line; the value of the propagating signal is captured on the first propagation line in response to one of a rising edge and a falling edge of the clock signal; the value of the propagation signal is captured on the first propagation line in response to the other of the rising edge and the falling edge of the clock signal; 13. The method for manufacturing a semiconductor device according to claim 12.

14. the at least one transmission line includes a first transmission line and a second transmission line; the value of the propagating signal is captured on the first propagation line in response to one of a rising edge and a falling edge of the clock signal; the value of the propagation signal is captured on the second propagation line in response to the other of the rising edge and the falling edge of the clock signal; 13. The method for manufacturing a semiconductor device according to claim 12.

15. A program to be installed in a manufacturing device including a connection device configured to be connected to a semiconductor device so as to be able to communicate bidirectionally with the semiconductor device, and a test device connected to the connection device, The semiconductor device includes a signal generation circuit including a delay circuit configured to generate delay signals having a plurality of trimmable delay times different from one another, a signal propagation circuit connected to the signal generation circuit, and an input / output circuit connected to the signal generation circuit and the signal propagation circuit, the input / output circuit of the semiconductor device is configured to be connected to the test device via an electrode of the semiconductor device; the test device and the semiconductor device are operable in synchronization with a clock signal; the test device includes a processor and a memory coupled to the processor; the memory is configured to store program code executable by the processor; The program code, when executed by the processor, causes the processor to perform the following processes: controlling the signal propagation circuit to propagate at least one reference signal to the signal propagation circuit, the signal propagation circuit including at least one propagation line including signal acquisition circuits connected in series, the at least one propagation line forming an arrangement of the signal acquisition circuits from the first stage to the last stage in the series connection, each of the signal acquisition circuits acquiring a respective propagation signal propagating on the propagation line in response to one or other of a rising edge and a falling edge of the clock signal to generate an acquired value of the propagation signal, the signal propagation circuit being configured to generate one or more specific signals associated with the acquired value; controlling an output circuit of the input / output circuit to provide, from the semiconductor device to the test device, one or more output signals generated by the input / output circuit so as to be associated with the particular signal; controlling the test device to receive the output signal; generating one or more trimming code signals based on the received output signals; controlling an input circuit of the input / output circuit so that the trimming code signal can be provided from the test device to the semiconductor device, the input circuit providing the trimming code signal to the delay circuit; configured to cause program.

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