Hub chiplet and hub chiplet package

Abstract

To disclose a hub chiplet and a hub chiplet package.SOLUTION: A hub chiplet can install a functional module. The hub chiplet includes: a top connection module formed on a cross-section of the hub chiplet in a first direction; a bottom connection module formed on a cross-section of the hub chiplet in a second direction opposite to the first direction; a left connection module formed on a cross-section of the hub chiplet in a third direction perpendicular to a first straight line connecting the top connection module to the bottom connection module; and a right connection module formed on a cross-section of the hub chiplet in a fourth direction that is perpendicular to the first straight line and is opposite to the third direction. The top connection module is connectable to the bottom connection module through a device-to-device (D2D) connection, and the left connection module is connectable to the right connection module through the D2D connection.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a hub chiplet and a hub chiplet package, and more particularly to a hub chiplet using a chiplet structure and a hub chiplet package including the hub chiplet. [Background technology]

[0002] Over the past few years, artificial intelligence (AI) technology has been considered one of the most promising technologies worldwide, as it is a core technology of the Fourth Industrial Revolution. However, the biggest problem with AI technology is computing performance. For AI technology to realize human learning, reasoning, perception, natural language understanding and generation capabilities, the most important thing is to process large amounts of data quickly.

[0003] The semiconductor industry has developed in the direction of reducing power consumption by achieving smaller chips and higher integration through the reduction of line width. However, the reduction of line width is reaching its physical limit, and the difficulty of the semiconductor manufacturing process is rapidly increasing. In addition, the distance between circuits is getting closer, which is causing various problems, such as reduced yields due to leakage current.

[0004] As a result, semiconductor manufacturers are turning their attention to chiplets, a post-process packaging technology that integrates multiple chips to reduce costs. Chiplets are a technology that combines sub-modules with multiple functions to create a single chip (or system-on-chip). Although each sub-module only functions as a material that does not function independently, it differs from conventional chip (or system-on-chip) structures in that it offers a high degree of freedom in expansion and combination. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Publication No. 10-2023-0038082 Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION An object of the present invention is to provide a hub chiplet with a freely expandable chiplet structure.

[0007] Another object of the present invention is to provide a hub chiplet package with a freely expandable chiplet structure.

[0008] The objects of the present invention are not limited to the objects mentioned above, and other unmentioned objects and advantages of the present invention will be understood from the following description and will become more clearly understood by the embodiments of the present invention. Furthermore, it will be easily understood that the objects and advantages of the present invention can be realized by the means recited in the claims and combinations thereof. [Means for solving the problem]

[0009] A hub chiplet according to some embodiments of the present invention for solving the above problem is a hub chiplet capable of mounting a functional module, the hub chiplet including a top connection module formed on a cross section of the hub chiplet in a first direction, a bottom connection module formed on a cross section of the hub chiplet in a second direction opposite to the first direction, a left connection module formed on a cross section of the hub chiplet in a third direction perpendicular to a first line connecting the top connection module and the bottom connection module of the hub chiplet, and a right connection module formed on a cross section of the hub chiplet in a fourth direction perpendicular to the first line and opposite to the third direction, wherein the top connection module is capable of D2D (Device-to-Device) connection with the bottom connection module, and the left connection module is capable of D2D connection with the right connection module.

[0010] In addition, the light connection module may be coupled to the light connection module in a state in which the first direction and the second direction are reversed.

[0011] Also, the left connection module may be coupled to the left connection module in a state in which the first direction and the second direction are reversed.

[0012] Furthermore, the top connection module may be coupled to the top connection module in a state in which the third direction and the fourth direction are reversed.

[0013] In addition, the bottom connection module may be coupled to the bottom connection module in a state where the third direction and the fourth direction are reversed.

[0014] Also, the functional module may be at least one of a processor, a memory controller, a D2D interface, a resource scheduler, a security engine, a debug interface, and a peripheral logic circuit.

[0015] Additionally, the top connection module, the bottom connection module, the left connection module, and the right connection module may each be coupled to a custom logic die that operates similarly to the hub chiplet.

[0016] To solve the other problems, a hub chiplet package according to some embodiments of the present invention includes a first hub chiplet and a second hub chiplet having the same shape and coupled to each other by D2D, a first custom logic die coupled to the first hub chiplet by D2D, and a second custom logic die coupled to the second hub chiplet by D2D, and the first and second hub chiplets and the first and second custom logic dies can drive system on chip (SoC) operation.

[0017] Additionally, the first hub chiplet may include a first processor and a first memory controller, and the first custom logic die may include a first memory controlled by the first memory controller.

[0018] Additionally, the second hub chiplet may include a second processor and a second memory controller, and the second custom logic die may include a second memory controlled by the second memory controller. [Effects of the Invention]

[0019] The hub chiplet and hub chiplet package of the present invention are freely expandable due to the chiplet structure.

[0020] Furthermore, the goal can be achieved by combining hub chiplets without developing new system-on-chip devices to scale up.

[0021] In addition to the above, specific effects of the present invention will be described below together with specific matters for carrying out the invention. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a conceptual diagram illustrating a hub chiplet according to some embodiments of the present invention. [Figure 2] 2 is a diagram for explaining a D2D interface of the hub chiplet of FIG. 1. [Figure 3] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 4] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 5] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 6] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 7] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 8] 1 is a diagram illustrating a D2D connection type of a hub chiplet according to some embodiments of the present invention. FIG. [Figure 9] 1A-1C are diagrams illustrating packaging types for hub chiplets according to some embodiments of the present invention. [Figure 10] 1A-1C are diagrams illustrating packaging types for hub chiplets according to some embodiments of the present invention. [Figure 11]1A-1C are diagrams illustrating packaging types for hub chiplets according to some embodiments of the present invention. [Figure 12] 1A-1C are diagrams illustrating a method for manufacturing a hub chiplet package according to some embodiments of the present invention. [Figure 13] 1A-1C are diagrams illustrating methods for scaling up hub chiplet packages according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The terms and phrases used in this specification and claims should not be interpreted as being limited to their general or dictionary meanings. They should be interpreted based on the meanings and concepts that are consistent with the technical idea of ​​the present invention, based on the principle that the inventor can define the concepts of the terms and phrases in order to best describe his or her invention. Furthermore, the embodiments described in this specification and the configurations shown in the drawings are merely examples of how the present invention can be realized, and do not represent the entire technical idea of ​​the present invention. It should be understood that various equivalents, modifications, and applications that can replace them may exist at the time of filing this application.

[0024] Terms such as "first," "second," "A," and "B" used in this specification and claims may be used to describe various components, but these components should not be limited by these terms. These terms are used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present invention. The term "and / or" means the inclusion of a combination of multiple associated listed items or any of multiple associated listed items.

[0025] The terms used in this specification and claims are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions also include plural expressions unless the context clearly indicates otherwise. In this application, terms such as "comprises" or "has" should be understood as not precluding the presence or additional possibility of features, numerical values, steps, operations, components, parts, or combinations thereof described herein.

[0026] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0027] Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0028] Furthermore, the configurations, processes, steps, methods, etc. included in the embodiments of the present invention may be shared to the extent that they are not technically inconsistent with each other.

[0029] Hub chiplets according to some embodiments of the present invention will now be described with reference to Figures 1-11.

[0030] FIG. 1 is a conceptual diagram illustrating a hub chiplet according to some embodiments of the present invention.

[0031] 1, a hub chiplet 100 according to some embodiments of the present invention may be a type of semiconductor chiplet. A chiplet is a small chip, and unlike an integrated circuit chip, it may be a relatively small unit module that performs a specific function. Chiplets may be used to build larger systems, primarily through communication and connection between various devices.

[0032] The hub chiplet 100 may house various functional modules therein. In this case, the functional modules may include at least one of a processor 130, memory controllers 110 and 120, a device-to-device (D2D) interface 150, a resource scheduler, a security engine, a debug interface 140, and a peripheral logic circuit. In this case, the processor may be at least one of a central processing unit (CPU), a graphic processing unit (GPU), and a neural processing unit (NPU). However, this embodiment is not limited thereto.

[0033] The memory controllers 110 and 120 may include, for example, a DDR controller 110 that controls a DDR DRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) 210, and a CXL (Compute Express Link) controller 120 that controls a CXL memory 220. However, the present embodiment is not limited to this, and may include various other memory controllers such as an SRAM controller, an SDR controller that controls an SDR DRAM, and a PCIe host interface.

[0034] D2D interface 150 may be an interface that physically connects hub chiplet 100 to other devices to exchange data and signals. Hub chiplet 100 can be coupled to other devices via D2D interface 150 to build a system on chip (SoC) system package. For example, other hub chiplets 230 and custom logic dies 240 required for other systems can be coupled to hub chiplet 100 via D2D interface 150.

[0035] The resource scheduler may determine how to allocate and schedule power and frequency for each functional block. The resource scheduler may be implemented as hardware or software.

[0036] The security engine may perform operations related to the security of the hub chiplet 100 and the package system to which the hub chiplet 100 belongs. That is, the security engine may perform validation checks and security inspections through tamper-proof memory such as a root of trust. However, the present embodiment is not limited thereto.

[0037] Debug interface 140 may monitor and debug the operation of hub chiplet 100 and the software / hardware of the package system that hub chiplet 100 is included in. This allows debug interface 140 to correct the operation of hub chiplet 100 if it behaves abnormally.

[0038] The peripheral logic circuit refers to various logic circuits other than the above-mentioned functional blocks, and may include, for example, at least one of serial communication interfaces supporting serial communication protocols such as UART (Universal Asynchronous Receiver-Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit), general-purpose input / output (GPIO) pins, timers, counters, DMA (Direct Memory Access) controllers, interrupt controllers, and analog interfaces.

[0039] Hub chiplet 100 can be connected to various custom logic dies via the various functional blocks described above to build an overall hub chiplet package. Specifically, hub chiplet 100 can be combined with at least one of DDR DRAM 210, CXL memory 220, other hub chiplets 230, and custom logic dies 240. This easy expandability allows hub chiplet 100 to easily derive the configuration of an overall system by combining multiple module devices.

[0040] FIG. 2 is a diagram illustrating the D2D interface of the hub chiplet of FIG.

[0041] 2, the hub chiplet 100 may include at least one D2D connector for connection to other devices. The D2D connectors may be positioned in four directions on a plane, as shown in FIG. 2, for example.

[0042] Specifically, the hub chiplet 100 may include a top connection module 100T located on an upper cross section on the plane of the hub chiplet 100, a bottom connection module 100B located on a lower cross section on the plane of the hub chiplet 100, a left connection module 100L located on a left cross section on the plane of the hub chiplet 100, and a right connection module 100R located on a right cross section on the plane of the hub chiplet 100.

[0043] In this case, the top connection module 100T and the bottom connection module 100B may be located in cross sections in opposite directions, and the left connection module 100L and the right connection module 100R may be located in cross sections in opposite directions. Furthermore, a first line connecting the top connection module 100T and the bottom connection module 100B and a second line connecting the left connection module 100L and the right connection module 100R may intersect rather than be parallel to each other. Furthermore, the first line and the second line may be perpendicular to each other. However, this embodiment is not limited thereto.

[0044] The top connection module 100T, bottom connection module 100B, left connection module 100L, and right connection module 100R may be connected to connection modules of other hub chiplets 230 to physically connect the hub chiplets 100 together. This allows each hub chiplet 100 to route data and signals between the hub chiplets 100. In this case, signal transmission between multiple functional modules is performed quickly without delay, thereby improving the overall speed of the package.

[0045] 2 shows an example of a rectangular hub chiplet 100. While a configuration having four connection modules, one on each of the four sides, has been described, this embodiment is not limited thereto. This embodiment may include any shape in which multiple hub chiplets 100 can be aligned with each other and easily coupled using D2D connection. Furthermore, as long as this condition is met, the number of connection modules arranged in one hub chiplet 100 may be changed arbitrarily.

[0046] 3 to 8 are diagrams illustrating D2D connection types of hub chiplets according to some embodiments of the present invention.

[0047] 3, a first hub chiplet 100_1 and a second hub chiplet 100_2 may be connected to each other via a D2D connection. The first hub chiplet 100_1 may include a first top connection module 100T1, a first bottom connection module 100B1, a first left connection module 100L1, and a first right connection module 100R1. The second hub chiplet 100_2 may include a second top connection module 100T2, a second bottom connection module 100B2, a second left connection module 100L2, and a second right connection module 100R2.

[0048] In this case, the first top connection module 100T1 may have the same shape as the second top connection module 100T2, and the first bottom connection module 100B1 may have the same shape as the second bottom connection module 100B2. Similarly, the first left connection module 100L1 may have the same shape as the second left connection module 100L2, and the first right connection module 100R1 may have the same shape as the second right connection module 100R2.

[0049] The first right connection module 100R1 can be connected to the second left connection module 100L2 via D2D connection. That is, the first right connection module 100R1 can be configured to be connectable to the first left connection module 100L1. Similarly, the second right connection module 100R2 can be configured to be connectable to the second left connection module 100L2.

[0050] 4, the first bottom connection module 100B1 may be connected to the second top connection module 100T2 via a D2D connection. That is, the first bottom connection module 100B1 may have a shape that allows it to be coupled to the first top connection module 100T1. Similarly, the second bottom connection module 100B2 may have a shape that allows it to be coupled to the second top connection module 100T2.

[0051] 5, the first light connection module 100R1 may be coupled to the second light connection module 100R2 in an upside-down state. In this case, the first direction in which the first top connection module 100T1 and the first bottom connection module 100B1 of the first hub chiplet 100_1 are sequentially arranged may be opposite to the second direction in which the second top connection module 100T2 and the second bottom connection module 100B2 of the second hub chiplet 100_2 are sequentially arranged.

[0052] Therefore, the first light connecting module 100R1 may have the same shape whether it is arranged in the first direction or the second direction, but the present embodiment is not limited thereto.

[0053] 6, the first left connection module 100L1 may be coupled to the second left connection module 100L2 in an upside-down state. In this case, the first direction in which the first top connection module 100T1 and the first bottom connection module 100B1 of the first hub chiplet 100_1 are sequentially arranged may be opposite to the second direction in which the second top connection module 100T2 and the second bottom connection module 100B2 of the second hub chiplet 100_2 are sequentially arranged.

[0054] For this reason, the first left connection module 100L1 may have the same shape whether it is arranged in the first direction or the second direction, although this embodiment is not limited thereto.

[0055] 7, the first top connection module 100T1 may be coupled to the second top connection module 100T2 in an upside-down state. In this case, the third direction in which the first left connection module 100L1 and the first right connection module 100R1 of the first hub chiplet 100_1 are sequentially arranged may be opposite to the fourth direction in which the second left connection module 100L2 and the second right connection module 100R2 of the second hub chiplet 100_2 are sequentially arranged.

[0056] Therefore, the first top connection module 100T1 may have the same shape whether it is arranged in the third direction or the fourth direction, although the present embodiment is not limited thereto.

[0057] 8, the first bottom connection module 100B1 may be coupled to the second bottom connection module 100B2 in an upside-down state. In this case, the third direction in which the first left connection module 100L1 and the first right connection module 100R1 of the first hub chiplet 100_1 are sequentially arranged may be opposite to the fourth direction in which the second left connection module 100L2 and the second right connection module 100R2 of the second hub chiplet 100_2 are sequentially arranged.

[0058] Therefore, the first bottom connecting module 100B1 may have the same shape whether it is arranged in the third direction or the fourth direction, but the present embodiment is not limited thereto.

[0059] 2 and 9-11 are diagrams illustrating packaging types for hub chiplets according to some embodiments of the present invention.

[0060] 2, a hub chiplet package can be constructed using only one hub chiplet 100. In other words, a hub chiplet package can be completed when multiple functional modules are configured inside the hub chiplet 100 to operate as a single SoC.

[0061] 9, a hub chiplet package can also be constructed using multiple hub chiplets 100. For example, a first hub chiplet 100_1, a second hub chiplet 100_2, a third hub chiplet 100_3, and a fourth hub chiplet 100_4 can be connected to each other via D2D connections to construct one hub chiplet package.

[0062] 10, at least one custom logic die may be coupled to one hub chiplet. For example, a first custom logic die CL1, a second custom logic die CL2, a third custom logic die CL3, and a fourth custom logic die CL4 may be coupled to a first hub chiplet 100_1. In this case, the number of custom logic dies may be changed as desired. Furthermore, the custom logic dies may have the same configuration or different configurations.

[0063] That is, the hub chiplet package can be realized as a configuration that can perform required functions not only through combination with the same hub chiplet but also through variously designed custom logic dies.

[0064] 11, a hub chiplet package according to some embodiments of the present invention may be constructed by combining at least one hub chiplet and at least one custom logic die. For example, as shown in FIG. 11, first through fourth hub chiplets 100_1 through 100_4 may be connected in a continuous horizontal direction via D2D connections. Also, first through fourth custom logic dies CL1 through CL4 may be connected horizontally below the first through fourth hub chiplets 100_1 through 100_4, respectively. Furthermore, a fifth hub chiplet 100_5 may be coupled above the second hub chiplet 100_2, and a fifth custom logic die CL5 may be coupled above the fourth hub chiplet 100_4.

[0065] That is, the hub chiplet package of this embodiment can very easily configure required functional configurations by various combinations of hub chiplets and custom logic dies. In addition, because each is very easy to connect, it is very easy to configure a package having required functions.

[0066] FIG. 12 is a diagram illustrating a method for manufacturing a hub chiplet package according to some embodiments of the present invention.

[0067] Referring to FIG. 12, to manufacture a hub chiplet, first, a requirement specification and architecture step is performed (S100).

[0068] The requirement definition may be a stage where multiple requirements such as the functions that the hub chiplet package should perform, performance, power consumption, size, and cost must be determined. The design stage may be a stage where the main functional modules of the package are defined based on the above requirements and a method of communication between them is determined.

[0069] Next, the RTL (Register-Transfer Level) design stage is performed (S200).

[0070] In this stage, digital logic circuits are designed based on the requirements and design, and the interactions and data processing of each component are defined. The digital logic circuits can then be converted to the register transfer level, and data flow and control paths, etc., can be set.

[0071] Next, verification and debugging are performed (S300).

[0072] The verification stage can be a stage where the RTL design is verified to see if it works, and the debug stage can be a stage where problems are resolved and optimized through hardware debugging and software debugging.

[0073] Next, the Place & Route step is performed (S400).

[0074] The placement stage may be a stage in which logic elements such as gates, registers, and memory cells are physically placed on a semiconductor. At this time, the logic elements may be placed taking into consideration physical size, etc. At this time, connections between the logic elements may also be placed, and a power supply network may also be placed.

[0075] The route stage may be the stage where connections between logic elements are implemented on the actual layout and wired, where the wires may be wired to transmit signals in an electrically optimized manner.

[0076] Next, fabrication and unit testing are performed (S500).

[0077] The manufacturing stage may be a stage in which the layout completed in the place and route stage is converted into a semiconductor hub chiplet through an actual microfabrication process on a semiconductor wafer. The hub chiplet and hub chiplet package of this embodiment may be manufactured through various processes such as lithography, etching, and deposition.

[0078] The unit test stage may be a stage in which each sub-module of the hub chiplet package is tested to see if it operates normally. Various types of tests may be performed, such as a functional test, a performance test, and a power consumption test.

[0079] Next, a qualification step is performed (S600).

[0080] The qualification stage may be a stage in which the completed hub chiplet package is verified to meet quality and reliability standards. Environmental tests, life tests, reliability tests, etc. may be performed during the qualification stage.

[0081] In this manner, the hub chiplet package can be manufactured in multiple steps similar to conventional semiconductor packages.

[0082] FIG. 13 is a diagram illustrating a method for scaling up a hub chiplet package according to some embodiments of the present invention.

[0083] 12 and 13, the difference between the scale-up method of the conventional SoC and the present embodiment can be seen. The left side of Fig. 13 shows the scale-up method of the conventional SoC. To expand the memory capacity from 512 GB to 1 TB and then to 2 TB, steps S100 to S600 in Fig. 12 must be repeated each time.

[0084] Specifically, even if SoC-I production is completed, SoC-II and SoC-III production must start again from step S100. This means that the traditional SoC manufacturing process can be very long and expensive. Current estimates put the manufacturing time at approximately 24 to 30 months, and it could potentially be longer.

[0085] In contrast, when implementing an SoC using a hub chiplet package according to some embodiments of the present invention, steps S100 to S600 can be performed initially, and then steps S500 and S600 can be performed again to facilitate scale-up. Since the functional modules required to build a smaller-scale SoC are already included in the existing hub chiplet, the larger-scale SoC can be manufactured simply by increasing the quantity. For example, a 512 GB SoC can be manufactured with one hub chiplet, a 1 TB SoC with two hub chiplets, and a 2 TB SoC with four hub chiplets. In other words, simply adjusting the number of hub chiplets during hub chiplet manufacturing can omit steps S100 to S400, thereby minimizing manufacturing time and costs. The expected manufacturing speed is approximately five to ten times faster than conventional processes, and even faster speeds are possible in certain processes.

[0086] In addition to expanding the memory capacity shown in Figure 13, adding processors for AI computation also enables faster processing by using the scale-up method described above. In this case, integrating D2D connections and off-chip switch interfaces makes it easy to build larger and more complex structures.

[0087] The above description merely exemplifies the technical concept of the present embodiment, and those skilled in the art will understand that various changes and modifications can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiment is intended to illustrate, not limit, the technical concept of the present embodiment, and the scope of the technical concept of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

Claims

1. A hub chiplet capable of mounting a functional module, the hub chiplet comprising: a top connection module formed on a cross section of the hub chiplet in a first direction; a bottom connection module formed on a cross section of the hub chiplet in a second direction opposite to the first direction; a left connection module formed on a cross section in a third direction perpendicular to a first straight line connecting the top connection module and the bottom connection module of the hub chiplet; a light connection module formed on a cross section of the hub chiplet in a fourth direction perpendicular to the first straight line and opposite to the third direction; The top connection module is capable of D2D (Device-to-Device) connection with the bottom connection module; The left connection module is a hub chiplet capable of D2D connection with the right connection module.

2. The hub chiplet of claim 1 , wherein the light connection module is connectable to the light connection module in a state where the first and second directions are reversed.

3. The hub chiplet of claim 1 , wherein the left connection module is matable with the left connection module in a state where the first and second directions are reversed.

4. The hub chiplet of claim 1 , wherein the top connection module is matable with the top connection module in a state where the third orientation and the fourth orientation are reversed.

5. The hub chiplet of claim 1 , wherein the bottom connection module is matable with the bottom connection module in a state where the third orientation and the fourth orientation are reversed.

6. The hub chiplet of claim 1 , wherein the functional module is at least one of a processor, a memory controller, a D2D interface, a resource scheduler, a security engine, a debug interface, and a peripheral logic circuit.

7. The hub chiplet of claim 1 , wherein the top connection module, the bottom connection module, the left connection module, and the right connection module are each matable with a custom logic die that operates in the same manner as the hub chiplet.

8. a first hub chiplet and a second hub chiplet having the same shape and coupled to each other by D2D; a first custom logic die coupled to the first hub chiplet in a D2D manner; a second custom logic die coupled to the second hub chiplet by D2D; a hub chiplet package that drives system on chip (SoC) operation with the first and second hub chiplets and the first and second custom logic dies;

9. the first hub chiplet includes a first processor and a first memory controller; The hub chiplet package of claim 8 , wherein the first custom logic die includes a first memory controlled by the first memory controller.

10. the second hub chiplet includes a second processor and a second memory controller; The hub chiplet package of claim 9 , wherein the second custom logic die includes a second memory controlled by the second memory controller.

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