Amplitude limiting circuit and operational amplifier

Abstract

To provide an amplitude limiting circuit and an operational amplifier capable of limiting the amplitude of a signal output from a fully differential output circuit.SOLUTION: An amplitude limiting circuit includes a first NMOS transistor connected to a positive output terminal of an output circuit, a second NMOS transistor connected to a negative output terminal of the output circuit, a first current source connected in common between the first NMOS transistor and the second NMOS transistor and ground, and a voltage generating unit that generates a voltage to be applied to the gates of the first NMOS transistor and the second NMOS transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an amplitude limiting circuit and an operational amplifier. [Background technology]

[0002] Patent Document 1 describes an amplitude limiting circuit that includes an amplifier and an amplitude limiter that limits the amplitude of a signal output from the amplifier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 04-081008 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide an amplitude limiting circuit and an operational amplifier that are capable of limiting the amplitude of a signal output from a fully differential output circuit. [Means for solving the problem]

[0005] The amplitude limiting circuit of the present disclosure includes a first NMOS transistor connected to a positive output terminal of an output circuit, a second NMOS transistor connected to a negative output terminal of the output circuit, a first current source connected in common between the first NMOS transistor and the second NMOS transistor and ground, and a voltage generating unit that generates a voltage to be applied to the gates of the first NMOS transistor and the second NMOS transistor.

[0006] The operational amplifier of the present disclosure includes the amplitude limiting circuit of the present disclosure, and a differential amplifier circuit having a plurality of transistors and a third current source, and connected to the amplitude limiting circuit via the output circuit. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram of an operational amplifier according to a first embodiment of the present disclosure. [Figure 2] FIG. 10 is a circuit diagram of an operational amplifier according to a second embodiment of the present disclosure. [Figure 3] FIG. 10 is a circuit diagram of an operational amplifier of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] [First embodiment] Next, embodiments of the present disclosure will be described with reference to the drawings. Fig. 1 is a circuit diagram of an operational amplifier 1 according to a first embodiment of the present disclosure.

[0009] As shown in FIG. 1, the operational amplifier 1 of the first embodiment is a two-stage amplifier that combines a differential amplifier circuit 11, a common-source amplifier circuit 12, a common-mode feedback circuit (hereinafter referred to as a CMFB (Common Mode Feedback) circuit) 13, and an amplitude limiting circuit 14.

[0010] The operational amplifier 1 is a fully differential operational amplifier having a positive input terminal INP, a negative input terminal INM, a positive output terminal OUTP2, a negative output terminal OUTM2, and a reference voltage terminal Vref to which a reference voltage Vref is input.

[0011] The differential amplifier circuit 11 includes NMOS (N-type Metal Oxide Semiconductor) transistors M1 and M2, PMOS (P-type Metal Oxide Semiconductor) transistors M3 and M4, and a current source 10. The current source 10 is an example of a third current source in the technology of the present disclosure.

[0012] The common-source amplifier circuit 12 includes PMOS transistors M5 and M6 and current sources I1 and I2. The common-source amplifier circuit 12 is an example of an output circuit in the technology of the present disclosure.

[0013] Resistors R1 and R2 are resistors for generating a common mode voltage (average voltage) Vcm of the voltages at OUTP2 and OUTM2.

[0014] The CMFB circuit 13 is a circuit that controls the gate potentials of the PMOS transistors M3 and M4 based on the voltage difference obtained by comparing the reference voltage Vref and the common-mode voltage Vcm, and operates so that the common-mode voltage Vcm is equal to the reference voltage Vref.

[0015] The amplitude limiting circuit 14 is composed of NMOS transistors M7 and M8, a current source I3, and a voltage generating unit 15. The NMOS transistor M7 is an example of a first NMOS transistor in the technology of the present disclosure. The NMOS transistor M8 is an example of a second NMOS transistor in the technology of the present disclosure. The current source I3 is an example of a first current source in the technology of the present disclosure.

[0016] The drain of the NMOS transistor M7 is connected to the positive output terminal OUTP2 of the source-grounded amplifier circuit 12, which is an output circuit.

[0017] The drain of the NMOS transistor M8 is connected to the negative output terminal OUTM2 of the source-grounded amplifier circuit 12, which is an output circuit.

[0018] The current source I3 is commonly connected between the sources of the NMOS transistors M7 and M8 and the ground.

[0019] The voltage generation unit 15 generates a voltage to be applied to the gates of the NMOS transistors M7 and M8. The voltage generation unit 15 includes a voltage setting unit 16 consisting of one NMOS transistor M9, and a current source I4 connected to the voltage setting unit 16. The current source I4 is an example of a second current source in the technology of the present disclosure.

[0020] Resistors R3 and R4 are zero-point compensation resistors, and capacitors C1 and C2 are phase compensation capacitors. The currents flowing through current sources I1 and I2 are the same.

[0021] Next, the operation and effects of the operational amplifier 1 of this embodiment will be described.

[0022] In the operational amplifier 1, the potential difference between the input signals INP and INN applied to the gates of the NMOS transistors M1 and M2 is slightly amplified by the differential amplifier circuit 11 having a current mirror load, and is output to OUTP1 and OUTM1.

[0023] The voltages OUTP1 and OUTM1 are applied to the gates of the PMOS transistors M5 and M6, respectively, and are amplified by the PMOS transistors M5 and M6 before being output to the output terminals OUTP2 and OUTM2.

[0024] Here, a case where the voltage of OUTP2 increases and the voltage of OUTM2 decreases will be described.

[0025] The gate voltage of the NMOS transistors M7 and M8 of the amplitude limiting circuit 14 is a bias voltage generated by the voltage generating unit 15. The source voltage of the NMOS transistors M7 and M8 is lower than the gate voltage by the gate-source voltage required for the NMOS transistors M7 and M8 to operate.

[0026] Since the gate voltage, source voltage, and gate-source voltage of the NMOS transistors M7 and M8 are constant, even if the voltage of OUTP2 applied to the drain of the NMOS transistor M7 gradually increases, the NMOS transistor M7 continues to conduct current.

[0027] On the other hand, when the voltage of OUTM2 applied to the drain of the NMOS transistor M8 gradually decreases, the voltage of OUTM2 applied to the drain of the NMOS transistor M8 gradually approaches the source voltage of the NMOS transistor M8, and the NMOS transistor M8 gradually approaches a state in which no current flows.

[0028] When no current flows through the NMOS transistor M8, the voltage at OUTM2 stops decreasing, and amplitude limitation is imposed on the negative output terminal OUTM2.

[0029] At this time, all of the current flowing from the current source I3 to the NMOS transistor M8 now flows to the NMOS transistor M7, so the voltage at OUTP2 stops rising and amplitude is limited at the positive output terminal OUTP2.

[0030] Fig. 3 is a circuit diagram of a comparative example operational amplifier 100. As shown in Fig. 3, the comparative example operational amplifier 100 has the same configuration as the operational amplifier 1 of this embodiment, except that it does not include an amplitude limiting circuit 14.

[0031] The operational amplifier 100 of the comparative example does not include the amplitude limiting circuit 14, and therefore there is a risk that signals exceeding the allowable input amplitude of the subsequent circuit may be output from the positive output terminal OUTP2 and the negative output terminal OUTM2.

[0032] In contrast to this, the operational amplifier 1 of this embodiment is provided with an amplitude limiting circuit 14, which makes it possible to limit the voltage range of the positive output terminal OUTP2 and the negative output terminal OUTM2, thereby making it possible to prevent the output of a signal that exceeds the allowable input amplitude of the subsequent circuit.

[0033] [Second embodiment] Next, a second embodiment of the present disclosure will be described with reference to the drawings. Fig. 2 is a circuit diagram of an operational amplifier 2 according to the second embodiment of the present disclosure.

[0034] In the operational amplifier 2 of the second embodiment, the configuration of the voltage setting section 16 in the amplitude limiting circuit 14 is changed compared to the operational amplifier 1 of the first embodiment, but the other configurations are the same.

[0035] In the operational amplifier 2 of this embodiment, the same components as those in the operational amplifier 1 of the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted unless otherwise necessary.

[0036] As shown in FIG. 2, the voltage setting section 16 in the amplitude limiting circuit 14 of the operational amplifier 2 of the second embodiment is formed by connecting a plurality of NMOS transistors, including NMOS transistors M9 and M10, in series.

[0037] In the operational amplifier 2 of this embodiment, as in the operational amplifier 1 of the first embodiment, it is possible to limit the voltage range of the positive output terminal OUTP2 and the negative output terminal OUTM2, so that it is possible to prevent the output of a signal that exceeds the allowable input amplitude of the subsequent circuit.

[0038] Furthermore, in the voltage setting unit 16 of the amplitude limiting circuit 14, if a plurality of NMOS transistors are connected in series to increase the gate voltages of the NMOS transistors M7 and M8, the voltage ranges of the positive output terminal OUTP2 and the negative output terminal OUTM2 can be narrowed further compared to when the voltage setting unit 16 has one NMOS transistor.

[0039] Furthermore, by adjusting the number of NMOS transistors connected in series in the voltage setting section 16, the voltage ranges of the positive output terminal OUTP2 and the negative output terminal OUTM2 can be adjusted.

[0040] [Variations] Although the embodiments of the amplitude limiting circuit of the present disclosure have been described above, the present disclosure is not limited to the first and second embodiments and can be modified as appropriate.

[0041] For example, in the first and second embodiments, the amplitude limiting circuit 14 is used to limit the output amplitude of the source-grounded amplifier circuit 12, which is the output circuit, but it can also be used as a circuit for suppressing desaturation operation of the transistors that make up the source-grounded amplifier circuit 12, which is the output circuit.

[0042] Furthermore, in the above-described first and second embodiments, an operational amplifier in which the differential amplifier circuit 11, the source-grounded amplifier circuit 12 serving as the output circuit, the CMFB circuit 13, and the amplitude limiting circuit 14 are integrally formed has been described, but the output circuit and the amplitude limiting circuit 14 may be configured separately.

[0043] In addition to the above, appropriate changes may be made to the above-described and illustrated contents, such as deleting unnecessary parts, adding new elements, or substituting elements, within the scope of the gist of the technology of the present disclosure. [Explanation of symbols]

[0044] 1, 2 Op-amps 11 Differential amplifier circuit 12. Grounded-source amplifier circuit 13 Common-mode feedback circuit 14 Amplitude limiting circuit 15 Voltage generation unit 16 Voltage setting section C1, C2 capacity I0, I1, I2, I3, I4 Current sources M1, M2, M7, M8, M9, M10 NMOS transistors M3, M4, M5, M6 PMOS transistors R1, R2, R3, R4 resistance

Claims

1. a first NMOS transistor connected to a positive output terminal of the output circuit; a second NMOS transistor connected to the negative output terminal of the output circuit; a first current source commonly connected between the first NMOS transistor and the second NMOS transistor and a ground; a voltage generating unit that generates a voltage to be applied to the gates of the first NMOS transistor and the second NMOS transistor. Amplitude limiting circuit.

2. The voltage generating unit a voltage setting unit consisting of one NMOS transistor; a second current source connected to the voltage setting unit; 2. The amplitude limiting circuit according to claim 1.

3. The voltage generating unit a voltage setting unit formed by connecting a plurality of NMOS transistors in series; a second current source connected to the voltage setting unit; 2. The amplitude limiting circuit according to claim 1.

4. an amplitude limiting circuit according to any one of claims 1 to 3; a differential amplifier circuit having a plurality of transistors and a third current source, the differential amplifier circuit being connected to the amplitude limiting circuit via the output circuit; Operational amplifier.

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