Signal output circuit and integrated circuit

Abstract

To provide a signal output circuit capable of easily adjusting an output timing of a plurality of signals.SOLUTION: A signal output circuit according to an embodiment comprises a synthesizing circuit and a latch circuit. The synthesizing circuit generates a synthesized signal including at least two pulses having different minimum pulse widths using at least first data and second data. The latch circuit comprises an input terminal to which the synthesized signal is input, and a control terminal to which a clock is supplied. The latch circuit outputs the synthesized signal when a level of the control terminal is a first level, holds the synthesized signal when the level of the control terminal changes from the first level to a second level, and outputs the held synthesized signal when the level of the control terminal is the second level.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a signal output circuit and an integrated circuit. [Background technology]

[0002] Because integrated circuits have a limited number of terminals, they often need to switch between multiple different types of signals and output them from a single terminal. For this reason, integrated circuits are equipped with a signal output circuit. The signal output circuit receives multiple signals and has multiple signal paths for selecting one signal from the multiple signals. The signal output circuit outputs the multiple signals according to specifications that ensure that the receiving circuit at the downstream stage of the integrated circuit can reliably capture the data. The specifications include output delay time and output hold time. Output delay time is the time it takes for the signal level to be determined after the rising edge of the clock. Output hold time is the time the signal level is maintained after the rising edge of the clock.

[0003] Signal paths include circuit elements for switching and merging multiple signals. When designing an integrated circuit, delay elements (repeater buffers) are inserted or circuit elements with different drive capabilities are replaced so that the rise and fall timing (hereinafter referred to as output timing) of the signal output from one terminal on each of the multiple signal paths meets specifications. Increasing the number of delay elements in a signal path not only lengthens the signal delay time under standard conditions, but also increases the fluctuations in signal delay time due to environmental changes such as voltage and temperature. Even if the output timing is adjusted under standard conditions, variations in delay time caused by environmental changes or during the element manufacturing process can result in different output timing fluctuations for each signal path. Furthermore, replacing circuit elements with different drive capabilities requires trial and error because the manifestation of these variations changes. The maximum output delay time and output hold time depend on the signal delay time of the path that is the maximum under various conditions, and the minimum value depends on the signal delay time of the path that is the minimum under various conditions. Therefore, designing an integrated circuit so that the output timing of multiple signal paths meets specifications is difficult, as it requires long layout design times and output timing verification times. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-151498 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a signal output circuit that can easily adjust the output timing of a plurality of signals. [Means for solving the problem]

[0006] A signal output circuit according to an embodiment includes a combining circuit and a latch circuit. The combining circuit generates a combined signal including at least two pulses with different minimum pulse widths using at least first data and second data. The latch circuit includes an input terminal to which the combined signal is input and a control terminal to which a clock is supplied. The latch circuit outputs the combined signal input when the control terminal is at a first level, holds the combined signal input when the control terminal changes from the first level to a second level, and outputs the held combined signal when the control terminal is at the second level. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram for explaining an example of an integrated circuit including a signal output circuit according to the first embodiment. [Figure 2] FIG. 2 is a diagram for explaining an example of a signal output circuit according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing an example of a timing chart of a flip-flop according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing an example of a timing chart of a latch according to the first embodiment. [Figure 5] FIG. 2 is a diagram showing an example of a timing chart of the signal output circuit according to the first embodiment. [Figure 6] FIG. 10 is a diagram for explaining an example of an integrated circuit including an example of a signal output circuit according to a second embodiment. [Figure 7] FIG. 10 is a diagram for explaining an example of a signal output circuit according to a second embodiment. [Figure 8] FIG. 11 is a diagram for explaining an example of an integrated circuit including an example of a signal output circuit according to a third embodiment. [Figure 9] FIG. 10 is a diagram for explaining an example of a signal output circuit according to a third embodiment. [Figure 10] FIG. 11 is a diagram showing an example of a timing chart of the signal output circuit according to the third embodiment. [Figure 11] FIG. 10 is a diagram showing another example of the timing chart of the signal output circuit according to the third embodiment. [Figure 12]FIG. 10 is a diagram for explaining an example of an integrated circuit including an example of a signal output circuit according to a fourth embodiment. [Figure 13] FIG. 10 is a diagram for explaining an example of a signal output circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The following describes embodiments with reference to the drawings. The following description exemplifies devices and methods embodying the technical concepts of the embodiments. The technical concepts of the embodiments are not limited to the structures, shapes, arrangements, materials, etc. of the components described below. Modifications that can be easily conceived by those skilled in the art are naturally within the scope of the disclosure. For clarity of explanation, the drawings may schematically depict elements with different sizes, thicknesses, planar dimensions, shapes, etc. compared to the actual elements. Elements with different dimensional relationships or ratios may be included in multiple drawings. Corresponding elements may be designated by the same reference numerals in multiple drawings, and redundant description may be omitted. Some elements may be designated by multiple names, but these names are merely examples and do not exclude the use of other names for these elements. Elements without a plural name may also be designated by other names. "Connection" may include not only direct connection but also connection via other elements. Unless the number of elements is specified as being plural, the element may be a singular element or multiple elements.

[0009] First embodiment FIG. 1 is a diagram illustrating an example of an integrated circuit 121 including an example of a signal output circuit 101 according to the first embodiment. The integrated circuit 121 supplies a data signal (hereinafter abbreviated as data) to a downstream receiving circuit (not shown). The receiving circuit uses the data. A clock signal (hereinafter abbreviated as clock) is required to generate and use the data. In the first embodiment, the integrated circuit 121 generates a clock, generates data based on the clock, and supplies the data and clock to the receiving circuit. The receiving circuit, rather than the integrated circuit 121, may generate the clock and supply the clock to the integrated circuit 121.

[0010] In addition to the signal output circuit 101, the integrated circuit 121 includes a clock generation circuit 14, a data generation circuit 16, output buffers 18 and 20, and output terminals 22 and 24. The output terminals 22 and 24 are connected to a receiving circuit.

[0011] The clock generation circuit 14 generates a clock CLK and supplies the clock CLK to the signal output circuit 101 and the data generation circuit 16. The data generation circuit 16 generates data D1 and data D2 that change based on the clock CLK. This specification describes an example in which the multiple data are data SigA and data SigB or data SigC, which will be described later. The minimum pulse width of data SigA is equal to one cycle of the clock CLK. The minimum pulse widths of data SigB and data SigC are narrower than one cycle of the clock CLK.

[0012] The signal output circuit 101 supplies the output buffer 18 with composite data DAT derived from the data D1 and data D2. The signal output circuit 101 adjusts the output timing of the composite data DAT based on the clock CLK. The output buffer 18 supplies the composite data DAT as output data MDAT to the receiving circuit via the output terminal 22. The signal output circuit 101 supplies the clock CLK as is to the output buffer 20. The output buffer 20 supplies the clock CLK as an external clock MCLK to the receiving circuit via the output terminal 24.

[0013] 2 is a diagram illustrating an example of a signal output circuit 101 according to the first embodiment. The signal output circuit 101 includes D-type flip-flop circuits (hereinafter abbreviated as flip-flops) 32 and 34, an inverter 36, a delay circuit 38, an exclusive-OR (EX-OR) gate 40, an AND gate 42, and a D-type latch circuit (hereinafter abbreviated as latch) 46. The flip-flops 32 and 34 each include an input terminal D, a clock terminal CK, and an output terminal Q. The latch 46 includes an input terminal D, a control terminal G, and an output terminal Q.

[0014] Data D1 is input to an input terminal D of a flip-flop 32. Data D2 is input to an input terminal D of a flip-flop 34. A clock CLK is supplied to an output buffer 20 and an inverter 36. An output clock (an inverted signal of the clock CLK) of the inverter 36 is supplied to a clock terminal CK of the flip-flop 32, a clock terminal CK of the flip-flop 34, and a delay circuit 38.

[0015] 3 shows an example of a timing chart of the flip-flops 32 and 34 according to the first embodiment. The flip-flops 32 and 34 hold the level of the input terminal D in response to the rising edge of the clock terminal CK (the falling edge of the clock CLK), and maintain the level of the output terminal Q until the next rising edge of the clock terminal CK. The level of the output terminal Q of the flip-flops 32 and 34 does not change except at the rising edge of the clock terminal CK, even if the level of the input terminal D changes. The level of the output terminal Q can only change at the rising edge of the clock terminal CK.

[0016] Returning to the explanation of FIG. 2, the output terminal Q of the flip-flop 32 is connected to the first input terminal of the EX-OR gate 40. The output signal of the flip-flop 32 is referred to as data SigA. The output terminal Q of the flip-flop 34 is connected to the first input terminal of the AND gate 42. The output terminal of the delay circuit 38 is connected to the second input terminal of the AND gate 42. The delay amount of the delay circuit 38 is determined based on the pulse width specifications of the output data MDAT, which will be described later with reference to FIG. 5. For example, if the output data MDAT includes multiple positive pulses with different pulse widths and multiple negative pulses with different pulse widths, the delay amount is determined based on the pulse width specifications of the positive pulse with the narrowest pulse width and the negative pulse with the narrowest pulse width. The output terminal of the AND gate 42 is connected to the second input terminal of the EX-OR gate 40. The output signal of the AND gate 42 is referred to as data SigB.

[0017] The connection position of the delay circuit 38 is not limited to the input side of the AND gate 42. To obtain a similar pulse, the output terminal of the delay circuit 38 may be connected to the clock terminal CK of the flip-flop 34, and the output terminal of the inverter 36 may be connected to the second input terminal of the AND gate 42.

[0018] The output terminal of the EX-OR gate 40 is connected to an input terminal D of a latch 46. A clock CLK is supplied to a control terminal G of the latch 46.

[0019] 4 shows an example of a timing chart of the latch 46 according to the first embodiment. When the control terminal G (clock CLK) of the latch 46 is at a high level, the level of the output terminal Q of the latch 46 is at the level of the input terminal D. When the control terminal G falls, the latch 46 holds the level of the input terminal D. When the control terminal G is at a low level, the level of the output terminal Q of the latch 46 is at the hold level. The output signal of the latch 46 is composite data DAT.

[0020] 5 is a diagram showing an example of a timing chart of the signal output circuit 101 according to the first embodiment. In FIG. 5, (a) indicates the clock CLK, (b) indicates data D1, (c) indicates data D2, (d) indicates the output signal of the flip-flop 32, i.e., data SigA, (e) indicates the output signal of the flip-flop 34, (f) indicates the output signal of the delay circuit 38, (g) indicates the output signal of the AND gate 42, i.e., data SigB, (h) indicates the output signal of the EX-OR gate 40, (i) indicates the output signal of the latch 46, (j) indicates the output clock MCLK of the signal output circuit 101, and (k) indicates the output data MDAT of the signal output circuit 101.

[0021] The flip-flops 32 and 34 output data D1 and D2 (FIGS. 5(b) and (c)), respectively, in synchronization with the rising edge of the clock terminal CK (FIGS. 5(d) and (e)). In this specification, "synchronized" does not mean simultaneously, but rather after a certain amount of time has passed, taking into account the delay time of the elements.

[0022] The delay circuit 38 delays the clock CLK (FIG. 5(f)). The AND gate 42 outputs a logical AND signal (SigB) of the output signal of the flip-flop 34 and the output signal of the delay circuit 38 (FIG. 5(g)). That is, when a high level is given to the data D2, a positive pulse appears in the data SigB with a delay of about half a clock. The EX-OR gate 40 outputs an exclusive OR signal of the output signal of the flip-flop 32 and the output signal of the AND gate 42. The EX-OR gate 40 outputs a high-level signal when the level of the output signal of the flip-flop 32 and the level of the output signal of the AND gate 42 differ, and outputs a low-level signal when the level of the output signal of the flip-flop 32 and the level of the output signal of the AND gate 42 match (FIG. 5(h)).

[0023] When the control terminal G is at a high level, the latch 46 outputs the input signal (the output signal of the EX-OR gate 40). When the control terminal G falls, the latch 46 holds the input signal. When the clock CLK is at a low level, the latch 46 outputs a signal of the held input level (Figure 5(i)). In other words, the latch 46 functions to adjust the output timing of the output signal of the EX-OR gate 40 relative to the clock CLK.

[0024] The clock CLK is output from the integrated circuit 121 as the external clock MCLK via the output buffer 20 (FIG. 5(j)). The output signal of the latch 46 is output from the integrated circuit 121 as the output data MDAT via the output buffer 18 (FIG. 5(k)).

[0025] The output data MDAT includes at least two types of pulses with different minimum pulse widths. The minimum pulse width of one pulse is equal to the period of the clock CLK. The minimum pulse width of the other pulse is shorter than the period of the clock CLK. Figure 5 shows an example in which the output data MDAT includes five pulses. The five pulses, from the top, are the first positive pulse p1, the second negative pulse p2, the third positive pulse p3, the third positive pulse p4, the fourth negative pulse p5, and the fifth positive pulse p6. Of these, the pulse widths of the positive pulses p1 and p3 and the negative pulse p4 are derived from the data SigA and are equal to the period of the clock CLK. The pulse widths of the negative pulse p2 and the positive pulse p5 are derived from the data SigB and are shorter than the period of the clock CLK.

[0026] The timing specification of the output data MDAT relative to the external clock MCLK is defined by the time difference from the external clock MCLK and includes a rise delay time and a fall delay time. Because the output data MDAT includes two types of pulses, the rise delay time includes a rise delay time tDR1 relative to the first pulse derived from data SigA and a rise delay time tDR2 relative to the second pulse derived from data SigB. The fall delay time includes a fall delay time tDF1 relative to the first pulse and a fall delay time tDF2 relative to the second pulse. The delay times tDR1 and tDR2 are adjusted to the same time by latch 46, as are the delay times tDF1 and tDF2. This reduces the design time required for layout, delay verification, and other tasks to adjust the delay times tDR1, tDR2, tDF1, and tDF2 to meet the timing specifications.

[0027] According to the first embodiment, a composite signal of data SigA and SigB is supplied to latch 46. Latch 46 adjusts the output timing of the composite signal. In this way, by multiplexing multiple pieces of data SigA and SigB into signal MDAT output from one output terminal 22, the number of terminals of integrated circuit 10 can be reduced. As a result, material costs can be reduced by reducing package size, and assembly costs can be reduced by reducing the number of bonds between semiconductor elements and terminals, resulting in lower costs and increased profits.

[0028] In the first embodiment, data SigA and data SigB are combined using an EX-OR gate 40. As shown in FIG. 5, when data D2 is set to a high level, a positive pulse appears in data SigB. In other words, data D2 can be interpreted as switching whether or not to output a positive pulse, a characteristic of data SigB. Of course, a similar effect can be achieved by more directly switching data SigA and SigB using a signal selection element. In this case, data SigA is output from one terminal during a certain period, and data SigB is output during other periods. In other words, two pulses with different minimum pulse widths are output from one terminal. In this specification, a circuit capable of inputting two or more data and switching the output mode is referred to as a combining circuit, and its output is referred to as a combined signal. By combining or switching multiple data SigA and SigB before the latch 46, the delay time from the rising edge of the clock to the output of the pulse included in the output data MDAT is shortened, and the variability of this delay time is also reduced. Furthermore, compared to flip-flops, latches have a shorter delay time relative to the clock. As a result, it is possible to prevent a prolonged development period for the integrated circuit 10 and a deterioration in product quality due to specifications not being met or specifications being relaxed. Furthermore, when designing and manufacturing an integrated circuit that switches between multiple types of output signals, it is not necessary to separately design the rise and fall timings relative to the clock for each type of output signal.

[0029] Second embodiment 6 is a diagram illustrating an example of an integrated circuit 122 including an example of a signal output circuit 102 according to the second embodiment. The integrated circuit 122 includes the signal output circuit 102, a data generation circuit 16, an output buffer 18, an output terminal 22, an input terminal 62, and an input buffer 60. The integrated circuit 122 according to the second embodiment does not include a clock generation circuit. The receiving circuit includes a clock generation circuit, and the generated external clock MCLK is supplied to the input buffer 60 via the input terminal 62. The input buffer 60 outputs the external clock MCLK as a clock CLK to the signal output circuit 102 and the data generation circuit 16.

[0030] 7 is a diagram illustrating an example of a signal output circuit 102 according to the second embodiment. The signal output circuit 102 is composed of the same components as the signal output circuit 101 according to the first embodiment (FIG. 2). The signal output circuit 102 differs from the signal output circuit 101 in that the clock CLK is supplied from an input buffer 60 instead of the clock generation circuit 14.

[0031] The second embodiment differs from the first embodiment in that the clock CLK is generated by a receiving circuit rather than the integrated circuit 122, but the operations shown in FIGS. 3, 4 and 5 are the same as those of the first embodiment.

[0032] The second embodiment also achieves the same effect as the first embodiment. In integrated circuits that input a clock from an external source, it is not easy to meet the delay time specifications for the input clock, resulting in longer development times and reduced product quality due to specifications not being met or being relaxed. Furthermore, in integrated circuits that input a clock from an external source, satisfying the maximum delay time specifications between the external clock MCLK and the output data MDAT requires the use of circuit elements with large drive capabilities, resulting in problems such as increased circuit size and power consumption. The second embodiment solves these problems.

[0033] Third embodiment 8 is a diagram illustrating an example of an integrated circuit 123 including an example of a signal output circuit 103 according to the third embodiment. The integrated circuit 123 includes a test signal generation circuit 26 in addition to the components of the integrated circuit 121 (FIG. 1) according to the first embodiment. The test signal generation circuit 26 generates a test signal TS and a selection signal SEL. The test signal generation circuit 26 supplies the test signal TS and the selection signal SEL to the signal output circuit 103.

[0034] The integrated circuit 123 is tested before shipping to ensure that it operates correctly. This test is called a shipping test. The test is performed by inputting a known signal to the integrated circuit 123, having the integrated circuit 123 process the input signal, inputting the processing result to a semiconductor tester (not shown), and comparing the processing result with the known signal in the semiconductor tester. The processing result is the test signal. The test signal TS may not be based on the clock CLK, but may be a signal that changes independently of the clock CLK. The minimum pulse width of the test signal TS may be shorter than one cycle of the clock CLK. The selection signal SEL selects whether or not to output the test signal TS from the signal output circuit 103.

[0035] FIG. 9 is a diagram illustrating an example of a signal output circuit 103 according to the third embodiment. In addition to the components of the signal output circuit 101 (FIG. 2) according to the first embodiment, the signal output circuit 103 includes a selector 44 and an OR gate 48, which are signal selection elements. The output terminal of the EX-OR gate 40 is connected to a first input terminal A of the selector 44. The test signal TS is input to a second input terminal B of the selector 44. The test signal TS input to the second input terminal B of the selector 44 is referred to as data SigC. The minimum pulse width of the test signal TS is narrower than one cycle of the clock, and this example illustrates a signal that changes independently of the clock CLK. The selection signal SEL is input to a control terminal S of the selector 44.

[0036] When the level of the control terminal S is low, the selector 44 outputs the input signal of the first input terminal A from the output terminal Y. When the level of the control terminal S is high, the selector 44 outputs the input signal (data SigC) of the second input terminal B from the output terminal Y.

[0037] An output terminal Y of the selector 44 is connected to an input terminal D of a latch 46. A selection signal SEL and a clock CLK are supplied to a control terminal G of the latch 46 via an OR gate 48.

[0038] 10 is a diagram showing an example of a timing chart of the signal output circuit 103 according to the third embodiment. (a) of FIG. 10 shows the clock CLK, (b) the data D1, (c) the data D2, (d) the output signal of the flip-flop 32, i.e., data SigA, (e) the output signal of the flip-flop 34, (f) the output signal of the delay circuit 38, (g) the output signal of the AND gate 42, i.e., data SigB, (h) the output signal of the EX-OR gate 40, (i) the selection signal SEL, (j) the test signal TS, i.e., data SigC, (k) the output of the selector 44, (l) the output signal of the latch 46, (m) the output clock MCLK of the signal output circuit 101, and (n) the output data MDAT of the signal output circuit 101. FIG. 10 shows the timing chart when the selection signal SEL is at a low level.

[0039] The flip-flops 32 and 34 output (FIGS. 10(d) and (e)) the data D1 and D2 (FIGS. 10(b) and (c)), respectively, in synchronization with the falling edge of the clock CLK (FIG. 10(a)).

[0040] The delay circuit 38 delays and outputs the clock CLK (FIG. 10(f)). The AND gate 42 outputs a logical AND signal (SigB) of the output signal of the flip-flop 34 and the output signal of the delay circuit 38 (FIG. 10(g)). The EX-OR gate 40 outputs an exclusive OR signal of the output signal of the flip-flop 32 and the output signal of the AND gate 42. The EX-OR gate 40 outputs a high-level signal when the level of the output signal of the flip-flop 32 and the level of the output signal of the AND gate 42 differ, and outputs a low-level signal when the level of the output signal of the flip-flop 32 and the level of the output signal of the AND gate 42 match (FIG. 10(h)).

[0041] Since the selection signal SEL (FIG. 10(i)) is at a low level, the selector 44 outputs the output signal of the EX-OR gate 40 (FIG. 10(k)).

[0042] When the clock CLK is at a high level, the latch 46 outputs the input signal (the output signal of the selector 44). When the clock CLK is at a falling edge, the latch 46 holds the level of the input signal. When the clock CLK is at a low level, the latch 46 outputs a signal of the held input level (FIG. 10(l)).

[0043] The clock CLK is output from the integrated circuit 123 as the external clock MCLK via the output buffer 20 (FIG. 10(m)). The output signal of the latch 46 is output from the integrated circuit 123 as the output data MDAT via the output buffer 18 (FIG. 10(n)).

[0044] 11 shows another example of a timing chart of the signal output circuit 103 according to the third embodiment. 11(a) to 11(m) correspond to 10(a) to 10(m), respectively. 11 shows a timing chart when the selection signal SEL is at a high level.

[0045] Since the selection signal SEL (FIG. 11(i)) is at a high level, the selector 44 outputs the test signal TS (FIG. 11(k)).

[0046] Since the selection signal SEL (Fig. 11(i)) is always at a high level, the output of the OR gate 48 is also at a high level, the control terminal G of the latch 46 is fixed at a high level, and the latch 46 always outputs the input signal (the output signal of the selector 44) (Fig. 11(l)).

[0047] The clock CLK is output from the integrated circuit 123 as the external clock MCLK via the output buffer 20 (FIG. 11(m)). The output signal of the latch 46 is output from the integrated circuit 123 as the output data MDAT via the output buffer 18 (FIG. 11(n)).

[0048] Typically, a shipping test signal is merged with other data and output from a single terminal. Because the merging element is added immediately before the output buffer, not only does this increase signal delay under standard conditions, but it also increases the amount of delay time variation due to variations in voltage, temperature, and manufacturing process. According to the third embodiment, in addition to data SigA and data SigB, the test signal TS, i.e., data SigC, can also be merged before the latch 46. This allows the timing of the test signal TS to be easily adjusted when output as output data DMAT from a single output terminal 22.

[0049] Fourth embodiment 12 is a diagram illustrating an example of an integrated circuit 124 including an example of a signal output circuit 104 according to the fourth embodiment. The integrated circuit 124 includes a test signal generation circuit 26 in addition to the components of the integrated circuit 122 (FIG. 6) according to the second embodiment.

[0050] 13 is a diagram illustrating an example of a signal output circuit 104 according to the fourth embodiment. The signal output circuit 104 includes a selector 44 and an OR gate 48 in addition to the components of the signal output circuit 102 according to the second embodiment. The output terminal of the EX-OR gate 40 is connected to a first input terminal A of the selector 44. A test signal TS is input to a second input terminal B of the selector 44. A selection signal SEL is input to a control terminal S of the selector 44.

[0051] When the level of the control terminal S is low, the selector 44 outputs the input signal of the first input terminal A from the output terminal Y. When the level of the control terminal S is high, the selector 44 outputs the input signal (test signal TS) of the second input terminal B from the output terminal Y.

[0052] An output terminal Y of the selector 44 is connected to an input terminal D of a latch 46. A selection signal SEL and a clock CLK are supplied to a control terminal G of the latch 46 via an OR gate 48.

[0053] The fourth embodiment also provides the same effects as the third embodiment.

[0054] The present invention is not limited to the above-described embodiments, and modifications of the components can be made without departing from the spirit of the invention. According to the embodiments, a latch is provided after the synthesis circuit to control the rising or falling timing of two or more pulses with different minimum pulse widths, including pulses shorter than the clock period. The latch 46 has been described as outputting the level of the input terminal D when the control terminal G is at a high level and maintaining the output level when the control terminal G is at a low level. However, a similar effect can be achieved by using an element that outputs the level of the input terminal D when the control terminal G is at a low level and maintaining the output level when the control terminal G is at a high level. Furthermore, various inventions can be realized by appropriately combining multiple components disclosed in the above embodiments. For example, some components may be omitted from all of the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of symbols]

[0055] 10... signal output circuit, 12... integrated circuit, 14... clock generation circuit, 16... data generation circuit, 18, 20... output buffer, 32, 34... flip-flop, 36... inverter, 38... delay circuit, 40... EX-OR gate, 42... AND gate, 46... latch

Claims

1. a synthesis circuit that uses at least the first data and the second data to generate a synthesized signal including at least two pulses having different minimum pulse widths; a latch circuit having an input terminal to which the composite signal is input and a control terminal to which a clock is supplied, the latch circuit outputting the input composite signal when the level of the control terminal is at a first level, holding the input composite signal when the level of the control terminal changes from the first level to a second level, and outputting the held composite signal when the level of the control terminal is at the second level.

2. 2. The signal output circuit according to claim 1, wherein said latch circuit changes the output signal based on said clock.

3. 2. The signal output circuit according to claim 1, wherein the latch circuit controls rising timings of the at least two pulses or falling timings of the at least two pulses relative to the clock.

4. 2. The signal output circuit according to claim 1, wherein the at least two pulses include a first pulse whose minimum pulse width is equal to the period of the clock, and a second pulse whose minimum pulse width is shorter than the period of the clock.

5. The synthesis circuit a first flip-flop that receives the first data and changes an output signal based on the clock; a second flip-flop that receives the second data and changes an output signal based on the clock; a delay circuit that delays the clock; an AND gate to which the output signal of the second flip-flop and the output signal of the delay circuit are input; 2. The signal output circuit according to claim 1, further comprising an exclusive OR gate to which the output signal of said first flip-flop and the output signal of said AND gate are input.

6. The synthesis circuit a selector that receives the output signal of the exclusive OR gate and a first signal and outputs the output signal of the exclusive OR gate or the first signal based on a selection signal; an OR gate to which the clock and the selection signal are input, an output terminal of the selector is connected to the input terminal of the latch circuit; 6. The signal output circuit according to claim 5, wherein an output terminal of said OR gate is connected to said control terminal of said latch circuit.

7. 7. The signal output circuit according to claim 6, wherein the first data and the second data change based on the clock, and the first signal changes independently of the clock.

8. a clock generation circuit that generates the clock; a data generation circuit that generates the first data and the second data based on the clock; An integrated circuit comprising the signal output circuit according to any one of claims 1 to 7.

9. an input circuit to which the clock is input; a data generation circuit that generates the first data and the second data based on the clock; An integrated circuit comprising the signal output circuit according to any one of claims 1 to 7.

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