Signal transmission device, electronic apparatus, and vehicle

Abstract

To reduce an isolation element.SOLUTION: A signal transmission device 400 includes: a first logic 411; a second logic 421; a plurality of isolation elements 431 to 434 for performing isolation transmission of a plurality of sets of first signals ON_IN1 / 2 and second signals OFF_IN1 / 2 between the first logic 411 and the second logic 421; and a plurality of output circuits 422 and 423 for respectively generating a plurality of output signals OUT1 / 2 according to instructions from the second logic 421. The first logic 411 is capable of simultaneously transmitting different sets of signals by combining them within the plurality of sets of the first signals ON / IN1 / 2 and the second signals OFF_IN1 / 2. The second logic 421 operates according to the combination of received signals through the plurality of isolation elements 431 to 434 within the plurality of sets of the first signals ON_IN1 / 2 and the second signals OFF_IN1 / 2.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] As examples of the prior art related to the above, Patent Documents 1 and 2 filed by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-134686

[0005] [overview] However, in the conventional signal transmission device, there is room for reducing the number of insulating elements.

[0006] A signal transmission device according to the present disclosure comprises a first logic, a second logic, a plurality of isolation elements configured to transmit, in an isolated manner, a plurality of sets of first signals and second signals between the first logic and the second logic, respectively, and a plurality of output circuits configured to generate a plurality of output signals in response to instructions from the second logic, wherein the first logic is capable of simultaneously transmitting multiple combinations of different sets of signals from the multiple sets of first signals and second signals, and the second logic performs an operation in accordance with the combination of signals from the multiple sets of first signals and second signals received via the multiple isolation elements. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram illustrating a first embodiment (comparative example) of a signal transmission device. [Figure 11] FIG. 11 is a diagram illustrating an example of the second logic in the first embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of output control in the first embodiment. [Figure 13] FIG. 13 is a diagram showing an example of CMTI (common mode transient immunity) noise canceling. [Figure 14] FIG. 14 is a diagram showing a second embodiment of the signal transmission device. [Figure 15] FIG. 15 is a diagram illustrating an example of the second logic in the second embodiment. [Figure 16] FIG. 16 is a diagram illustrating an example of output control in the second embodiment. [Figure 17]FIG. 17 is a diagram showing the SPI communication mode of the signal transmission device. [Figure 18] FIG. 18 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0020] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0024] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Trans chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0074] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23. In this form, the dummy pattern 85 is routed at a line density equal to the line density of the high potential coil 23 per unit area. The line density of the dummy pattern 85 being equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <First embodiment (comparative example)> 10 is a diagram showing a first embodiment of a signal transmission device (corresponding to a comparative example to be compared with the second embodiment described later). A signal transmission device 400 of this embodiment can be mounted in an electronic device A together with various discrete components (for example, a switch element SW, diodes D1 to D4, and resistors R1 to R4).

[0154] The signal transmission device 400 includes a first chip 410, a second chip 420, and a third chip 430. The first chip 410, the second chip 420, and the third chip 430 may be sealed in a single package.

[0155] The signal transmission device 400 may be a semiconductor integrated circuit device (a so-called insulated gate driver IC) that generates an output pulse signal OUT according to an input pulse signal IN to drive a switch element SW while insulating between input and output, similar to the signal transmission device 200 (FIG. 1).

[0156] In this case, the first chip 410 corresponds to the aforementioned controller chip 210. The second chip 420 corresponds to the aforementioned driver chip 220. The third chip 430 corresponds to the aforementioned transformer chip 230.

[0157] The switch element SW may be, for example, an IGBT, or may be a GaN device or a SiC device.

[0158] First logic 411 is integrated on first chip 410. Second logic 421 and output circuits 422 and 423 are integrated on second chip 420. Transformers 431 to 434 (each corresponding to an isolation element) are integrated on third chip 430.

[0159] The first logic 411 receives the input pulse signal IN and the output selection signal GRSEL and generates a first set of transmission pulse signals ON_OUT1 and OFF_OUT1 and a second set of transmission pulse signals ON_OUT2 and OFF_OUT2, respectively.

[0160] When the output selection signal GRSEL is at a high level, the first logic 411 pulse-drives one of the transmission pulse signals ON_OUT1 and OFF_OUT1 in accordance with the logic level of the input pulse signal IN. More specifically, when the first logic 411 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal ON_OUT1. On the other hand, when the first logic 411 notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal OFF_OUT1.

[0161] Furthermore, when the output selection signal GRSEL is at a low level, the first logic 411 pulse-drives one of the transmission pulse signals ON_OUT2 and OFF_OUT2 in accordance with the logic level of the input pulse signal IN. More specifically, when the first logic 411 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal ON_OUT2. On the other hand, when the first logic 411 notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal OFF_OUT2.

[0162] The second logic 421 receives input of a first set of receiving pulse signals ON_IN1 and OFF_IN1 and a second set of receiving pulse signals ON_IN2 and OFF_IN2 from the third chip 430, and controls the output circuits 422 and 423. For example, the second logic 421 receives pulse driving of the receiving pulse signals ON_IN1 and OFF_IN1 to control the output circuit 422. Also, the second logic 421 receives pulse driving of the receiving pulse signals ON_IN2 and OFF_IN2 to control the output circuit 423.

[0163] The output circuit 422 generates a first output pulse signal OUT1 in response to an instruction from the second logic 421. As shown in the figure, the output circuit 422 may be a half-bridge output stage including a transistor P1 (e.g., a PMOSFET [P-channel type metal oxide semiconductor field effect transistor]) and a transistor N1 (e.g., an NMOSFET [N-channel type MOSFET]).

[0164] In terms of connections, the source of the transistor P1 is connected to the application terminal of the power supply voltage VCC2. The source of the transistor N1 is connected to the application terminal of the reference voltage VEE2. The drains of the transistors P1 and N1 are both connected to the application terminal of the first output pulse signal OUT1. The application terminal of the first output pulse signal OUT1 is connected to the anode of the diode D1 and the cathode of the diode D2. The cathode of the diode D1 is connected to the first terminal of the resistor R1. The anode of the diode D2 is connected to the first terminal of the resistor R2. The second terminals of the resistors R1 and R2 are both connected to the control terminal (= the application terminal of the output pulse signal OUT) of the switch element SW.

[0165] When transistor P1 is on and transistor N1 is off, the first output pulse signal OUT1 is at a high level (≈VCC2). Therefore, current flows from the application terminal of the power supply voltage VCC2 through transistor P1, diode D1, and resistor R1 toward the control terminal of the switch element SW. As a result, the output pulse signal OUT is at a high level, and the switch element SW is turned on. In other words, the high level of the first output pulse signal OUT1 can be understood as the logic level of the switch element SW when it is on. At this time, the slope at which the output pulse signal OUT rises from a low level to a high level (= the on-time slew rate) can be adjusted as desired by changing the resistance value of resistor R1.

[0166] On the other hand, when transistor P1 is off and transistor N1 is on, the first output pulse signal OUT1 is low (≈VEE2). Therefore, current flows from the control terminal of switch element SW through resistor R2, diode D2, and transistor N1 toward the terminal to which reference voltage VEE2 is applied. As a result, the output pulse signal OUT is low, and switch element SW is turned off. In other words, the low level of the first output pulse signal OUT1 can be understood as the logic level of switch element SW when it is off. At this time, the slope at which the output pulse signal OUT falls from high to low (=off-time slew rate) can be adjusted as desired by changing the resistance value of resistor R2.

[0167] The drains of the transistors P1 and N1 may be independently connected to the outside of the signal transmission device 400. That is, the drain of the transistor P1 may be individually connected to the first terminal of the resistor R1, and the drain of the transistor N1 may be individually connected to the first terminal of the resistor R2. With this configuration, the diodes D1 and D2 may be omitted.

[0168] The output circuit 423 generates a second output pulse signal OUT2 in response to an instruction from the second logic 421. The output circuit 423 may be a half-bridge output stage including a transistor P2 (e.g., a PMOSFET) and a transistor N2 (e.g., an NMOSFET), as shown in the figure.

[0169] In terms of connections, the source of transistor P2 is connected to the application terminal of power supply voltage VCC2. The source of transistor N2 is connected to the application terminal of reference voltage VEE2. The drains of transistors P2 and N2 are both connected to the application terminal of second output pulse signal OUT2. The application terminal of second output pulse signal OUT2 is connected to the anode of diode D3 and the cathode of diode D4. The cathode of diode D3 is connected to the first terminal of resistor R3. The anode of diode D4 is connected to the first terminal of resistor R4. The second terminals of resistors R3 and R4 are both connected to the control terminal (= application terminal of output pulse signal OUT) of switch element SW.

[0170] When transistor P2 is on and transistor N2 is off, the second output pulse signal OUT2 is at a high level (≈VCC2). Therefore, current flows from the application terminal of the power supply voltage VCC2 through transistor P2, diode D3, and resistor R3 toward the control terminal of the switch element SW. As a result, the output pulse signal OUT is at a high level, and the switch element SW is turned on. In other words, the high level of the second output pulse signal OUT2 can be understood as the logic level of the switch element SW when it is on. At this time, the slope at which the output pulse signal OUT rises from a low level to a high level (= the on-time slew rate) can be adjusted as desired by changing the resistance value of resistor R3.

[0171] On the other hand, when transistor P2 is off and transistor N2 is on, the second output pulse signal OUT2 is low (≈VEE2). Therefore, current flows from the control terminal of switch element SW through resistor R4, diode D4, and transistor N2 toward the terminal to which reference voltage VEE2 is applied. As a result, the output pulse signal OUT is low, and switch element SW is turned off. In other words, the low level of the second output pulse signal OUT2 can be understood as the logic level of switch element SW when it is off. At this time, the slope at which the output pulse signal OUT falls from high to low (=off-time slew rate) can be adjusted as desired by changing the resistance value of resistor R4.

[0172] The drains of the transistors P2 and N2 may be independently connected to the outside of the signal transmission device 400. That is, the drain of the transistor P2 may be independently connected to the first terminal of the resistor R3, and the drain of the transistor N2 may be independently connected to the first terminal of the resistor R4. With this configuration, the diodes D3 and D4 may be omitted.

[0173] Transformers 431 to 434 provide DC insulation between the first logic 411 and the second logic 421, and output the first set of transmission pulse signals ON_OUT1 and OFF_OUT1 and the second set of transmission pulse signals ON_OUT2 and OFF_OUT2 input from the first logic 411 to the second logic 421 as the first set of reception pulse signals ON_IN1 and OFF_IN2 and the second set of reception pulse signals ON_IN2 and OFF_IN2, respectively.

[0174] For example, when the output selection signal GRSEL is at a high level, the input pulse signal IN is separated into transmission pulse signals ON_OUT1 and OFF_OUT1, and then these are transmitted in an isolated manner from the first logic 411 to the second logic 421 via the transformers 431 and 432. On the other hand, when the output selection signal GRSEL is at a low level, the input pulse signal IN is separated into transmission pulse signals ON_OUT2 and OFF_OUT2, and then these are transmitted in an isolated manner from the first logic 411 to the second logic 421 via the transformers 433 and 434.

[0175] In this specification, the receiving pulse signal ON_IN1 corresponds to the first signal (on signal) of the first set. The receiving pulse signal OFF_IN1 corresponds to the second signal (off signal) of the first set. The receiving pulse signal ON_IN2 corresponds to the first signal (on signal) of the second set. The receiving pulse signal OFF_IN2 corresponds to the second signal (off signal) of the second set.

[0176] 11 is a diagram showing an example of the second logic 421 in the first embodiment. As shown in this diagram, the second logic 421 includes resistors R5 to R12, inverters INV1 to INV4, buffers BUF1 to BUF4, delay circuits DLY1 to DLY8, NOR gates NOR1 to NOR4, and RS flip-flops FF1 and FF2. This diagram also shows transformers 431 to 434 connected to the second logic 421.

[0177] The transformer 431 outputs a reception pulse signal ON_IN1 from the secondary coil 431s in response to a transmission pulse signal ON_OUT1 input to the primary coil 431p. The transformer 432 outputs a reception pulse signal OFF_IN1 from the secondary coil 432s in response to a transmission pulse signal OFF_OUT1 input to the primary coil 432p. The transformer 433 outputs a reception pulse signal ON_IN2 from the secondary coil 433s in response to a transmission pulse signal ON_OUT2 input to the primary coil 433p. The transformer 434 outputs a reception pulse signal OFF_IN2 from the secondary coil 434s in response to a transmission pulse signal OFF_OUT2 input to the primary coil 434p.

[0178] Resistor R5 is connected between the application terminal of the received pulse signal ON_IN1 and the input terminal of the inverter INV1. Resistor R6 is connected between the application terminal of the received pulse signal ON_IN1 and the input terminal of the buffer BUF1. Resistor R7 is connected between the application terminal of the received pulse signal OFF_IN1 and the input terminal of the inverter INV2. Resistor R8 is connected between the application terminal of the received pulse signal OFF_IN1 and the input terminal of the buffer BUF2.

[0179] Resistor R9 is connected between the application terminal of the received pulse signal ON_IN2 and the input terminal of the inverter INV3. Resistor R10 is connected between the application terminal of the received pulse signal ON_IN2 and the input terminal of the buffer BUF3. Resistor R11 is connected between the application terminal of the received pulse signal OFF_IN2 and the input terminal of the inverter INV4. Resistor R12 is connected between the application terminal of the received pulse signal OFF_IN2 and the input terminal of the buffer BUF4.

[0180] The inverter INV1 inverts the logic level of the received pulse signal ON_IN1 and outputs it. The inverter INV2 inverts the logic level of the received pulse signal OFF_IN1 and outputs it. The inverter INV3 inverts the logic level of the received pulse signal ON_IN2 and outputs it. The inverter INV4 inverts the logic level of the received pulse signal OFF_IN2 and outputs it.

[0181] The buffer BUF1 maintains the logic level of the received pulse signal ON_IN1 and outputs it. The buffer BUF2 maintains the logic level of the received pulse signal OFF_IN1 and outputs it. The buffer BUF3 maintains the logic level of the received pulse signal ON_IN2 and outputs it. The buffer BUF4 maintains the logic level of the received pulse signal OFF_IN2 and outputs it.

[0182] The threshold voltage VthH of each of the inverters INV1 to INV4 may be set to a voltage value higher than the threshold voltage VthL of each of the buffers BUF1 to BUF4. For example, VthH=0.80V. Alternatively, VthL=0.70V.

[0183] The delay circuit DLY1 generates a main signal ON1A from the output signal of the inverter INV1. The delay circuit DLY2 generates a sub-signal ON1B from the output signal of the buffer BUF1. The delay circuit DLY3 generates a main signal OFF1A from the output signal of the inverter INV2. The delay circuit DLY4 generates a sub-signal OFF1B from the output signal of the buffer BUF2. The main signal ON1A, the sub-signal ON1B, the main signal OFF1A, and the sub-signal OFF1B will be described in detail later.

[0184] The delay circuit DLY5 generates the main signal ON2A from the output signal of the inverter INV3. The delay circuit DLY6 generates the sub-signal ON2B from the output signal of the buffer BUF3. The delay circuit DLY7 generates the main signal OFF2A from the output signal of the inverter INV4. The delay circuit DLY8 generates the sub-signal OFF2B from the output signal of the buffer BUF4. The main signal ON2A, the sub-signal ON2B, the main signal OFF2A, and the sub-signal OFF2B will be described in detail later.

[0185] The NOR gate NOR1 generates the set signal SET1 by performing a NOR operation on the primary signal ON1A and the secondary signal OFF1B. Therefore, the set signal SET1 goes low when at least one of the primary signal ON1A and the secondary signal OFF1B is high. On the other hand, the set signal SET1 goes high when both the primary signal ON1A and the secondary signal OFF1B are low.

[0186] The NOR gate NOR2 generates the reset signal RST1 by performing a NOR operation on the primary signal OFF1A and the secondary signal ON1B. Therefore, the reset signal RST1 goes low when at least one of the primary signal OFF1A and the secondary signal ON1B is high. On the other hand, the reset signal RST1 goes high when both the primary signal OFF1A and the secondary signal ON1B are low.

[0187] The NOR gate NOR3 generates the set signal SET2 by performing a NOR operation on the primary signal ON2A and the secondary signal OFF2B. Therefore, the set signal SET2 is at a low level when at least one of the primary signal ON2A and the secondary signal OFF2B is at a high level. On the other hand, the set signal SET2 is at a high level when both the primary signal ON2A and the secondary signal OFF2B are at a low level.

[0188] The NOR gate NOR4 generates the reset signal RST2 by performing a NOR operation on the primary signal OFF2A and the secondary signal ON2B. Therefore, the reset signal RST2 is at a low level when at least one of the primary signal OFF2A and the secondary signal ON2B is at a high level. On the other hand, the reset signal RST2 is at a high level when both the primary signal OFF2A and the secondary signal ON2B are at a low level.

[0189] The RS flip-flop FF1 generates a latch output signal Q1 in response to a set signal SET1 and a reset signal RST1. For example, the RS flip-flop FF1 sets the latch output signal Q1 to a high level when the set signal SET1 rises to a high level. On the other hand, the RS flip-flop FF1 resets the latch output signal Q1 to a low level when the reset signal RST1 rises to a high level.

[0190] The RS flip-flop FF2 generates a latch output signal Q2 in response to the set signal SET2 and the reset signal RST2. For example, the RS flip-flop FF2 sets the latch output signal Q2 to a high level when the set signal SET2 rises to a high level. On the other hand, the RS flip-flop FF2 resets the latch output signal Q2 to a low level when the reset signal RST2 rises to a high level.

[0191] 12 is a diagram showing an example of output control in the first embodiment. This diagram shows the relationship between the pulse generation states of the main signals ON1A, OFF1A, ON2A, and OFF2A and the output state of the signal transmission device 400.

[0192] First, consider the case where the second logic 421 receives the receiving pulse signal ON_IN1 but does not receive any of the other receiving pulse signals OFF_IN1, ON_IN2, and OFF_IN2. In this case, as shown in the first row of the figure, a pulse is generated in the primary signal ON1A, but no pulses are generated in the primary signals OFF1A, ON2A, and OFF2A. Therefore, the set signal SET1 rises to a high level, and the latch output signal Q1 is set to a high level. At this time, the output circuit 422 turns on the transistor P1 and turns off the transistor N1, thereby setting the first output pulse signal OUT1 to a high level. Meanwhile, the output circuit 423 turns off both the transistors P2 and N2, thereby setting the second output pulse signal OUT2 to an output high-impedance state.

[0193] Next, consider a case where the second logic 421 receives the receiving pulse signal OFF_IN1 but does not receive any of the other receiving pulse signals ON_IN1, ON_IN2, and OFF_IN2. In this case, as shown in the second row of the figure, a pulse is generated in the main signal OFF1A, but no pulses are generated in the main signals ON1A, ON2A, and OFF2A. Therefore, the reset signal RST1 rises to a high level, resetting the latch output signal Q1 to a low level. At this time, the output circuit 422 turns off the transistor P1 and turns on the transistor N1, thereby setting the first output pulse signal OUT1 to a low level. Meanwhile, the output circuit 423 turns off both the transistors P2 and N2, thereby setting the second output pulse signal OUT2 to an output high-impedance state.

[0194] Next, consider a case where the second logic 421 receives the receiving pulse signal ON_IN2 but does not receive any of the other receiving pulse signals ON_IN1, OFF_IN1, and OFF_IN2. In this case, as shown in the third row of the figure, a pulse is generated in the primary signal ON2A, but no pulses are generated in the primary signals ON1A, OFF1A, and OFF2A. Therefore, the set signal SET2 rises to a high level, and the latch output signal Q2 is set to a high level. At this time, the output circuit 423 turns on transistor P2 and turns off transistor N2, thereby setting the second output pulse signal OUT2 to a high level. Meanwhile, the output circuit 422 turns off both transistors P1 and N1, thereby setting the first output pulse signal OUT1 to an output high-impedance state.

[0195] Next, consider a case where the second logic 421 receives the receiving pulse signal OFF_IN2 but does not receive any of the other receiving pulse signals ON_IN1, OFF_IN1, and ON_IN2. In this case, as shown in the fourth row of the figure, a pulse is generated in the main signal OFF2A, but no pulses are generated in the main signals ON1A, OFF1A, and ON2A. Therefore, the reset signal RST2 rises to a high level, resetting the latch output signal Q2 to a low level. At this time, the output circuit 423 turns off the transistor P2 and turns on the transistor N2, thereby setting the second output pulse signal OUT2 to a low level. Meanwhile, the output circuit 422 turns off both the transistors P1 and N1, thereby setting the first output pulse signal OUT1 to an output high-impedance state.

[0196] Next, consider the case where the second logic 421 simultaneously receives the received pulse signals ON_IN1 and OFF_IN1. In this case, as shown in the fifth row of the figure, pulses are generated in both the main signals ON1A and OFF1A. However, due to CMTI noise canceling (described later), the set signal SET1 and reset signal RST1 are both maintained at low level.

[0197] Next, consider the case where the second logic 421 simultaneously receives the received pulse signals ON_IN2 and OFF_IN2. In this case, as shown in the sixth row of the figure, pulses are generated in both the main signals ON2A and OFF2A. However, due to CMTI noise canceling (described later), the set signal SET2 and reset signal RST2 are both maintained at low level.

[0198] When a pulse driving signal for turning on / off the switch element SW is transmitted, basically, any one of the received pulse signals ON_IN1, OFF_IN1, ON_IN2, and OFF_IN2 can be pulse-driven in a single phase. Meanwhile, CMTI noise can be superimposed in phase on all of the received pulse signals ON_IN1, OFF_IN1, ON_IN2, and OFF_IN2. CMTI noise cancellation is performed by utilizing this difference in characteristics.

[0199] 13 is a diagram showing an example of CMTI noise canceling. In this diagram, from top to bottom, transmission pulse signals ON_OUT1 and OFF_OUT1, reception pulse signals ON_IN1 and OFF_IN1, main signal ON1A, sub-signal ON1B, main signal OFF1A, sub-signal OFF1B, and first output pulse signal OUT1 are depicted.

[0200] First, the behavior when CMTI noise is not superimposed (in this figure, when the transmission pulse signal ON_OUT1 is being transmitted) will be explained. When a pulse is generated in the transmission pulse signal ON_OUT1, a pulse is also induced in the reception pulse signal ON_IN1 via the transformer 431.

[0201] At this time, the primary signal ON1A falls to a low level a predetermined delay time after the received pulse signal ON_IN1 exceeds the threshold voltage VthH. The primary signal ON1A is maintained at a low level for the pulse width WA, and then rises to a high level again. Meanwhile, the secondary signal ON1B rises to a high level without delay when the received pulse signal ON_IN1 exceeds the threshold voltage VthL. The secondary signal ON1B is maintained at a high level for the pulse width WB, and then falls to a low level again.

[0202] Since no pulse is generated in the transmission pulse signal OFF_OUT1, the sub-signal OFF1B is maintained at a low level. Therefore, when the main signal ON1A falls to a low level, the set signal SET1 (not shown) rises to a high level, and the latch output signal Q1 (not shown) is set to a high level. As a result, the first output pulse signal OUT1 rises to a high level. In this way, when CMTI noise is not superimposed, the main signal ON1A is not masked by the sub-signal OFF1B.

[0203] Next, the behavior when CMTI noise is superimposed will be described. As shown by the dashed frame α in the figure, CMTI noise is superimposed in phase on both the received pulse signals ON_IN1 and OFF_IN1.

[0204] At this time, the primary signals ON1A and OFF1A fall to a low level a predetermined delay time after the receiving pulse signals ON_IN1 and OFF_IN1 exceed the threshold voltage VthH, respectively. Furthermore, the primary signals ON1A and OFF1A are maintained at a low level for the pulse width WA, and then rise to a high level again. Meanwhile, the secondary signals ON1B and OFF1B rise to a high level without delay when the receiving pulse signals ON_IN1 and OFF_IN1 exceed the threshold voltage VthL, respectively. Furthermore, the secondary signals ON1B and OFF1B are maintained at a high level for the pulse width WB, and then fall to a low level again.

[0205] As shown by the dashed-line frame β in the figure, the high-level period of the sub-signal ON1B encompasses the low-level period of the main signal OFF1A. In other words, when the main signal OFF1A is low, the sub-signal ON1B is always high. Therefore, even if the main signal OFF1A falls to low, the reset signal RST1 (not shown) does not rise to high, and as a result, the latch output signal Q1 (not shown) is not reset to low.

[0206] In this way, when CMTI noise is superimposed, the primary signal OFF1A is masked by the secondary signal ON1B. Therefore, even if CMTI noise is superimposed when the first output pulse signal OUT1 is at a high level, the first output pulse signal OUT1 will not be unintentionally pulled down to a low level.

[0207] Furthermore, as shown by the dashed-line frame β in the figure, when CMTI noise is superimposed, the primary signal ON1A is masked by the secondary signal OFF1B. Therefore, even if CMTI noise is superimposed when the first output pulse signal OUT1 is at a low level, the first output pulse signal OUT1 will not be unintentionally raised to a high level.

[0208] In addition, in this diagram, the same CMTI noise canceling as described above can also be performed on the second output pulse signal OUT2. In that case, the transmission pulse signals ON_OUT1 and OFF_OUT1, reception pulse signals ON_IN1 and OFF_IN1, main signal ON1A, sub-signal ON1B, main signal OFF1A, sub-signal OFF1B, and first output pulse signal OUT1 in this diagram can be read as transmission pulse signals ON_OUT2 and OFF_OUT2, reception pulse signals ON_IN2 and OFF_IN2, main signal ON2A, sub-signal ON2B, main signal OFF2A, sub-signal OFF2B, and second output pulse signal OUT2, respectively.

[0209] <Considerations on reducing insulating elements> Incidentally, the signal transmission device 400 of the first embodiment pulse-drives one of the transformers 431 to 434 in a single phase in accordance with the logic levels of the input pulse signal IN and the output selection signal GRSEL.

[0210] For example, referring to FIG. 12, the transformer 431 is pulse-driven in a single phase when the first output state (OUT1=H, OUT2=Hi-Z) is selected. The transformer 432 is pulse-driven in a single phase when the second output state (OUT1=L, OUT2=Hi-Z) is selected. The transformer 433 is pulse-driven in a single phase when the third output state (OUT1=Hi-Z, OUT2=H) is selected. The transformer 434 is pulse-driven in a single phase when the fourth output state (OUT1=Hi-Z, OUT2=L) is selected.

[0211] Therefore, if it is necessary to provide the signal transmission device 400 with output states other than those described above, for example, a fifth output state (OUT1=OUT2=H) and a sixth output state (OUT1=OUT2=L), a transformer must be added to the third chip 430. Furthermore, it may be necessary to add a transformer not only when increasing the output states of the signal transmission device 400 but also when switching the operation mode of the signal transmission device 400.

[0212] In view of the above considerations, a second embodiment will be proposed below that allows the number of output states of the signal transmission device 400 to be increased and the operation mode of the signal transmission device 400 to be switched without the need to add a transformer.

[0213] Second Embodiment 14 is a diagram showing a second embodiment of the signal transmission device 400. The signal transmission device 400 of this embodiment is based on the first embodiment (FIG. 10) described above, and can be in one of first to sixth output states according to the output selection signals GRSEL1 and GRSEL2.

[0214] For example, when (GRSEL1, GRSEL2)=(H, L), the signal transmission device 400 is in either a first output state (OUT1=H, OUT2=Hi-Z) or a second output state (OUT1=L, OUT2=Hi-Z) in response to the input pulse signal IN. Also, for example, when (GRSEL1, GRSEL2)=(L, H), the signal transmission device 400 is in either a third output state (OUT1=Hi-Z, OUT2=H) or a fourth output state (OUT1=Hi-Z, OUT2=L) in response to the input pulse signal IN.

[0215] Furthermore, for example, when (GRSEL1, GRSEL2)=(H, H), the signal transmission device 400 is in the fifth output state (OUT1=OUT2=H) regardless of the input pulse signal IN. Furthermore, for example, when (GRSEL1, GRSEL2)=(L, L), the signal transmission device 400 is in the sixth output state (OUT1=OUT2=L) regardless of the input pulse signal IN.

[0216] Furthermore, the signal transmission device 400 has a serial communication function with the outside of the device and an inter-chip serial communication function between the first chip 410 and the second chip 420, in addition to the main isolated communication function (IN→OUT).

[0217] For example, the first logic 411 performs serial communication with a master (not shown) provided outside the device in accordance with a predetermined communication protocol. In this diagram, the first logic 411 transmits and receives a chip select signal CSB, an input data signal MOSI, an output data signal MISO, and a clock signal SCLK in accordance with the SPI (serial peripheral interface) communication protocol. However, the communication protocol is not limited to this.

[0218] Furthermore, the first logic 411 switches the operation mode of the signal transmission device 400 between PWM (pulse width modulation) mode and SPI communication mode in response to serial communication with an external device. The first logic 411 may switch the operation mode of the signal transmission device 400 from PWM mode to SPI communication mode when the chip select signal CSB is at a low level (=logic level when the chip is selected). The first logic 411 may also switch the operation mode of the signal transmission device 400 from SPI communication mode to PWM mode when detecting a communication end command (or a communication end flag) included in the input data signal MOSI.

[0219] In the PWM mode, the input pulse signal IN is transmitted as the output pulse signal OUT in an insulated manner via the transformers 431 to 434. On the other hand, in the SPI communication mode, bidirectional serial communication is performed between the first logic 411 and the second logic 421 via the transformers 431 to 434 (details will be described later).

[0220] In particular, in the signal transmission device 400 of the second embodiment, in order to realize the above operation without increasing the number of transformers 431 to 434, the first logic 411 and the second logic 421 are each devised.

[0221] Specifically, the first logic 411 is capable of simultaneously transmitting multiple combinations of different sets of signals from a first set of transmission pulse signals ON_OUT1 and OFF_IN1 and a second set of transmission pulse signals ON_OUT2 and OFF_OUT2 (details will be described later).

[0222] In addition, the second logic 421 operates according to the combination of the first set of received pulse signals ON_IN1 and OFF_IN1 and the second set of received pulse signals ON_IN2 and OFF_IN2 received via the transformers 431 to 434 (details will be described later).

[0223] 15 is a diagram showing an example of the second logic 421 in the second embodiment. The second logic 421 of this configuration example is based on the above-mentioned FIG. 11, and further includes NOR gates NOR5 to NOR7, RS flip-flops FF3 and FF4, and mask circuits MSK1 and MSK2. Also, changes have been made to the input signals of the NOR gates NOR1 to NOR4. In the following, redundant explanations of the components already mentioned will be omitted, and the changes from FIG. 11 will be described in detail.

[0224] The NOR gate NOR1 generates the set signal SET1 by performing a NOR operation on four signals: the main signal ON1A, the sub-signal OFF1B, and the newly input sub-signals ON2B and OFF2B. Therefore, the set signal SET1 goes low when at least one of the main signal ON1A and the sub-signals OFF1B, ON2B, and OFF2B is high. On the other hand, the set signal SET1 goes high when all of the main signal ON1A and the sub-signals OFF1B, ON2B, and OFF2B are low.

[0225] The NOR gate NOR2 generates the reset signal RST1 by performing a NOR operation on four signals: the primary signal OFF1A, the sub-signal ON1B, and the newly input sub-signals ON2B and OFF2B. Therefore, the reset signal RST1 goes low when at least one of the primary signal OFF1A and the sub-signals ON1B, ON2B, and OFF2B is high. On the other hand, the reset signal RST1 goes high when all of the primary signal OFF1A and the sub-signals ON1B, ON2B, and OFF2B are low.

[0226] The NOR gate NOR3 generates the set signal SET2 by performing a NOR operation on four signals: the main signal ON2A, the sub-signal OFF2B, and the newly input sub-signals ON1B and OFF1B. Therefore, the set signal SET2 goes low when at least one of the main signal ON2A and the sub-signals OFF2B, ON1B, and OFF1B is high. On the other hand, the set signal SET2 goes high when all of the main signal ON2A and the sub-signals OFF2B, ON1B, and OFF1B are low.

[0227] The NOR gate NOR4 generates the reset signal RST2 by performing a NOR operation on four signals: the primary signal OFF2A, the secondary signal ON2B, and the newly input secondary signals ON1B and OFF1B. Therefore, the reset signal RST2 goes low when at least one of the primary signal OFF2A and the secondary signals ON2B, ON1B, and OFF1B is high. On the other hand, the reset signal RST2 goes high when all of the primary signal OFF2A and the secondary signals ON2B, ON1B, and OFF1B are low.

[0228] The NOR gate NOR5 generates the set signal SET3 by performing a NOR operation on the primary signals ON1A and ON2A. Therefore, the set signal SET3 is at a low level when at least one of the primary signals ON1A and ON2A is at a high level. On the other hand, the set signal SET3 is at a high level when both the primary signals ON1A and ON2A are at a low level.

[0229] The NOR gate NOR6 generates the reset signal RST3 by performing a NOR operation on the main signals OFF1A and OFF2A. Therefore, the reset signal RST3 goes low when at least one of the main signals OFF1A and OFF2A is high. On the other hand, the reset signal RST3 goes high when both the main signals OFF1A and OFF2A are low.

[0230] The NOR gate NOR7 generates the set signal SET4 from the primary signals ON1A and OFF2A by performing a NOR operation. Therefore, the set signal SET4 becomes low when at least one of the primary signals ON1A and OFF2A is high. On the other hand, the set signal SET4 becomes high when both the primary signals ON1A and OFF2A are low. Note that the primary signals OFF1A and ON2A may be input to the NOR gate NOR7 instead of the primary signals ON1A and OFF2A.

[0231] The RS flip-flop FF3 generates a latch output signal Q3 in response to the set signal SET3 and the reset signal RST3. For example, the RS flip-flop FF3 sets the latch output signal Q3 to a high level when the set signal SET3 rises to a high level. On the other hand, the RS flip-flop FF3 resets the latch output signal Q3 to a low level when the reset signal RST3 rises to a high level.

[0232] The RS flip-flop FF4 generates a latch output signal Q4 in response to the set signal SET4 and the reset signal RST4. For example, the RS flip-flop FF4 sets the latch output signal Q4 to a high level when the set signal SET4 rises to a high level. On the other hand, the RS flip-flop FF4 resets the latch output signal Q4 to a low level when the reset signal RST4 rises to a high level. Note that the reset signal RST4 may be, for example, a serial communication end signal SC_END that goes high when serial communication ends.

[0233] The mask circuit MSK1 masks (for example, fixes to low level) the reception pulse signal OFF_IN1 when a pulse occurs in the reception pulse signal ON_IN1. The mask circuit MSK1 also masks (for example, fixes to low level) the reception pulse signal ON_IN1 when a pulse occurs in the reception pulse signal OFF_IN1.

[0234] The mask circuit MSK2 masks (for example, fixes to low level) the reception pulse signal OFF_IN2 when a pulse occurs in the reception pulse signal ON_IN2. The mask circuit MSK2 also masks (for example, fixes to low level) the reception pulse signal ON_IN2 when a pulse occurs in the reception pulse signal OFF_IN2.

[0235] Fig. 16 is a diagram showing an example of output control in the second embodiment. As with Fig. 12, this diagram shows the relationship between the pulse generation states of the main signals ON1A, OFF1A, ON2A, and OFF2A and the output state of the signal transmission device 400. Below, redundant explanations of the operating states already mentioned will be omitted, and the changes from Fig. 12 (the seventh to tenth rows enclosed in bold frames) will be described in detail.

[0236] First, consider the case where the second logic 421 simultaneously receives the receiving pulse signals ON_IN1 and ON_IN2. In this case, as shown in the seventh row of the figure, pulses are generated in both the main signals ON1A and ON2A. Therefore, the set signal SET3 rises to a high level, and the latch output signal Q3 is set to a high level. At this time, the output circuit 422 turns on transistor P1 and turns off transistor N1, thereby setting the first output pulse signal OUT1 to a high level. Furthermore, the output circuit 423 turns on transistor P2 and turns off transistor N2, thereby setting the second output pulse signal OUT2 to a high level.

[0237] When the receiving pulse signals ON_IN1 and ON_IN2 are received simultaneously, not only are pulses generated in both the primary signals ON1A and ON2A, but also in both the secondary signals ON1B and ON2B. The secondary signal ON2B is input to the NOR gates NOR1 and NOR2. Therefore, the set signal SET1 and the reset signal RST1 are maintained at a low level. Furthermore, the secondary signal ON1B is input to the NOR gates NOR3 and NOR4. Therefore, the set signal SET2 and the reset signal RST2 are also maintained at a low level.

[0238] Next, consider the case where the second logic 421 simultaneously receives the receiving pulse signals OFF_IN1 and OFF_IN2. In this case, as shown in the eighth row of the figure, pulses are generated in both the main signals OFF1A and OFF2A. Therefore, the reset signal RST3 rises to a high level, and the latch output signal Q3 is reset to a low level. At this time, the output circuit 422 turns off the transistor P1 and turns on the transistor N1, thereby setting the first output pulse signal OUT1 to a low level. Furthermore, the output circuit 423 turns off the transistor P2 and turns on the transistor N2, thereby setting the second output pulse signal OUT2 to a low level.

[0239] When the received pulse signals OFF_IN1 and OFF_IN2 are received simultaneously, not only are pulses generated in both the primary signals OFF1A and OFF2A, but also in both the secondary signals OFF1B and OFF2B. The secondary signal OFF2B is input to the NOR gates NOR1 and NOR2. Therefore, the set signal SET1 and the reset signal RST1 are maintained at a low level. The secondary signal OFF1B is input to the NOR gates NOR3 and NOR4. Therefore, the set signal SET2 and the reset signal RST2 are also maintained at a low level.

[0240] Next, consider the case where the second logic 421 simultaneously receives the reception pulse signals ON_IN1 and OFF_IN2. In this case, as shown in the ninth row of the figure, pulses are generated in both the main signals ON1A and OFF2A. Therefore, the set signal SET4 rises to a high level, and the latch output signal Q4 is set to a high level. At this time, the second logic 421 switches from a PWM mode in which it receives pulse drive signals (e.g., reception pulse signals ON_IN1, OFF_IN1, ON_IN2, and OFF_IN2) via the transformers 431 to 434 to an SPI communication mode in which it transmits and receives serial communication signals. Meanwhile, when the serial communication end signal SC_END (=reset signal RST4) rises to a high level, the latch output signal Q4 is reset to a low level. At this time, the second logic 421 switches from the SPI communication mode to the PWM mode.

[0241] When the receiving pulse signals ON_IN1 and OFF_IN2 are received simultaneously, not only are pulses generated in both the primary signals ON1A and OFF2A, but also in both the secondary signals ON1B and OFF2B. The secondary signal OFF2B is input to the NOR gates NOR1 and NOR2. Therefore, the set signal SET1 and the reset signal RST1 are maintained at a low level. Furthermore, the secondary signal ON1B is input to the NOR gates NOR3 and NOR4. Therefore, the set signal SET2 and the reset signal RST2 are also maintained at a low level.

[0242] Finally, consider the case where the second logic 421 simultaneously receives the receiving pulse signals ON_IN2 and OFF_IN1. In this case, as shown in the tenth row of the figure, pulses are generated in both the main signals ON2A and OFF1A. In this state, the set signals SET1 to SET4 and the reset signals RST1 to RST4 are all maintained at a low level. Therefore, the output state and operating mode of the signal transmission device 400 do not change. However, the signal transmission device 400 may be configured to switch its output state or operating mode when the receiving pulse signals ON_IN2 and OFF_IN1 are simultaneously received.

[0243] To summarize the bold frames in Figure 16, the transformers 431 and 433 are pulse-driven simultaneously when the fifth output state (OUT1 = OUT2 = H) is selected. The transformers 432 and 434 are pulse-driven simultaneously when the sixth output state (OUT1 = OUT2 = L) is selected. The transformers 431 and 434 (or the transformers 432 and 433) are pulse-driven simultaneously when the operation mode is switched from PWM mode to SPI communication mode.

[0244] In this way, with the signal transmission device 400 of the second embodiment, by simultaneously pulse-driving multiple transformers 431 to 434, it is possible to increase the output states of the signal transmission device 400 and switch the operating mode of the signal transmission device 400 without the need to add additional transformers.

[0245] The number of transformers integrated in the third chip 430 is not limited to four. The more transformers there are, the more combinations of transformers that can be pulse-driven simultaneously. This makes it possible to increase the number of state transition patterns (output states or operation modes) of the signal transmission device 400.

[0246] 17 is a diagram showing the SPI communication mode of the signal transmission device 400. When the signal transmission device 400 is in the SPI communication mode, a first data signal DATA12 is transmitted in an isolated manner from the first chip 410 to the second chip 420 via a transformer 431. Furthermore, a first clock signal CLK12 is transmitted in an isolated manner from the first chip 410 to the second chip 420 via a transformer 432. The first data signal DATA1 may be an operating parameter (detection threshold or release threshold of various protection functions) to be set in the second chip 420.

[0247] Furthermore, when the signal transmission device 400 is in the SPI communication mode, the second data signal DATA21 is transmitted from the second chip 420 to the first chip 410 via the transformer 433. Furthermore, the second clock signal CLK21 is transmitted from the second chip 420 to the first chip 410 via the transformer 434. The second data signal DATA2 may be an operating parameter that has actually been set in the second chip 420.

[0248] In this way, if the transformers 431 to 434 are shared between the PWM mode and the SPI communication mode, it is possible to implement an inter-chip serial communication function without increasing the number of isolation elements integrated into the third chip 430.

[0249] When the signal transmission device 400 is in the SPI communication mode, both the first output pulse signal OUT1 and the second output pulse signal OUT2 may be set to a low level or a high impedance state. With this configuration, unintended driving of the switch element SW can be prevented.

[0250] <Application to vehicles> 18 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0251] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0252] The signal transmission device 200 or 400 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0253] <Additional Notes> According to the present disclosure, the number of insulating elements can be reduced.

[0254] [Appendix 1] First logic (411) and Second logic (421) and a plurality of insulating elements (431 to 434) configured to insulate and transmit a plurality of sets of first signals (ON_IN1 / 2) and second signals (OFF_IN1 / 2) between the first logic (411) and the second logic (421); a plurality of output circuits (422, 423) configured to generate a plurality of output signals (OUT1 / 2), respectively, in response to instructions from the second logic (421); Equipped with The first logic (411) can simultaneously transmit a plurality of different sets of signals from among a plurality of sets of the first signals (ON_IN1 / 2) and the second signals (OFF_IN1 / 2), The second logic (421) is a signal transmission device (400) that performs an operation according to a combination of signals received through a plurality of the insulating elements (431 to 434) from among a plurality of sets of the first signals (ON_IN1 / 2) and the second signals (OFF_IN1 / 2).

[0255] [Appendix 2] the plurality of sets of the first signals (ON_IN1 / 2) and the second signals (OFF_IN1 / 2) include a first set of an on signal (ON_IN1) and an off signal (OFF_IN1) and a second set of an on signal (ON_IN2) and an off signal (OFF_IN2); The signal transmission device (400) described in Appendix 1, wherein the plurality of output circuits (422, 423) include a first output circuit (422) configured to generate a first output signal (OUT1) in response to an instruction from the second logic (421), and a second output circuit (423) configured to generate a second output signal (OUT2) in response to an instruction from the second logic (421).

[0256] [Appendix 3] The signal transmission device (400) described in Appendix 2, wherein the second logic (421) controls the first output circuit (422) and the second output circuit (423) respectively so that when the first set of on signals (ON_IN1) and the second set of on signals (ON_IN2) are received simultaneously, the first output signal (OUT1) and the second output signal (OUT2) are both set to an on logic level, and when the first set of off signals (OFF_IN1) and the second set of off signals (OFF_IN2) are received simultaneously, the first output signal (OUT1) and the second output signal (OUT2) are both set to an off logic level.

[0257] [Appendix 4] The signal transmission device (400) described in Appendix 2 or 3, wherein the second logic (421) switches from a first mode of receiving a pulse drive signal via the plurality of isolation elements (431-434) to a second mode of transmitting and receiving a serial communication signal when the second logic (421) receives the first set of on signals (ON_IN1) and the second set of off signals (OFF_IN2) simultaneously or when the second logic (421) receives the first set of off signals (OFF_IN1) and the second set of on signals (ON_IN2) simultaneously.

[0258] [Appendix 5] The second logic (421) sets the first output signal (OUT1) to a logic level for an on state and sets the second output signal (OUT2) to an output high impedance state when it receives the first set of on signals (ON_IN1) and none of the other signals (OFF_IN1, ON_IN2, OFF_IN2), sets the first output signal (OUT1) to a logic level for an off state and sets the second output signal (OUT2) to an output high impedance state when it receives the first set of off signals (OFF_IN1) and none of the other signals (ON_IN1, ON_IN2, OFF_IN2), and sets the first output signal (OUT1) to a logic level for an off state and sets the second output signal (OUT2) to an output high impedance state when it receives the second set of on signals (ON_IN2) and none of the other signals (ON_IN1, ON_IN2, OFF_IN2). The signal transmission device (400) according to any one of appendices 2 to 4 controls the first output circuit (422) and the second output circuit (423) so that when none of the signals (ON_IN1, OFF_IN1, OFF_IN2) is received, the second output signal (OUT2) is set to an on-time logic level and the first output signal (OUT1) is set to an output high impedance state, and when the second set of off signals (OFF_IN2) is received but none of the remaining signals (ON_IN1, OFF_IN1, ON_IN2) is received, the second output signal (OUT2) is set to an off-time logic level and the first output signal (OUT1) is set to an output high impedance state.

[0259] [Appendix 6] The second logic (421) a first delay circuit (DLY1) configured to generate a first main signal (ON1A) from the first set of on signals (ON_IN1); a second delay circuit (DLY2) configured to generate a first sub-signal (ON1B) from the first set of on-signals (ON_IN1); a third delay circuit (DLY3) configured to generate a second main signal (OFF1A) from the first set of off signals (OFF_IN1); a fourth delay circuit (DLY4) configured to generate a second sub-signal (OFF1B) from the first set of off signals (OFF_IN1); a fifth delay circuit (DLY5) configured to generate a third primary signal (ON2A) from the second set of ON signals (ON_IN2); a sixth delay circuit (DLY6) configured to generate a third sub-signal (ON2B) from the second set of on-signals (ON_IN2); a seventh delay circuit (DLY7) configured to generate a fourth main signal (OFF2A) from the second set of off signals (OFF_IN2); an eighth delay circuit (DLY8) configured to generate a fourth sub-signal (OFF2B) from the second set of off signals (OFF_IN2); 6. A signal transmission device (400) according to any one of appendices 2 to 5, comprising:

[0260] [Appendix 7] The second logic (421) a first logic gate (NOR1) configured to generate a first set signal (SET1) from the first main signal (ON1A), the second sub-signal (OFF1B), the third sub-signal (ON2B) and the fourth sub-signal (OFF2B); a second logic gate (NOR2) configured to generate a first reset signal (RST1) from the second main signal (OFF1A), the first sub-signal (ON1B), the third sub-signal (ON2B) and the fourth sub-signal (OFF2B); a third logic gate (NOR3) configured to generate a second set signal (SET2) from the third main signal (ON2A), the first sub-signal (ON1B), the second sub-signal (OFF1B), and the fourth sub-signal (OFF2B); a fourth logic gate (NOR4) configured to generate a second reset signal (RST2) from the fourth main signal (OFF2A), the first sub-signal (ON1B), the second sub-signal (OFF1B) and the third sub-signal (ON2B); a fifth logic gate (NOR5) configured to generate a third set signal (SET3) from the first primary signal (ON1A) and the third primary signal (ON2A); a sixth logic gate (NOR6) configured to generate a third reset signal (RST3) from the second primary signal (OFF1A) and the fourth primary signal (OFF2A); a seventh logic gate (NOR7) configured to generate a fourth set signal (SET4) from the first primary signal (ON1A) and the fourth primary signal (OFF2A) or from the second primary signal (OFF2A) and the third primary signal (ON2A); 7. The signal transmission device (400) of claim 6, comprising:

[0261] [Appendix 8] The second logic (421) a first flip-flop (FF1) configured to set the first output signal (OUT1) to an on-time logic level and the second output signal (OUT2) to an output high impedance state in response to the first set signal (SET1), and to set the first output signal (OUT1) to an off-time logic level and the second output signal (OUT2) to an output high impedance state in response to the first reset signal (RST1); a second flip-flop (FF2) configured to set the second output signal (OUT2) to an on-state logic level in response to the second set signal (SET2) to put the first output signal (OUT1) into an output high impedance state, and to set the second output signal (OUT2) to an off-state logic level in response to the second reset signal (RST2) to put the first output signal (OUT1) into an output high impedance state; a third flip-flop (FF3) configured to set both the first output signal (OUT1) and the second output signal (OUT2) to an on-state logic level in response to the third set signal (SET3), and to set both the first output signal (OUT1) and the second output signal (OUT2) to an off-state logic level in response to the third reset signal (RST3); a fourth flip-flop (FF4) configured to switch the operation mode of the second logic (421) from a first mode in which a pulse drive signal is received via the plurality of isolation elements (431 to 434) to a second mode in which a serial communication signal is transmitted and received in response to the fourth set signal (SET4), and to switch the operation mode of the second logic (421) from the second mode to the first mode in response to a fourth reset signal (RST4); 8. The signal transmission device (400) of claim 7, comprising:

[0262] [Appendix 9] An electronic device (A) comprising a signal transmission device (400) according to any one of appendices 1 to 8.

[0263] [Appendix 10] A vehicle (B) equipped with an electronic device (A) according to Appendix 9.

[0264] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0265] 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Signal Transmission Device 410 First Chip 411 First Logic 420 Second Chip 421 Second Logic 422, 423 output circuit 430 3rd Chip 431, 432, 433, 434 Transformers (Isolation elements) 431p, 432p, 433p, 434p Primary coil 431s, 432s, 433s, 434s Secondary coil a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B vehicle BUF1~BUF4 buffers D1~D4 Diodes DLY1~DLY8 delay circuits FF1~FF4 RS flip-flop INV1~INV4 inverters L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil MSK1, MSK2 mask circuits N1, N2 transistors (NMOSFET) NOR1~NOR7 NOT OR gates P1, P2 transistors (PMOSFET) R1~R12 Resistors SW switch element T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 Internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. The first logic; The second logic; a plurality of isolation elements configured to insulate and transmit a plurality of sets of first signals and second signals between the first logic and the second logic, respectively; a plurality of output circuits configured to generate a plurality of output signals, respectively, in response to instructions from the second logic; Equipped with the first logic is capable of simultaneously transmitting a plurality of combinations of different sets of signals from among a plurality of sets of the first signals and the second signals; The second logic performs an operation according to a combination of signals received via a plurality of the isolation elements, among a plurality of pairs of the first signal and the second signal.

2. the plurality of sets of first signals and second signals include a first set of on signals and off signals and a second set of on signals and off signals; 2. The signal transmission device according to claim 1, wherein the plurality of output circuits include a first output circuit configured to generate a first output signal in response to an instruction from the second logic, and a second output circuit configured to generate a second output signal in response to an instruction from the second logic.

3. 3. The signal transmission device according to claim 2, wherein the second logic controls the first output circuit and the second output circuit so that when the first set of on signals and the second set of on signals are received simultaneously, the first output signal and the second output signal are both set to an on logic level, and when the first set of off signals and the second set of off signals are received simultaneously, the first output signal and the second output signal are both set to an off logic level.

4. 3. The signal transmission device according to claim 2, wherein the second logic switches from a first mode in which pulse drive signals are received via the plurality of isolation elements to a second mode in which serial communication signals are transmitted and received when the first set of on signals and the second set of off signals are received simultaneously or when the first set of off signals and the second set of on signals are received simultaneously.

5. 3. The signal transmission device according to claim 2, wherein the second logic controls the first output circuit and the second output circuit so that, when the first set of on signals is received but none of the other signals are received, the first output signal is set to an on-time logic level, putting the second output signal into an output high-impedance state; when the first set of off signals is received but none of the other signals are received, the first output signal is set to an off-time logic level, putting the second output signal into an output high-impedance state; when the second set of on signals is received but none of the other signals are received, the second output signal is set to an on-time logic level, putting the first output signal into an output high-impedance state; and when the second set of off signals is received but none of the other signals are received, the second output signal is set to an off-time logic level, putting the first output signal into an output high-impedance state.

6. The second logic: a first delay circuit configured to generate a first main signal from the first set of ON signals; a second delay circuit configured to generate a first sub-signal from the first set of ON signals; a third delay circuit configured to generate a second main signal from the first set of off signals; a fourth delay circuit configured to generate a second sub-signal from the first set of off signals; a fifth delay circuit configured to generate a third primary signal from the second set of ON signals; a sixth delay circuit configured to generate a third sub-signal from the second set of ON signals; a seventh delay circuit configured to generate a fourth main signal from the second set of OFF signals; an eighth delay circuit configured to generate a fourth sub-signal from the second set of OFF signals; The signal transmission device of claim 2 , comprising:

7. The second logic: a first logic gate configured to generate a first set of signals from the first primary signal, the second secondary signal, the third secondary signal, and the fourth secondary signal; a second logic gate configured to generate a first reset signal from the second primary signal, the first secondary signal, the third secondary signal, and the fourth secondary signal; a third logic gate configured to generate a second set of signals from the third primary signal, the first secondary signal, the second secondary signal, and the fourth secondary signal; a fourth logic gate configured to generate a second reset signal from the fourth main signal, the first sub-signal, the second sub-signal, and the third sub-signal; a fifth logic gate configured to generate a third set of signals from the first primary signal and the third primary signal; a sixth logic gate configured to generate a third reset signal from the second primary signal and the fourth primary signal; a seventh logic gate configured to generate a fourth set signal from the first primary signal and the fourth primary signal or from the second primary signal and the third primary signal; The signal transmission device of claim 6 , comprising:

8. The second logic: a first flip-flop configured to set the first output signal to an ON logic level in response to the first set signal, to place the second output signal in an output high impedance state, and to set the first output signal to an OFF logic level in response to the first reset signal, to place the second output signal in an output high impedance state; a second flip-flop configured to set the second output signal to an ON logic level in response to the second set signal, to place the first output signal in an output high impedance state, and to set the second output signal to an OFF logic level in response to the second reset signal, to place the first output signal in an output high impedance state; a third flip-flop configured to set both the first output signal and the second output signal to an ON logic level in response to the third set signal, and to set both the first output signal and the second output signal to an OFF logic level in response to the third reset signal; a fourth flip-flop configured to switch an operation mode of the second logic from a first mode in which a pulse drive signal is received via the plurality of isolation elements to a second mode in which a serial communication signal is transmitted and received in response to the fourth set signal, and to switch the operation mode of the second logic from the second mode to the first mode in response to a fourth reset signal; The signal transmission device of claim 7, comprising:

9. An electronic device comprising the signal transmission device according to any one of claims 1 to 8.

10. A vehicle comprising the electronic device according to claim 9.

Images