Semiconductor device and electronic apparatus having semiconductor device

Abstract

To provide a semiconductor device having improved a generation of write-in voltage.SOLUTION: A semiconductor device 100 includes an oscillation circuit OSC, signal generation circuits 10 and 20 configured to generate pulse signals HICLK and HIBCLK, and a charge pump circuit 2. The signal generation circuits 10 and 20 include high-side switches Q1 and Q3, low-side switches Q2 and Q4, and an output restriction circuit 30 configured to restrict high level voltage values of the pulse signals HICLK and HIBCLK to values lower than a voltage value of input voltage Vcc.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a semiconductor device and an electronic device including the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there are semiconductor devices equipped with a charge pump circuit, which generates a write voltage by boosting the voltage of the charge pump and performs operations of erasing and writing data to a nonvolatile memory.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-124078

[0005] [overview] The semiconductor device disclosed in Patent Document 1 leaves room for further consideration regarding generation of the write voltage.

[0006] The semiconductor device disclosed in this specification includes an oscillator circuit, a signal generation circuit, and a charge pump circuit. The oscillator circuit is configured to generate a reference clock signal. The signal generation circuit is configured to generate a pulse signal that is in phase or opposite phase to the reference clock signal and has high-level and low-level voltage values ​​corresponding to an input voltage. The charge pump circuit is configured to generate a boosted voltage that is higher than the input voltage in response to the pulse signal. The signal generation circuit includes a high-side switch and a low-side switch connected in series between an application terminal for the input voltage and an application terminal for the low-level voltage, and an output limiting circuit connected between the high-side switch and a connection node between the high-side switch and the low-side switch, and configured to limit the high-level voltage value of the pulse signal to a value lower than the voltage value of the input voltage.

[0007] The electronic device disclosed in this specification includes the semiconductor device having the above-described configuration and an electronic circuit configured to be driven by receiving an input of a boosted voltage. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a semiconductor device 50 of a comparative example. [Figure 2] FIG. 2 is a graph showing the in-phase clock signal HICLK and the write voltage VPP during the charge pump operation of the charge pump circuit 2. As shown in FIG. [Figure 3] FIG. 3 is a diagram showing the configuration of the semiconductor device 100. As shown in FIG. [Figure 4] FIG. 4 is a diagram showing the internal configuration of the boost clock generation circuit 1x. [Figure 5] FIG. 5 is a timing chart showing pulse waveforms of the reference clock signal CLK and the in-phase clock signal HICLK. [Figure 6] FIG. 6 is a graph showing the in-phase clock signal HICLK and the write voltage VPP during the charge pump operation of the charge pump circuit 2. [Figure 7]FIG. 7 is a diagram showing the output limiting circuit 30 of the semiconductor device 100 according to the second embodiment. [Figure 8] FIG. 8 is a graph showing the relationship between the drive voltage Vreg and the voltage value of the in-phase clock signal HICLK at a high level, and the temperature. [Figure 9] FIG. 9 is a graph showing the relationship between the voltage value of the write voltage VPP and the temperature.

[0009] [Detailed explanation] First, the semiconductor device 50 will be described as a comparative example to the semiconductor device 100 of the present disclosure. Next, problems with the comparative example will be described, followed by a description of the semiconductor device 100 of the present disclosure.

[0010] <Regarding the semiconductor device 50 of the comparative example> 1 is a diagram illustrating a semiconductor device 50 according to a comparative example. The semiconductor device 50 according to the comparative example is configured to generate a write voltage VPP for erasing and writing data in a nonvolatile memory (not shown) (e.g., an EEPROM [Electrically Erasable Programmable Read-Only Memory], etc.). As shown in FIG. 1, the semiconductor device 50 includes an oscillator OSC, a boost clock generation circuit 1y, a charge pump circuit 2, a voltage detection circuit 3, and an input voltage generation circuit 4.

[0011] The oscillator OSC generates a reference clock signal CLK that pulses at a predetermined cycle. The oscillator OSC may be, for example, a ring oscillator (not shown) configured to include multiple inverter stages.

[0012] The boost clock generation circuit 1y receives a reference clock signal CLK and generates an in-phase clock signal HICLK and an anti-phase clock signal HIBCLK. The in-phase clock signal HICLK is a pulse signal in phase with the reference clock signal CLK. The anti-phase clock signal HIBCLK is a pulse signal in phase with the reference clock signal CLK and the in-phase clock signal HICLK.

[0013] The charge pump circuit 2 is a Dickson-type charge pump circuit composed of multiple stages, from the first stage St1 to the final stage Stn. Each stage includes capacitors C1 to Cn and rectifier elements T1 to Tn (diode-connected MOSFETs [Metal-Oxide-Semiconductor Field-Effect Transistors]). The gates of the capacitor C1 and rectifier element T1 in the first stage St1 are connected to the terminal to which the input voltage Vin is applied. The source of the rectifier element Tn in the final stage Stn is connected to the output terminal of the charge pump circuit 2 (the terminal to which the write voltage VPP is applied).

[0014] The first terminals of the capacitors C1 to Cn are connected to the drain and gate of the rectifying elements T1 to Tn, respectively. The second terminals of the capacitors C1 to Cn in the odd-numbered stages are connected to the signal line of the in-phase clock signal HICLK. The capacitors C2 to Cn-1 in the even-numbered stages are connected to the signal line of the anti-phase clock signal HIBCLK.

[0015] The voltage detection circuit 3 is connected to the output terminal of the write voltage VPP. The voltage detection circuit 3 monitors the write voltage VPP and generates an enable signal EN according to the write voltage VPP. The boost clock generation circuit 1y starts / stops generating the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK upon receiving the enable signal EN. Specifically, this is as follows.

[0016] The voltage detection circuit 3 drops the enable signal EN to low level when the write voltage VPP becomes equal to or higher than the target voltage, and raises the enable signal EN to high level when the write voltage VPP falls below the target voltage. When the enable signal EN falls to low level, the boost clock generation circuit 1y stops generating the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK. Conversely, when the enable signal EN rises to high level, the boost clock generation circuit 1y resumes generating the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK.

[0017] The input voltage generating circuit 4 is connected between the application terminal of the power supply voltage Vcc and the charge pump circuit 2. The input voltage generating circuit 4 receives the supply of the power supply voltage Vcc and generates the input voltage Vin.

[0018] The odd-numbered capacitors C1 to Cn are charged and discharged by the potential difference between the input voltage Vin and the in-phase clock signal HICLK, and the even-numbered capacitors C2 to Cn-1 are charged and discharged by the potential difference between the input voltage Vin and the out-of-phase clock signal HIBCLK. The oscillator OSC generates the desired write voltage VPP by boosting the input voltage Vin while charging and discharging each of the capacitors C1 to Cn as described above.

[0019] As described above, the boost clock generation circuit 1y repeatedly starts and stops generating the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK in response to the monitoring state (=logic level of the enable signal EN) of the write voltage VPP by the voltage detection circuit 3. This repetition stabilizes the write voltage VPP at around the target voltage.

[0020] 2 is a graph showing the in-phase clock signal HICLK, the write voltage VPP, and the node voltage Vn-1 during the charge pump operation of the charge pump circuit 2. The node voltage Vn-1 is the voltage generated at the connection node between the rectifier element Tn-1 and the rectifier element Tn (see FIG. 1).

[0021] 2, when the charge pump operation starts, the in-phase clock signal HICLK pulses at a predetermined cycle. As described above, the write voltage VPP is boosted to the desired voltage value VPPa by repeatedly charging and discharging using the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK.

[0022] A ripple voltage Vrpy1 occurs in the write voltage VPP, and a ripple voltage Vrpy2 occurs in the node voltage Vn-1.

[0023] At this time, the amplitude of the in-phase clock signal HICLK corresponds to the power supply voltage Vcc. Therefore, when the voltage values ​​of the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK are at a low level, they correspond to the ground voltage GND (0 V in this case), and when they are at a high level, they correspond to the power supply voltage Vcc, as shown in FIG.

[0024] <Considerations on the amplitude of the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK> As described above, the amplitudes of the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK correspond to the voltage value of the power supply voltage Vcc. If the voltage value of the power supply voltage Vcc is set to a relatively high value, the following problems may occur.

[0025] One problem is that the ripple voltage Vrpy1 and the ripple voltage inside the charge pump circuit 2 (for example, the ripple voltage Vrpy2 shown in FIG. 2) may become large. If the ripple voltage inside the charge pump circuit 2 becomes large, the voltage inside the charge pump circuit 2 (for example, the node voltage Vn-1 shown in FIG. 2) may reach the breakdown voltage of each element (specifically, the capacitors C1 to Cn and the rectifying elements T1 to Tn) that make up the charge pump circuit 2. This may result in the destruction of the elements.

[0026] If high-voltage elements are used as the capacitors C1 to Cn and the rectifying elements T1 to Tn in order to prevent such element breakdown, the circuit area of ​​the charge pump circuit 2 may increase, and the cost of the semiconductor device 50 may also increase. Furthermore, if the voltage value of the write voltage VPP is set low in order to prevent element breakdown, the write capability (write speed, number of writes, etc.) of the nonvolatile memory may decrease.

[0027] Furthermore, if the ripple voltage Vrpy1 becomes large, the ripple voltage Vrpy1 may generate relatively large noise in various places inside the IC (= semiconductor device 50, or electronic device in which the semiconductor device 50 is mounted). This noise may lead to malfunctions inside the IC, set failures, etc.

[0028] Another problem is the risk of unnecessary operating current consumption. Specifically, this is as follows. When the voltage value of the power supply voltage Vcc is near the upper limit of the operating voltage range of the charge pump circuit 2 (= the voltage range of the power supply voltage Vcc required for the charge pump circuit 2 to operate), the charge pump circuit 2 generates the write voltage VPP with a relatively large margin for its own boosting capability. This results in unnecessary operating current consumption during charge pump operation. More specifically, this is as follows.

[0029] The operating current of the charge pump circuit 2 is determined by "capacitor capacitance × frequency of the in-phase clock signal HICLK × amplitude of the write voltage VPP." According to this formula, for example, when the power supply voltage Vcc is near the upper limit of the operating voltage range, i.e., when the amplitude of the write voltage VPP is relatively large, the operating current of the charge pump circuit 2 increases. This increases the power consumption of the charge pump circuit 2, which may reduce the power consumption efficiency of the semiconductor device 50.

[0030] On the other hand, the semiconductor device 100 of the present disclosure is capable of suppressing the occurrence of the various problems described above. The semiconductor device 100 according to the embodiment of the present disclosure and the electronic device 200 including the semiconductor device 100 will be described in detail below. Note that the semiconductor device 100 according to each embodiment of the present disclosure includes configurations in common with the semiconductor device 50 described above. For this reason, the common configurations are denoted by the same reference numerals and descriptions thereof will be omitted.

[0031] <Regarding the semiconductor device 100 according to the first embodiment of the present disclosure> 3 is a diagram showing the configuration of the electronic device 200. The electronic device 200 includes a memory circuit 150 and a semiconductor device 100.

[0032] The memory circuit 150 is a nonvolatile memory such as an EEPROM, etc. The memory circuit 150 includes a memory cell array MCA, a row decoder RD, and a column decoder CD.

[0033] The semiconductor device 100 includes the same oscillator OSC as described above, a charge pump circuit 2, a voltage detection circuit 3, and an input voltage generation circuit 4. In addition, the semiconductor device 100 includes a boost clock generation circuit 1x and a control circuit 5.

[0034] The boost clock generation circuit 1x receives a reference clock signal CLK and generates an in-phase clock signal HICLK and an anti-phase clock signal HIBCLK. Similar to the above-mentioned boost clock generation circuit 1y, the boost clock generation circuit 1x receives an enable signal EN and starts / stops generating the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK. A detailed configuration of the boost clock generation circuit 1x will be described later.

[0035] The control circuit 5 is connected between the application terminal of the write voltage VPP and the memory circuit 150. The control circuit 5 generates a write signal S1 based on the write voltage VPP in response to a write operation to the memory circuit 150. The write signal S1 is a digital signal consisting of high-level (=write voltage VPP level) and low-level (=ground voltage GND level) voltage values. The control circuit 5 applies the write signal S1 to the row decoder RD, the column decoder CD, and the memory cell array MCA to erase and write data in the memory circuit 150.

[0036] <About the boost clock generation circuit 1x> 4 is a diagram showing the internal configuration of the boost clock generation circuit 1x. As shown in Fig. 4, the boost clock generation circuit 1x includes an in-phase signal generation circuit 10, an anti-phase signal generation circuit 20, and an output limiting circuit 30.

[0037] The in-phase signal generating circuit 10 generates an in-phase clock signal HICLK in response to a reference clock signal CLK. The detailed configuration of the in-phase signal generating circuit 10 is as follows.

[0038] The in-phase signal generating circuit 10 includes transistors Q1 and Q2, a NAND circuit N1, and a buffer circuit Bf1.

[0039] Transistor Q1 is a P-channel MOSFET. Transistor Q2 is an N-channel MOSFET. Transistors Q1 and Q2 are connected in series between the power supply voltage Vcc application terminal and the ground terminal GND. More specifically, the configuration is as follows.

[0040] The source of transistor Q1 is connected to the application terminal of power supply voltage Vcc. The drain of transistor Q1 is connected to the source of transistor Q5 (described later). The source of transistor Q2, together with the drain of transistor Q5 (described later), is connected to the output terminal of the in-phase clock signal HICLK. The gates of transistors Q1 and Q2 are connected to each other.

[0041] The NAND circuit N1 generates an output signal corresponding to a reference clock signal CLK input to its first terminal and a drive signal G2 (described later). The buffer circuit Bf1 generates a drive signal G1 by performing a predetermined buffering process on the output signal of the NAND circuit N1 and inputs the drive signal G1 to the gates of the transistors Q1 and Q2. The transistors Q1 and Q2 are turned on and off by the drive signal G1.

[0042] The reverse-phase signal generating circuit 20 generates the reverse-phase clock signal HIBCLK in response to the reference clock signal CLK. The detailed configuration of the reverse-phase signal generating circuit 20 is as follows.

[0043] The reverse phase signal generating circuit 20 includes transistors Q3 and Q4, an inverter circuit IV1, a NAND circuit N2, and a buffer circuit Bf2.

[0044] Transistor Q3 is a P-channel MOSFET. Transistor Q4 is an N-channel MOSFET. Transistors Q3 and Q4 are connected in series between the power supply voltage Vcc application terminal and the ground terminal GND. More specifically, the following applies.

[0045] The source of transistor Q3 is connected to the application terminal of power supply voltage Vcc. The drain of transistor Q4 is connected to the source of transistor Q6 (described later). The source of transistor Q4, together with the drain of transistor Q6 (described later), is connected to the output terminal of the inverted clock signal HIBCLK. The gates of transistors Q3 and Q4 are connected to each other. Transistors Q3 and Q4 are controlled to be turned on and off by drive signal G1.

[0046] The inverter circuit IV1 inverts the logic level of the reference clock signal CLK and inputs the inverted output signal to a first terminal of the NAND circuit N2. The NAND circuit N2 generates an output signal corresponding to the output signal of the inverter circuit IV1 and the drive signal G1 input to its second terminal. The buffer circuit Bf2 performs a predetermined buffering process on the output signal of the NAND circuit N2 to generate the drive signal G2 and inputs it to the gates of the transistors Q3 and Q4.

[0047] By logical operations by the NAND circuits N1 and N2, the drive signal G1 becomes a pulse signal in phase with the reference clock signal CLK, and the drive signal G2 becomes a pulse signal in opposite phase to the reference clock signal CLK.

[0048] The output limiting circuit 30 includes a drive voltage generating circuit 31 and transistors Q5 and Q6.

[0049] The drive voltage generating circuit 31 receives the reference voltage Vref and generates the drive voltage Vreg, as follows.

[0050] The drive voltage generating circuit 31 includes an amplifier AP1 and variable resistors VR1 and VR2. The reference voltage Vref is a predetermined constant voltage. The reference voltage Vref is input to the non-inverting input terminal (+) of the amplifier AP1. The output terminal of the amplifier AP1 is connected to the inverting input terminal (-) of the amplifier AP1 via the variable resistor VR1. In this way, the amplifier AP1 outputs the drive voltage Vreg by negative feedback control in which the output is input to the inverting input terminal (-).

[0051] The variable resistors VR1 and VR2 are connected in series to form a voltage divider circuit. Specifically, the first terminal of the variable resistor VR1 is connected to the output terminal of the amplifier AP1. The second terminal of the variable resistor VR2 is connected to the inverting input terminal (-) of the amplifier AP1. The first terminal of the variable resistor VR2 is connected to the connection node between the variable resistor VR1 and the inverting input terminal (-) of the amplifier AP1. The second terminal of the variable resistor VR2 is connected to the ground terminal GND.

[0052] The drive voltage Vreg is divided by a voltage division ratio according to the resistance values ​​of the variable resistors VR1 and VR2, and input to the non-inverting input terminal (-) of the amplifier AP1 as a feedback input. Therefore, the amplifier AP1 outputs the drive voltage Vreg by negative feedback amplifier control so that the divided voltage obtained by dividing the drive voltage Vreg is equal to the reference voltage Vref (= imaginary short). In other words, the voltage value of the drive voltage Vreg can be set to a desired value by varying the resistance values ​​of the variable resistors VR1 and VR2.

[0053] The transistors Q5 and Q6 are depletion-mode N-channel MOSFETs. The gates of the transistors Q5 and Q6 are both connected to the output terminal of the amplifier AP1. The transistors Q5 and Q6 are driven and controlled by the drive voltage Vreg. In other words, the on-resistance of the transistors Q5 and Q6 changes depending on the drive voltage Vreg.

[0054] <Output Limitation by Output Limiting Circuit 30> The output limiting circuit 30 limits the voltage values ​​of the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK when they are at high level to a value lower than the power supply voltage Vcc.

[0055] When the drive signal G1 is at a high level, the transistor Q1 is turned off and the transistor Q2 is turned on, and the in-phase clock signal HICLK becomes a low level (=ground voltage GND reference).

[0056] Conversely, when drive signal G1 is low, transistor Q1 is on and transistor Q2 is off. At this time, the in-phase clock signal HICLK goes high. Here, transistor Q5 is on with a certain on-resistance according to drive voltage Vreg. For this reason, the voltage value of the high-level in-phase clock signal HICLK is a value obtained by dropping the drain-source voltage of transistor Q5 from the power supply voltage Vcc.

[0057] Similarly, the negative-phase clock signal HIBCLK is low (based on the ground voltage GND) when the drive signal G2 is high, and is high when the drive signal G2 is low. When high, the negative-phase clock signal HIBCLK is a voltage drop from the power supply voltage Vcc by the drain-source voltage of transistor Q6.

[0058] In this way, the output limiting circuit 30 limits the voltage values ​​of the in-phase clock signal HICLK and the anti-phase clock signal HIBCLK when they are at high level to a value lower than the power supply voltage Vcc (=a value corresponding to the on-resistance of the transistors Q5 and Q6).

[0059] 5 is a timing chart showing pulse waveforms of the reference clock signal CLK and the in-phase clock signal HICLK. Fig. 5 shows the in-phase clock signal HICLK when the power supply voltage Vcc has a first voltage value Vcc1, a second voltage value Vcc2, a third voltage value Vcc3, and a fourth voltage value Vcc4. The in-phase clock signal HICLK generated by the boost clock generation circuit 1y according to the comparative example is indicated by a dashed line, and the in-phase clock signal HICLK generated by the boost clock generation circuit 1x according to the present disclosure is indicated by a solid line.

[0060] As shown in Fig. 5, the voltage value of the reference clock signal CLK at a high level is equivalent to the voltage value of the power supply voltage Vcc. Furthermore, as shown by the dashed line in Fig. 5, the voltage value of the in-phase clock signal HICLK at a high level according to the comparative example is equivalent to the voltage value of the power supply voltage Vcc. On the other hand, as shown by the solid line in Fig. 5, the voltage value of the in-phase clock signal HICLK at a high level according to the present disclosure is substantially constant, regardless of the magnitude of the voltage value of the power supply voltage Vcc.

[0061] 6 is a graph showing the in-phase clock signal HICLK, the write voltage VPP, and the node voltage Vn-1 during charge pump operation of the charge pump circuit 2. As shown in FIG. 6, when the charge pump operation starts, the in-phase clock signal HICLK pulses at a predetermined cycle. The amplitude of the in-phase clock signal HICLK is smaller than the voltage value of the power supply voltage Vcc.

[0062] The write voltage VPP is boosted to the desired voltage value by repeatedly charging and discharging according to the in-phase clock signal HICLK and the out-of-phase clock signal HIBCLK. A ripple voltage Vrpx1 occurs in the write voltage VPP. A ripple voltage Vrpx2 also occurs in the node voltage Vn-1 (see Figure 1).

[0063] As shown in Fig. 6, the ripple voltages Vrpx1 and Vrpx2 are relatively small. In particular, the ripple voltages Vrpx1 and Vrpx2 are small compared to the ripple voltages Vrpy1 and Vrpy2 (see Fig. 2) described above.

[0064] As described above, according to the semiconductor device 100 of the above embodiment, the voltage value of the high-level write voltage VPP can be made lower than the voltage value of the power supply voltage Vcc. This makes it possible to make the ripple voltage Vrpx1 and the ripple voltage inside the charge pump circuit 2 (e.g., ripple voltage Vrpx2) relatively small. This prevents the voltage inside the charge pump circuit 2 (e.g., node voltage Vn-1) from reaching the breakdown voltage of each element (specifically, capacitors C1 to Cn and rectifying elements T1 to Tn) that make up the charge pump circuit 2. This in turn prevents breakdown of elements inside the charge pump circuit 2.

[0065] Furthermore, it is possible to prevent breakdown of elements inside the charge pump circuit 2 without requiring each element constituting the charge pump circuit 2 to withstand high voltages, thereby preventing increases in circuit area and manufacturing costs.

[0066] Furthermore, it is possible to prevent breakdown of elements inside the charge pump circuit 2 without reducing the write voltage VPP, and therefore it is possible to prevent a decrease in the write capability (=write speed, number of writes, etc.) for the nonvolatile memory.

[0067] As described above, the ripple voltage Vrpx1 is relatively small, which makes it possible to suppress noise generation at various locations inside the IC (=semiconductor device 100 or electronic device incorporating the semiconductor device 100).

[0068] As described above, the operating current of the charge pump circuit 2 is determined by "capacitor capacitance × frequency of the in-phase clock signal HICLK × amplitude of the write voltage VPP." Therefore, even if the power supply voltage Vcc is near the upper limit of the operating voltage range, the write voltage VPP is limited as described above, so the operating current of the charge pump circuit 2 is also smaller than a predetermined value. Therefore, according to the semiconductor device 100, it is possible to prevent the operating current of the charge pump circuit 2 from becoming unnecessarily large, and to prevent a decrease in power consumption efficiency.

[0069] <Increase in current load of charge pump circuit 2 at high temperatures> Here, at high temperatures, the leakage current increases, increasing the current load of the charge pump circuit 2. When the current load exceeds a predetermined value (i.e., when the temperature exceeds a predetermined value), the write voltage VPP output by the charge pump circuit 2 drops below the target voltage VPPa.

[0070] In contrast, the semiconductor device 100 according to the second embodiment is configured to maintain the write voltage VPP at the target value VPPa until the temperature reaches a relatively high level. The second embodiment of the semiconductor device 100 will be described below. Note that the following will focus on differences from the first embodiment, and the same components as those in the first embodiment will be denoted by the same reference numerals and will not be described again.

[0071] <Regarding the semiconductor device 100 according to the second embodiment> The output limiting circuit 30 of this embodiment is configured to have a positive temperature characteristic. Specifically, this is as follows.

[0072] 7 is a diagram showing the output limiting circuit 30 of the semiconductor device 100 according to the second embodiment. As shown in FIG. 7, the output limiting circuit 30 includes a temperature detection circuit 32 in addition to the configuration described above. The temperature detection circuit 32 detects the temperature, generates a control signal S2 corresponding to the detected temperature (=detection result), and inputs the control signal S2 to the variable resistors VR1 and VR2. More specifically, the temperature detection circuit 32 changes the resistance values ​​of the variable resistors VR1 and VR2 using the control signal S2 so that the drive voltage Vreg increases as the detected temperature increases.

[0073] For example, the temperature detection circuit 32 has a diode (not shown) and is configured to be able to detect temperature from fluctuations in the forward voltage of the diode due to its temperature characteristics. The temperature detection circuit 32 is configured to analogically fluctuate the voltage value of the control signal S2 so as to correspond to the forward voltage of the diode (and therefore the temperature characteristics of the diode).

[0074] 8 is a graph showing the relationship between the drive voltage Vreg and the voltage value of the in-phase clock signal HICLK at a high level and temperature. As shown in FIG. 8, the output limiting circuit 30 increases the drive voltage Vreg as the temperature increases.

[0075] As the drive voltage Vreg increases, the on-resistance of the transistors Q5 and Q6 decreases. That is, as shown in FIG. 8, the voltage values ​​of the high-level in-phase clock signal HICLK and the anti-phase clock signal HIBCLK (not shown) increase in response to an increase in the drive voltage Vreg. This increases the potential difference between the high-level in-phase clock signal HICLK and the anti-phase clock signal HIBCLK and the input voltage Vin. Therefore, the boosting capability of the charge pump circuit 2 improves in response to an increase in the detected temperature.

[0076] FIG. 9 is a graph showing the relationship between the voltage value of the write voltage VPP and temperature. In FIG. 9, the graph of the write voltage VPP generated by the semiconductor device 50 of the comparative example is shown by a dashed line. The graph of the write voltage VPP generated by the semiconductor device 100 of this embodiment is shown by a solid line. As shown in FIG. 9, in the semiconductor device 50, when the temperature reaches a predetermined first temperature t1, the write voltage VPP drops from the target value VPPa. In contrast, in the semiconductor device 100 of this embodiment, the write voltage VPP is maintained at the target value VPPa until the temperature rises and reaches a second temperature t2 that is higher than the first temperature t1. In this way, in the semiconductor device 100, the write voltage VPP can be maintained at the target value until the detected temperature reaches a relatively high temperature.

[0077] <Modification> The present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, although the transistors Q5 and Q6 are described as being depression-type MOSFETs, they can be enhancement-type MOSFETs. Furthermore, in this case, the transistors Q5 and Q6 can be P-channel MOSFETs.

[0078] In addition, the temperature detection circuit 32 has a diode and detects temperature by detecting a change in the forward voltage of the diode, but this is not limited to this. As long as the drive voltage Vreg can be controlled to have a positive temperature characteristic, the temperature detection means is not limited to this and a predetermined temperature sensor or the like can be used.

[0079] <Additional Notes> The semiconductor device (100) disclosed in this specification comprises an oscillator circuit (OSC) configured to generate a reference clock signal (CLK), signal generation circuits (10, 20) configured to generate pulse signals (HICLK, HIBCLK) that are in phase or opposite phase to the reference clock signal (CLK) and have high-level and low-level voltage (GND) values ​​according to an input voltage (Vcc), and a charge pump circuit (2) configured to generate a boost voltage (VPP) that is higher than the input voltage (Vcc) according to the pulse signals (HICLK, HIBCLK), The signal generating circuits (10, 20) are configured to include high-side switches (Q1, Q3) and low-side switches (Q2, Q4) connected in series between an application terminal of an input voltage (Vcc) and an application terminal of a low-level voltage (GND), and an output limiting circuit (30) connected between the high-side switch (Q1, Q3) and a connection node between the high-side switch (Q1, Q3) and the low-side switch (Q2, Q4), and configured to limit the high-level voltage value of the pulse signals (HICLK, HIBCLK) to a value lower than the voltage value of the input voltage (Vcc) (first configuration).

[0080] In a semiconductor device (100) according to a first configuration, the output limiting circuit (30) includes switch elements (Q5, Q6) whose gates are driven and controlled by receiving a drive voltage (Vreg) input thereto, and a drive voltage generating circuit (31) configured to generate the drive voltage (Vreg), and may be configured to limit the high-level voltage value of the pulse signals (HICLK, HIBCLK) by the on-resistance values ​​of the switch elements (Q5, Q6) according to the drive voltage (Vreg) (second configuration).

[0081] In the semiconductor device (100) according to the second configuration, the switch elements (Q5, Q6) may be depletion type transistors (third configuration).

[0082] In the semiconductor device (100) according to the second or third configuration, the drive voltage generating circuit (31) may be configured to have temperature characteristics such that the drive voltage (Vreg) increases as the temperature increases (fourth configuration).

[0083] In the semiconductor device (100) according to any one of the first to fourth configurations, the signal generating circuit (10, 20) may be configured to generate both an in-phase pulse signal (HICLK) and an opposite-phase pulse signal (HIBCLK), and the output limiting circuit (30) may be configured to limit the high-level voltage values ​​of the in-phase pulse signal (HICLK) and the opposite-phase pulse signal (HIBCLK) (fifth configuration).

[0084] The electronic device (200) disclosed in this specification comprises a semiconductor device (100) according to any one of the first to fifth embodiments and an electronic circuit (150) configured to operate based on a boosted voltage (VPP) (sixth configuration).

[0085] In the electronic device (200) according to the sixth configuration, the electronic circuit (150) may be configured to include a non-volatile memory configured to write / read data when a boost voltage (VPP) is applied (seventh configuration). [Explanation of symbols]

[0086] 1x boost clock generation circuit 1y Boost clock generation circuit 2. Charge pump circuit 3 Voltage detection circuit 4 Input voltage generation circuit 5 Control circuit 10 Common mode signal generation circuit 20 Negative phase signal generation circuit 30 Output limiting circuit 31 Drive voltage generation circuit 32 Temperature detection circuit 50 Semiconductor devices 100 Semiconductor device 150 Memory Circuit 200 Electronic equipment AP1 Amplifier Bf1 buffer circuit Bf2 buffer circuit C1~Cn capacitors GND grounding end IV1 Inverter circuit MCA Memory Cell Array N1, N2 NAND circuits OSC Oscillator St1 First Dan Stn final stage Q1~Q6 transistors T1~Tn rectifying elements VR1, VR2 variable resistors t1 1st temperature t2 2nd temperature GND Ground voltage VPP write voltage Vcc power supply voltage Vin Input voltage Vn-1 node voltage Vref Reference voltage Vreg drive voltage Vrpx1 ripple voltage Vrpx2 ripple voltage Vrpy1 ripple voltage Vrpy2 ripple voltage CLK Reference clock signal EN Enable signal G1 drive signal G2 drive signal HICLK In-phase clock signal HIBCLK Inverted clock signal S1 Write signal S2 control signal CD Column Decoder RD Row Decoder

Claims

1. an oscillator circuit configured to generate a reference clock signal; a signal generating circuit configured to generate a pulse signal that is in phase or opposite phase to the reference clock signal and has high-level and low-level voltage values ​​according to an input voltage; a charge pump circuit configured to generate a boosted voltage higher than the input voltage in response to the pulse signal; Equipped with The signal generating circuit a high-side switch and a low-side switch connected in series between an application terminal of the input voltage and an application terminal of the low-level voltage; an output limiting circuit connected between the high-side switch and a connection node between the high-side switch and the low-side switch, and configured to limit a high-level voltage value of the pulse signal to a value lower than a voltage value of the input voltage; A semiconductor device comprising:

2. The output limiting circuit a switch element whose gate is driven and controlled by receiving a drive voltage; a drive voltage generating circuit configured to generate the drive voltage; 2. The semiconductor device according to claim 1, further comprising: a switching element configured to switch a voltage applied to a high level of the pulse signal;

3. 3. The semiconductor device according to claim 2, wherein the switching element is a depletion type transistor.

4. 3. The semiconductor device according to claim 2, wherein the drive voltage generating circuit is configured to have a temperature characteristic such that the drive voltage increases as the temperature increases.

5. the signal generating circuit generates both the in-phase pulse signal and the anti-phase pulse signal; 2. The semiconductor device according to claim 1, wherein the output limiting circuit limits the high-level voltage values ​​of the in-phase pulse signal and the opposite-phase pulse signal.

6. A semiconductor device according to claim 1; an electronic circuit configured to operate based on the boosted voltage; An electronic device comprising:

7. The electronic device according to claim 6 , wherein the electronic circuit includes a nonvolatile memory configured to write / read data when the boosted voltage is applied.

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