Comparator circuit
The comparator circuit design minimizes current through cascode circuits to reduce power consumption and input capacitance, addressing noise and speed limitations, enabling efficient comparison with multiple reference voltages.
Patent Information
- Application Number
- JP2024041443
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-29
AI Technical Summary
Existing comparator circuits face challenges with high noise and power consumption due to the input stage design, which limits the number of reference voltages and increases input capacitance, especially when multiple latch circuits are connected, leading to interference and larger input stages.
A comparator circuit design that includes differential input terminals, a switch, an input differential pair, and multiple comparison units with cascode circuits and latch circuits, where the current through the cascode circuit is minimized, reducing power consumption and input capacitance, allowing high-speed operation.
The proposed design achieves low noise and high-speed operation with reduced power consumption and input capacitance, enabling efficient comparison with a larger number of reference voltages.
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Figure 2025141487000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a comparator circuit. [Background technology]
[0002] Voltage comparators (or simply comparator circuits) are important fundamental components in semiconductor integrated circuits. In some applications, such as flash A / D converters, a common input voltage is compared with several different reference voltages (threshold voltages).
[0003] This can be achieved by using multiple voltage comparators in parallel, but in this case all voltage comparators must meet noise requirements, and power consumption and input capacitance increase proportionally with the number of reference voltages.
[0004] Non-Patent Documents 1 and 2 disclose a technique for comparing an input voltage with a plurality of reference voltages without arranging a plurality of comparators in parallel. [Prior art documents] [Non-patent literature]
[0005] [Non-Patent Document 1] Miyahara, M., Mano, I., Nakayama, M., Okada, K., & Matsuzawa, A. (2014, February). "22.6 A 2.2 GS / s 7b 27.4 mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers". In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (pp. 388-389). IEEE. [Non-patent document 2] Wang, JC, & Kuo, TH (2023, February). "A 3mW 2.7 GS / s 8b Subranging ADC with Multiple-Reference-Embedded Comparators". In 2023 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 276-278). IEEE. Summary of the Invention [Problem to be solved by the invention]
[0006] The noise and power consumption of a comparator are largely determined by the input stage. In Non-Patent Document 1, the output of the input stage is interpolated to compare it with more reference voltages. In this configuration, at least two input stages are required, and since the output of the input stage is in the time domain, it is difficult for one input stage to maintain an appropriate operating point over a wide range of voltages, so the number of reference voltages for one input stage is limited.
[0007] Furthermore, the circuit in Non-Patent Document 2 employs a configuration in which multiple latch circuits are directly connected to one input stage (Non-Patent Document 2). With this method, the currents of all the latch circuits flow through the input stage, which requires the input stage to be large, resulting in increased input capacitance. Furthermore, because the latch circuits cause a non-linear current to flow through the input stage relative to the input voltage, the latch circuits interfere with each other, limiting the number of reference voltages for one input stage.
[0008] The present disclosure has been made in light of such a situation, and one of its exemplary purposes is to provide a comparator circuit that is capable of operating at high speed with low power consumption. [Means for solving the problem]
[0009] One aspect of the present disclosure relates to a comparator circuit that compares a differential input voltage with a plurality of N reference voltages. The comparator circuit includes differential input terminals that receive the differential input voltage, a switch, an input differential pair including a first transistor whose gate is connected to one of the differential input terminals and whose source is connected to the switch, and a second transistor whose gate is connected to the other of the differential input terminals and whose source is connected to the switch, and a plurality of N comparison units corresponding to the plurality of reference voltages. Each comparison unit includes a first capacitance, a second capacitance, a reset circuit that resets the charges on the first capacitance and the second capacitance, a cascode circuit including a third transistor connected between the first capacitance and the first transistor and a fourth transistor connected between the second capacitance and the second transistor, and a latch circuit that receives voltages generated across the first capacitance and the second capacitance. A differential bias voltage that defines the i-th reference voltage is applied to the gates of the third transistor and the fourth transistor of the i-th (1≦i≦N) comparison unit. [Effects of the Invention]
[0010] According to an aspect of the present disclosure, a comparator circuit capable of operating at high speed with low noise can be provided. [Brief explanation of the drawings]
[0011] [Figure 1] FIG. 2 is a circuit diagram of a comparator circuit according to an embodiment. [Figure 2] FIG. 1 is a circuit diagram of a comparator circuit according to an embodiment. [Figure 3] FIG. 2 is a circuit diagram of a latch circuit according to an embodiment. [Figure 4] 5A and 5B are waveform diagrams illustrating the operation of the comparator circuit. [Figure 5] 5A and 5B are waveform diagrams illustrating the operation of the comparator circuit. [Figure 6] FIG. 10 is a circuit diagram of a comparator circuit according to a first modification. [Figure 7] FIG. 10 is a circuit diagram of a comparator circuit according to a second modification. DETAILED DESCRIPTION OF THE INVENTION
[0012] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.
[0013] A comparator circuit according to one embodiment compares a differential input voltage with a plurality of N reference voltages. The comparator circuit includes differential input terminals receiving the differential input voltages, a switch, an input differential pair including a first transistor having a gate connected to one of the differential input terminals and a source connected to the switch, and a second transistor having a gate connected to the other of the differential input terminals and a source connected to the switch, and a plurality of N comparison units corresponding to the plurality of reference voltages. The i-th (1≦i≦N) comparison unit includes a first capacitance, a second capacitance, a reset circuit that resets the charges of the first capacitance and the second capacitance, a third transistor connected between the first capacitance and the first transistor, and a fourth transistor connected between the second capacitance and the second transistor, wherein a differential bias voltage that defines the i-th reference voltage is applied to the third and fourth transistors, and a latch circuit that receives the voltages generated across the first capacitance and the second capacitance.
[0014] Prior to voltage comparison, the charges on the first and second capacitances are reset by the reset circuit, and then the switch is turned on. When the switch is turned on, current flows through the third and fourth transistors in each comparison section. This current changes the charges on the first and second capacitances over time, and the voltages on the first and second capacitances also change. The current flowing through the third transistor is determined by one side of the differential input voltage and one side of the differential bias voltage applied to the gate of the third transistor, while the current flowing through the fourth transistor is determined by the other side of the differential input voltage and the other side of the differential bias voltage applied to the gate of the fourth transistor. Therefore, a potential difference determined by the relationship between the differential input voltage and the differential bias voltage is generated across the first and second capacitances. The output of the latch circuit indicates the result of comparing the differential input voltage with a reference voltage determined by the differential bias voltage.
[0015] In this comparator circuit, the current flowing through the cascode circuit does not determine the operating speed of the comparator circuit, so the current flowing through the cascode circuit can be reduced, which makes it possible to reduce power consumption.In addition, the current flowing through the input differential pair is also reduced, so the size of the input differential pair can be reduced, and the input capacitance can be reduced, enabling high-speed operation.
[0016] In one embodiment, the comparator circuit may further include a reset circuit that resets the drain voltages of the first transistor and the second transistor.
[0017] In one embodiment, the comparison unit may include a time-to-digital converter that is provided instead of or in addition to the latch circuit and that measures the time it takes for the voltages generated across the first capacitance and the second capacitance to change, thereby further improving the resolution.
[0018] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
[0019] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.
[0020] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.
[0021] 1 is a circuit diagram of a comparator circuit 100 according to an embodiment. The comparator circuit 100 compares a differential input voltage Vinp / Vinn with each of a plurality of N (N≧2) reference voltages Vref1 to VrefN, and outputs a signal indicating the comparison result.
[0022] The comparator circuit 100 includes differential input terminals INP / INN, a switch SW1, an input differential pair 102, a first transistor M1, a second transistor M2, and N comparing units 104_1 to 104_N.
[0023] Differential input voltages Vinp / Vinn are input to the differential input terminals INP / INN. One end of the switch SW1 is grounded. The input differential pair 102 includes a first transistor M1 and a second transistor M2. In this embodiment, the first transistor M1 and the second transistor M2 are N-channel MOSFETs. The gates of the first transistor M1 and the second transistor M2 are connected to the differential input terminals INP / INN. The sources of the first transistor M1 and the second transistor M2 are commonly connected and connected to the switch SW1.
[0024] The first line L1 is connected to the drain of the first transistor M1, and the second line L2 is connected to the drain of the second transistor M2.
[0025] A plurality of N comparing sections 104_1 to 104_N are provided corresponding to the N reference voltages Vref1 to VrefN. The comparing sections 104 have the same configuration.
[0026] Each comparison unit 104 includes a capacitance circuit 130, a reset circuit 140, and a latch circuit 150. The capacitance circuit 130 includes a first capacitance Cp and a second capacitance Cn. One end of each of the first capacitance Cp and the second capacitance Cn is grounded. The first capacitance Cp and the second capacitance Cn may be a MOS (Metal Oxide Semiconductor) capacitor or a MIM (Metal-Insulator-Metal) capacitor. The first capacitance Cp and the second capacitance Cn may be formed using parasitic capacitance.
[0027] The reset circuit 140 resets the charges of the first capacitance Cp and the second capacitance Cn prior to the voltage comparison. The reset circuit 140 may include a switch SW2p provided between the first capacitance Cp and a constant voltage line Vr, and a switch SW2n provided between the second capacitance Cn and the constant voltage line Vr. The switches SW2p and SW2n are turned on in response to a reset signal Reset asserted prior to the voltage comparison. When the switches SW2p and SW2n are turned on, the voltages V2p and V2n of the first capacitance Cp and the second capacitance Cn are initialized to be equal to Vr. Vr may be a power supply voltage or a voltage regulated to an appropriate voltage level.
[0028] The cascode circuit 120 includes a third transistor M3 and a fourth transistor M4, which are MOSFETs of the same type (i.e., N-channel) as the input differential pair 102. The third transistor M3 is connected between the first capacitance Cp and the first line L1 (the drain of the first transistor M1), and the fourth transistor M4 is connected between the second capacitance Cn and the second line L2 (the drain of the second transistor M2).
[0029] The bias voltages REFPi / REFNi are input to the gates of the third transistor M3 and the fourth transistor M4 in the i-th comparing unit 104_i. The reference voltage Vrefi of the comparing unit 104_i is determined by the bias voltages REFPi / REFNi.
[0030] The latch circuit 150 receives the voltages V2p and V2n generated across the first capacitor Cp and the second capacitor Cn. The output of the latch circuit 150 has a level corresponding to the potential difference between its input voltages V2p and V2n. The output OUTi of the latch circuit 150 of the i-th comparator 104_i indicates the result of comparing the differential input voltage Vinp / Vinn with the i-th reference voltage Vrefi.
[0031] The above is the basic configuration of the comparator circuit 100. Next, a more specific implementation example will be described.
[0032] FIG. 2 is a circuit diagram of a comparator circuit 100A according to one embodiment. The comparator circuit 100A includes a reset circuit 106. The reset circuit 106 resets the voltages of the first line L1 and the second line L2 prior to voltage comparison. Similar to the reset circuit 140, the reset circuit 106 includes switches SW3p and SW3n. The switches SW3p and SW3n are turned on in response to assertion of a reset signal. In this embodiment, the switches SW3p and SW3n are P-channel MOSFETs, and a clock signal CLK is input as a reset signal. This clock signal CLK is also the signal input to the switch SW1.
[0033] The switches SW2p and SW2n of the reset circuit 140A are configured by P-channel MOSFETs, and the clock signal CLK is input to the gates of these switches as a reset signal.
[0034] 3 is a circuit diagram of a latch circuit 150 according to one embodiment. The latch circuit 150 is a double-tail type and includes transistors M11 to M18. The transistors M11 and M12 form a first inverter 152, and the transistors M14 and M15 form a second inverter 154. The inputs and outputs of the two inverters 152 and 154 are cross-coupled.
[0035] The transistor M13 is connected in series with the transistor M11, and the input signal INP is input to its gate. The transistor M17 is connected in parallel with the transistor M12, and the input signal INP is input to its gate.
[0036] Similarly, the transistor M16 is connected in series with the transistor M14, and the input signal INN is input to its gate. The transistor M18 is connected in parallel with the transistor M15, and the input signal INN is input to its gate.
[0037] Next, the operation of the comparator circuit 100 will be described.
[0038] 4 is a waveform diagram illustrating the operation of the comparator circuit 100. Here, a comparison operation regarding one reference voltage Vrefi will be described.
[0039] The comparator circuit 100A performs a comparison operation when the clock signal CLK is high, and performs an initialization operation when the clock signal CLK is low. The low state of the clock signal CLK corresponds to the assertion of a reset signal.
[0040] When the clock signal CLK is low, the switch SW1 is turned off. At this time, the switches SW3p and SW3n of the reset circuit 106 are turned on, and the voltages V1p and V1n of the first line L1 and the second line L2 are initialized to the constant voltage Vr.
[0041] Furthermore, when the clock signal CLK is low, the switches SW2p and SW2n of the reset circuits 140 in the comparison units 104_1 to 104_N are turned on, and the voltages of the capacitances Cp and Cn are also initialized to the constant voltage Vr.
[0042] Subsequently, when the clock signal CLK transitions to high, the switches SW2p, SW2n, SW3p, and SW3n are turned off and the switch SW1 is turned on.
[0043] When the switch SW1 is turned on, the discharge paths from the capacitances Cp and Cn of the capacitance circuit 130 to ground are conductive. A discharge current flows from the capacitance Cp to ground via the third transistor M3 and the first transistor M1, and a discharge current flows from the capacitance Cn to ground via the fourth transistor M4 and the second transistor M2. Here, the amount of discharge current from the capacitance Cp is determined by the differential input voltage Vinp and the bias voltage REFPi, and the amount of discharge current from the capacitance Cn is determined by the differential input voltage Vinn and the bias voltage REFNi.
[0044] When the differential input voltage Vinp / Vinn is equal to the reference voltage Vrefi, the discharge current from the capacitance Cp and the discharge current from the capacitance Cn are substantially equal, and therefore the voltages V2p and V2n of the capacitances Cp and Cn transition with the same waveform, as shown by the dashed dotted lines.
[0045] When the differential input voltage Vin is higher than the reference voltage Vrefi, the discharge current from the capacitance Cp is greater than the discharge current from the capacitance Cn. Therefore, the voltage V2p of the capacitance Cp drops first, and the voltage V2n of the capacitance Cn drops later. At this time, if the potential difference between the voltages V2p and V2n of the two capacitances Cp and Cn exceeds the threshold value of the latch circuit 150, the output of the latch circuit 150 changes.
[0046] 5 is a waveform diagram (simulation results) illustrating the operation of the comparator circuit 100. The simulation was performed with N=16. It can be seen that of the 16 outputs OUT1 to OUTN, those for which the differential input voltage Vin exceeds the reference voltage Vref transition to high, and those that do not remain low.
[0047] The above is the operation of the comparator circuit 100. The advantages of the comparator circuit 100 will now be described.
[0048] Simulation results for the comparator circuit 100 according to the embodiment show that, compared to a configuration in which multiple conventional double-tailed comparators are arranged in parallel, the power consumption is 65% lower and the input capacitance is 70% smaller, assuming the same amount of noise is tolerated.
[0049] Furthermore, the result was that the speed was approximately 30% faster even in the worst case compared to the circuit described in Non-Patent Document 2. In this embodiment, the operating speed does not decrease even if the current flowing through the cascode circuit 120 is reduced, and therefore, by reducing this current, the size of the input differential pair 102 can be designed to be smaller.
[0050] Next, a modification of the comparator circuit 100 will be described.
[0051] (Variation 1) 6 is a circuit diagram of a comparator circuit 100B according to Modification 1. This comparator circuit 100B has a configuration in which the polarity of the transistors in the comparator circuit 100A of FIG. 2 is swapped and the top and bottom (power supply and ground) are inverted. This modification also provides the same effects as the comparator circuit 100A of FIG. 2.
[0052] (Variation 2) 7 is a circuit diagram of a comparator circuit 100C according to Modification 2. In this comparator circuit 100C, each comparing unit 104 includes a TDC (time-to-digital converter) 160 instead of the latch circuit 150. The TDC 160 measures the time it takes for the potential difference between two capacitances Cp and Cn to reach a predetermined level. Note that this TDC 160 does not need to be multi-bit, and may be configured with approximately 1 to 3 bits.
[0053] According to this second modification, the number of effective reference voltages can be increased to be greater than the number N of comparing sections 104. [Explanation of symbols]
[0054] 100 Comparator Circuit 102 Input Differential Pair M1 First transistor M2 Second transistor 104 Comparison Section SW1 switch L1 First Line L2 Second Line 120 Cascode Circuit M3 Third transistor M4 4th transistor 130 capacitive circuit Cp 1st capacity Cn 2nd capacity 140 Reset Circuit 150 Latch Circuit 106 Reset Circuit
Claims
1. A comparator circuit for comparing a differential input voltage with a plurality of N reference voltages, differential input terminals for receiving the differential input voltage; Switch and an input differential pair including a first transistor having a gate connected to one of the differential input terminals and a source connected to the switch, and a second transistor having a gate connected to the other of the differential input terminals and a source connected to the switch; a plurality of N comparison units corresponding to the plurality of N reference voltages; Equipped with Each comparison unit is A first capacitance; and A second capacitance; and a reset circuit that resets the charges of the first capacitance and the second capacitance; a cascode circuit including a third transistor connected between the first capacitor and the first transistor and a fourth transistor connected between the second capacitor and the second transistor; a latch circuit that receives a voltage generated across the first capacitor and the second capacitor; a differential bias voltage that defines an i-th reference voltage is applied to gates of the third transistor and the fourth transistor of the i-th (1≦i≦N) comparison unit.
2. 2. The comparator circuit according to claim 1, further comprising a reset circuit that resets the drain voltages of the first transistor and the second transistor.
3. 3. The comparator circuit according to claim 1, wherein the comparison unit includes a time-to-digital converter that is provided in place of or in addition to the latch circuit and that measures the time it takes for the voltages generated across the first capacitance and the second capacitance to change.