Auxiliary bus master circuit, and electronic equipment

Abstract

To make it possible for a high-priority master to complete data transfer in a short time when carrying out the data transfer continuously for a plurality of times.SOLUTION: An auxiliary bus master circuit 100 has a control circuit which is connected or can be connected to a bus 400 of a system 500 in which a high priority master 200 having a high priority bus access right and a low priority master 300 having a lower priority bus access right as compared with the high priority master 200 are connected to the single bus 400, and which outputs an access request signal for requesting an access right to the bus 400 based on a timing of outputting at least one of high-priority master signals which are signals exchanged on the bus 400 from the high-priority master 200.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an auxiliary bus master circuit and an electronic device. [Background technology]

[0002] Burst transfers are sometimes used when you want to transfer large amounts of data at high speed. In normal transfers, you specify both the address value and the data value each time you transfer a piece of data, and that piece of data is transferred and the transfer is completed each time. In contrast, in burst transfers, you first specify the starting address value and the value of a specified number of data, and then transfer the specified number of data from the starting address. In other words, in burst transfers, data transfers are pipelined, so data at consecutive addresses can be transferred at high speed.

[0003] Furthermore, when there are multiple bus masters performing data transfer, it is necessary to give priority to bus masters with strict time constraints, for example, in granting permission to transfer data. For this reason, there are systems that set priorities for each bus master so that bus masters with higher priorities are given priority in granting permission to transfer data. For example, Patent Document 1 discloses a data transfer system that improves the transfer efficiency of the entire system by dynamically changing the priority based on weight data corresponding to the period from the theoretical time when the data transfer is completed to the time when the next transfer request is issued. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-82103 Summary of the Invention [Problem to be solved by the invention]

[0005] The data transfer system disclosed in Patent Document 1 aims to improve the transfer efficiency of the entire system by dynamically changing the priority of data transfers in response to transfer requests issued by multiple masters. However, in this system, even when a specific bus master (herein referred to as a high-priority master) needs to complete multiple consecutive data transfers to discrete address spaces in a short period of time, transfer requests from other masters may interrupt the transfer requests (single transfers or burst transfers) issued consecutively by the high-priority master. Therefore, even if the priority of the high-priority master is set to the highest, consecutive transfers cannot be performed with the highest priority, and there is a problem in that it takes a long time for all consecutive transfers issued by the high-priority master to be completed.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide an auxiliary bus master circuit and electronic equipment that enable a high-priority master to complete multiple consecutive data transfers in a short time. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, one aspect of the auxiliary bus master circuit of the present invention is connected to or connectable to a bus in a system in which a high-priority master having a high-priority bus access right and a low-priority master having a bus access right with a lower priority than the high-priority master are connected to one bus, and is equipped with a control circuit that outputs an access request signal to the bus requesting access right based on the timing at which at least one of the high-priority master signals, which are signals exchanged on the bus, is output from the high-priority master. [Effects of the Invention]

[0008] According to the present invention, when a high-priority master performs multiple consecutive data transfers, the data transfers can be completed in a short time. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 illustrates an example of the configuration of a system according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a configuration example of an auxiliary bus master circuit according to an embodiment; [Figure 3] FIG. 10 is a diagram illustrating a configuration example of a D flip-flop with a load function. [Figure 4] FIG. 10 is a diagram illustrating a configuration example of a D flip-flop with a load function that supports 2-bit input and output. [Figure 5] FIG. 10 is a diagram showing an example of a time chart when a write burst transfer is being performed. [Figure 6] FIG. 10 is a diagram illustrating an example of the configuration of a system having three low-priority masters. [Figure 7] 7A is a diagram showing an example of bus access when the auxiliary bus master circuit is operating in the system shown in Fig. 6, and FIG. 7B is a diagram showing an example of bus access when the auxiliary bus master circuit is not operating in the system shown in Fig. 6. [Figure 8] FIG. 10 is a diagram showing an example of a time chart when a read burst transfer is being performed. [Figure 9] FIG. 10 is a diagram showing an example of a time chart when the operation of the auxiliary bus master circuit is stopped during a write burst transfer. [Figure 10] 7 is a diagram showing an example of bus access when the auxiliary bus master circuit is not operating and none of the low-priority masters is transferring data in the system shown in FIG. 6. FIG. [Figure 11] FIG. 10 is a diagram illustrating an example of a portion of code describing a control sequence of a control circuit according to an embodiment. [Figure 12] FIG. 1 is a diagram illustrating an example of the configuration of a sound source system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] An auxiliary bus master circuit and the like according to an embodiment will be described with reference to the drawings, in which the same or corresponding parts are designated by the same reference numerals.

[0011] 1, an auxiliary bus master circuit 100 according to an embodiment is connected to a bus 400 of a system 500 in which a high-priority master 200 having a high-priority bus access right and a low-priority master 300 having a bus access right with a lower priority than the high-priority master 200 are connected to the same bus 400. The low-priority master 300 may be a single master or multiple masters.

[0012] The bus 400 of this system 500 is AHB (Advanced High-performance Bus)-Lite of the AMBA (Advanced Microcontroller Bus Architecture) standard. The specific specifications of this bus 400 are described in the ARM specifications published by ARM Ltd. As of January 22, 2024, the ARM specifications are, for example: https: / / developer.arm.com / documentation / ihi0011 / a / https: / / developer.arm.com / documentation / ihi0033 / a It can be downloaded from etc.

[0013] 1, the system 500 includes a control unit 510 and a storage unit 520. The control unit 510 is configured with at least one processor, such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The control unit 510 operates the system 500 by executing a program stored in the storage unit 520. The storage unit 520 stores the program executed by the control unit 510 and necessary data. The storage unit 520 may include, but is not limited to, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, etc.

[0014] Furthermore, in the system 500, data transfer is performed between the high-priority master 200 or the low-priority master 300 and the storage unit 520. At that time, if there is a conflict between the data transfers of the high-priority master 200 and the low-priority master 300, such as when the high-priority master 200 and the low-priority master 300 attempt to access the storage unit 520 at the same time, the system 500 is set with a priority for bus access rights so that the data transfer of the high-priority master 200 is given priority.

[0015] In order to give priority to bus access by such high-priority bus masters, the system 500 includes an arbiter. The arbiter arbitrates the acquisition of bus access rights among multiple bus masters connected to the bus 400. Specifically, the arbiter acquires signals (signals requesting access rights to the bus 400, such as NONSEQ in the transfer type (HTRANS) signal; hereinafter, these signals are referred to as access request signals) output from the auxiliary bus master circuit 100, the high-priority master 200, and the low-priority master 300, and determines which bus master should be given access to the bus 400. Note that the bus 400 may not be simply a bus, but may be configured as a bus circuit including an arbiter.

[0016] For example, if there is one bus master outputting an access request signal, the arbiter grants the right to access the bus 400 to that bus master (outputting the access request signal).

[0017] Furthermore, if there are multiple bus masters outputting access request signals, the arbiter grants access to the bus 400 to the bus master with the highest priority among the multiple bus masters outputting access request signals. If there are multiple bus masters with the highest priority, the arbiter grants access to the bus 400 to the multiple bus masters with the highest priority in order in a round-robin manner.

[0018] Conventionally, when a high-priority master performs multiple burst transfers, even if the priority is set so that the data transfer of the high-priority master is given priority, data transfers of a low-priority master may interrupt each of the multiple burst transfers (as shown in FIG. 7(b) to be described later). The auxiliary bus master circuit 100 of the present disclosure is a circuit for preventing the low-priority master 300 from acquiring bus access rights in such a case, thereby preventing the transfers of the low-priority master 300 from interrupting each of the multiple burst transfers (as shown in FIG. 7(a) to be described later). Therefore, in the system 500, a higher priority (e.g., the same priority as the high-priority master 200) is set as the priority of the bus access right for the auxiliary bus master circuit 100 than for the low-priority master.

[0019] 2, the auxiliary bus master circuit 100 includes a control circuit 110, a plurality of selectors (selectors 161, 162, 163, and 164), and a plurality of D flip-flops with load functions (ldD-FFs 171, 172, 173, 174, 175, 176, and 177). The selectors 161, 162, 163, and 164 included in the auxiliary bus master circuit 100 are collectively referred to as selectors 160, and the plurality of ldD-FFs 171, 172, 173, 174, 175, 176, and 177 are collectively referred to as ldD-FFs 170.

[0020] A D flip-flop with load function is a logic circuit that loads (takes in) the input value of the D terminal when a signal is input to the load (ld) terminal (for example, when ld=1 (HIGH)), and latches that input value. A D flip-flop with load function can be configured, for example, as shown in FIG. 3, with a selector 181 and a normal D flip-flop 182. The D flip-flop with load function (ldD-FF180) shown in FIG. 3 is configured so that when HIGH is input to the load (ld) terminal, the input value of the D terminal is loaded (taken in) into the internal D flip-flop 182 and latched (held).

[0021] Returning to Figure 2, the auxiliary bus master circuit 100 has, as input terminals, an operation mode terminal 121 to which a signal for switching the operation mode of the control circuit 110 is input, a bus clock terminal 122 to which a bus clock (HCLK) signal is input, a bus reset terminal 123 to which a bus reset (HRESETn) signal is input, a high-priority master signal acquisition terminal 130 to which signals exchanged by the high-priority master 200 on the bus 400 (HREADY, HTRANS, HWRITE, etc., signals described in the above-mentioned AMBA specification, also referred to here as high-priority master signals), a bus input terminal 140 to which a signal from the bus 400 is input, and a bus output terminal 150 to which a signal is output to the bus 400. As shown in FIG. 1, the bus 400 includes: (1) control signals including a high priority master transfer type (HTRANS) signal, a high priority master transfer direction (HWRITE) signal, a high priority master slave select (HSEL) signal, and a high priority master transfer size (HSIZE) signal, each output from the high priority master 200; a high priority master ready (HREADY) signal input to the high priority master 200; a high priority master address bus (HADDR) signal output from the high priority master 200; (2) a first bus line group 400A for exchanging a priority master write data bus (HWDATA) signal and a high priority read data bus (HRDATA) signal input to the high priority master 200; (3) control signals output from the auxiliary bus master circuit 100, including an auxiliary bus master transfer type (HTRANS2) signal, an auxiliary bus master transfer direction (HWRITE2) signal, an auxiliary bus master slave selection (HSEL2) signal, an auxiliary bus master transfer size (HSIZE2) signal, and an auxiliary bus master transfer mode (HBURST2) signal; (3) a second bus line group 400B for exchanging an auxiliary bus master ready (HREADY2) signal input to the auxiliary bus master circuit 100, an auxiliary bus master address bus (HADDR2) signal output from the auxiliary bus master circuit 100, and an auxiliary bus master write data bus (HWDATA2) signal output from the auxiliary bus master circuit 100; and (4) a transfer type (HTRANS3) signal, a low priority master transfer direction (HWRITE3) signal, a low priority master slave selection (HSEL3) signal, and a low priority master slave selection (HSEL4) signal output from the low priority master 300. and a third bus line group 400C for exchanging control signals including a data transfer size (HSIZE3) signal and a transfer mode (HBURST3) signal, a low priority master ready (HREADY3) signal input to the low priority master 300, a low priority master address bus (HADDR3) signal output from the low priority master 300, a low priority master write data bus (HWDATA3) signal output from the low priority master 300, and a low priority read data bus (HRDATA3) signal input to the low priority master 300. Here, the first bus line group 400A is connected to the auxiliary bus master circuit 100 so that the control signal, high priority master address bus (HADDR) signal, and high priority master write data bus (HWDATA) signal output from the high priority master 200, and the high priority master ready (HREADY) signal input to the high priority master 200, are input to the auxiliary bus master circuit 100.

[0022] 2, the bus clock signal is input to the clock terminals of all flip-flops in the auxiliary bus master circuit 100, including the clock terminals of all IDD-FFs 170 and flip-flops (not shown) in the control circuit 110. The auxiliary bus master circuit 100 is reset by a bus reset signal. Furthermore, a signal (NONSEQUENTIAL) described as "NONSEQ" as a transfer type in the ARM specifications is written as "NSQ" in FIG. 2 and other figures due to space limitations. NONSEQ indicates the start of a burst transfer or a single transfer.

[0023] In addition, the control circuit 110 receives, as control input signals, an operating mode signal, a high priority master ready (HREADY) signal, a high priority master transfer type (HTRANS) signal, a high priority master address bus (HADDR) signal, a high priority master slave select (HSEL) signal, a high priority master transfer direction (HWRITE) signal, an auxiliary bus master ready (HREADY2) signal, and an auxiliary bus master transfer type (HTRANS2) signal.

[0024] The control circuit 110 outputs a 0th selector (sel0) signal, a 1st selector (sel1) signal, a 0th load (ld0) signal, a 1st load (ld1) signal, a 2nd load (ld2) signal, and a 3rd load (ld3) signal as control output signals to control the selector 160 and ldD-FF 170 included in the auxiliary bus master circuit 100. The control circuit 110 controls the timing at which each ldD-FF 170 latches signals such as a high-priority master signal and the timing at which each latched signal is output from the bus output terminal 150 using these control output signals.

[0025] These control input signals and control output signals can be 1-bit or multi-bit signals depending on the type of signal. For example, the high-priority master transfer type (HTRANS) signal is a 2-bit signal, and the high-priority master address bus (HADDR) signal, high-priority master write data bus (HWDATA) signal, and high-priority read data bus (HRDATA) signal are each 32-bit signals. The ldD-FF 170 shown in FIG. 2 does not distinguish between different numbers of input bits (to avoid complexity), but in reality, the ldD-FF 170 that receives multi-bit signals has multi-bit Q and D terminals that support multi-bit signals. For example, the ldD-FF 171 that receives and outputs 2-bit signals is configured using two selectors 181 and two normal D flip-flops 182, each for two bits, as shown in FIG. 4. An ldD-FF 170 that supports a larger number of bits is similarly configured using multiple selectors 181 and normal D flip-flops 182.

[0026] Furthermore, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal. Therefore, regardless of the transfer mode (HBURST) signal output by the high priority master 200, the auxiliary bus master circuit 100 always performs single transfer.

[0027] That is, the auxiliary bus master circuit 100 acquires signals exchanged by the high-priority master 200 over the bus 400, latches them in the ldD-FF 170, and controls the latch timing of the ldD-FF 170 and the output timing to the bus 400 using the control circuit 110. As a result, when the high-priority master 200 starts a data transfer, the auxiliary bus master circuit 100 attempts to perform a single transfer of dummy data immediately thereafter. This makes it possible to prevent the low-priority master 300 from obtaining access rights to the bus 400 while the high-priority master 200 is performing continuous data transfers.

[0028] The operation of the control circuit 110 will be described in more detail. Among the signals output by the control circuit 110, the 0th selector (sel0) signal and the 0th load (ld0) signal are used to fetch (load) data into ldD-FFs 171, 172, and 173 for outputting the auxiliary bus master transfer type (HTRANS2) signal, auxiliary bus master transfer direction (HWRITE2) signal, and auxiliary bus master slave select (HSEL2) signal of the auxiliary bus master circuit 100 based on the high priority master ready (HREADY) signal and high priority master transfer type (HTRANS) signal of the high priority master 200. In addition, the first load (ld1) signal is used to input the high priority master address bus (HADDR) signal obtained from the high priority master 200 into ldD-FF174 and ldD-FF175 to output as the auxiliary bus master address bus (HADDR2) signal of the auxiliary bus master circuit 100, and to output the high priority transfer size (HSIZE) signal obtained from the high priority master 200 as the auxiliary bus master transfer size (HSIZE2) signal of the auxiliary bus master circuit 100, respectively.

[0029] In addition, among the signals output by the control circuit 110, the second load (ld2) signal, the third load (ld3) signal, and the first selector (sel1) signal are used to adjust the timing at which the high-priority master write data bus (HWDATA) signal obtained from the high-priority master 200 is taken into ldD-FF176 or ldD-FF177 and output as the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100.

[0030] The auxiliary bus master circuit 100 starts data transfer after the high-priority master 200 completes the write data transfer, and at this time, the auxiliary bus master circuit 100 writes the data written by the high-priority master 200 (as dummy data) to the address where the high-priority master 200 previously wrote. By doing so, the auxiliary bus master circuit 100 writes the data that has already been written to the same address, so that bus access can be performed without affecting devices (such as the storage unit 520) connected to the bus 400. In order to perform such data transfer, the auxiliary bus master circuit 100 needs to output the signal before the update as the auxiliary bus master write data bus (HWDATA2) signal, even if the high-priority master write data bus (HWDATA) signal of the high-priority master 200 is updated.

[0031] Therefore, the high-priority master write data bus (HWDATA) signal of the high-priority master 200 is alternately loaded to ldD-FF176 and ldD-FF177, and the signal before update is output as the auxiliary bus master write data bus (HWDATA2) signal. To control the signal output in this way, the control circuit 110 periodically inverts the value of the first selector (sel1) signal and determines whether the second load (ld2) signal or the third load (ld3) signal should be set to HIGH depending on the value of the first selector (sel1) signal.

[0032] The operation mode signal is a signal that switches between operation and stop of the auxiliary bus master circuit 100, and includes a total of 36 bits of information including threshold address information (32 bits), threshold address condition information (2 bits), and transfer direction condition information (2 bits).

[0033] The threshold address information sets the threshold address. The auxiliary bus master circuit 100 switches whether to operate when "the address indicated by the address bus signal is equal to or greater than the threshold address" depending on whether the first bit of the threshold address condition information is 1 (HIGH) or 0 (LOW), and switches whether to operate when "the address indicated by the address bus signal is less than the threshold address" depending on whether the second bit of the threshold address condition information is HIGH or LOW. This makes it possible, for example, to operate the auxiliary bus master circuit 100 only when a device located at a specific address performs a data transfer.

[0034] Furthermore, the auxiliary bus master circuit 100 switches whether to operate in the case of a read (high priority master transfer direction (HWRITE) signal is LOW) depending on whether the first bit of the transfer direction condition information is HIGH or LOW, and switches whether to operate in the case of a write (high priority master transfer direction (HWRITE) signal is HIGH) depending on whether the second bit of the transfer direction condition information is HIGH or LOW. This makes it possible, for example, to operate the auxiliary bus master circuit 100 only when a read data transfer is performed.

[0035] The auxiliary bus master circuit 100 starts a control sequence when the 0th selector (sel0) signal of the control circuit 110 becomes HIGH. However, when the operation of the auxiliary bus master circuit 100 is stopped based on the conditions set by the operation mode signal, the 0th selector (sel0) signal becomes fixed LOW, and the control sequence is no longer generated. As a result, the output terminal of the auxiliary bus master circuit 100 is held in a stopped state, and the operation of the auxiliary bus master circuit 100 is stopped.

[0036] In operation, the auxiliary bus master circuit 100 receives and latches (holds) a signal from the high-priority master signal acquisition terminal 130, and immediately after the high-priority master 200 completes bus access, outputs a signal from the bus output terminal 150 to the bus 400 so that the auxiliary bus master circuit 100 can acquire the bus access right. This prevents the bus access right from being acquired by the low-priority master group, and allows the high-priority master 200 (and the auxiliary bus master circuit 100) to occupy the bus.

[0037] To give an overview of this mechanism in the case of write data transfer, when the high priority master transfer type (HTRANS) signal output from the high priority master 200 is NONSEQ and the high priority master ready (HREADY) signal is HIGH, the auxiliary bus master circuit 100 takes in and latches the high priority master address bus (HADDR) signal at the timing of a clock switch in the bus clock (HCLK) signal (for example, a switch from LOW to HIGH), and after latching, sets the auxiliary bus master transfer type (HTRANS2) signal to NONSEQ to be output to the bus 400 at the timing of a clock switch in the bus clock (HCLK) signal (for example, a switch from LOW to HIGH, the same switch as the switch when the high priority master address bus (HADDR) signal is latched), and outputs the held high priority master address bus (HADDR) signal as the auxiliary bus master address bus (HADDR2) signal. The high-priority master write data bus (HWDATA) signal output from the high-priority master 200 is captured and latched, and the latched high-priority master write data bus (HWDATA) signal is output as the auxiliary bus master write data bus (HWDATA2) signal at the timing of the next clock transition (e.g., from LOW to HIGH) in the bus clock (HCLK) signal after the auxiliary bus master transfer type (HTRANS2) signal is NONSEQ and the auxiliary bus master ready (HREADY2) signal has switched from LOW to HIGH. Here, the next clock transition in the bus clock (HCLK) signal refers to the transition one cycle later of the bus clock (HCLK) signal, and refers to only a transition from LOW to HIGH or only a transition from HIGH to LOWH.

[0038] As described above, the arbiter of the system 500 grants the bus master that is outputting the access request signal the right to access the bus 400. Therefore, when the high priority master 200 outputs an access request signal, the auxiliary bus master circuit 100 captures the signal and outputs an access request signal immediately after the high priority master 200, so that the auxiliary bus master circuit 100 can obtain the right to access the bus 400 after the high priority master 200 has completed its data transfer.

[0039] In this embodiment, each bus master requests access right to the bus 400 when it outputs NONSEQ as the transfer type (HTRANS) signal. Therefore, the auxiliary bus master circuit 100's output of NONSEQ as the auxiliary bus master transfer type (HTRANS2) signal corresponds to outputting an access request signal. Also, the high priority master 200's output of NONSEQ as the high priority master transfer type (HTRANS) signal corresponds to the high priority master 200 outputting a signal requesting access right to the bus 400, and this signal is also called a high priority master request signal to distinguish it from the access request signal output by the auxiliary bus master circuit 100.

[0040] Next, the operation of the control circuit 110 when the high priority master 200 writes data to the storage unit 520 in successive burst transfers will be described with reference to FIG.

[0041] As a premise, it is assumed that the high-priority master 200 has been assigned a high-priority bus access right, and therefore when the high-priority master 200 attempts to start a write burst transfer at the initial point (timing t0 in FIG. 5, which is one of the timings when the bus clock (HCLK) signal switches from LOW to HIGH), it can obtain the bus access right. It is also assumed that the address from which the burst transfer starts is A0, followed by A1, A2, .... It is also assumed that the data at address A0 is D0, and the data at subsequent addresses Ax is Dx. It is also assumed that the high-priority transfer size (HSIZE) signal continues for every eight addresses Ax, starting with S0 (e.g., half-word (16 bits)), S1, ..., and that the transfer mode (HBURST) is INCR8 (an 8-beat incremental burst transfer mode).

[0042] Then, at timing t0, the high priority master 200 sets the high priority master transfer direction (HWRITE) signal to HIGH (indicating a write transfer), sets the high priority master transfer type (HTRANS) signal to NONSEQ, and outputs A0 to the high priority master address bus (HADDR) signal in order to start a write burst transfer from address A0. At this time, the high priority master slave select (HSEL) signal is also output at timing t0 based on the content of the high priority master address bus (HADDR) signal (because the HSEL signal is a combinational decode of the address bus).

[0043] Then, at timing t1, which is the next clock switching timing after timing t0 in the bus clock (HCLK) signal, the high priority master 200 acquires bus access rights, and the high priority master ready (HREADY) signal from the bus 400 becomes HIGH.

[0044] As shown by the dotted line box and the thick dotted line at timing t1 in Figure 5, when the high priority master ready (HREADY) signal from the bus 400 becomes HIGH, the control circuit 110 sets the 0th selector (sel0) signal, the 0th load (ld0) signal, and the 1st load (ld1) signal to HIGH for one clock (one cycle of the bus clock (HCLK) signal) in response to the high priority master slave select (HSEL) signal and the high priority master transfer direction (HWRITE) signal being HIGH and the high priority master transfer type (HTRANS) signal being NONSEQ.

[0045] Then, as a result of the first load (ld1) signal becoming HIGH, A0, which is the high-priority master address bus (HADDR) signal of the high-priority master 200, is loaded into ldD-FF174 and latched, and S0, which is the high-priority transfer size (HSIZE) signal of the high-priority master 200, is loaded into ldD-FF175 and latched. Then, at timing t2, which is the timing of the next clock change after timing t1, A0 is latched and output from ldD-FF174 as the auxiliary bus master address bus (HADDR2) signal of the auxiliary bus master circuit 100, as shown by the dash-dot line extending from address A0 in the dotted-line box at timing t1. At the same time, that is, at timing t2, S0 is latched and output from ldD-FF175 as the auxiliary bus master transfer size (HSIZE2) signal of the auxiliary bus master circuit 100.

[0046] At timing t1, the 0th selector (sel0) signal and 0th load (ld0) signal become HIGH, so that NONSEQ is loaded into ldD-FF171 and latched, and at timing t2, which is the next clock switching timing after timing t1, NONSEQ is latched and output as the auxiliary bus master transfer type (HTRANS2) signal of the auxiliary bus master circuit 100. Similarly, at timing t1, the high-priority master transfer direction (HWRITE) signal and high-priority master slave select (HSEL) signal of the high-priority master 200 are loaded into ldD-FF172 and ldD-FF173 and latched, and at timing t2 after timing t1, the signals are latched and output as the auxiliary bus master transfer direction (HWRITE2) signal and auxiliary bus master slave select (HSEL2) signal of the auxiliary bus master circuit 100.

[0047] In this way, the auxiliary bus master circuit 100 outputs the NONSEQ auxiliary bus master transfer type (HTRANS2) signal to the bus 400, so that immediately after the high-priority master 200 starts burst transfer (at timing t2, which is the next clock switching timing after timing t1), the auxiliary bus master circuit 100 requests access to the bus 400. Like the high-priority master 200, the auxiliary bus master circuit 100 is set to have a higher priority for access to the bus 400 than the other low-priority masters 300. Therefore, even if a low-priority master 300 requests access to the next bus 400, the arbiter will give priority to granting access to the bus 400 to the auxiliary bus master circuit 100 in response to a request for access to the next bus 400 while the high-priority master 200 is performing burst transfer.

[0048] The value of the first selector (sel1) signal is periodically inverted, but is HIGH at timing t1, so the control circuit 110 sets the second load (ld2) signal to HIGH at timing t2, which is the next clock switching timing after timing t1, in response to the first load (ld1) signal and the first selector (sel1) signal at timing t1.

[0049] Then, D0, which is the high-priority master write data bus (HWDATA) signal of the high-priority master 200, is loaded into the ldD-FF 176 and latched. However, since the first selector (sel1) signal remains HIGH at this point, the output from the ldD-FF 177 (the previous data bus signal, indicated by "?" in FIG. 5) continues to be output as the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100 until timing t4 when the first selector (sel1) signal becomes LOW.

[0050] Then, at timing t3 when the auxiliary bus master ready (HREADY2) signal of the auxiliary bus master circuit 100 transferred from the bus 400 switches from LOW to HIGH, the auxiliary bus master transfer type (HTRANS2) signal becomes NONSEQ, and in response, the control circuit 110 sets the 0th load (ld0) signal to HIGH for one clock (one cycle of the bus clock (HCLK) signal). At this time, because the 0th selector (sel0) signal is LOW, IDLE is loaded into ldD-FF171 and LOW is loaded into ldD-FF172 and ldD-FF173 from the selectors 161, 162, and 163, respectively, and latched. These latched signals are then output at the clock switching timing. That is, at timing t4, which is the next clock switch after timing t3, IDLE is output as the auxiliary bus master transfer type (HTRANS2) signal of the auxiliary bus master circuit 100, and LOW is output as the auxiliary bus master transfer direction (HWRITE2) signal and the auxiliary bus master slave selection (HSEL2) signal.

[0051] Then, at timing t4, the first selector (sel1) signal goes LOW, and D0 latched in the ldD-FF 176 is output as the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100. In other words, the auxiliary bus master circuit 100 writes D0, which serves as dummy data, to address A0 in a single transfer.

[0052] As described above, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal. At timing t4, the auxiliary bus master circuit 100 switches the auxiliary bus master transfer type (HTRANS2) signal from NONSEQ to IDLE, which indicates that there is no data to be burst transferred. Therefore, the auxiliary bus master circuit 100 that has acquired access rights to the bus 400 transfers D0 output to the auxiliary bus master write data bus (HWDATA2) signal in single transfer mode, and then immediately hands over the access rights to the bus 400 to another bus master. At timing t2, the high priority master 200 switches the high priority master transfer type (HTRANS) signal from NONSEQ, which indicates that this is the beginning of the burst transfer, to SEQ, which indicates that there is a remaining portion of the burst transfer, outputs the high priority master address bus (HADDR) signal for addresses A1, A2, and A3 in that order, and outputs the final address A7 as one of multiple address blocks to the bus 400, and then switches the high priority master transfer type (HTRANS) signal from SEQ to IDLE, which indicates that there are no addresses for the burst transfer.

[0053] Then, after the burst transfer of data D7 corresponding to address A7 is completed, the high-priority master 200 sets the high-priority master transfer direction (HWRITE) signal, which had been temporarily switched to LOW, to HIGH (indicating a write transfer), switches the high-priority master transfer type (HTRANS) signal from IDLE to NONSEQ, and outputs A8 to the high-priority master address bus (HADDR) signal, in order to start a burst transfer of write data from the next address A8 at timing t5. Thereafter, similar signals are output from the auxiliary bus master circuit 100 at timings t5, t6, t7, t8, and t9, corresponding to the above-mentioned timings t0, t1, t2, t3, and t4, respectively. Note that after timing t5, the high-priority transfer size (HSIZE) is switched from S0 to S1, but these may be the same size (S0=S1).

[0054] In this way, the auxiliary bus master circuit 100 outputs the NONSEQ auxiliary bus master transfer type (HTRANS2) signal as an access request signal to the bus 400 at the same timing (timing t2 of the same clock) as when it acquires the NONSEQ high priority master transfer type (HTRANS) signal as a high priority master request signal from the high priority master 200. Furthermore, upon acquiring the high priority master request signal, the auxiliary bus master circuit 100 acquires and latches a high priority master address signal, which is the high priority master address bus (HADDR) signal (a signal indicating an address value to be accessed by the high priority master 200) of the high priority master 200, and outputs the acquired high priority master address signal to the bus 400 as an address signal, which is the auxiliary bus master address bus (HADDR2) signal (a signal indicating an address value to be accessed by the auxiliary bus master circuit 100) of the auxiliary bus master circuit 100, at the same timing (timing t2 of the same clock) as when it acquires the high priority master address signal.

[0055] Then, at timing t3 (timing t3 a predetermined number of clocks (e.g., one clock cycle) after the timing (timing t2) at which the high-priority master address signal is acquired), the high-priority master data signal, which is the high-priority master write data bus (HWDATA) signal (a signal indicating the data value to be written by the high-priority master 200) of the high-priority master 200, is acquired and latched, and a predetermined number of clocks after timing t3 (e.g., timing t4 one clock cycle) after the timing t3 at which the auxiliary bus master ready (HREADY2) signal from the bus 400 becomes HIGH, this latched signal is output to the bus 400 as the auxiliary bus master write data bus (HWDATA2) signal (a signal indicating the data value to be written by the auxiliary bus master circuit). By outputting these signals, when the high-priority master 200 transfers data, the auxiliary bus master circuit 100 transfers dummy data to the same address after a predetermined number of clocks, so that the bus 400 can be occupied and access to the bus 400 can be prevented from being interrupted by the low-priority master 300.

[0056] An example of bus access when the auxiliary bus master circuit 100 functions in the system 501 shown in Fig. 6 will be described with reference to Fig. 7(a). However, as shown in Fig. 6, the system 501 includes the high-priority master 200 and the auxiliary bus master circuit 100, as well as three low-priority bus masters (low-priority master A 301, low-priority master B 302, and low-priority master C 303; hereinafter, these three are collectively referred to as the "low-priority master group"), and is configured such that when there is a conflict between bus accesses among multiple bus masters with the same priority, bus access rights are acquired among the multiple bus masters in a round-robin manner.

[0057] In this example, the high-priority master 200 needs to perform four consecutive burst transfers, and the low-priority masters also have large amounts of data that need to be transferred. For example, when the high-priority master 200 processes four channels of stream data in a time-division manner, it is common for such four consecutive burst transfers to be performed.

[0058] In the system 501, the bus masters with higher priority are the high-priority master 200 and the auxiliary bus master circuit 100, but since the auxiliary bus master circuit 100 does not have data that needs to be transferred, the high-priority master 200 starts the first burst transfer at the initial point in time.

[0059] 5, the auxiliary bus master circuit 100 attempts to perform a single transfer of dummy data based on the signal output by the high-priority master 200. Therefore, as shown in FIG. 7(a), the auxiliary bus master circuit 100 enters a transfer waiting state a little later than the low-priority master group. However, because the auxiliary bus master circuit 100 has a higher priority than the low-priority master group, it obtains bus access rights after the high-priority master 200 completes its burst transfer and performs a single transfer.

[0060] The high-priority master 200 then enters a transfer waiting state in order to perform the next burst transfer while the auxiliary bus master circuit 100 is performing the single transfer. Since the high-priority master 200 has a higher priority than the low-priority masters, it obtains bus access rights and performs a burst transfer after the auxiliary bus master circuit 100 completes the single transfer.

[0061] Then, when the high-priority master 200 completes all of the consecutive burst transfers, the low-priority masters start transferring sequentially in a round-robin manner.

[0062] On the other hand, if the auxiliary bus master circuit 100 is not operated in the system 501, the situation will be the same as in the prior art, and one of the bus masters included in the low-priority master group will acquire bus access rights after the high-priority master 200 completes its burst transfer, as shown in FIG. 7(b). As a result, it will take longer for the high-priority master 200 to complete successive burst transfers than when the auxiliary bus master circuit 100 is operated (FIG. 7(a)). Therefore, it can be seen that by operating the auxiliary bus master circuit 100, when the high-priority master 200 performs multiple consecutive data transfers, these data transfers can be completed in a short time.

[0063] Although the operation of the auxiliary bus master circuit 100 during continuous write burst transfer has been described with reference to FIG. 5, the auxiliary bus master circuit 100 also functions effectively during continuous read burst transfer and continuous single transfer.

[0064] For example, the operation of the control circuit 110 when the high-priority master 200 reads data from the storage unit 520 in successive burst transfers will be described with reference to FIG.

[0065] As in the case of FIG. 5, the high-priority master 200 is set with high-priority bus access rights, so when the high-priority master 200 attempts to start a read burst transfer at the initial point in time (timing t0 in FIG. 8), it is assumed that it can obtain the bus access rights. Furthermore, the address from which the burst transfer starts is A0, followed by A1, A2, .... Furthermore, the data at address A0 is assumed to be D0, and the data at subsequent addresses Ax is assumed to be Dx. Furthermore, the high-priority transfer size (HSIZE) is assumed to be S0 (e.g., half-word (16 bits)), S1, ... for every eight addresses Ax, and the transfer mode (HBURST) is assumed to be INCR8 (an 8-beat incremental burst transfer mode).

[0066] Then, at timing t0, the high priority master 200 sets the high priority master transfer direction (HWRITE) signal to LOW (indicating a read transfer), sets the high priority master transfer type (HTRANS) signal to NONSEQ, and outputs A0 to the high priority master address bus (HADDR) signal in order to start a read burst transfer from address A0. At this time, the high priority master slave select (HSEL) signal is also output at timing t0 based on the contents of the high priority master address bus (HADDR) (because the HSEL signal is a combinational decode of the address bus).

[0067] Then, at timing t1, which is the next clock switching timing after timing t0 in the bus clock (HCLK) signal, the high priority master 200 acquires bus access rights, and the high priority master ready (HREADY) signal from the bus 400 becomes HIGH.

[0068] As shown by the dotted line box and the thick dotted line at timing t1 in Figure 8, when the high priority master ready (HREADY) signal from the bus 400 becomes HIGH, the control circuit 110 sets the 0th selector (sel0) signal, the 0th load (ld0) signal, and the 1st load (ld1) signal to HIGH for one clock (one cycle of the bus clock (HCLK) signal) in response to the high priority master slave select (HSEL) signal being HIGH, the high priority master transfer direction (HWRITE) signal being LOW, and the high priority master transfer type (HTRANS) signal being NONSEQ.

[0069] Then, as a result of the first load (ld1) signal becoming HIGH, A0, which is the high-priority master address bus (HADDR) signal of the high-priority master 200, is loaded and latched into ldD-FF174, and S0, which is the high-priority transfer size (HSIZE) signal of the high-priority master 200, is loaded and latched into ldD-FF175. Then, at timing t2, which is the timing of the next clock change after timing t1, A0 latched at timing t1 is output from ldD-FF174 as the auxiliary bus master address bus (HADDR2) signal of the auxiliary bus master circuit 100, as shown by the dash-dotted line extending from address A0 in the dotted-line box at timing t1. At the same time, that is, at timing t2, S0 is latched and output from ldD-FF175 as the auxiliary bus master transfer size (HSIZE2) signal of the auxiliary bus master circuit 100.

[0070] At timing t1, the 0th selector (sel0) signal and 0th load (ld0) signal become HIGH, so that NONSEQ is loaded into ldD-FF171 and latched, and at timing t2, which is the next clock switching timing after timing t1, NONSEQ is latched and output as the transfer type (HTRANS2) signal of the auxiliary bus master circuit 100. Similarly, at timing t1, the high-priority master transfer direction (HWRITE) signal and high-priority master slave select (HSEL) signal of the high-priority master 200 are loaded into ldD-FF172 and ldD-FF173 and latched, and at timing t2 after timing t1, the signals are latched and output as the auxiliary bus master transfer direction (HWRITE2) signal and auxiliary bus master slave select (HSEL2) signal of the auxiliary bus master circuit 100.

[0071] In this way, the auxiliary bus master circuit 100 outputs the NONSEQ auxiliary bus master transfer type (HTRANS2) signal to the bus 400, so that immediately after the high-priority master 200 starts burst transfer (at timing t2, which is the next clock switching timing after timing t1), the auxiliary bus master circuit 100 requests access to the bus 400. Like the high-priority master 200, the auxiliary bus master circuit 100 is set to have a higher priority for access to the bus 400 than the other low-priority masters 300. Therefore, even if a low-priority master 300 requests access to the next bus 400, the arbiter will give priority to granting access to the bus 400 to the auxiliary bus master circuit 100 in response to a request for access to the next bus 400 while the high-priority master 200 is performing burst transfer.

[0072] When the high priority master transfer direction (HWRITE) signal of the high priority master 200 is LOW, the auxiliary bus master write data bus (HWDATA2) signal of the auxiliary bus master circuit 100 is not output, so the control circuit 110 does not need to control the first selector (sel1) signal, the second load (ld2) signal, and the third load (ld3) signal, and the values ​​are fixed (Hold) in Figure 8.

[0073] The high priority read data bus (HRDATA) signal of the high priority master 200 is data D0, D1, ..., D7 read by burst transfer from the storage unit 520, but these are not used by the auxiliary bus master circuit 100. After the high priority master 200 completes the burst transfer, D0 is read as the auxiliary bus master read data bus (HRDATA2) signal of the auxiliary bus master circuit 100, but this is also not used by the auxiliary bus master circuit 100.

[0074] Then, at timing t3 when the auxiliary bus master ready (HREADY2) signal input from the bus 400 to the auxiliary bus master circuit 100 switches from LOW to HIGH, the auxiliary bus master transfer type (HTRANS2) signal becomes NONSEQ, and in response, the control circuit 110 sets the 0th load (ld0) signal to HIGH for one clock (one cycle of the bus clock (HCLK) signal). At this time, because the 0th selector (sel0) signal is LOW, IDLE is loaded into ldD-FF 171 and LOW is loaded into ldD-FFs 172 and 173 from the selectors 161, 162, and 163, respectively, and latched. These latched signals are then output at the next clock switch timing. That is, at timing t4, which is the next clock switch after timing t3, IDLE is output as the auxiliary bus master transfer type (HTRANS2) signal of the auxiliary bus master circuit 100, and LOW is output as the auxiliary bus master transfer direction (HWRITE2) signal and the auxiliary bus master slave selection (HSEL2) signal.

[0075] As described above, the auxiliary bus master circuit 100 always outputs SINGLE (single transfer mode) as the auxiliary bus master transfer mode (HBURST2) signal, and therefore, in the case of read data transfer, the auxiliary bus master circuit 100 always performs single transfer regardless of the transfer mode (HBURST) of the high priority master 200. Therefore, the auxiliary bus master circuit 100 that has acquired the access right to the bus 400 acquires D0 as the auxiliary bus master read data bus (HRDATA2) signal (single transfer), and then immediately hands over the access right to the bus 400 to another bus master.

[0076] Then, after completing the burst transfer of data D7 corresponding to address A7, the high priority master 200 keeps the high priority master transfer direction (HWRITE) signal LOW (indicating a read transfer) and switches the high priority master transfer type (HTRANS) signal from IDLE to NONSEQ, in order to start a burst transfer of read data from the next address A8 at timing t5. After that, similar signals are output from the auxiliary bus master circuit 100 at timings t5, t6, t7, t8, and t9, corresponding to the above-mentioned timings t0, t1, t2, t3, and t4, respectively.

[0077] In this way, it can be confirmed that the auxiliary bus master circuit 100 functions effectively even during read burst transfers.

[0078] As described above, by additionally connecting the auxiliary bus master circuit 100 to the bus 400 and the high-priority master 200 of the systems 500 and 501, and having the auxiliary bus master circuit 100 perform bus access using dummy data based on the bus access signal of the high-priority master 200, the high-priority master 200 (and the auxiliary bus master circuit) can temporarily occupy the access right to the bus 400. Simulation results show that the functioning of the auxiliary bus master circuit 100 can reduce the data transfer time of the high-priority master 200 by approximately 10% to 50% when the bus 400 is congested. In the AMBA standard AHB-Lite, the data bus is separate for write and read, which significantly reduces the data transfer time for the high-priority master when there are many write access requests from a low-priority master in a short period of time, or when there are many read access requests from a low-priority master in a short period of time.

[0079] An operation mode signal is input to the control circuit 110, and the operation of the auxiliary bus master circuit 100 can be stopped depending on the threshold address, threshold address condition, and transfer direction condition included in the operation mode signal. As an example, if a value of "A8" is set as the threshold address and the threshold address condition is set to operate when "the address indicated by the address bus signal is less than the threshold address," the auxiliary bus master circuit 100 operates when the high-priority master address bus (HADDR) signal of the high-priority master 200 is A0 (A0<threshold address), but stops when it is A8, as shown in an example of a time chart in FIG.

[0080] The operation of the auxiliary bus master circuit 100 in this case will be described with reference to Fig. 9. In this case, burst transfer from A0 is performed between timings t0 and t5, so the auxiliary bus master circuit 100 operates in the same manner as in Fig. 5. At timing t5, the high priority master address bus (HADDR) signal of the high priority master 200 becomes A8, which no longer satisfies the threshold address condition included in the operation mode signal, so the operation of the auxiliary bus master circuit 100 stops.

[0081] As a result, the 0th selector (sel0) signal remains fixed at LOW even after timing t6, and the control sequence of the control circuit 110 is not started. As a result, the 0th load (ld0) signal, the 1st load (ld1) signal, etc. are also fixed at LOW, and the auxiliary bus master transfer type (HTRANS2) signal of the auxiliary bus master circuit 100 remains IDLE. Therefore, the auxiliary bus master circuit 100 will not acquire access rights to the bus 400.

[0082] If the low priority masters do not have data to transfer, the high priority master 200 can continue to perform burst transfers as shown in FIG. 10, even if the auxiliary bus master circuit 100 is stopped.

[0083] Since the auxiliary bus master circuit 100 always performs single transfers, the time for which the bus 400 is occupied is short, but as shown in Figure 7(a), there will be a time when the bus 400 is occupied, even if only for a short time, while the auxiliary bus master circuit 100 is operating. Therefore, if it is known that the high-priority master 200 can reliably perform continuous burst transfers, the operation of the auxiliary bus master circuit 100 can be stopped by an operation mode signal, thereby further increasing the speed of the continuous burst transfers of the high-priority master 200, as shown in Figure 10.

[0084] Regarding the control sequence for the control circuit 110 to output control output signals (0th selector (sel0) signal, 0th load (ld0) signal, etc.) in response to control input signals (operation mode signal, high priority master ready (HREADY) signal, auxiliary bus master ready (HREADY2) signal, etc.), even a beginner digital circuit designer can design the control circuit from a time chart. As an example, a minimum RTL (Register Transfer Level) description example using Verilog HDL (Hardware Description Language) is shown in FIG. 11.

[0085] In the above embodiment, the operation mode signal is described as including a total of 36 bits of information, including threshold address information (32 bits), threshold address condition information (2 bits), and transfer direction condition information (2 bits), but this is merely an example of an operation mode signal. For example, the threshold address information may be a total of 69 bits of information, including threshold address A information (32 bits), threshold address B information (32 bits), threshold address condition information (3 bits), and transfer direction condition information (2 bits).

[0086] In this example, it is possible to freely set how threshold address A and threshold address B are used, but for example, threshold address A < threshold address B, and whether or not it operates when "address indicated by address bus signal ≧ threshold address B" is switched depending on whether the first bit of the threshold address condition is HIGH or LOW, whether or not it operates when "threshold address B > address indicated by address bus signal ≧ threshold address A" is switched depending on whether the second bit of the threshold address condition is HIGH or LOW, and whether or not it operates when "address indicated by address bus signal < threshold address A" is switched depending on whether the third bit of the threshold address condition is HIGH or LOW.

[0087] In this way, by including a plurality of threshold addresses in the operation mode signal, the operation of the auxiliary bus master circuit 100 can be switched more flexibly depending on the address.

[0088] Next, a sound source system 601 shown in FIG. 12 will be described as an example in which the auxiliary bus master circuit 100 is applied to an electronic musical instrument.

[0089] The tone generator system 601 includes a tone generator core unit 615 and an auxiliary bus master circuit 620 as bus masters with high-priority bus access rights. The auxiliary bus master circuit 620 has the same or equivalent circuit configuration and functions as the auxiliary bus master circuit 100. The other components of the tone generator system 601 are similar to those of the tone generator system 1 shown in FIG. 1 of JP 2023-140619 A, and therefore detailed description thereof will be omitted.

[0090] However, the CPU 610, RAM 611, ROM 612, GPIO (General Purpose Input / Output) 613, MEMIF (Memory Interface) 614, sound source core unit 615, and bus 616 provided in the sound source system 601 correspond to the CPU 10, RAM 11, ROM 12, GPIO 13, MEMIF 14, core unit 15, and bus 16 of the sound source system 1 of Patent Publication No. 2023-140619, respectively.

[0091] The tone generator system 601 is connected to an external DRAM (Dynamic RAM) 602 and a sound system 603. For example, SMF (Standard MIDI File) is stored in the DRAM 602. The sound system 603 includes a D / A (Digital / Analog) converter, an amplifier, a speaker, etc., and digital musical sound data generated by the tone generator core unit 615 is output from the speaker provided in the sound system 603.

[0092] The tone generator core unit 615 includes a DSP (Digital Signal Processor), and since delays in data transfer in the DSP prevent the digital musical sound data from being output normally from the sound system 603 (for example, the sound may be interrupted or distorted), a higher priority is set for the bus access right of the tone generator core unit 615 than for other bus masters. Similarly to the tone generator core unit 615, a higher priority is set for the bus access right of the auxiliary bus master circuit 620 than for other bus masters.

[0093] When the tone generator core unit 615 wants to occupy the bus continuously (for example, when performing multiple consecutive burst transfers), the auxiliary bus master circuit 620, which operates in conjunction with the tone generator core unit 615, prevents other bus masters from using the bus.

[0094] Therefore, by providing the auxiliary bus master circuit 620, the tone generator system 601 can always output digital musical sound data normally, since the tone generator core section 615 can perform multiple consecutive data transfers without being interrupted by other bus masters.

[0095] Also, for example, since the SRAM 611 built into the sound source system 601 is fast, there may be a case where the auxiliary bus master circuit 100 does not need to be operated, and the auxiliary bus master circuit 100 is to be operated only when accessing the external DRAM 602. In this case, by setting the threshold address information and threshold address condition information of the operation mode signal, it becomes possible to operate the auxiliary bus master circuit 100 only when accessing the external DRAM 602.

[0096] In the above embodiment, the bus 400 is described as conforming to the AHB-Lite specification, but the specification of the bus 400 is not limited to the AHB-Lite specification. For example, the bus 400 may be conforming to the AHB specification or a bus specification other than AMBA.

[0097] In addition, in this embodiment, the output of NONSEQ as a high priority master transfer type (HTRANS) signal is considered to be the output of an access request signal, but the output of an access request signal is not limited to the output of NONSEQ. Any output of a signal that ultimately requests the arbiter to grant access to the bus 400 can be considered to be the output of an access request signal.

[0098] In this embodiment, when the high-priority master 200 performs a write data transfer, the auxiliary bus master circuit 100 performs a single data transfer for writing the first data (D0). However, depending on the system (for example, in a system that satisfies certain specifications, such as a system in which a writable address is always configured to be readable), the auxiliary bus master circuit 100 may perform a single data transfer for reading to the same address. In other words, when the auxiliary bus master circuit 100 can access the bus for a read data transfer, it does not need to perform a write data transfer. In the above disclosure, "after a predetermined number of clocks" means after one clock cycle, but it may be after two or more clock cycles, although this will result in a slight delay in data transfer compared to after one clock cycle. Furthermore, the auxiliary bus master circuit of the present disclosure is not limited to electronic devices such as sound source systems, but can be applied to any electronic device that includes a computer that exchanges transfer data with multiple priorities. In addition, in the above disclosure, the auxiliary bus master circuit may be physically separable from the system, and if necessary, the auxiliary bus master circuit may be connected to an interface of a system bus connected to the system's memory unit.

[0099] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such specific embodiments, and the present invention includes the inventions described in the claims and their equivalents. [Explanation of symbols]

[0100] 100, 620... auxiliary bus master circuit, 110... control circuit, 121... operation mode terminal, 122... bus clock terminal, 123... bus reset terminal, 130... high-priority master signal acquisition terminal, 140... bus input terminal, 150... bus output terminal, 160, 161, 162, 163, 164, 181... selector, 170, 171, 172, 173, 174, 175, 176, 177, 180... ldD-FF, 182... D flip-flop , 200...High priority master, 300...Low priority master, 301...Low priority master A, 302...Low priority master B, 303...Low priority master C, 400, 616...Bus, 500, 501...System, 510...Control unit, 520...Memory unit, 601...Sound source system, 602...DRAM, 603...Sound system, 610...CPU, 611...SRAM, 612...ROM, 613...GPIO, 614...MEMIF, 615...Sound source core unit

Claims

1. A system is provided in which a high-priority master having a high-priority bus access right and a low-priority master having a bus access right lower in priority than the high-priority master are connected to one bus, and the system is connected or connectable to the bus; An auxiliary bus master circuit including a control circuit that outputs an access request signal requesting access rights to the bus based on the timing at which at least one of the high priority master signals, which are signals exchanged on the bus, is output from the high priority master.

2. a logic circuit for latching the high priority master signal obtained from the high priority master; 2. The auxiliary bus master circuit according to claim 1, wherein said control circuit controls a timing for latching said high priority master signal and a timing for outputting said acquired high priority master signal to said bus as said access request signal.

3. 3. The auxiliary bus master circuit of claim 2, wherein the high priority master signal latched in the logic circuit is at least one of a high priority master address bus signal and a high priority master write data bus signal.

4. 4. The auxiliary bus master circuit according to claim 3, wherein the control circuit controls to output the access request signal to at least one of the buses through which the high priority master address bus signal is exchanged and the bus through which the high priority master write data bus signal is exchanged.

5. the priority of the bus access right of the auxiliary bus master circuit is set to be higher than that of the low-priority master; receiving a high-priority master request signal from the high-priority master requesting access to the bus; outputting the access request signal based on the timing at which the high-priority master request signal is acquired; 2. The auxiliary bus master circuit of claim 1.

6. as an output of a transfer mode signal indicating whether the transfer mode is a single transfer mode or a burst transfer mode, a transfer mode signal indicating the single transfer mode is output regardless of the transfer mode of the high-priority master; 2. The auxiliary bus master circuit of claim 1.

7. When the high-priority master request signal is acquired, a high-priority master address signal indicating an address value to be accessed by the high-priority master is acquired and latched; When outputting the access request signal, the acquired high-priority master address signal is output as an address signal indicating an address value to be accessed by the auxiliary bus master circuit.

6. The auxiliary bus master circuit of claim 5.

8. obtaining a high-priority master transfer direction signal indicating a transfer direction when the high-priority master accesses the bus; If the acquired high-priority master transfer direction signal indicates a write, acquiring a high-priority master data signal indicating a data value to be written by the high-priority master after the timing of acquiring the high-priority master address signal; When outputting the access request signal, the auxiliary bus master circuit outputs a signal identical to the acquired high priority master data signal as a write data bus signal indicating a data value to be written.

8. The auxiliary bus master circuit of claim 7.

9. Acquire an operating mode signal; switching whether to output the access request signal based on the acquired operation mode signal; 2. The auxiliary bus master circuit of claim 1.

10. the operation mode signal includes information on a threshold address and information on a threshold address condition; switching whether to output the access request signal depending on whether an address value indicated by a high-priority master address signal, which is a signal on an address bus among the high-priority master signals, satisfies the threshold address and the threshold address condition; 10. The auxiliary bus master circuit of claim 9.

11. Acquire an operating mode signal; The acquired operation mode signal includes information on a transfer direction condition, switching whether to output the access request signal depending on whether the information indicated by the acquired high-priority master transfer direction signal satisfies the transfer direction condition; 9. The auxiliary bus master circuit of claim 8.

12. an auxiliary bus master circuit according to any one of claims 1 to 11; the high priority master; An electronic device comprising:

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