Semiconductor device and manufacturing method of the same

Abstract

To provide a semiconductor device capable of suppressing deterioration of data retention characteristics, and to provide a manufacturing method of the same.SOLUTION: According to one embodiment, a semiconductor device includes a plurality of conductive layers, a charge storage film, and an insulating film. The plurality of conductive layers is separated from each other in a first direction. The plurality of conductive layers include a metal film and a first film covering the metal film and containing titanium silicon nitride. The charge storage film faces a side surface of the conductive layer. The insulating film is provided between the conductive layer and the charge storage film.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In semiconductor devices such as 3D semiconductor memories, electron loss, in which electrons captured in the charge storage film escape to the block insulating film due to the diffusion of hydrogen into the block insulating film, can occur, which can degrade data retention characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-3741 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing deterioration of data retention characteristics and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a plurality of conductive layers, a charge storage film, and an insulating film. The plurality of conductive layers are spaced apart from one another in a first direction. The plurality of conductive layers include a metal film and a first film covering the metal film and containing titanium silicon nitride. The charge storage film faces a side surface of the conductive layer. The insulating film is provided between the conductive layer and the charge storage film. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment; [Figure 2] 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment; [Figure 3] FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor memory device according to the embodiment. [Figure 4] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment. [Figure 5] 1 is a cross-sectional view showing a cross-sectional structure of a columnar portion in a semiconductor memory device according to an embodiment; [Figure 6] 6 is a cross-sectional view showing the semiconductor memory device according to the embodiment taken along line VI-VI of FIG. 5. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 10A to 10C are cross-sectional views showing in detail a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 9A to 9C are cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment, following FIG. 8. [Figure 10] 10A to 10C are cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment, following FIG. 9. [Figure 11] 10A and 10B are explanatory diagrams for explaining data retention characteristics of a semiconductor memory device according to an embodiment; [Figure 12] 10 is a graph showing the relationship between the thickness of the barrier metal film and the hydrogen concentration in the second blocking film in the semiconductor memory device according to the example. [Figure 13] 10 is a graph showing the relationship between the depth of a memory hole in a direction from the periphery toward the center and the hydrogen concentration in a semiconductor memory device according to an embodiment. [Figure 14] 10 is a graph showing the relationship between the thickness of a barrier metal film and data retention characteristics in a semiconductor memory device according to an embodiment. [Figure 15] 10 is a graph showing the relationship between the hydrogen concentration in the second blocking film and the data retention characteristics in the semiconductor memory device according to the example. [Figure 16] 10 is a graph showing the relationship between the thickness of a barrier metal film and data retention characteristics in a semiconductor memory device according to an embodiment. [Figure 17]10 is a graph showing the relationship between the cycle ratio of SiN to TiN and the data retention characteristics in the semiconductor memory device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0008] FIG. 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment. As shown in FIG. 1, the memory system of this embodiment includes a memory controller 100 and a semiconductor memory device 200. The semiconductor memory device 200 is an example of a semiconductor device. The semiconductor memory device 200 is a non-volatile semiconductor memory device configured as a NAND-type flash memory. The memory system is connectable to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal. Note that while FIG. 1 shows only one semiconductor memory device 200, an actual memory system will include multiple semiconductor memory devices 200.

[0009] The memory controller 100 controls writing of data to the semiconductor memory device 200 in accordance with a write request from the host. The memory controller 100 also controls reading of data from the semiconductor memory device 200 in accordance with a read request from the host. The following signals are transmitted and received between the memory controller 100 and the semiconductor memory device 200: a chip enable signal / CE, a ready / busy signal / RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, a write protect signal / WP, a data signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0010] The chip enable signal / CE is a signal for enabling the semiconductor memory device 200. The ready / busy signal / RB is a signal for indicating whether the semiconductor memory device 200 is in a ready state or a busy state. The "ready state" is a state in which an external command is accepted. The "busy state" is a state in which an external command is not accepted. The command latch enable signal CLE is a signal indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. The write enable signal / WE is a signal for loading a received signal into the semiconductor memory device 200. The write enable signal / WE is asserted by the memory controller 100 each time a command, address, and data are received. The memory controller 100 instructs the semiconductor memory device 200 to load the signal DQ<7:0> while the signal / WE is at an "Low" level.

[0011] The read enable signals RE and / RE are signals that allow the memory controller 100 to read data from the semiconductor memory device 200. The read enable signals RE and / RE are used to control the operation timing of the semiconductor memory device 200 when outputting, for example, the signal DQ<7:0>. The write protect signal / WP is a signal that instructs the semiconductor memory device 200 to prohibit data writing and erasing. The signal DQ<7:0> is the entity of data exchanged between the semiconductor memory device 200 and the memory controller 100, and includes a command, address, and data. The data strobe signals DQS and / DQS are signals that control the timing of input and output of the signal DQ<7:0>.

[0012] The memory controller 100 includes a RAM 101, a processor 102, a host interface 103, an ECC circuit 104, and a memory interface 105. The RAM 101, the processor 102, the host interface 103, the ECC circuit 104, and the memory interface 105 are connected to one another via an internal bus 106.

[0013] The host interface 103 outputs requests and user data (write data) received from the host to the internal bus 106. The host interface 103 also transmits user data read from the semiconductor memory device 200 and responses from the processor 102 to the host.

[0014] The memory interface 105 controls the process of writing user data and the like to the semiconductor memory device 200 and the process of reading user data and the like from the semiconductor memory device 200 based on instructions from the processor 102. The processor 102 performs overall control of the memory controller 100. The processor 102 is, for example, a CPU or an MPU. When the processor 102 receives a request from the host via the host interface 103, it performs control in accordance with the request. For example, the processor 102 instructs the memory interface 105 to write user data and parity to the semiconductor memory device 200 in accordance with a request from the host. Furthermore, the processor 102 instructs the memory interface 105 to read user data and parity from the semiconductor memory device 200 in accordance with a request from the host.

[0015] The processor 102 determines a storage area (memory area) on the semiconductor memory device 200 for user data accumulated in the RAM 101. The user data is stored in the RAM 101 via the internal bus 106. The processor 102 determines the memory area for data (page data) in units of pages, which are write units. User data stored in one page of the semiconductor memory device 200 is also referred to as "unit data" hereinafter. The unit data is generally encoded and stored in the semiconductor memory device 200 as a code word. In this embodiment, encoding is not essential. The memory controller 100 may store the unit data in the semiconductor memory device 200 without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 100 does not perform encoding, the page data matches the unit data. Furthermore, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing the unit data. Furthermore, one code word may be generated using multiple unit data.

[0016] The processor 102 determines a memory area in the semiconductor memory device 200 to which the unit data is to be written for each unit data. A physical address is assigned to the memory area in the semiconductor memory device 200. The processor 102 manages the memory area to which the unit data is to be written using the physical address. The processor 102 instructs the memory interface 105 to write the user data to the semiconductor memory device 200 by specifying the determined memory area (physical address). The processor 102 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 102 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 105 to read the user data by specifying the physical address.

[0017] The ECC circuit 104 encodes user data stored in the RAM 101 to generate code words. The ECC circuit 104 also decodes code words read from the semiconductor memory device 200. The RAM 101 temporarily stores user data received from the host before storing it in the semiconductor memory device 200, and temporarily stores data read from the semiconductor memory device 200 before transmitting it to the host. The RAM 101 is, for example, a general-purpose memory such as an SRAM or a DRAM.

[0018] 1 shows a configuration example in which the memory controller 100 includes an ECC circuit 104 and a memory interface 105. However, the ECC circuit 104 may be built into the memory interface 105. Alternatively, the ECC circuit 104 may be built into the semiconductor memory device 200. The specific configuration and arrangement of the elements shown in FIG. 1 are not particularly limited.

[0019] 1 operates as follows when a write request is received from the host. The processor 102 temporarily stores the data to be written in the RAM 101. The processor 102 reads the data stored in the RAM 101 and inputs it to the ECC circuit 104. The ECC circuit 104 encodes the input data and inputs the codeword to the memory interface 105. The memory interface 105 writes the input codeword to the semiconductor memory device 200.

[0020] 1 operates as follows when a read request is received from the host: The memory interface 105 inputs a code word read from the semiconductor memory device 200 to the ECC circuit 104. The ECC circuit 104 decodes the input code word and stores the decoded data in the RAM 101. The processor 102 transmits the data stored in the RAM 101 to the host via the host interface 103.

[0021] 2 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment. As shown in FIG. 2, a semiconductor memory device 200 includes a memory cell array 201, an input / output circuit 202, a logic control circuit 203, a register 204, a sequencer 205, a voltage generation circuit 206, a row decoder 207, a sense amplifier 208, an input / output pad group 300, a logic control pad group 301, and a power supply input terminal group 302.

[0022] The memory cell array 201 is a section for storing data. The memory cell array 201 is configured to have a plurality of memory cell transistors associated with a plurality of bit lines and a plurality of word lines. The input / output circuit 202 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS to and from the memory controller 100. The input / output circuit 202 also transfers commands and addresses in the signals DQ<7:0> to a register 204. The input / output circuit 202 also transmits and receives write data and read data to and from a sense amplifier 208.

[0023] The logic control circuit 203 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP from the memory controller 100. The logic control circuit 203 also transfers a ready / busy signal / RB to the memory controller 100 to notify the outside of the state of the semiconductor memory device 200.

[0024] The register 204 temporarily stores various data. For example, the register 204 stores commands instructing write, read, erase, and other operations. These commands are input from the memory controller 100 to the input / output circuit 202, and then transferred from the input / output circuit 202 to the register 204 where they are stored. The register 204 also stores addresses corresponding to the above commands. These addresses are input from the memory controller 100 to the input / output circuit 202, and then transferred from the input / output circuit 202 to the register 204 where they are stored. The register 204 also stores status information indicating the operating state of the semiconductor memory device 200. The status information is updated by the sequencer 205 each time depending on the operating state of the memory cell array 201, etc. The status information is output as a status signal from the input / output circuit 202 to the memory controller 100 in response to a request from the memory controller 100.

[0025] The sequencer 205 controls the operation of each part including the memory cell array 201 based on control signals input from the memory controller 100 to the input / output circuit 202 and the logic control circuit 203. The voltage generation circuit 206 is a part that generates voltages required for data write operations, read operations, and erase operations in the memory cell array 201. These voltages include, for example, voltages applied to a plurality of word lines and a plurality of bit lines of the memory cell array 201. The operation of the voltage generation circuit 206 is controlled by the sequencer 205.

[0026] The row decoder 207 is a circuit configured with a group of switches for applying voltages to each of the multiple word lines of the memory cell array 201. The row decoder 207 receives a block address and a row address from the register 204, selects a block based on the block address, and selects a word line based on the row address. The row decoder 207 switches the open / close states of the group of switches so that a voltage from the voltage generation circuit 206 is applied to the selected word line. The operation of the row decoder 207 is controlled by the sequencer 205.

[0027] The sense amplifier 208 is a circuit for adjusting the voltage applied to the bit lines of the memory cell array 201 and for reading the voltage of the bit lines and converting it into data. When reading data, the sense amplifier 208 acquires data read from the memory cell transistors of the memory cell array 201 to the bit lines and transfers the acquired read data to the input / output circuit 202. When writing data, the sense amplifier 208 transfers data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifier 208 is controlled by the sequencer 205.

[0028] The input / output pad group 300 is a portion provided with a plurality of terminals (pads) for transmitting and receiving signals between the memory controller 100 and the input / output circuit 202. Each terminal is provided individually corresponding to the signal DQ<7:0> and the data strobe signals DQS and / DQS.

[0029] The logic control pad group 301 is a portion provided with a plurality of terminals for transmitting and receiving signals between the memory controller 100 and the logic control circuit 203. The terminals are individually provided corresponding to the chip enable signal / CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signals RE, / RE, the write protect signal / WP, and the ready / busy signal / RB.

[0030] The power input terminal group 302 is a section provided with a plurality of terminals for receiving the voltages required for the operation of the semiconductor memory device 200. The voltages applied to the respective terminals include power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc is a circuit power supply voltage provided from the outside as an operating power supply, and is, for example, a voltage of about 3.3 V. The power supply voltage VccQ is, for example, a voltage of 1.2 V. The power supply voltage VccQ is a voltage used when transmitting and receiving signals between the memory controller 100 and the semiconductor memory device 200. The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, and is, for example, a voltage of 12 V.

[0031] FIG. 3 is a circuit diagram showing an equivalent circuit of a semiconductor device according to an embodiment. Next, with reference to FIG. 3, the electronic circuit configuration of the memory cell array 201 will be described. As shown in FIG. 3, the memory cell array 201 has a plurality of string units SU0 to SU3. Each of the string units SU0 to SU3 has a plurality of NAND strings SR. Each NAND string SR has, for example, eight memory cell transistors MT0 to MT7 and two select transistors STD, STS. Note that the number of memory cell transistors and the number of select transistors included in the NAND string SR can be changed as desired.

[0032] The string units SU0 to SU3 together form one block. Although only a single block is shown in FIG. 3, in reality, the memory cell array 201 is provided with a plurality of such blocks. Hereinafter, the string units SU0 to SU3 will also be referred to as "string units SU" without distinction. Furthermore, the memory cell transistors MT0 to MT7 will also be referred to as "memory cell transistors MT" without distinction.

[0033] The memory cell array 201 has N bit lines BL0 to BL(N-1), where "N" is a positive integer. Each string unit SU has NAND strings SR, the same number as the number N of bit lines BL0 to BL(N-1). The memory cell transistors MT0 to MT7 provided in the NAND string SR are arranged in series between the source of the select transistor STD and the drain of the select transistor STS. The drain of the select transistor STD is connected to one of the multiple bit lines BL0 to BL(N-1). The source of the select transistor STS is connected to a source line SL. In the following description, the bit lines BL0 to BL(N-1) may be referred to as "bit lines BL" without distinction.

[0034] Each memory cell transistor MT is configured as a transistor having a charge storage film at the gate portion. The amount of charge stored in the charge storage film corresponds to the data held in the memory cell transistor MT.

[0035] As will be described later, the memory cell transistor MT in this embodiment is configured to suppress deterioration of data retention characteristics due to electron loss from the charge storage film. The memory cell transistor MT is a charge trap type memory cell transistor that uses, for example, a silicon nitride film as a charge storage film. The memory cell transistor MT may also be a floating gate type memory cell transistor that uses, for example, a silicon film as a charge storage film.

[0036] The gates of the select transistors STD provided in the string unit SU0 are all connected to a select gate line SGD0. A voltage is applied to the select gate line SGD0 to switch the open / close states of the select transistors STD. Similarly, the string units SU1 to SU3 are connected to select gate lines SGD1 to SGD3, respectively.

[0037] The gates of the select transistors STS provided in the string unit SU0 are all connected to a select gate line SGS0. A voltage is applied to the select gate line SGS0 to switch the open / close states of the select transistors STS. Similarly, the string units SU1 to SU3 are connected to select gate lines SGS1 to SGS3, respectively. Note that the select gate line may be shared among the string units SU0 to SU3 that make up one block, and the gates of the select transistors STS of the string units SU0 to SU3 may be connected to a common select gate line.

[0038] The gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Voltages are applied to the word lines WL0 to WL7 to switch the memory cell transistors MT0 to MT7 between open and closed states, change the amount of charge stored in the charge storage film of each of the memory cell transistors MT0 to MT7, and so on.

[0039] Data writing and reading in the semiconductor memory device 200 is performed collectively for a unit called a "page" of multiple memory cell transistors MT connected to any word line WL in any string unit SU. On the other hand, data erasure in the semiconductor memory device 200 is performed collectively for all memory cell transistors MT included in a block. Specific methods for writing, reading, and erasing data in this manner can be various well-known methods, and therefore detailed description thereof will be omitted.

[0040] FIG. 4 is a cross-sectional view showing the cross-sectional structure of a semiconductor memory device 200 according to an embodiment. Next, with reference to FIG. 4, the structure of the semiconductor memory device 200, particularly the structure in the vicinity of the memory cell array 201, will be specifically described. As shown in FIG. 4, the semiconductor memory device 200 is a three-dimensional memory in which an array chip C1 having the memory cell array 201 and a circuit chip C2 having peripheral circuits are bonded together. The peripheral circuits include the sense amplifier 208 and row decoder 207 shown in FIG. 2. The array chip C1 and the circuit chip C2 are bonded together at a bonding surface S. That is, the array chip C1 and the circuit chip C2 are electrically connected to each other via wiring bonded at the bonding surface S. Therefore, the semiconductor memory device 200 of this embodiment has a CMOS directly bonded to array (CBA) structure.

[0041] The circuit chip C2 includes a substrate 15, a plurality of transistors 31, a plurality of contact plugs 33, wiring layers 34, 35, and 36, a plurality of via plugs 37, a plurality of metal pads 38, and an interlayer insulating film 14. Hereinafter, directions parallel to the surface, i.e., the top surface, of the substrate 15 and perpendicular to each other are defined as the X direction and the Y direction. Also, the direction perpendicular to the surface of the substrate 15 is defined as the Z direction. The Z direction is an example of a first direction. Also, hereinafter, the Z direction may be referred to as the upward direction. Also, the direction opposite to the Z direction may be referred to as the downward direction.

[0042] The substrate 15 is a semiconductor substrate such as a silicon substrate. A plurality of transistors 31 constitute a CMOS circuit. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 15. In addition to the transistors 31, semiconductor elements such as resistors and capacitors may also be formed on the substrate 15.

[0043] The contact plugs 33 are provided on the source diffusion layer or the drain diffusion layer of the corresponding transistor 31 .

[0044] The wiring layer 34 is provided on the plurality of contact plugs 33. The wiring layer 34 includes a plurality of wires connected to the corresponding contact plugs 33. The wiring layer 35 is provided on the wiring layer 34. The wiring layer 35 includes a plurality of wires connected to the corresponding wires in the wiring layer 34. The wiring layer 36 is provided on the wiring layer 35. The wiring layer 36 includes a plurality of wires connected to the corresponding wires in the wiring layer 35.

[0045] A plurality of via plugs 37 are provided on corresponding wirings of the wiring layer 36. A plurality of metal pads 38 are provided on the corresponding via plugs 37. The wiring layers 34 to 36, the via plugs 37, and the metal pads 38 may be formed of a low-resistance metal such as copper or tungsten. The interlayer insulating film 14 covers and protects the transistor 31, the contact plug 33, the wiring layers 34 to 36, the via plugs 37, and the metal pads 38. The interlayer insulating film 14 is made of, for example, silicon oxide (SiO x ) membrane.

[0046] The array chip C1 includes a stacked film 11, a columnar portion CL, a source line SL, an interlayer insulating film 13, and an insulating film 12.

[0047] The laminated film 11 is provided above the transistor 31 of the circuit chip C2. That is, the laminated film 11 is arranged in the Z direction with respect to the substrate 15. The laminated film 11 is configured by alternately stacking multiple conductive layers 111 and multiple insulating layers (not shown) in the Z direction. One or more conductive layers 111 at the upper and lower ends of the laminated film 11 in the Z direction function, for example, as a source-side select gate line SGS and a drain-side select gate line SGD. The source-side select gate line SGS is provided, for example, in an upper region of the laminated film 11. The drain-side select gate line SGD is provided, for example, in a lower region of the laminated film 11. The conductive layer 111 arranged between the source-side select gate line SGS and the drain-side select gate line SGD functions as a word line WL. A bit line BL is arranged below the laminated film 11. The bit line BL is formed to extend in the Y direction.

[0048] A staircase structure 21 is provided at an end of the laminated film 11 in the X direction. A portion of the laminated film 11 that functions as a word line WL is electrically connected to a wiring layer 23 via a contact 22. The source line SL is provided above the laminated film 11 via an insulating film. The source line SL has a lower layer SL1 and an upper layer SL2. The lower layer SL1 is made of a semiconductor material such as silicon. The upper layer SL2 is made of a metal material such as tungsten.

[0049] The columnar portion CL is provided in the stacked film 11 so as to penetrate in the Z direction. The lower end of the columnar portion CL is electrically connected to the bit line BL through a via plug 24. The bit line BL is included in the wiring layer 23. The upper end of the columnar portion CL is electrically connected to the source line SL. A wiring layer 43 including a via plug V is provided below the wiring layer 23. A via plug 42 is provided below the wiring layer 43. A plurality of metal pads 41 are provided below the via plug 42. The via plug 24, the wiring layers 23, 42, 43, and the metal pad 41 are formed of a low-resistance metal such as copper or tungsten.

[0050] The insulating film 12 is provided above the stacked film 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride (SiN) film. A via plug 45 is provided in a portion of the array chip C1 that is offset from the stacked film 11 in the X direction. The via plug 45 is formed to extend upward from the wiring layer 23. A metal pad 46 is provided on the upper surface of the insulating film 12. The upper end of the via plug 45 penetrates the insulating film 12 and is electrically connected to the metal pad 46. The metal pad 46 is, for example, a metal film containing copper. The metal pad 46 functions as an external connection pad for the semiconductor memory device 200. A passivation film 47 is further provided on the upper surface of the insulating film 12 so as to expose the metal pad 46. The passivation film 47 is, for example, a silicon oxide film. The passivation film 47 has an opening P for exposing the upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or another device via a bonding wire or the like through the opening P.

[0051] The interlayer insulating film 13 of the array chip C1 and the interlayer insulating film 14 of the circuit chip C2 are bonded to each other at a bonding surface S. Furthermore, the metal pads 41 of the array chip C1 and the metal pads 38 of the circuit chip C2 are joined to each other at the bonding surface S. As a result, the array chip C1 and the circuit chip C2 are electrically connected to each other via the metal pads 38, 41.

[0052] Fig. 5 is a cross-sectional view showing the cross-sectional structure of a columnar portion CL in a semiconductor memory device 200 according to an embodiment. That is, Fig. 5 is a cross-sectional view showing the cross-sectional structure of the laminated film 11 when the columnar portion CL is cut along a plane (XZ plane) passing through its central axis. Fig. 6 is a cross-sectional view showing the cross section VI-VI of Fig. 5 in the semiconductor device according to the embodiment. Next, the structure of the laminated film 11 will be described with reference to Figs. 5 and 6.

[0053] As shown in FIG. 5, the stacked film 11 has a structure in which conductive layers 111 and insulating layers 51 are alternately stacked in the Z direction. The conductive layer 111 is a layer having conductivity. The conductive layer 111 has a metal film 111b, a barrier metal film 111a, and a first block film 53b. The first block film 53b is a part of the block insulating film 53. The barrier metal film 111a is an example of a first film. The block insulating film 53 is an example of an insulating film. The first block film 53b is an example of a first insulating film.

[0054] A plurality of memory holes MH are formed in the stacked film 11 so as to extend in the Z direction. The memory holes MH are an example of first recesses. A columnar portion CL shown in FIG. 4 is provided inside each memory hole MH. Each columnar portion CL corresponds to a NAND string SR shown in FIG. 3.

[0055] As shown in FIG. 6, the columnar portion CL has a circular or elliptical cross-sectional shape. The columnar portion CL has, from the outside to the inside of the memory hole MH, a second block film 53a, a charge storage film 61, a tunnel insulating film 62, a channel semiconductor film 63, and a core insulating film 64, in that order. The second block film 53a is another part of the block insulating film 53. The second block film 53a is an example of a second insulating film. The tunnel insulating film 62 is an example of a third insulating film. The channel semiconductor film 63 is an example of a semiconductor film. The core insulating film 64 is an example of a fourth insulating film. The second block film 53a, the charge storage film 61, and the tunnel insulating film 62 are collectively referred to as a memory film. The channel semiconductor film 63 and the core insulating film 64 are collectively referred to as a body.

[0056] The metal film 111b of the conductive layer 111 contains, for example, molybdenum (Mo) as a main component. The metal film 111b may contain transition elements other than molybdenum, such as tungsten (W), titanium (Ti), and niobium (Nb).

[0057] The barrier metal film 111a of the conductive layer 111 covers the metal film 111b. The barrier metal film 111a improves adhesion between the conductive layer 111 and the first block film 53b. To suppress deterioration of data retention characteristics, the barrier metal film 111a contains titanium silicon nitride (TiSiN) as a main component. The silicon concentration in the barrier metal film 111a may be 54% or more. The thickness of the barrier metal film 111a may be 3 nm or less.

[0058] The conductive layers 111 are used as the word lines WL0 to WL7 and the select gate lines SGS, SGD, etc. in FIG.

[0059] The insulating layer 51 is disposed between the conductive layers 111, 111 adjacent to each other in the Z direction. The insulating layer 51 electrically insulates the conductive layers 111, 111 adjacent to each other. The insulating layer 51 is formed of, for example, silicon oxide (SiO2).

[0060] The first blocking film 53b of the block insulating film 53 is provided in contact with the barrier metal film 111a. The first blocking film 53b suppresses back tunneling of charges from the conductive layer 111 to the memory films 53a, 61, and 62. The first blocking film 53b contains, for example, aluminum oxide (Al2O3) as a main component.

[0061] The second block film 53a is provided between the first block film 53b and the charge storage film 61. That is, the block insulating film 53 is provided between the conductive layer 111 and the charge storage film 61. The second block film 53a suppresses back tunneling of charges from the conductive layer 111 to the memory films 61, 62. The second block film 53a also protects the charge storage film 61 from being etched in a replacement step in which the sacrificial layer 55 (see FIG. 8) is replaced with the conductive layer 111 during the manufacture of the semiconductor memory device 200. The second block film 53a is also called a cover insulating film. The second block film 53a contains, for example, silicon oxide (SiO2) as a main component.

[0062] In this embodiment, the barrier metal film 111a contains titanium silicon nitride (TiSiN), which has barrier properties against hydrogen. Since the barrier metal film 111a contains titanium silicon nitride, the concentration of hydrogen contained in the memory cell array 201 is set to a concentration suitable for suppressing electron leakage in the charge storage film 61. Hydrogen is an example of an impurity.

[0063] Specifically, the hydrogen concentration is high at the interface between the barrier metal film 111a and the first blocking film 53b, and low in the second blocking film 53a. The hydrogen concentration is an example of the concentration of an impurity.

[0064] Furthermore, the hydrogen concentration in the first blocking film 53b may be high, and the hydrogen concentration in the second blocking film 53a may be low.

[0065] The hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b is 1×10 20 atoms / cm 3 The second blocking film 53a may have a first portion having a hydrogen concentration lower than that at the interface between the barrier metal film 111a and the first blocking film 53b, and a second portion located closer to the charge storage film 61 than the first portion. The second portion is thicker than the first portion (i.e., the thickness in the radial direction of the memory hole MH) and has a hydrogen concentration lower than that of the first portion, 1×10 20 atoms / cm 3 That is, the second block film 53a has a lower hydrogen concentration than the interface between the barrier metal film 111a and the block insulating film 53, and the hydrogen concentration is 1×10 20 atoms / cm 3 It may be the following:

[0066] The hydrogen concentration in the barrier metal film 111a may increase from the metal film 111b side toward the block insulating film 53. The hydrogen concentration in the block insulating film 53 may decrease from the barrier metal film 111a side toward the charge storage film 61 side.

[0067] The hydrogen concentration in the barrier metal film 111a may substantially monotonically increase from the metal film 111b side toward the block insulating film 53 side. The hydrogen concentration in the block insulating film 53 may substantially monotonically decrease from the barrier metal film 111a side toward the charge storage film 61 side.

[0068] In addition, the hydrogen concentration may have a maximum value when it changes from an increasing trend to a decreasing trend near the interface between the barrier metal film 111a and the first blocking film 53b.

[0069] The hydrogen concentration in the barrier metal film 111a on the block insulating film 53 side is 1×10 20 atoms / cm 3 In this case, the part of the barrier metal film 111a may be a portion closer to the other end than the intermediate position between one end of the barrier metal film 111a on the metal film 111b side and the other end of the barrier metal film 111a on the block insulating film 53 side.

[0070] Furthermore, in the second blocking film 53a, the amount of decrease in hydrogen concentration from the barrier metal film 111a side toward the charge storage film 61 side may be larger than the amount of decrease in hydrogen concentration in the first blocking film 53b.

[0071] The charge storage film 61 faces the side surface of the conductive layer 111. The charge storage film 61 is, for example, a silicon nitride film. The charge storage film 61 has trap sites that trap charges within the film. The portion of the charge storage film 61 sandwiched between the conductive layer 111 and the channel semiconductor film 63 forms a region that stores charges, i.e., a storage region of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT changes depending on the presence or absence of charges in the charge storage film 61 or the amount of the charges. The memory cell transistor MT of this embodiment is a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that uses an insulating film for the charge storage film 61.

[0072] The tunnel insulating film 62 is provided on the side of the charge storage film 61 opposite to the block insulating film 53. The tunnel insulating film 62 contains, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 62 functions as a potential barrier between the channel semiconductor film 63 and the charge storage film 61. For example, when electrons are injected from the channel semiconductor film 63 to the charge storage film 61 (i.e., during a write operation), the electrons pass through the potential barrier of the tunnel insulating film 62 (i.e., tunneling). Also, when holes are injected from the channel semiconductor film 63 to the charge storage film 61 (i.e., during an erase operation), the holes pass through the potential barrier of the tunnel insulating film 62.

[0073] The channel semiconductor film 63 is provided on the side of the tunnel insulating film 62 opposite to the charge storage film 61. The channel semiconductor film 63 is made of, for example, polysilicon (Poly-Si). The channel semiconductor film 63 forms channels of the memory cell transistors MT and the like.

[0074] The core insulating film 64 is provided on the side of the channel semiconductor film 63 opposite to the tunnel insulating film 62. The core insulating film 64 is made of, for example, silicon oxide.

[0075] Next, a manufacturing method of the semiconductor memory device 200 will be described. FIG. 7 is a cross-sectional view showing a manufacturing method of the semiconductor memory device 200 according to the embodiment. First, as shown in FIG. 7, a memory cell array 201, an insulating film 12, an interlayer insulating film 13, a staircase structure 21, a metal pad 41, and the like are formed on the substrate 16 of the memory wafer W1. At this time, via plugs 45, a wiring layer 44, a wiring layer 43, a via plug 42, and a metal pad 41 are formed in this order on the substrate 16. Also, an interlayer insulating film 14, a transistor 31, a metal pad 38, and the like are formed on the substrate 15 of the circuit wafer W2. At this time, contact plugs 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, and a metal pad 38 are formed in this order on the substrate 15. Next, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400°C. As a result, the metal pad 41 and the metal pad 38 are bonded together.

[0076] Thereafter, the substrate 15 is thinned by CMP, the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor memory device 200 shown in Fig. 4 is manufactured. Note that the metal pads 46 and the passivation film 47 are formed on the insulating film 12, for example, after the substrate 15 is thinned and the substrate 16 is removed.

[0077] FIG. 8 is a cross-sectional view illustrating a detailed manufacturing method of the semiconductor memory device 200 according to the embodiment. More specifically, as shown in FIG. 8(a), a stacked film 70 is first formed above the substrate 16 (see FIG. 7) by alternately stacking multiple insulating layers 51 and multiple sacrificial layers 55. The sacrificial layer 55 is an example of a first layer. The insulating layer 51 is, for example, a SiO2 film. The insulating layer 51 is formed, for example, by plasma CVD (Chemical Vapor Deposition) using SiH4 gas and N2O gas. The sacrificial layer 55 is a layer to be replaced with the conductive layer 111. The sacrificial layer 55 is, for example, a SiN film. The sacrificial layer 55 is formed, for example, by plasma CVD using SiH2Cl2 gas and NH3 gas. After the stacked film 70 is formed, memory holes MH are formed through the stacked film 70 as shown in FIG. 8(b). The memory holes MH are formed, for example, by lithography and RIE (Reactive Ion Etching).

[0078] 9A to 9C are cross-sectional views showing the manufacturing method of the semiconductor memory device 200 according to the embodiment, following FIG. 8. After the memory holes MH are formed, the columnar portions CL are embedded in the memory holes MH, as shown in FIG.

[0079] That is, first, second block films 53a are formed on the side surfaces of the conductive layer 51 and the sacrificial layer 55. The second block film 53a is, for example, a SiO2 film. The second block film 53a is formed by, for example, an atomic layer deposition (ALD) method using tris(dimethylamino)silane (TDMAS) gas. The second block film 53a may be formed on the side surfaces of the sacrificial layer 55 by directly oxidizing the side surfaces of the sacrificial layer 55 by radical oxidation.

[0080] After forming the second blocking film 53a, a charge storage film 61 is formed on the side of the second blocking film 53a opposite to the conductive layer 51 and the sacrificial layer 55. The charge storage film 61 is, for example, a SiN film. The charge storage film 61 is formed by, for example, the ALD method using SiH2Cl2 gas and NH3 gas in a reduced pressure environment (2000 Pa or less) at a temperature of 300°C or higher and 800°C or lower.

[0081] After forming the charge storage film 61, a tunnel insulating film 62 is formed on the side of the charge storage film 61 opposite the second block film 53a. The tunnel insulating film 62 is, for example, a SiON film. The tunnel insulating film 62 is formed by, for example, the ALD method using HCD (hexachlorodisilane) gas, NH gas, and O gas in a reduced pressure environment (2000 Pa or less) at a temperature of 400°C or higher and 800°C or lower.

[0082] After forming the tunnel insulating film 62, a channel semiconductor film 63 is formed on the side of the tunnel insulating film 62 opposite to the charge storage film 61. The channel semiconductor film 63 is, for example, a Si film. The channel semiconductor film 63 is formed by, for example, CVD using SiH4 gas in a reduced pressure environment (2000 Pa or less) at a temperature of 400°C or higher and 800°C or lower, and is then crystallized by annealing. This changes the Si film from amorphous silicon to polysilicon.

[0083] After forming the channel semiconductor film 63, a core insulating film 64 is formed on the side of the channel semiconductor film 63 opposite to the tunnel insulating film 62. The core insulating film 64 is, for example, an SiO2 film. The core insulating film 64 is formed by, for example, a CVD method using TEOS (tetraethyl orthosilicate).

[0084] After the columnar portion CL is embedded in the memory hole MH as described above, a groove (not shown) is formed in the stacked film 70. After the groove is formed, the sacrificial layer 55 is removed by wet etching using the formed groove. A chemical solution such as hot phosphoric acid is used for the wet etching. By removing the sacrificial layer 55, a cavity C is formed between the adjacent insulating layers 51, 51, as shown in FIG. 9(b). The cavity C is an example of a second recess. In the cavity C, the surface of the insulating layer 51 in the Z direction and the side surface of the second block film 53a are exposed.

[0085] 10 is a cross-sectional view showing a manufacturing method of the semiconductor memory device 200 according to the embodiment, following FIG. 9. After forming the cavity C, as shown in FIG. 10(a), a first blocking film 53b is formed on the Z-direction surface of the insulating layer 51 and on the side surface of the second blocking film 53a. The first blocking film 53b is, for example, an Al2O3 film. The first blocking film 53b is formed by, for example, the ALD method using AlCl3 gas and O3 gas in a reduced pressure environment (2000 Pa or less) at a temperature of 200°C or higher and 500°C or lower.

[0086] After forming the first block film 53b, as shown in FIG. 10(b), a barrier metal film 111a is formed in the cavity C in which the first block film 53b is formed. The barrier metal film 111a is, for example, a TiSiN film. The barrier metal film 111a is formed by repeating cyclic film formation of a TiN film and a SiN film, for example, by a CVD method or an ALD method. The TiN film is formed using TiCl4 gas and NH3 gas. The SiN film is formed using SiH2Cl2 gas and NH3 gas. After forming the barrier metal film 111a, a metal film 111b (see FIG. 5) is formed in the cavity C in which the barrier metal film 111a is formed. The metal film 111b is, for example, a Mo film. The metal film 111b is formed, for example, by an ALD method using MoO2Cl2 gas and H2 gas in an environment of 600°C.

[0087] (Example) Next, a specific example of the above-described embodiment will be described. In the following example, the data retention characteristics of the semiconductor memory device 200 will be described in comparison with a comparative example. Figure 11 is an explanatory diagram for explaining the data retention characteristics of the semiconductor memory device 200 according to the example.

[0088] 11, the semiconductor memory device according to the comparative example includes, in order in the X direction, a metal film 111b made of a Mo film, a barrier metal film 111a made of a TiN film, a first block film 53b made of an Al2O3 film, a second block film 53a made of a SiO2 film, and a charge storage film 61 made of a SiN film. Note that the configuration inside the memory hole MH from the charge storage film 61 is omitted. In the semiconductor memory device according to the comparative example, the barrier metal film 111a is made of a TiN film. Therefore, it is difficult for the barrier metal film 111a to suppress the diffusion of hydrogen from the metal film 111b side to the block insulating film 53 side. Note that in FIG. 11, "H" represents hydrogen, "O" represents oxygen, "OH" represents OH radicals (i.e., hydroxyl radicals), and "e" represents electrons. Because it is difficult for the barrier metal film 111a to suppress the diffusion of hydrogen, hydrogen and oxygen combine to generate OH radicals in the second block film 53a. Because OH radicals have strong oxidizing power, they tend to steal electrons stored in the charge storage film 61. This causes electron loss, in which electrons move toward the second block film 53a, in the charge storage film 61. This electron loss deteriorates the data retention characteristics.

[0089] 11 , the semiconductor memory device 200 according to the embodiment differs from the semiconductor memory device according to the comparative example in that the barrier metal film 111a is made of a TiSiN film. Because it is made of a TiSiN film, the barrier metal film 111a according to the embodiment can suppress hydrogen diffusion from the metal film 111b side to the block insulating film 53 side. Because the barrier metal film 111a can suppress hydrogen diffusion, it can suppress the generation of OH radicals due to the combination of hydrogen and oxygen in the second block film 53a. This can suppress electron loss in the charge storage film 61. By suppressing electron loss, it is possible to suppress degradation of data retention characteristics.

[0090] Next, we will explain the characteristics related to hydrogen concentration measured from the semiconductor memory device of the comparative example and the semiconductor memory device 200 of the example. The characteristics shown below can be obtained by composition analysis such as SIMS (Secondary Ion Mass Spectrometry), for example.

[0091] 12 is a graph showing the relationship between the thickness of the barrier metal film 111a and the hydrogen concentration in the second blocking film 53a in the semiconductor memory device 200 according to the embodiment. In FIG. 12, the horizontal axis represents the thickness (nm) of the barrier metal film 111a, and the vertical axis represents the hydrogen concentration (atoms / cm) in the second blocking film 53a. 3 ) in FIG. 12, the symbol A indicates the hydrogen concentration in the second block film 53a in the semiconductor memory device 200 according to the embodiment. That is, the symbol A indicates the hydrogen concentration in the second block film 53a when the barrier metal film 111a is made of a TiSiN film. The symbol B in FIG. 12 indicates the hydrogen concentration in the second block film 53a in the semiconductor memory device according to the comparative example. That is, the symbol B indicates the hydrogen concentration in the second block film 53a when the barrier metal film 111a is made of a TiN film.

[0092] 12, the hydrogen concentration in the second block film 53a varies depending on the thickness of the barrier metal film 111a. As is clear from Fig. 12, for the same thickness of the second block film 53a, the hydrogen concentration in the second block film 53a is lower when the barrier metal film 111a is made of a TiSiN film than when the barrier metal film 111a is made of a TiN film. This shows that the semiconductor memory device 200 according to the example is better at suppressing hydrogen diffusion from the metal film 111b side to the block insulating film 53 side than the semiconductor memory device according to the comparative example.

[0093] 13 is a graph showing the relationship between the depth of the memory hole MH in the direction from the periphery toward the center and the hydrogen concentration in the semiconductor memory device 200 according to the embodiment. In FIG. 13, the horizontal axis represents the depth (nm). The vertical axis represents the hydrogen concentration (atoms / cm 3 ) in FIG. 13. In FIG. 13, components corresponding to a range of depths are shown corresponding to the horizontal axis. In FIG. 13, the position of depth 0 (nm) is taken on the metal film 111b. Hydrogen concentrations corresponding to a depth range of 0 (nm) to 40 (nm) are not shown. Symbol A in FIG. 13 indicates the hydrogen concentration of the semiconductor memory device 200 according to the embodiment in which the barrier metal film 111a is made of a TiSiN film. Symbol B in FIG. 13 indicates the hydrogen concentration of the semiconductor memory device according to the comparative example in which the barrier metal film 111a is made of a TiN film.

[0094] 13, the semiconductor memory device according to the comparative example has a low hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b and a high hydrogen concentration in the second blocking film 53a. In contrast, the semiconductor memory device 200 according to the embodiment has a high hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b and a low hydrogen concentration in the second blocking film 53a. Therefore, the semiconductor memory device according to the comparative example and the semiconductor memory device 200 according to the embodiment have opposite magnitude relationships between the hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b and the hydrogen concentration in the second blocking film 53a. A high hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b means that hydrogen diffusion from the metal film 111b side to the block insulating film 53 side at the interface is suppressed.

[0095] 13, the semiconductor memory device according to the comparative example has a low hydrogen concentration in the first blocking film 53b and a high hydrogen concentration in the second blocking film 53a. In contrast, the semiconductor memory device 200 according to the embodiment has a high hydrogen concentration in the first blocking film 53b and a low hydrogen concentration in the second blocking film 53a. Therefore, the magnitude relationship between the hydrogen concentration in the first blocking film 53b and the hydrogen concentration in the second blocking film 53a is reversed between the semiconductor memory device according to the comparative example and the semiconductor memory device 200 according to the embodiment.

[0096] In the example shown in FIG. 13, the semiconductor memory device according to the comparative example has a hydrogen concentration of 1×10 at the interface between the barrier metal film 111a and the first blocking film 53b. 20 (i.e., 1E+20) atoms / cm 3 In contrast, in the semiconductor memory device 200 according to the embodiment, the hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b is lower than 1×10 20 atoms / cm 3Therefore, the semiconductor memory device according to the comparative example and the semiconductor memory device 200 according to the embodiment have a hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b that is higher than 1×10 20 atoms / cm 3 The magnitude relationship between these is reversed.

[0097] In the example shown in FIG. 13, the second blocking film 53a of the semiconductor memory device according to the comparative example has a hydrogen concentration of 1×10 20 atoms / cm 3 a first portion having a hydrogen concentration of 1×10 or more; 20 atoms / cm 3 The first portion is located closer to the charge storage film 61 than the second portion. The dashed line b2 in FIG. 13 indicates the boundary between the first portion and the second portion in the second blocking film 53a of the comparative example. In the second blocking film 53a of the comparative example, the thickness of the second portion is approximately the same as the thickness of the first portion. In contrast, the second blocking film 53a of the semiconductor memory device 200 according to the embodiment also has a hydrogen concentration of 1×10 20 atoms / cm 3 a first portion having a hydrogen concentration of 1×10 or more; 20 atoms / cm 3 13 indicates the boundary between the first and second portions in the second blocking film 53a of the example. Also, in the second blocking film 53a of the example, the first portion has a lower hydrogen concentration than the interface between the barrier metal film 111a and the first blocking film 53b. Also, in the second blocking film 53a of the example, the second portion is thicker than the first portion. That is, the second blocking film 53a of the example has a lower hydrogen concentration than the interface between the barrier metal film 111a and the block insulating film 53, and the hydrogen concentration is 1×10 20 atoms / cm 3 Therefore, in the semiconductor memory device according to the comparative example and the semiconductor memory device 200 according to the embodiment, the hydrogen concentration in the second blocking film 53a is 1×10 20 atoms / cm3 The arrangement of the following parts is different from each other.

[0098] 13 , in the semiconductor memory device according to the comparative example, the hydrogen concentration in the barrier metal film 111a frequently increases and decreases from the metal film 111b side toward the block insulating film 53 side, and suddenly rises at the interface with the first block film 53b. In addition, in the semiconductor memory device according to the comparative example, the hydrogen concentration in the block insulating film 53 increases from the barrier metal film 111a side toward the charge storage film 61 side. In contrast, in the semiconductor memory device 200 according to the embodiment, the hydrogen concentration in most of the barrier metal film 111a increases from the metal film 111b side toward the block insulating film 53 side. That is, the hydrogen concentration in the barrier metal film 111a increases substantially monotonically from the metal film 111b side toward the block insulating film 53 side. In addition, in the semiconductor memory device 200 according to the embodiment, the hydrogen concentration in most of the block insulating film 53 decreases from the barrier metal film 111a side toward the charge storage film 61 side. That is, the hydrogen concentration in the block insulating film 53 decreases substantially monotonically from the barrier metal film 111a side toward the charge storage film 61 side. Therefore, the semiconductor memory device according to the comparative example and the semiconductor memory device 200 according to the embodiment have different characteristics of changes in the hydrogen concentration in the barrier metal film 111a and the block insulating film 53.

[0099] 13, the hydrogen concentration has a maximum value LM in the first blocking film 53b near the interface between the barrier metal film 111a and the first blocking film 53b when the hydrogen concentration changes from an increasing trend to a decreasing trend.

[0100] In addition, in the semiconductor memory device 200 according to the embodiment, the hydrogen concentration in the barrier metal film 111a on the block insulating film 53 side is 1×10 20 atoms / cm 3The part of the barrier metal film 111a is a portion closer to the other end than the intermediate position between one end of the barrier metal film 111a on the metal film 111b side and the other end of the barrier metal film 111a on the block insulating film 53 side.

[0101] Furthermore, in the semiconductor memory device 200 according to the embodiment, the amount of decrease in hydrogen concentration in the second blocking film 53a in the direction from the barrier metal 111a side to the charge storage film 61 side is greater than the amount of decrease in hydrogen concentration in the first blocking film 53b in the direction from the barrier metal 111a side to the charge storage film 61 side.

[0102] FIG. 14 is a graph showing the relationship between the thickness of the barrier metal film 111a and the data retention characteristics in a semiconductor memory device 200 according to an embodiment. In FIG. 14, the horizontal axis represents the thickness (nm) of the barrier metal film 111a. The vertical axis represents the Vth shift (V), which is the shift in threshold voltage Vth when a write process is performed at 8V. A smaller Vth shift indicates better data retention characteristics. Symbol A in FIG. 14 represents the Vth shift of the semiconductor memory device 200 according to an embodiment in which the barrier metal film 111a is made of a TiSiN film. Symbol B in FIG. 14 represents the Vth shift of the semiconductor memory device according to a comparative example in which the barrier metal film 111a is made of a TiN film.

[0103] As can be seen from FIG. 14, for the same thickness of the barrier metal film 111a, the semiconductor memory device 200 according to the embodiment has a smaller Vth shift amount than the semiconductor memory device according to the comparative example. That is, for the same thickness of the barrier metal film 111a, the semiconductor memory device 200 according to the embodiment has better data retention characteristics than the semiconductor memory device according to the comparative example. Also, as can be seen from FIG. 14, in the semiconductor memory device 200 according to the embodiment, when the thickness of the barrier metal film 111a is greater than 3 nm, the Vth shift amount actually increases as the thickness of the barrier metal film 111a increases. Therefore, it is preferable that the thickness of the barrier metal film 111a be 3 nm or less.

[0104] FIG. 15 is a graph showing the relationship between the hydrogen concentration in the second block film 53a and the data retention characteristics in a semiconductor memory device 200 according to an embodiment. In FIG. 15, the horizontal axis represents the thickness (nm) of the barrier metal film 111a. The vertical axis represents the Vth shift (V). Four circular points in FIG. 15 represent the Vth shift of the semiconductor memory device 200 according to an embodiment in which the barrier metal film 111a is composed of a TiSiN film. The four circular points in FIG. 15 correspond to the four circular points on the graph for the embodiment in FIG. 12. Two square points in FIG. 15 represent the Vth shift of a semiconductor device according to a comparative example in which the barrier metal film 111a is composed of a TiN film. The two square points in FIG. 15 correspond to the two square points on the graph for the comparative example in FIG. 12.

[0105] 15, the hydrogen concentration in the second block film 53a is lower in the semiconductor memory device 200 according to the embodiment than in the semiconductor memory device according to the comparative example. Also, as can be seen from FIGS. 12 and 15, the Vth shift amount is significantly smaller in the semiconductor memory device 200 according to the embodiment than in the semiconductor memory device according to the comparative example, when the thickness of the barrier metal film 111a is the same.

[0106] FIG. 16 is a graph showing the relationship between the thickness of the barrier metal film 111a and the data retention characteristics in a semiconductor memory device 200 according to an embodiment. In FIG. 16, the horizontal axis represents the thickness (nm) of the barrier metal film 111a. The vertical axis represents the Vth shift (V). Symbol A1 in FIG. 16 represents the Vth shift of the semiconductor memory device 200 according to the first embodiment, in which the barrier metal film 111a is composed of a TiSiN film. The TiSiN film (i.e., the barrier metal film 111a) of the semiconductor memory device 200 according to the first embodiment is formed by repeating cyclic film formation of TiN and cyclic film formation of SiN under the condition that the SiN / TiN cycle ratio is 1. Symbol A2 in FIG. 16 represents the Vth shift of the semiconductor memory device 200 according to the second embodiment, in which the barrier metal film 111a is composed of a TiSiN film. The TiSiN film of the semiconductor memory device 200 according to the second embodiment is formed by repeating cyclic film formation of TiN and cyclic film formation of SiN under the condition of a SiN / TiN cycle ratio of 3. Reference symbol A3 in FIG. 16 indicates the Vth shift amount of the semiconductor memory device 200 according to the third embodiment, in which the barrier metal film 111a is composed of a TiSiN film. The TiSiN film of the semiconductor memory device 200 according to the third embodiment is formed by repeating cyclic film formation of TiN and cyclic film formation of SiN under the condition of a SiN / TiN cycle ratio of 5. Reference symbol A4 in FIG. 16 indicates the Vth shift amount of the semiconductor memory device 200 according to the fourth embodiment, in which the barrier metal film 111a is composed of a TiSiN film. The TiSiN film of the semiconductor memory device 200 according to the fourth embodiment is formed by repeating cyclic film formation of TiN and cyclic film formation of SiN under the condition of a SiN / TiN cycle ratio of 7. The symbol B in FIG. 16 indicates the Vth shift amount of the semiconductor memory device according to the comparative example in which the barrier metal film 111a is made of a TiN film.

[0107] 16, the higher the SiN / TiN cycle ratio, the higher the silicon content in the barrier metal film 111a, and the more effectively the Vth shift can be reduced. In the semiconductor memory device 200 according to the third embodiment, the silicon concentration in the barrier metal film 111a is 54%.

[0108] 17 is a graph showing the relationship between the cycle ratio between SiN and TiN and the data retention characteristics in the semiconductor memory device 200 according to the embodiment. In FIG. 17, the horizontal axis represents the SiN / TiN cycle ratio, and the vertical axis represents the Vth shift amount (V). Symbol A in FIG. 1nm indicates the Vth shift amount when the thickness of the barrier metal film 111a is 1 nm. 2nm indicates the Vth shift amount when the thickness of the barrier metal film 111a is 2 nm. 3nm indicates the Vth shift amount when the thickness of the barrier metal film 111a is 3 nm.

[0109] As can be seen from FIG. 17, when the thickness of the barrier metal film 111a is 3 nm, the Vth shift amount can be reduced more effectively.

[0110] As described above, the semiconductor memory device 200 of this embodiment includes a plurality of conductive layers 111, a charge storage film 61, and a block insulating film 53. The plurality of conductive layers 111 are spaced apart from one another in the Z direction. The plurality of conductive layers 111 include a metal film 111b and a barrier metal film 111a that covers the metal film 111b and contains titanium silicon nitride. The charge storage film 61 faces a side surface of the conductive layer 111. The block insulating film 53 is provided between the conductive layer 111 and the charge storage film 61.

[0111] As a result, the barrier metal film 111a containing titanium silicon nitride can suppress the diffusion of hydrogen from the metal film 111b side to the block insulating film 53 side. Since the diffusion of hydrogen can be suppressed, the generation of OH radicals, which have high oxidizing power, in the block insulating film 53 can be suppressed. Since the generation of OH radicals can be suppressed, electron loss, in which charges stored in the charge storage film 61 move to the block insulating film 53, can be suppressed. As a result, deterioration of data retention characteristics can be suppressed.

[0112] In this embodiment, the concentration of silicon in the barrier metal film 111a is 54% or more.

[0113] This further enhances the barrier properties of the barrier metal film 111a against hydrogen, thereby more effectively suppressing the diffusion of hydrogen from the metal film 111b side to the block insulating film 53 side, thereby more effectively suppressing the deterioration of data retention characteristics.

[0114] In this embodiment, the thickness of the barrier metal film 111a is 3 nm or less.

[0115] This allows selection of a film thickness that is effective in reducing the Vth shift amount, thereby making it possible to more effectively suppress the deterioration of data retention characteristics.

[0116] In this embodiment, the block insulating film 53 has a first block film 53b provided in contact with the barrier metal film 111a, and a second block film 53a provided between the first block film 53b and the charge storage film 61.

[0117] This makes it possible to suppress the diffusion of hydrogen at the interface between the barrier metal film 111a and the first blocking film 53b, thereby reducing the hydrogen concentration in the second blocking film 53a.

[0118] In this embodiment, the first blocking film 53b contains aluminum oxide, and the second blocking film 53a contains silicon oxide.

[0119] This effectively suppresses the diffusion of hydrogen at the interface between the barrier metal film 111a and the first blocking film 53b, and effectively reduces the hydrogen concentration in the second blocking film 53a.

[0120] In this embodiment, the hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b is higher than the hydrogen concentration in the second blocking film 53a.

[0121] This makes it possible to sufficiently suppress the diffusion of hydrogen at the interface between the barrier metal film 111a and the first blocking film 53b, thereby more effectively reducing the hydrogen concentration in the second blocking film 53a.

[0122] In this embodiment, the hydrogen concentration in the first blocking film 53b is higher than the hydrogen concentration in the second blocking film 53a.

[0123] This makes it possible to further reduce the hydrogen concentration in the second blocking film 53a.

[0124] In this embodiment, the hydrogen concentration at the interface between the barrier metal film 111a and the first blocking film 53b is 1×10 20 atoms / cm 3 The second blocking film 53a has a first portion having a lower hydrogen concentration than the interface between the barrier metal film 111a and the first blocking film 53b, and a second portion located closer to the charge storage film 61 than the first portion. The second portion is thicker than the first portion and has a lower hydrogen concentration than the first portion, 1×10 20 atoms / cm 3 The following is the result.

[0125] As a result, the hydrogen concentration in most of the second blocking film 53a is reduced to 1×10 20 atoms / cm 3 Since the amount of the charge can be suppressed to below 100%, the deterioration of the data retention characteristics can be more effectively suppressed.

[0126] In this embodiment, the hydrogen concentration in the barrier metal film 111a increases from the metal film 111b side toward the block insulating film 53. The hydrogen concentration in the block insulating film 53 decreases from the barrier metal film 111a side toward the charge storage film 61 side.

[0127] As a result, the barrier metal film 111a and the block insulating film 53 have hydrogen concentration change characteristics that are effective in reducing the hydrogen concentration in the second block film 53a, making it possible to effectively suppress deterioration of the data retention characteristics.

[0128] In this embodiment, the hydrogen concentration in the barrier metal film 111a substantially monotonically increases from the metal film 111b side toward the block insulating film 53 side. The hydrogen concentration in the block insulating film 53 substantially monotonically decreases from the barrier metal film 111a side toward the charge storage film 61 side.

[0129] This makes it possible to more effectively reduce the hydrogen concentration in the second blocking film 53a.

[0130] In this embodiment, the hydrogen concentration has a maximum value near the interface between the barrier metal film 111a and the block insulating film 53.

[0131] This makes it possible to more effectively suppress the diffusion of hydrogen at the interface between the barrier metal film 111a and the block insulating film 53.

[0132] In this embodiment, the hydrogen concentration in the part of the barrier metal film 111a on the block insulating film 53 side is 1×10 20 atoms / cm 3 The part of the barrier metal film 111a is a portion closer to the other end than the intermediate position between one end of the barrier metal film 111a on the metal film 111b side and the other end of the barrier metal film 111a on the block insulating film 53 side.

[0133] This allows the barrier metal film 111a to more effectively suppress the diffusion of hydrogen from the metal film 111b side to the block insulating film 53 side.

[0134] In this embodiment, the decrease in hydrogen concentration in the second blocking film 53a from the barrier metal film 111a side toward the charge storage film 61 is greater than the decrease in hydrogen concentration in the first blocking film 53b from the barrier metal film 111a side toward the charge storage film 61.

[0135] This makes it possible to more effectively reduce the hydrogen concentration in the second blocking film 53a.

[0136] In this embodiment, the metal film 111b contains molybdenum.

[0137] Compared to tungsten, molybdenum has superior processability and is advantageous for achieving narrower pitches and higher integration. However, compared to tungsten, molybdenum has a higher impurity diffusion coefficient and is more likely to diffuse hydrogen, resulting in greater degradation of data retention characteristics due to the generation of OH radicals than tungsten. However, in this embodiment, the barrier metal film 111a containing TiSiN effectively suppresses hydrogen diffusion, thereby effectively suppressing degradation of data retention characteristics.

[0138] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel wafers and methods described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the wafers and methods described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0139] 111 conductive layer, 111a barrier metal film, 111b metal film, 53 block insulating film, 53a second block film, 53b first block film, 61 charge storage film, 62 tunnel insulating film, 63 channel semiconductor film, 64 core insulating film, 200 semiconductor memory device

Claims

1. a plurality of conductive layers spaced apart from one another in a first direction, the plurality of conductive layers including a metal film and a first film covering the metal film and including titanium silicon nitride; a charge storage film facing a side surface of the conductive layer; an insulating film provided between the conductive layer and the charge storage film; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the concentration of silicon in said first film is 54% or more.

3. 2. The semiconductor device according to claim 1, wherein the first film has a thickness of 3 nm or less.

4. 2. The semiconductor device according to claim 1, wherein said insulating film comprises a first insulating film provided in contact with said first film, and a second insulating film provided between said first insulating film and said charge storage film.

5. 5. The semiconductor device according to claim 4, wherein said first insulating film contains aluminum oxide, and said second insulating film contains silicon oxide.

6. 5. The semiconductor device according to claim 4, wherein the concentration of the impurity at the interface between the first film and the first insulating film is higher than the concentration of the impurity in the second insulating film.

7. 7. The semiconductor device according to claim 6, wherein the concentration of the impurity in the first insulating film is higher than the concentration of the impurity in the second insulating film.

8. The concentration of the impurity at the interface between the first film and the first insulating film is 1×10 ２０ atoms / cm ３ Higher than The second insulating film is a first portion having a lower concentration of the impurity than the interface; a first portion located on the charge storage film side of the first portion, having a thickness greater than that of the first portion, and having a lower impurity concentration than that of the first portion; ２０ atoms / cm ３ a second portion, The semiconductor device according to claim 6 , comprising:

9. 2. The semiconductor device according to claim 1, wherein a concentration of the impurity in said first film increases from said metal film side toward said insulating film side, and a concentration of the impurity in said insulating film decreases from said first film side toward said charge storage film side.

10. 10. The semiconductor device according to claim 9, wherein a concentration of the impurity in the first film substantially monotonically increases from the metal film side toward the insulating film side, and a concentration of the impurity in the insulating film substantially monotonically decreases from the first film side toward the charge storage film side.

11. 10. The semiconductor device according to claim 9, wherein the concentration of said impurity has a maximum value in the vicinity of the interface between said first film and said insulating film.

12. The concentration of the impurity in the part of the first film on the insulating film side is 1×10 ２０ atoms / cm ３ 10. The semiconductor device according to claim 9.

13. 13. The semiconductor device according to claim 12, wherein the portion of the first film is a portion closer to the other end than a midpoint between one end of the first film on the metal film side and the other end of the first film on the insulating film side.

14. the insulating film includes a first insulating film provided in contact with the first film, and a second insulating film provided between the first insulating film and the charge storage film; The second insulating film has a lower impurity concentration than the interface between the first film and the insulating film, and the impurity concentration is partially 1×10 ２０ atoms / cm ３ 13. The semiconductor device according to claim 12, wherein:

15. 15. The semiconductor device according to claim 14, wherein a decrease in concentration of the impurity in the second insulating film from the metal film side toward the charge storage film side is greater than a decrease in concentration of the impurity in the first insulating film from the metal film side toward the charge storage film side.

16. 16. The semiconductor device according to claim 6, wherein the impurity is hydrogen.

17. 2. The semiconductor device according to claim 1, wherein said metal film contains molybdenum.

18. a plurality of insulating layers spaced apart from one another in the first direction and stacked alternately with the conductive layers; a third insulating film provided on a side surface of the charge storage film opposite to the insulating film; a semiconductor film provided on a side surface of the third insulating film opposite to the charge storage film; a fourth insulating film provided on a side surface of the semiconductor film opposite to the third insulating film; The semiconductor device according to claim 1 , further comprising:

19. forming a plurality of conductive layers spaced apart from one another in a first direction, the plurality of conductive layers having a metal film and a first film covering the metal film and containing titanium silicon nitride; forming a charge storage film facing a side surface of the conductive layer; forming an insulating film between the conductive layer and the charge storage film; A method for manufacturing a semiconductor device, comprising:

20. forming a laminated film having a plurality of insulating layers and a plurality of first layers alternately in the first direction; forming a first recess penetrating the laminated film; removing the plurality of first layers to form a plurality of second recesses in the film stack; It further includes: forming the insulating film includes forming a second insulating film in the first recess and forming a first insulating film in the plurality of second recesses; the charge storage film is formed in the first recess via the second insulating film, 20. The method for manufacturing a semiconductor device according to claim 19, wherein forming the plurality of conductive layers includes forming the first film in the plurality of second recesses, and forming the metal film in the plurality of second recesses via the first film.

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