Semiconductor device

Abstract

To provide a semiconductor device in which the electric characteristic and the degree of integration are improved.SOLUTION: A semiconductor device according to one embodiment of the present invention includes a substrate including a first region and a second region apart from the first region, a cell stack structure in contact with the first region, and a peripheral gate structure in contact with the second region. The cell stack structure includes channel patterns that are overlapped on each other, a bit line electrically connected to at least one of the channel patterns and extending in a first direction, and a word line extending in a second direction intersecting with the first direction.SELECTED DRAWING: Figure 2C

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices that include peripheral gate structures. [Background technology]

[0002] Semiconductor devices have emerged as important components in the electronics industry due to their compact size, multi-functionality, and / or low manufacturing costs. Semiconductor devices may be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, as electronic devices become faster and consume less power, the semiconductor devices built therein are also required to have faster operating speeds and / or lower operating voltages. To meet these requirements, more highly integrated semiconductor devices are needed. However, as the integration of semiconductor devices becomes more advanced, the electrical characteristics and production yield of the semiconductor devices can decrease. Therefore, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 11,637,104 B2 Summary of the Invention

[0005] [Problem to be solved by the invention] The problem to be solved by the present invention is to provide a semiconductor device with improved electrical characteristics and integration density.

[0006] [Means for solving the problem] According to some embodiments, a semiconductor device may include a substrate including a first region and a second region spaced apart from the first region, a cell stack structure in contact with the first region, and a peripheral gate structure in contact with the second region, wherein the cell stack structure may include overlapping channel patterns, a bit line electrically connected to at least one of the channel patterns and extending in a first direction, and a word line extending in a second direction intersecting the first direction.

[0007] A semiconductor device according to some embodiments may include a substrate including a first region and a second region separated from the first region, a cell stack structure on the first region, a dummy stack structure on the second region, a semiconductor structure on the cell stack structure and the dummy stack structure, and a peripheral gate structure on the semiconductor structure, wherein the cell stack structure may include a channel pattern and an insulating pattern alternately stacked with each other, and the dummy stack structure may include a dummy channel pattern and a dummy pattern alternately stacked with each other.

[0008] According to some embodiments, a semiconductor device may include a substrate including a first region and a second region separated from the first region, a cell stack structure in contact with the first region, a peripheral gate insulating film in contact with the second region, a peripheral gate electrode on the peripheral gate insulating film, a peripheral gate capping film on the peripheral gate electrode, a liner covering the peripheral gate capping film, and a peripheral gate contact passing through the liner and the peripheral gate capping film to contact the peripheral gate electrode, wherein the cell stack structure may include a data storage structure, a bit line separated from the data storage structure, channel patterns disposed between the bit line and the data storage structure and overlapping each other, and a word line disposed between the bit line and the data storage structure.

[0009] According to some embodiments, a method for manufacturing a semiconductor device may include providing a substrate including a first region and a second region spaced from the first region; forming a sacrificial layer and a preliminary channel layer on the substrate; etching the preliminary channel layer and the sacrificial layer; etching the preliminary channel layer to separate it into a preliminary channel pattern overlapping the first region and a sacrificial channel pattern overlapping the second region; etching the sacrificial layer to separate it into a sacrificial pattern overlapping the first region and a dummy sacrificial pattern overlapping the second region; forming word line holes to separate the preliminary channel patterns into channel patterns; replacing the sacrificial pattern with an insulating pattern; forming word lines in the word line holes; removing the sacrificial channel pattern and the dummy sacrificial pattern to expose the second region; and forming a peripheral gate structure on the second region.

[0010] A method for manufacturing a semiconductor device according to some embodiments may include providing a substrate including a first region and a second region separated from the first region; forming a cell stack structure on the first region and a dummy stack structure on the second region; forming a semiconductor structure on the cell stack structure and the dummy stack structure; and forming a peripheral gate structure on the semiconductor structure.

[0011] [Effects of the invention] A semiconductor device according to an embodiment of the inventive concept can improve the process difficulty of forming peripheral transistors, thereby improving the reliability of the semiconductor device. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic circuit diagram illustrating a semiconductor device according to some embodiments. [Figure 2A] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 2B]FIG. 2B is a cross-sectional view taken along the line A1-A1' in FIG. 2A. [Figure 2C] FIG. 2B is a cross-sectional view taken along line B1-B1' in FIG. 2A. [Figure 2D] FIG. 2B is a cross-sectional view taken along the line C1-C1' in FIG. 2A. [Figure 2E] FIG. 2B is a cross-sectional view taken along line D1-D1' in FIG. 2A. [Figure 3] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 4] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 5] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 6] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 7] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 8] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 9A] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 9B] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 10A] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 10B] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 11] 2A to 2E are cross-sectional views for explaining a method of manufacturing the semiconductor device according to FIGS. 2A to 2E. [Figure 12A] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 12B] 1 is a cross-sectional view of a semiconductor device according to some embodiments. [Figure 13]12C is a cross-sectional view for explaining a method of manufacturing the semiconductor device according to FIGS. 12A and 12B. FIG. [Figure 14] 12C is a cross-sectional view for explaining a method of manufacturing the semiconductor device according to FIGS. 12A and 12B. FIG. [Figure 15A] FIG. 1 is a plan view of a semiconductor device according to some embodiments. [Figure 15B] FIG. 15B is a cross-sectional view taken along the line A2-A2′ in FIG. 15A. [Figure 15C] FIG. 15B is a cross-sectional view taken along line B2-B2' in FIG. 15A. DETAILED DESCRIPTION OF THE INVENTION

[0013] FIG. 1 is a schematic circuit diagram illustrating a semiconductor device according to some embodiments.

[0014] Referring to FIG. 1, the semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0015] The memory cell array 1 may include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC may be arranged three-dimensionally, and each memory cell MC may be connected to one word line WL, one bit line BL, and one source line SL. In some embodiments, each memory cell MC may be formed of one transistor including a memory film (or data storage film).

[0016] The row decoder 2 may decode an externally input address and select one of the word lines WL of the memory cell array 1. The address decoded by the row decoder 2 may be provided to a row driver (not shown), which may provide a predetermined voltage to each of the selected word lines WL and the unselected word lines WL in response to control by a control circuit.

[0017] The sense amplifier 3 may sense, amplify, and output a voltage difference between a selected bit line BL and a reference bit line according to an address decoded from the column decoder 4 .

[0018] The column decoder 4 may provide a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller, etc.) and may decode an address input from the outside to select one of the bit lines BL.

[0019] The control logic 5 may generate a control signal that controls the operation of writing or reading data to or from the memory cell array 1.

[0020] FIG. 2A is a plan view of a semiconductor device according to some embodiments. FIG. 2B is a cross-sectional view taken along line A1-A1′ in FIG. 2A. FIG. 2C is a cross-sectional view taken along line B1-B1′ in FIG. 2A. FIG. 2D is a cross-sectional view taken along line C1-C1′ in FIG. 2A. FIG. 2E is a cross-sectional view taken along line D1-D1′ in FIG. 2A.

[0021] 2A to 2E, a semiconductor device may include a substrate 100. The substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect with each other. For example, the first direction D1 and the second direction D2 may be horizontal directions that are perpendicular to each other.

[0022] The substrate 100 may be a semiconductor substrate. By way of example, the substrate 100 may comprise silicon, germanium, or silicon-germanium. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0023] The substrate 100 may include a first region R1 and a second region R2 spaced apart from each other. The first region R1 and the second region R2 may be located above the substrate 100. The first region R1 and the second region R2 may be regions separated in a plane by a first direction D1 and a second direction D2. The second region R2 may be disposed between bit lines BO, which will be described later.

[0024] A cell stack structure CS may be provided on the first region R1 of the substrate 100. A lower surface of the cell stack structure CS may contact an upper surface R1_T of the first region R1 of the substrate 100. The cell stack structure CS may include bit lines BO, word lines WO, a word line capping layer 123, a gate insulating layer GI, an insulating pattern 111, a channel pattern CL, a bit line insulating pattern 112, a first insulating structure IS1, a second insulating structure IS2, a third insulating structure IS3, a data storage structure DS, an outer channel pattern 115, an outer insulating pattern 116, an intervening pattern 114, a first cell insulating layer 121, a second cell insulating layer 122, a third cell insulating layer 124, a fourth cell insulating layer 125, a word line contact 126, a bit line contact 129, a bit line capping layer 128, and a data contact 127.

[0025] The data storage structure DS may be a capacitor including a first electrode EL1, a second electrode EL2, and a capacitor dielectric CI. The first electrode EL1 may be spaced apart from the second electrode EL2. The capacitor dielectric CI may be provided between the first electrode EL1 and the second electrode EL2.

[0026] The first electrode EL1 may be provided on both sides of the second electrode EL2. Capacitor insulating films CI may be provided on both sides of the second electrode EL2. The first and second electrodes EL1 and EL2 may include a conductive material. The capacitor insulating films CI may include an insulating material.

[0027] In some embodiments, the data storage structure DS may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse, and may include a phase-change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, whose crystalline state changes depending on the amount of current.

[0028] The channel patterns CL and the insulating patterns 111 may be alternately stacked along a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0029] The channel patterns CL may include channel patterns CL overlapping each other in a third direction D3. The channel patterns CL may be electrically connected to the data storage structure DS. The channel patterns CL may include a first source / drain region, a channel region, and a second source / drain region. The second source / drain region of the channel pattern CL may contact the first electrode EL1 of the data storage structure DS. The channel patterns CL may be disposed between the bit line BO and the data storage structure DS. The first and second source / drain regions may be doped with impurities.

[0030] The channel patterns CL overlapping each other in the third direction D3 may include a channel pattern CL arranged at the same level as a peripheral gate structure PGA (described later) and a channel pattern CL arranged at a higher level than the peripheral gate structure PGA.

[0031] The channel pattern CL may include at least one of a single crystal semiconductor, a polycrystalline semiconductor, an oxide semiconductor, or a two-dimensional material. The single crystal semiconductor may be, for example, single crystal silicon. The polycrystalline semiconductor may be, for example, polysilicon. The oxide semiconductor may be, for example, IGZO (Indium Gallium Zinc Oxide). The two-dimensional material may be, for example, MoS2, WS2, MoSe2, or WSe2.

[0032] The insulating patterns 111 may be provided between the channel patterns CL or between the channel pattern CL and the first region R1 of the substrate 100. A lowermost insulating pattern L111 disposed at the bottom of the insulating patterns 111 may contact the top surface R1_T of the first region R1 of the substrate 100. The insulating patterns 111 may include an insulating material. For example, the insulating pattern 111 may include an oxide.

[0033] The outer channel patterns 115 and the outer insulating patterns 116 may be alternately stacked along the third direction D3. The outer channel patterns 115 may include the same material as the channel patterns CL. The outer insulating patterns 116 may include the same material as the insulating patterns 111. The outer channel patterns 115 and the outer insulating patterns 116 may be adjacent to the isolation structures 130, which will be described later. The outer channel patterns 115 and the outer insulating patterns 116 may be adjacent to the second region R2.

[0034] The outer channel patterns 115 and the intervening patterns 114 may be alternately arranged along the third direction D3. The intervening patterns 114 may be provided between the outer channel patterns 115 or between the outer channel patterns 115 and the first region R1 of the substrate 100. Sidewalls of the intervening patterns 114 may contact sidewalls of the isolation structures 130. The intervening patterns 114 may include an insulating material. For example, the intervening patterns 114 may include an oxide.

[0035] The bit lines BO and the bit line insulating patterns 112 may be alternately stacked in the third direction D3. The bit lines BO may be electrically connected to the channel patterns CL. The bit lines BO may contact first source / drain regions of the channel patterns CL. The bit lines BO may extend in the first direction D1. The bit lines BO may include bit lines BO overlapping each other in the third direction D3. The bit lines BO may be spaced apart from the data storage structures DS. The data storage structures DS may be disposed between the bit lines BO. The bit lines BO may include a conductive material.

[0036] The bit line insulating patterns 112 may be provided between the bit lines BO or between the bit lines BO and the first region R1 of the substrate 100. The bottom bit line insulating pattern 112, which is disposed at the bottom among the bit line insulating patterns 112, may contact the top surface R1_T of the first region R1 of the substrate 100. The bit line insulating patterns 112 may include an insulating material. For example, the bit line insulating pattern 112 may include nitride.

[0037] A bit line capping layer 128 may be provided on the bit line BO. The bit line capping layer 128 may include an insulating material.

[0038] A gate insulating film GI may be provided between the channel patterns CL adjacent to each other in the first direction D1 or between the channel patterns CL adjacent to each other in the first direction D1 and the outer channel pattern 115. The gate insulating film GI may be provided between the data storage structure DS and the bit line BO. The gate insulating film GI may be in contact with the channel patterns CL overlapping in the third direction D3. The gate insulating film GI may extend in the third direction D3. The gate insulating film GI may be in contact with the first region R1 of the substrate 100. The gate insulating film GI may include an insulating material. For example, the gate insulating film GI may include an oxide.

[0039] In some embodiments, the gate insulating film GI, the insulating pattern 111, and the outer insulating pattern 115 may have an integral structure that is connected to each other without a boundary.

[0040] Word lines WO may be provided between the channel patterns CL adjacent to each other in the first direction D1 or between the channel patterns CL adjacent to each other in the first direction D1 and the outer channel patterns 115. The word lines WO may be provided on the gate insulating film GI. The word lines WO may extend in the third direction D3. In the plan view according to FIG. 2A , the word lines WO may be surrounded by the gate insulating film GI. The word lines WO may be provided between the data storage structures DS and the bit lines BO. The word lines WO may include a conductive material.

[0041] A word line capping layer 123 may be provided on the word lines WO. The word line capping layer 123 may include an insulating material. For example, the word line capping layer 123 may include an oxide.

[0042] A first insulating structure IS1 may be provided between the word line WO and the bit line BO. In some embodiments, the third insulating structure IS3 may be a multi-layer structure including multiple insulating films.

[0043] A second insulating structure IS2 and a third insulating structure IS3 may be provided between the word line WO and the data storage structure DS. In some embodiments, the second insulating structure IS2 may be a multi-layer structure including multiple insulating layers. In some embodiments, the third insulating structure IS3 may be a multi-layer structure including multiple insulating layers.

[0044] The first cell insulating film 121 may be provided on an uppermost channel pattern UCL arranged at the uppermost position among the channel patterns CL and on an uppermost outer channel pattern U115 arranged at the uppermost position among the outer channel patterns 115. The first cell insulating film 121 may be in contact with a sidewall of a first isolation film 131 (described later) of the isolation structure 130 and a gate insulating film GI.

[0045] A second cell insulating film 122 may be provided on the first cell insulating film 121. The second cell insulating film 122 may be in contact with a sidewall of the first isolation film 131 of the isolation structure 130 and the gate insulating film GI. A lower surface of the second cell insulating film 122 may be in contact with an upper surface of a second isolation film 132 (described later) of the isolation structure 130. The second cell insulating film 122 may be in contact with a word line contact 126.

[0046] A third cell insulating film 124 may be provided on the second cell insulating film 122. The third cell insulating film 124 may contact a sidewall of the word line capping film 123 and the first isolation film 131 of the isolation structure 130. A fourth cell insulating film 125 may be provided on the third cell insulating film 124 and the word line capping film 123.

[0047] The first to fourth cell insulating layers 121, 122, 124, and 125 may include an insulating material. For example, the first to fourth cell insulating layers 121, 122, 124, and 125 may include nitride.

[0048] The word line contact 126 may be in contact with the word line WO. The word line contact 126 may penetrate the fourth cell insulating film 125 and the word line capping film 123. The word line contact 126 may be disposed at a higher level than the peripheral gate structure PGA. The distance in the third direction D3 between the word line contact 126 and the substrate 100 may be greater than the distance in the third direction D3 between the peripheral gate structure PGA and the substrate 100.

[0049] The bit line contact 129 may be in contact with the bit line BO. The bit line contact 129 may penetrate the bit line capping layer 128. At least one of the bit line contacts 129 may penetrate the bit line insulating pattern 112. The data contact 127 may be in contact with the second electrode EL2 of the data storage structure DS. The data contact 127 may penetrate the second to fourth cell insulating layers 122, 124, and 125. The data contact 127 may be disposed at a higher level than the peripheral gate structure PGA. The word line contact 126, the bit line contact 129, and the data contact 127 may include a conductive material.

[0050] A peripheral gate structure PGA may be provided on the second region R2 of the substrate 100. The peripheral gate structure PGA may be in contact with an upper surface R2_T of the second region R2 of the substrate 100. The peripheral gate structure PGA may include a peripheral gate insulating film PGI in contact with the upper surface R2_T of the second region R2 of the substrate 100, a peripheral gate electrode PGE on the peripheral gate insulating film PGI, a peripheral gate capping film PGP on the peripheral gate electrode PGE, and peripheral gate spacers PGS on sidewalls of the peripheral gate electrode PGE and the peripheral gate capping film PGP.

[0051] The peripheral gate insulating film PGI may include an insulating material. For example, the peripheral gate insulating film PGI may include an oxide. A lower surface of the peripheral gate insulating film PGI may be in contact with an upper surface R2_T of the second region R2 of the substrate 100.

[0052] The peripheral gate electrode PGE may include a first gate electrode 151, a second gate electrode 152 on the first gate electrode 151, and a third gate electrode 153 on the second gate electrode 152. The first to third gate electrodes 151, 152, and 153 may include a conductive material. For example, the first gate electrode 151 may include polysilicon, and the second and third gate electrodes 152 and 153 may include a metal.

[0053] The peripheral gate capping film PGP may include an insulating material. For example, the peripheral gate capping film PGP may include a nitride. The peripheral gate spacer PGS may include an insulating material. In some embodiments, the peripheral gate spacer PGS may be a multi-layer film including multiple insulating films.

[0054] Impurity regions may be provided on both sides of the peripheral gate structure PGA, and a peripheral transistor may be defined that includes the impurity regions and the peripheral gate structure PGA.

[0055] An isolation structure 130 may be provided between the peripheral gate structure PGA and the cell stack structure CS. The isolation structure 130 may include a first portion P1 extending in the second direction D2 and a second portion P2 extending in the first direction D1. The first portion P1 of the isolation structure 130 may be disposed between the data storage structure DS and the peripheral gate structure PGA. The first portion P1 of the isolation structure 130 may be disposed between the word line WO and the peripheral gate structure PGA. The second portion P2 of the isolation structure 130 may be disposed between the bit line BO and the peripheral gate structure PGA. The second portion P2 of the isolation structure 130 may be coupled to both sides of the first portion P1 of the isolation structure 130. A second region R2 of the substrate 100 may be disposed between the second portion P2 of the isolation structure 130. The peripheral gate structure PGA may be disposed between the second portion P2 of the isolation structure 130.

[0056] The isolation structure 130 may be provided between the first region R1 and the second region R2 of the substrate 100. A bottom surface of the isolation structure 130 may contact the substrate 100. A sidewall of the isolation structure 130 may contact the first region R1 or the second region R2 of the substrate 100. The isolation structure 130 may include a first isolation film 131 and a second isolation film 132 therein. The first isolation film 131 and the second isolation film 132 may include different insulating materials. For example, the first isolation film 131 may include an oxide, and the second isolation film 132 may include a nitride.

[0057] A peripheral insulating structure PIS may be provided on the peripheral gate structure PGA. The peripheral insulating structure PIS may include a liner 142 on the peripheral gate structure PGA, a first peripheral insulating film 143 on the liner 142, a second peripheral insulating film 144 on the first peripheral insulating film 143 and the liner 142, a third peripheral insulating film 145 on the second peripheral insulating film 144, and a fourth peripheral insulating film 146 on the third peripheral insulating film 145. The peripheral insulating structure PIS may surround the peripheral gate structure PGA. The peripheral insulating structure PIS may surround at least a portion of a peripheral gate contact 154, which will be described later. At least a portion of the channel pattern CL may be disposed at the same level as the peripheral insulating structure PIS. A sidewall of the peripheral insulating structure PIS may contact a sidewall of the isolation structure 130. The channel pattern CL overlapping in the third direction D3 may include a channel pattern CL disposed at the same level as the peripheral gate structure PGA.

[0058] The liner 142 may cover the peripheral gate capping film PGP and the peripheral gate spacer PGS of the peripheral gate structure PGA. The liner 142 may contact an upper surface of the peripheral gate capping film PGP, an upper surface and sidewalls of the peripheral gate spacer PGS, a sidewall of the peripheral gate insulating film PGI, and an upper surface of the second region R2 of the substrate 100. The liner 142 may have a constant thickness. The liner 142 may include an insulating material. For example, the liner 142 may include nitride.

[0059] An intervening insulating pattern 141 may be provided between the liner 142 and the second region R2 of the substrate 100. A lower surface of the intervening insulating pattern 141 may contact the second region R2 of the substrate 100. An upper surface of the intervening insulating pattern 141 may contact the liner 142. A sidewall of the intervening insulating pattern 141 may contact the first isolation film 131 of the isolation structure 130. A lower surface of the intervening insulating pattern 141 may be bendable. An upper surface of the intervening insulating pattern 141 may be flat. The intervening insulating pattern 141 may include an insulating material. For example, the intervening insulating pattern 141 may include an oxide.

[0060] The first peripheral insulating layer 143 may surround the peripheral gate structure PGA. The first to fourth peripheral insulating layers 143, 144, 145, and 146 may include insulating materials. For example, the first and third peripheral insulating layers 143 and 145 may include oxide, and the second and fourth peripheral insulating layers 144 and 146 may include nitride.

[0061] A peripheral gate contact 154 may be provided through the peripheral gate capping layer PGP, the liner 142, and the second to fourth peripheral insulating layers 144, 145, and 146. The peripheral gate contact 154 may contact the peripheral gate electrode PGE of the peripheral gate structure PGA. The peripheral gate contact 154 may include a conductive material.

[0062] The length of the peripheral gate contact 154 in the third direction D3 may be greater than the length of the word line contact 126 in the third direction D3 and the length of the data contact 127 in the third direction D3. The length of the peripheral gate contact 154 in the third direction D3 may be greater than the length of at least one of the bit line contacts 129 in the third direction D3.

[0063] A first cover insulating film 161 may be provided on the fourth cell insulating film 125 of the cell stack structure CS and the fourth peripheral insulating film 146 of the peripheral insulating structure PIS. A second cover insulating film 162 may be provided on the first cover insulating film 161. A third cover insulating film 163 may be provided on the second cover insulating film 162. A fourth cover insulating film 164 may be provided on the third cover insulating film 163. A fifth cover insulating film 165 may be provided on the fourth cover insulating film 164. The first to fifth cover insulating films 161, 162, 163, 164, and 165 may include an insulating material. For example, the first and second cover insulating films 161 and 162 may include nitride, and the third to fifth cover insulating films 163, 164, and 165 may include oxide.

[0064] A first conductive line 181, a second conductive line 182, a third conductive line 183, and a fourth conductive line 184 may be provided in the first cover insulating layer 161. A lower surface of the first conductive line 181 may contact an upper surface of the data contact 127. A lower surface of the second conductive line 182 may contact an upper surface of the word line contact 126. A lower surface of the third conductive line 183 may contact an upper surface of the peripheral gate contact 154. A lower surface of the fourth conductive line 184 may contact an upper surface of the bit line contact 129. The first to fourth conductive lines 181, 182, 183, and 184 may be disposed at the same level. The first to fourth conductive lines 181, 182, 183, and 184 may include a conductive material.

[0065] A conductive contact 185 may be provided through the second to fourth cover insulating layers 162, 163, and 164. The conductive contact 185 may be in contact with one of the first to fourth conductive lines 181, 182, 183, and 184. The conductive contact 185 may include a conductive material.

[0066] Fifth conductive lines 186 may be provided in the fifth cover insulating film 165. At least one of the fifth conductive lines 186 may contact the conductive contact 185. The fifth conductive lines 186 may include a conductive material.

[0067] In some embodiments, by providing peripheral transistors on the second region R2 of the substrate 100, the difficulty of the process of forming the peripheral transistors can be improved, and the reliability of the semiconductor device can be improved.

[0068] Figures 3, 4, 5, 6, 7, 8, 9A, 9B, 10A, and 10B are cross-sectional views for explaining a method for manufacturing the semiconductor device shown in Figures 2A to 2E. Figures 3, 4, 5, 6, 7, 8, 9A, 9B, and 10A may correspond to Figure 2C. Figures 9B and 10B may correspond to Figure 2E.

[0069] Referring to FIG. 3, a substrate 100 may be provided. The substrate 100 may include a first region R1 and a second region R2. Sacrificial layers 171 and preliminary channel layers 172 may be alternately formed on the substrate 100. The sacrificial layers 171 and preliminary channel layers 172 may be alternately stacked along a third direction D3. The sacrificial layers 171 may have an etch selectivity with respect to the preliminary channel layers 172. For example, the preliminary channel layers 172 may include silicon, and the sacrificial layers 171 may include silicon-germanium. A lowermost sacrificial layer 171 disposed at the bottom of the sacrificial layers 171 may contact the first region R1 and the second region R2 of the substrate 100.

[0070] A first preliminary insulating film 173 may be formed on the uppermost preliminary channel film 172, which is disposed at the top of the preliminary channel films 172. The first preliminary insulating film 173 may include an insulating material. For example, the first preliminary insulating film 173 may include a nitride.

[0071] 4, the isolation structure 130 may be formed. Forming the isolation structure 130 may include etching the first preliminary insulating film 173, the sacrificial film 171, and the preliminary channel film 172 to form a trench TR, and forming the isolation structure 130 in the trench TR. A bottom surface of the trench TR may be defined by the surface of the substrate 100.

[0072] The sacrificial layer 171 may be etched to separate the sacrificial layer 171 into a sacrificial pattern 174 and a dummy sacrificial pattern 175. The preliminary channel layer 172 may be etched to separate the preliminary channel layer 172 into a preliminary channel pattern 176 and a sacrificial channel pattern 177. The first preliminary insulating layer 173 may be etched to separate the first preliminary insulating layer 173 into a second preliminary insulating layer 178 and a third preliminary insulating layer 179.

[0073] The sacrificial pattern 174 and the preliminary channel pattern 176 may overlap with the first region R1 of the substrate 100 along the third direction D3. The sacrificial pattern 174 and the preliminary channel pattern 176 may be alternately stacked with each other along the third direction D3. The dummy sacrificial pattern 175 and the sacrificial channel pattern 177 may overlap with the second region R2 of the substrate 100 along the third direction D3. The dummy sacrificial pattern 175 and the sacrificial channel pattern 177 may be alternately stacked with each other along the third direction D3. The second preliminary insulating film 178 may overlap with the first region R1 of the substrate 100 along the third direction D3. The third preliminary insulating film 179 may overlap with the second region R2 of the substrate 100 along the third direction D3.

[0074] Before the isolation structure 130 is formed, the sacrificial pattern 174, the preliminary channel pattern 176, the dummy sacrificial pattern 175, and the sacrificial channel pattern 177 may be etched through the trench TR. The intervening pattern 114 may be formed in the empty space formed by etching the sacrificial pattern 174, the preliminary channel pattern 176, the dummy sacrificial pattern 175, and the sacrificial channel pattern 177. After the intervening pattern 114 is formed, the first isolation film 131 may be formed, and the second isolation film 132 may be formed in the first isolation film 131.

[0075] 5, a first photoresist pattern PR1 may be formed. The first photoresist pattern PR1 may be formed on the third preliminary insulating film 179. The first photoresist pattern PR1 may overlap the second region R2 of the substrate 100 in the third direction D3. For example, the first photoresist pattern PR1 may overlap the entire second region R2 of the substrate 100 in the third direction D3. The first photoresist pattern PR1 may not overlap the first region R1 of the substrate 100 in the third direction D3.

[0076] A first etching process may be performed using the first photoresist pattern PR1 as an etching mask. The first etching process may etch the second preliminary insulating film 178 and the isolation structure 130. The etched second preliminary insulating film 178 may be defined as the first cell insulating film 121.

[0077] 6, a second cell insulating film 122 may be formed on the first cell insulating film 121 and the isolation structure 130. A second photoresist pattern PR2 may be formed on the third preliminary insulating film 179 and the second cell insulating film 122. The second photoresist pattern PR2 may overlap the second region R2 of the substrate 100 in the third direction D3. For example, the second photoresist pattern PR2 may overlap the entire second region R2 of the substrate 100 in the third direction D3.

[0078] A second etching process may be performed using the second photoresist pattern PR2 as an etching mask. A word line hole OP1 may be formed by the second etching process. A preliminary channel pattern 176 may be etched by the second etching process, and the preliminary channel pattern 176 may be separated into a channel pattern CL and an outer channel pattern 115. A sacrificial pattern 174 may be etched by the second etching process, and the sacrificial pattern 174 may be separated into a plurality of sacrificial patterns 174. The first cell insulating film 121 and the second cell insulating film 122 may be etched by the second etching process. A first region R1 of the substrate 100 may be etched by the second etching process. The word line hole OP1 may extend in a third direction D3. A bottom surface of the word line hole OP1 may be defined by the surface of the first region R1 of the substrate 100.

[0079] 7, the sacrificial pattern 174 (shown in FIG. 6) may be replaced with the insulating pattern 111 and the outer insulating pattern 116. The sacrificial pattern 174 may be removed, and the insulating pattern 111 and the outer insulating pattern 116 may be formed in the empty space formed by removing the sacrificial pattern 174. A gate insulating layer GI may also be formed. In some embodiments, the insulating pattern 111, the outer insulating pattern 116, and the gate insulating layer GI may be formed through a single deposition process.

[0080] A word line WO may be formed on the gate insulating film GI. The word line WO may be formed in the word line hole OP1. A word line capping film 123 may be formed on the word line WO. A third cell insulating film 124 may be formed on the second cell insulating film 122. A fourth cell insulating film 125 may be formed on the third cell insulating film 124 and the word line capping film 123.

[0081] The bit line BO, the bit line insulating pattern 112, the bit line capping layer 128, the first insulating structure IS1, the second insulating structure IS2, the third insulating structure IS3, and the data storage structure DS may be formed (FIGS. 2A to 2E).

[0082] 8, a third photoresist pattern PR3 may be formed on the fourth cell insulating film 125. The third photoresist pattern PR3 may overlap the first region R1 of the substrate 100 along the third direction D3. The third photoresist pattern PR3 may not overlap the second region R2 of the substrate 100 along the third direction D3.

[0083] A third etching process may be performed using the third photoresist pattern PR3 as an etching mask. An opening OP2 may be formed by the third etching process. The opening OP2 may expose an upper surface R2_T of the second region R2 of the substrate 100.

[0084] The third etching process may remove the third preliminary insulating film 179, the sacrificial channel pattern 177, and the dummy sacrificial pattern 175. The third etching process may remove a portion of the intervening pattern 114 overlapping the second region R2 of the substrate 100 in the third direction D3. The third etching process may etch the lowermost intervening pattern 114 of the intervening patterns 114 overlapping the second region R2 of the substrate 100 in the third direction D3 to form the intervening insulating pattern 141. The third etching process may expose sidewalls of the isolation structure 130.

[0085] 9A and 9B, a peripheral gate insulating film PGI may be formed on the second region R2 of the substrate 100. A peripheral gate electrode PGE may be formed on the peripheral gate insulating film PGI. A peripheral gate capping film PGP may be formed on the peripheral gate electrode PGE. A peripheral gate spacer PGS may be formed on sidewalls of the peripheral gate electrode PGE and the peripheral gate capping film PGP. A liner 142 may be formed to cover the peripheral gate capping film PGP and the peripheral gate spacer PGS. A first peripheral insulating film 143 may be formed on the liner 142.

[0086] A second peripheral insulating film 144 may be formed on the first peripheral insulating film 143. A third peripheral insulating film 145 may be formed on the second peripheral insulating film 144. A fourth peripheral insulating film 146 may be formed on the third peripheral insulating film 145.

[0087] The word line contacts 126, the bit line contacts 129, and the peripheral gate contacts 154 may be formed. In some embodiments, the word line contacts 126, the bit line contacts 129, and the peripheral gate contacts 154 may be formed simultaneously in a single step. In some embodiments, the word line contacts 126 and the bit line contacts 129 may be formed before the third photoresist pattern PR3 is formed.

[0088] 10A and 10B, a first cover insulating layer 161 may be formed. A first conductive line 181 (FIG. 2B), a second conductive line 182, a third conductive line 183, and a fourth conductive line 184 may be formed in the first cover insulating layer 161. In some embodiments, the first to fourth conductive lines 181, 182, 183, and 184 may be formed simultaneously in a single process.

[0089] 2A to 2E, a second cover insulating film 162 may be formed on a first cover insulating film 161. A third cover insulating film 163 and a fourth cover insulating film 164 may be sequentially formed on the second cover insulating film 162. A conductive contact 185 may be formed penetrating the second to fourth cover insulating films 162, 163, and 164. A fifth cover insulating film 165 may be formed on the fourth cover insulating film 164. A fifth conductive line 186 may be formed in the fifth cover insulating film 165.

[0090] In some embodiments, the method for manufacturing a semiconductor device may expose the second region R2 of the substrate 100 and form a peripheral gate structure PGA on the second region R2 of the substrate 100. The second region R2 of the substrate 100 may have a relatively large thickness, which may improve the stability of the process for forming the peripheral gate structure PGA and the reliability of the semiconductor device.

[0091] FIG. 11 is a cross-sectional view for explaining a method for manufacturing the semiconductor device shown in FIGS. 2A to 2E.

[0092] Referring to FIG. 11, similar to what has been described with reference to FIGS. 3 and 4, a substrate 100, a sacrificial pattern 174, a preliminary channel pattern 176, a dummy sacrificial pattern 175, a sacrificial channel pattern 177, a second preliminary insulating film 178, a third preliminary insulating film 179, and an isolation structure 130 may be formed.

[0093] A mask film MA may be formed on the third preliminary insulating film 179. The mask film MA may overlap the second region R2 along the third direction D3. As an example, the mask film MA may overlap the entire second region R2 along the third direction D3.

[0094] Similar to what has been described with reference to Figures 5 to 7, a cell manufacturing process may be performed to form a channel pattern CL, an insulation pattern 111, an outer channel pattern 115, an outer insulation pattern 116, a first cell insulating film 121, a second cell insulating film 122, a gate insulating film GI, a word line WO, a word line capping film 123, a third cell insulating film 124, and a fourth cell insulating film 125.

[0095] During the cell manufacturing process, the mask film MA may protect the dummy sacrificial pattern 175, the sacrificial channel pattern 177, and the third preliminary insulating film 179. After the cell manufacturing process is completed, the mask film MA may be removed.

[0096] Subsequently, similar to what has been described with reference to Figures 8, 9A, and 9B, the third preliminary insulating film 179, the sacrificial channel pattern 177, and the dummy sacrificial pattern 175 may be removed, and the peripheral gate structure PGA may be formed.

[0097] 12A and 12B are cross-sectional views of semiconductor devices according to some embodiments. The semiconductor devices according to Figures 12A and 12B may be similar to the semiconductor devices according to Figures 2A to 2E, except as described below.

[0098] 12A and 12B, a dummy stack structure DU may be provided on the second region R2 of the substrate 100. The lower surface of the dummy stack structure DU may be in contact with the upper surface R2_T of the second region R2 of the substrate 100.

[0099] The dummy stack structure DU may include dummy patterns 211 and dummy channel patterns 212 alternately stacked along the third direction D3. The dummy patterns 211 may include a material having an etch selectivity relative to the dummy channel patterns 212. For example, the dummy patterns 211 may include silicon-germanium, and the dummy channel patterns 212 may include silicon. A bottom surface of a bottom dummy pattern L211 disposed at the bottom of the dummy patterns 211 may contact the top surface T2_T of the second region R2 of the substrate 100. Some of the dummy channel patterns 212 may be disposed at a higher level than the channel patterns CL. For example, an uppermost dummy channel pattern U212 disposed at the top of the dummy channel patterns 212 may be disposed at a higher level than the channel patterns CL.

[0100] The dummy stacked structure DU may further include a dummy intervening pattern 213. The dummy intervening patterns 213 and the dummy channel patterns 212 may be alternately arranged along the third direction D3. A sidewall of the dummy intervening pattern 213 may contact a sidewall of the isolation structure 130. The dummy intervening pattern 213 may include an insulating material.

[0101] The cell stack structure CS may include a fifth cell insulating film 221 on the fourth cell insulating film 125 and a sixth cell insulating film 222 on the fifth cell insulating film 221. The fifth cell insulating film and the sixth cell insulating film 221, 222 may include an insulating material. For example, the fifth cell insulating film and the sixth cell insulating film 221, 222 may include a nitride.

[0102] The cell stack structure CS may include a first conductive line 223 and a second conductive line 224 in a fifth cell insulating layer 221. The first conductive line 223 may be coupled to a word line contact 126. The second conductive line 224 may be coupled to a bit line contact 129.

[0103] A semiconductor structure 230 may be provided on the cell stack structure CS and the dummy stack structure DU. The semiconductor structure 230 may include a seed film 231 and a semiconductor film 232 on the seed film 231. A lower surface of the seed film 231 may contact an upper surface of the sixth cell insulating film 222 and an upper surface of the uppermost dummy pattern U211 of the dummy patterns 211.

[0104] The seed film 231 may be a polycrystalline semiconductor film. For example, the seed film 231 may include polysilicon. The semiconductor film 232 may be formed through a growth process using the seed film 231 as a seed. The semiconductor film 232 may be a single-crystal semiconductor film. For example, the semiconductor film 232 may include single-crystal silicon.

[0105] The thickness of the semiconductor film 232 in the third direction D3 may be greater than the thickness of the seed film 231 in the third direction D3, the thickness of the channel pattern CL in the third direction D3, and the thickness of the dummy channel pattern 212 in the third direction D3.

[0106] A peripheral gate structure PGAa may be provided on an upper surface of the semiconductor film 232 of the semiconductor structure 230. The peripheral gate structure PGAa may include a peripheral gate insulating film PGIa, a peripheral gate electrode PGEa, a peripheral gate capping film PGPa, and a peripheral gate spacer PGSa. A lower surface of the peripheral gate insulating film PGIa may contact an upper surface of the semiconductor film 232. The peripheral gate electrode PGEa may include a first gate electrode 251, a second gate electrode 252, and a third gate electrode 253. The peripheral gate structure PGAa may overlap the isolation structure 130 along a third direction D3.

[0107] A liner 241 may be provided to cover the peripheral gate structure PGAa. The liner 241 may be in contact with an upper surface of the semiconductor film 232. A first cover insulating film 242 may be provided on the liner 241. A second cover insulating film 243 may be provided on the first cover insulating film 242 and the liner 241. The liner 241, the first cover insulating film 242, and the second cover insulating film 243 may include an insulating material. For example, the liner 241 and the second cover insulating film 243 may include a nitride, and the first cover insulating film 242 may include an oxide.

[0108] A peripheral gate contact 271 may be provided through the second cover insulating film 243, the liner 241, and the peripheral gate capping film PGPa. The peripheral gate contact 271 may contact the peripheral gate electrode PGEa.

[0109] A third cover insulating film 244 may be provided on the second cover insulating film 243. A fourth cover insulating film 245, a fifth cover insulating film 246, a sixth cover insulating film 247, and a seventh cover insulating film 248 may be provided sequentially on the third cover insulating film 244. The third to seventh cover insulating films 244, 245, 246, 247, and 248 may include an insulating material. For example, the third cover insulating film, the fifth cover insulating film, the sixth cover insulating film, and the seventh cover insulating film 244, 246, 247, and 248 may include an oxide, and the fourth cover insulating film 245 may include a nitride.

[0110] Third conductive lines 261 may be provided in the third cover insulating film 244. One of the third conductive lines 261 may be in contact with the peripheral gate contact 271. Conductive contacts 262 may be provided through the fourth to sixth cover insulating films 245, 246, and 247. The conductive contact 262 may be in contact with the third conductive line 261. A fourth conductive line 263 may be provided in the seventh cover insulating film 248. The fourth conductive line 263 may be in contact with the conductive contact 262.

[0111] The third conductive line 261 may be disposed at a higher level than the first conductive line 223 and the second conductive line 224. The peripheral gate structure PGAa may be disposed between the first conductive line 223 and the third conductive line 261.

[0112] In a semiconductor device according to some embodiments, a semiconductor structure 230 may be disposed on the cell stack structure CS and the dummy stack structure DU, and a peripheral gate structure PGAa may be disposed on the semiconductor structure 230. This can improve the difficulty of the process of forming the peripheral transistors, and can improve the reliability of the semiconductor device.

[0113] 13 and 14 are cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIGS. 12A and 12B.

[0114] 13, a cell stack structure CS may be formed on a first region R1 of the substrate 100, and a dummy stack structure DU may be formed on a second region R2 of the substrate 100. Forming the dummy channel pattern 212 may include forming a spare channel film and separating the spare channel film into a spare channel pattern and a dummy channel pattern 212. Forming the dummy pattern 211 may include forming a sacrificial film and separating the sacrificial film into a sacrificial pattern and a dummy pattern 211. The spare channel film, spare channel pattern, sacrificial film, and sacrificial pattern may be similar to those described with reference to FIGS. 3 and 4.

[0115] A seed film 231 may be formed on the cell stacked structure CS and the dummy stacked structure DU.

[0116] 14, a semiconductor film 232 may be formed on a seed film 231. The semiconductor film 232 may be formed through an epitaxial growth process using the seed film 231 as a seed.

[0117] 12A and 12B, a peripheral gate structure PGAa may be formed on the semiconductor layer 232. Then, subsequent processes may be performed.

[0118] In some embodiments, the method for manufacturing a semiconductor device can improve the stability of the process for forming the peripheral gate structure PGAa by forming the peripheral gate structure PGAa on a semiconductor film 232 having a relatively large thickness, thereby improving the reliability of the semiconductor device.

[0119] Figure 15A is a plan view of a semiconductor device according to some embodiments, Figure 15B is a cross-sectional view taken along line A2-A2' in Figure 15A, and Figure 15C is a cross-sectional view taken along line B2-B2' in Figure 15A.

[0120] 15A, 15B, and 15C, a semiconductor device may include a substrate 300. The substrate 300 may include a first region R1b and a second region R2b spaced apart from each other. The second region R2b may be disposed between word lines WOb, which will be described later.

[0121] A cell stack structure CSb may be provided on the first region R1b of the substrate 300. The cell stack structure CSb may include bit lines BOb, word lines WOb, a gate insulating film GIb, an insulating pattern 313, a first capping pattern 314, a second capping pattern 315, a channel pattern CLb, a first insulating structure IS1b, a second insulating structure IS2b, and a data storage structure DSb.

[0122] The data storage structure DSb may be a capacitor including a first electrode EL1b, a second electrode EL2b, and a capacitor insulating film CIb.

[0123] The bit lines BOb may extend in a third direction D3. The bit lines BOb may be disposed on both sides of the data storage structure DSb. The data storage structure DSb may be disposed between the bit lines Bob. The bit lines BOb disposed on one side of the data storage structure DSb may be arranged in the first direction D1.

[0124] The word lines WOb may be provided between the bit lines BOb and the data storage structures DSb. The word lines WOb may be provided on both sides of the data storage structures DSb. The data storage structures DSb may be disposed between the word lines WOb. The word lines WOb disposed on one side of the data storage structures DSb may overlap along the third direction D3. The word lines WOb may extend in the first direction D1.

[0125] The channel pattern CLb may electrically connect the bit line BOb and the data storage structure DSb. The channel pattern CLb overlapping in the third direction D3 may be electrically connected to one bit line BOb.

[0126] A gate insulating layer GIb may be provided between the word line WOb and the channel pattern CL. A first capping pattern 314 may be provided between the word line WOb and the bit line BOb. The word line WOb and the bit line BOb may be separated by the first capping pattern 314. The first capping pattern 314 may include an insulating material.

[0127] The second capping pattern 315 may be provided between the word line WOb and the data storage structure DSb, and may separate the word line WOb from the data storage structure DSb. The second capping pattern 315 may include an insulating material.

[0128] The first insulating structures IS1b may be provided between the bit lines Bob. The first insulating structures IS1b and the bit lines Bob may be alternately arranged along the first direction D1. The second insulating structures IS2b may be provided between the first electrodes EL1b. The second insulating structures IS2b and the first electrodes EL1b may be alternately arranged along the first direction D1.

[0129] The insulating patterns 313 may be alternately arranged with the channel patterns CLb along the third direction D3. The lower surface of the lowermost insulating pattern L313 arranged at the bottom of the insulating patterns 313 may contact the upper surface of the first region R1b of the substrate 300.

[0130] A peripheral gate structure PGAb may be provided on the second region R2b of the substrate 300. The peripheral gate structure PGAb may contact an upper surface of the second region R2b of the substrate 300. The peripheral gate structure PGAb may include a peripheral gate insulating film PGIb, a peripheral gate electrode PGEb, a peripheral gate capping film PGPb, and a peripheral gate spacer PGSb. The peripheral gate electrode PGEb may include a first gate electrode 351, a second gate electrode 352, and a third gate electrode 353.

[0131] An isolation structure 330 may be provided between the peripheral gate structure PGAb and the cell stack structure CSb. The isolation structure 330 may be provided between the first region R1b and the second region R2b of the substrate 300. The isolation structure 330 may include a first isolation film 331 and a second isolation film 332 within the first isolation film 331.

[0132] A peripheral insulating structure PISb may be provided on the peripheral gate structure PGAb. The peripheral insulating structure PISb may include a liner 361, a first peripheral insulating film 362 on the liner 361, a second peripheral insulating film 363 on the first peripheral insulating film 362 and the liner 361, and a third peripheral insulating film 364 on the second peripheral insulating film 363.

[0133] A first cover insulating film 321 may be provided on the cell stack structure CSb and the peripheral insulating structure PISb. A second cover insulating film 322 may be provided on the first cover insulating film 321.

[0134] A bit line contact 341 contacting the bit line BOb, a data contact 342 contacting the data storage structure DSb, and a peripheral gate contact 343 contacting the peripheral gate structure PGAb may be provided. The length of the peripheral gate contact 343 in the third direction D3 may be greater than the length of the bit line contact 341 in the third direction D3 and the length of the data contact 342 in the third direction D3.

[0135] A conductive line 345 may be provided in the second cover insulating layer 322. The conductive line 345 may contact a bit line contact 341, a data contact 342, or a peripheral gate contact 343.

[0136] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. Furthermore, the embodiments of the present invention may be combined with each other.

[0137] [Explanation of symbols] 100 boards 111 Insulation pattern 126 Word Line Contact 130 Separation structure 141 Intervening insulation pattern 142 Liner 154 Peripheral Gate Contact 181, 182, 183, 184 Conductive lines 211 Dummy Pattern 212 Dummy Channel Pattern 230 Semiconductor Structure 231 Seed Film 232 Semiconductor Film BO Bit Line CI capacitor insulating film CL Channel Pattern CS cell stack structure DU Dummy laminated structure DS data storage structure EL1, EL2 electrode GI gate insulating film IS1, IS2, IS3 insulating structures PGA peripheral gate structure PGE Peripheral gate electrode PGI peripheral gate insulating film PGP peripheral gate capping film PGS Peripheral Gate Spacer PIS peripheral insulation structure WO Word Line

Claims

1. A semiconductor device, the semiconductor device comprising: a substrate including a first region and a second region spaced apart from the first region; a cell stack structure in contact with the first region; a peripheral gate structure in contact with the second region; The cell stack structure includes: Channel patterns superimposed on each other; a bit line electrically connected to at least one of the channel patterns and extending in a first direction; word lines extending in a second direction intersecting the first direction; Semiconductor device.

2. The peripheral gate structure comprises: a peripheral gate insulating film in contact with an upper surface of the second region; The semiconductor device according to claim 1 , further comprising: a peripheral gate electrode on the peripheral gate insulating film.

3. The channel pattern is a first channel pattern disposed at the same level as the peripheral gate structure; 10. The semiconductor device of claim 1, further comprising: a second channel pattern disposed at a higher level than the peripheral gate structure.

4. further comprising an isolation structure between the cell stack structure and the peripheral gate structure; The semiconductor device of claim 1 , wherein the isolation structure is disposed between the first region and the second region.

5. a liner covering the peripheral gate structure; The semiconductor device of claim 4 , further comprising an intervening insulating pattern between the liner and the second region.

6. 6. The semiconductor device of claim 5, wherein the intervening insulating pattern contacts a lower surface of the liner and a sidewall of the isolation structure.

7. the cell stack structure further includes a word line contact contacting the word line; The semiconductor device of claim 1 , wherein the word line contact is disposed at a higher level than the peripheral gate structure.

8. a peripheral gate contact contacting the peripheral gate structure; The semiconductor device of claim 7 , wherein the length of the peripheral gate contact is greater than the length of the word line contact.

9. A semiconductor device, the semiconductor device comprising: a substrate including a first region and a second region spaced apart from the first region; a cell stack above the first region; a dummy stack structure above the second region; a semiconductor structure on the cell stack structure and the dummy stack structure; a peripheral gate structure over the semiconductor structure; The cell stack structure includes channel patterns and insulating patterns alternately stacked with each other, The dummy stacked structure includes dummy channel patterns and dummy patterns alternately stacked with each other. Semiconductor device.

10. The semiconductor structure comprises: a seed film on the cell stack structure and the dummy stack structure; 10. The semiconductor device according to claim 9, further comprising: a semiconductor film on the seed film.

11. the seed film is a polycrystalline semiconductor film, 11. The semiconductor device according to claim 10, wherein the semiconductor film is a single-crystal semiconductor film.

12. 10. The semiconductor device of claim 9, wherein the uppermost dummy channel pattern of the dummy channel pattern is disposed at a higher level than the uppermost channel pattern of the channel pattern.

13. The cell stack structure includes: A word line; a word line contact contacting the word line; a first conductive line contacting the word line contact; a peripheral gate contact contacting the peripheral gate structure; a second conductive line contacting the peripheral gate contact; the second conductive line is disposed at a higher level than the first conductive line; 10. The semiconductor device of claim 9, wherein the peripheral gate structure is disposed between the first conductive line and the second conductive line.

14. 10. The semiconductor device according to claim 9, wherein a lower surface of the semiconductor structure contacts an upper surface of an uppermost dummy pattern of the dummy patterns.

15. further comprising an isolation structure between the cell stack structure and the dummy stack structure; The semiconductor device of claim 9 , wherein the peripheral gate structure overlaps the isolation structure.

16. A semiconductor device, the semiconductor device comprising: a substrate including a first region and a second region spaced apart from the first region; a cell stack structure in contact with the first region; a peripheral gate insulating film in contact with the second region; a peripheral gate electrode on the peripheral gate insulating film; a peripheral gate capping film on the peripheral gate electrode; a liner covering the peripheral gate capping film; a peripheral gate contact that penetrates the liner and the peripheral gate capping layer and contacts the peripheral gate electrode; The cell stack structure includes: a data storage structure; a bit line spaced apart from the data storage structure; a channel pattern disposed between the bit line and the data storage structure, the channel pattern overlapping the bit line and the data storage structure; a word line disposed between the bit line and the data storage structure; Semiconductor device.

17. 17. The semiconductor device according to claim 16, wherein the liner contacts the second region.

18. the cell stack structure further includes a word line contact contacting the word line; a first conductive line contacting the word line contact and a second conductive line contacting the peripheral gate contact; 17. The semiconductor device of claim 16, wherein the first conductive line and the second conductive line are disposed at the same level.

19. 17. The semiconductor device of claim 16, wherein at least one of the channel patterns is disposed at the same level as the peripheral gate electrode.

20. a peripheral insulating structure surrounding at least a portion of the peripheral gate contact; 17. The semiconductor device of claim 16, wherein at least a portion of the channel pattern is disposed at the same level as the peripheral insulating structure.

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