Solid-state imaging element and imaging apparatus

Abstract

To improve S / N ratio at the time of reading out with high sensitivity while enabling enlargement of a dynamic range.SOLUTION: An element 4 includes: a plurality of pixel blocks BL having one photoelectric conversion part PD, a first node Pa, and one transfer switch which transfers electric charges to the first node Pa from the photoelectric conversion part PD provided corresponding to one photoelectric conversion part PD; two first switch parts SWA which electrically connect and cut off among the first node Pa of one pixel block BL, a first node Pa of the other one pixel block BL, and two second nodes Pb respectively corresponding to these two first nodes Pa; a second switch part SWB which electrically connects and cuts off between two second nodes Pb; and two third switch parts RST which supply predetermined potential VDD to two second nodes Pb, respectively.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device and an imaging apparatus using the same. [Background technology]

[0002] Patent Document 1 listed below discloses a solid-state imaging device having a plurality of pixels, at least two of which each include (a) a photodetector, (b) a charge-voltage conversion region forming a floating capacitance portion, and (c) an input portion to an amplifier, and a connecting switch that selectively connects the charge-voltage conversion regions together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2008-546313 Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional solid-state imaging device, by turning on the connection switch to connect the charge-voltage conversion regions together, the number of saturated electrons in all connected charge-voltage conversion regions is increased, thereby expanding the dynamic range.

[0005] Furthermore, in the conventional solid-state imaging device, by turning off the connection switch and isolating the charge-voltage conversion region from other charge-voltage conversion regions, the charge-voltage conversion capacity becomes smaller and the charge-voltage conversion coefficient becomes larger, thereby increasing the signal-to-noise ratio during high-sensitivity readout.

[0006] However, in the conventional solid-state imaging device, even if the connection switch is turned off, the signal-to-noise ratio during high-sensitivity readout cannot be increased significantly.

[0007] The present invention has been made in view of the above circumstances, and aims to provide a solid-state imaging element that can expand the dynamic range and improve the signal-to-noise ratio during high-sensitivity readout, and an imaging device using the same. [Means for solving the problem]

[0008] As means for solving the above problems, the following aspects are presented: A solid-state imaging device according to a first aspect includes a plurality of pixel blocks each having one photoelectric conversion unit, a first node, and one transfer switch provided corresponding to the one photoelectric conversion unit and transferring charges from the photoelectric conversion unit to the first node, two second nodes corresponding to the first node of one of the pixel blocks and the first node of another of the pixel blocks, two first switch units electrically connecting and disconnecting the first node of one of the pixel blocks and the first node of the other of the pixel blocks to the two second nodes, a second switch unit electrically connecting and disconnecting the two second nodes, and two third switch units supplying predetermined potentials to the two second nodes, respectively.

[0009] The pixel block may have only one photoelectric conversion unit and be configured with one pixel, or may have two or more photoelectric conversion units and be configured with a plurality of pixels, as in each aspect described below.

[0010] A solid-state imaging device according to a second aspect is the solid-state imaging device of the first aspect, wherein each of the pixel blocks includes a plurality of the photoelectric conversion units and a plurality of the transfer switches.

[0011] A solid-state imaging element according to a third aspect is the first or second aspect, and is provided with a control unit that controls each of the first switch units and each of the third switch units so that, in a first operating mode, the first switch unit that electrically connects and disconnects the first node of the one pixel block and the corresponding second node turns on once only when the potential of the first node of the one pixel block is reset, and the third switch unit that supplies the predetermined potential to the second node corresponding to the first node of the one pixel block turns on at least when the potential of the first node of the one pixel block is reset.

[0012] A solid-state imaging element according to a fourth aspect is the third aspect, wherein the control unit controls each of the first switch units, the second switch unit, and the third switch units in a second operating mode so that the first switch unit, which electrically connects and disconnects the first node of the one pixel block and the corresponding second node, is turned on, the second switch unit is turned off, and the third switch unit, which supplies the predetermined potential to the second node corresponding to the first node of the one pixel block, is turned on only when the potential of the first node of the one pixel block is reset.

[0013] A solid-state imaging element according to a fifth aspect is the third or fourth aspect, wherein the control unit controls each of the first switch units, the second switch unit, and the third switch units in a third operating mode so that the first switch unit, which electrically connects and disconnects the first node of the one pixel block and the corresponding second node, is turned on, the second switch unit is turned on, and the third switch unit, which supplies the predetermined potential to the second node corresponding to the first node of the one pixel block, is turned on only when the potential of the first node of the one pixel block is reset.

[0014] A solid-state imaging element according to a sixth aspect is the first or second aspect, and further comprises three or more first switch units that electrically connect and disconnect the electrical connections between the first nodes of three or more pixel blocks among the plurality of pixel blocks and three or more second nodes corresponding to these three or more first nodes, the three or more second nodes being connected in a daisy-chain fashion by a plurality of second switch units, and three or more third switch units that supply the predetermined potential to the three or more second nodes, respectively.

[0015] A solid-state imaging element according to a seventh aspect is the same as that of the sixth aspect, and is provided with a control unit that controls each of the first switch units and each of the third switch units so that, in a first operating mode, the first switch unit that electrically connects and disconnects the first node of one of the three or more pixel blocks to and from the corresponding second node is turned on once only when the potential of the first node of the one of the three or more pixel blocks is reset, and the third switch unit that supplies the predetermined potential to the second node corresponding to the first node of the one of the three or more pixel blocks is turned on at least when the potential of the first node of the one of the three or more pixel blocks is reset.

[0016] In an eighth aspect of the solid-state imaging element, in the seventh aspect, the control unit controls each of the first switch units, each of the second switch units, and each of the third switch units so that, in a second operating mode, the first switch unit electrically connecting and disconnecting the first node of one of the three or more pixel blocks to the corresponding second node is turned on, the second switch unit electrically connected to the second node corresponding to the first node of the one of the three or more pixel blocks is turned off, and the third switch unit supplying the predetermined potential to the second node corresponding to the first node of the one of the three or more pixel blocks is turned on only when the potential of the first node of the one of the three or more pixel blocks is reset.

[0017] A solid-state imaging element according to a ninth aspect is the seventh or eighth aspect, wherein in a third operating mode, the control unit controls each of the first switch units, each of the second switch units, and each of the third switch units so that the first switch unit electrically connecting and disconnecting the first node of one of the three or more pixel blocks to the corresponding second node is turned on, the second switch unit electrically connected to the second node corresponding to the first node of the one of the three or more pixel blocks is turned on, and the third switch unit supplying the predetermined potential to the second node corresponding to the first node of the one of the three or more pixel blocks is turned on only when the potential of the first node of the one of the three or more pixel blocks is reset.

[0018] An imaging device according to a tenth aspect includes the solid-state imaging element according to any one of the first to ninth aspects.

[0019] An imaging device according to an eleventh aspect includes a solid-state imaging element according to the third, fourth, fifth, seventh, eighth or ninth aspect, and a control means for switching between the operating modes depending on the ISO sensitivity setting value. [Effects of the Invention]

[0020] According to the present invention, it is possible to provide a solid-state imaging device that can expand the dynamic range and improve the S / N ratio during high-sensitivity readout, and an imaging apparatus using the same. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device in FIG. [Figure 3] FIG. 2 is an enlarged circuit diagram showing the vicinity of four pixel blocks in FIG. [Figure 4] FIG. 4 is a schematic plan view showing the vicinity of three pixel blocks in FIG. 3. [Figure 5] 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block in FIG. 4. FIG. [Figure 6] 3 is a timing chart showing a predetermined operation mode of the solid-state imaging device shown in FIG. 2. [Figure 7] 3 is a timing chart showing another operation mode of the solid-state imaging device shown in FIG. 2. [Figure 8] 10 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 9] 10 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 10] 10 is a timing chart showing still another operation mode of the solid-state imaging device shown in FIG. [Figure 11] FIG. 10 is a circuit diagram showing the vicinity of three pixel blocks of a solid-state imaging device according to a comparative example. [Figure 12]10 is a schematic plan view showing the vicinity of the three pixel blocks shown in FIG. 9. FIG. [Figure 13] FIG. 10 is a circuit diagram showing a schematic configuration of a solid-state imaging device of an electronic camera according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] A solid-state imaging device and an imaging apparatus according to the present invention will be described below with reference to the drawings.

[0023] [First embodiment] FIG. 1 is a schematic block diagram showing an electronic camera 1 according to a first embodiment of the present invention.

[0024] The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, and electronic cameras such as video cameras that capture moving images.

[0025] A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographing lens 2 are driven by a lens control unit 3. In the image space of this photographing lens 2, the imaging surface of a solid-state imaging device 4 is arranged.

[0026] The solid-state imaging device 4 is driven by commands from the imaging control unit 5 and outputs a digital image signal. During normal actual shooting (still image shooting), the imaging control unit 5 controls the solid-state imaging device 4 to perform a predetermined readout operation after, for example, performing a so-called global reset in which all pixels are reset simultaneously, followed by exposure using a mechanical shutter (not shown). In addition, during electronic viewfinder mode or video shooting, the imaging control unit 5 controls the solid-state imaging device 4 to perform a predetermined readout operation while using, for example, a so-called rolling electronic shutter. In these cases, the imaging control unit 5 controls the solid-state imaging device 4 to perform a readout operation in each operating mode, as described below, according to the ISO sensitivity setting. The digital signal processing unit 6 performs image processing, such as digital amplification, color interpolation, and white balance adjustment, on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in a memory 7. The memory 7 is connected to a bus 8. The bus 8 is also connected to the lens control unit 3, the imaging control unit 5, the CPU 9, a display unit 10 such as an LCD panel, a recording unit 11, an image compression unit 12, and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. The ISO sensitivity can be set using the operation unit 14. A recording medium 11a is detachably attached to the recording unit 11.

[0027] When an instruction for electronic viewfinder mode, video recording, or normal main shooting (still image recording) is issued via the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the lens control unit 3 adjusts the focus and aperture as appropriate. The solid-state imaging element 4 is driven by commands from the imaging control unit 5 to output a digital image signal. The digital image signal from the solid-state imaging element 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. In the electronic viewfinder mode, the CPU 9 displays the image signal on the display unit 10, and during video recording, the CPU 9 records the image signal on the recording medium 11a. During normal main shooting (still image recording), the CPU 9 processes the digital image signal from the solid-state imaging element 4 in the digital signal processing unit 6 and stores it in the memory 7. Based on commands from the operation unit 14, the CPU 9 then performs desired processing as necessary via the image processing unit 13 or image compression unit 12, and then causes the recording unit 11 to output the processed signal, which is then recorded on the recording medium 11a.

[0028] Fig. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging element 4 in Fig. 1. Fig. 3 is a circuit diagram showing an enlarged view of the vicinity of four pixel blocks BL arranged in sequence in the column direction in Fig. 2. Fig. 4 is a schematic plan view showing an enlarged view of the vicinity of three pixel blocks BL in Fig. 3. Fig. 5 is a schematic plan view showing an enlarged view of the vicinity of one pixel block BL in Fig. 4. In this embodiment, the solid-state imaging element 4 is configured as a CMOS-type solid-state imaging element, but is not limited to this and may be configured as, for example, another XY-address type solid-state imaging element.

[0029] As shown in FIGS. 2 to 4, the solid-state imaging device 4 includes pixel blocks BL arranged in a two-dimensional matrix of N rows and M columns, each having two pixels PX (PXA, PXB), a first transistor SWA serving as a first switch unit that electrically connects and disconnects a first node Pa to a corresponding second node Pb, which will be described later, a second transistor SWB serving as a second switch unit that electrically connects and disconnects two second nodes Pb, and a third switch TFT that supplies a power supply voltage VDD as a predetermined potential to the second node Pb. The pixel circuit 20 includes a reset transistor RST as a switch, a vertical scanning circuit 21, control lines 22 to 27 provided for each row of the pixel block BL, a plurality (M) of vertical signal lines 28 provided for each column of the pixels PX (for each column of the pixel block BL) and receiving signals from the pixels PX (pixel block BL) in the corresponding column, a constant current source 29 provided for each vertical signal line 28, a column amplifier 30, a CDS circuit (correlated double sampling circuit) 31 and an A / D converter 32 provided corresponding to each vertical signal line 28, and a horizontal readout circuit 33.

[0030] An analog amplifier or a so-called switched capacitor amplifier may be used as the column amplifier 30. Also, the column amplifier 30 does not necessarily have to be provided.

[0031] For convenience of illustration, FIG. 2 shows M=2, but in reality, the number of columns M can be any larger number. The number of rows N is also not limited. When pixel blocks BL are distinguished by row, the pixel block BL in the jth row is indicated by the symbol BL(j). This also applies to other elements and control signals described later. Four pixel blocks BL(n-1) to BL(n+2) are shown in FIGS. 2 and 3, one for each of the n-1th row to the other for each of the n+2th row.

[0032] In the drawings, the pixel in the pixel block BL at the bottom in FIGS. 2 and 3 is designated PXA, and the pixel in the upper in FIGS. 2 and 3 is designated PXB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol PX may be used to refer to both. In the drawings, the photodiode in pixel PXA is designated PDA, and the photodiode in pixel PXB is designated PDB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol PD may be used to refer to both. Similarly, the transfer transistor in pixel PXA is designated TXA, and the transfer transistor in pixel PXB is designated TXB, to distinguish between them. However, when describing the two without distinguishing between them, the symbol TX may be used to refer to both. In this embodiment, the photodiodes PD of the pixels PX are arranged in a two-dimensional matrix of 2N rows and M columns.

[0033] In this embodiment, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charge in response to incident light, and a transfer transistor TX as a transfer switch that transfers the charge from the photodiode PD to a first node Pa.

[0034] In this embodiment, the multiple pixels PX form a pixel block BL, with each pair of pixels PX (PXA, PXB) having photodiodes PD arranged in sequence in the column direction. As shown in FIGS. 2 and 3, for each pixel block BL, the two pixels PX (PXA, PXB) belonging to that pixel block BL share a set of a first node Pa, an amplification transistor AMP, and a selection transistor SEL. A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa and a reference potential, and the capacitance converts the charge transferred to the first node Pa into a voltage. The amplification transistor AMP constitutes an amplifier that outputs a signal corresponding to the potential of the first node Pa. The selection transistor SEL constitutes a selection unit for selecting the pixel block BL. The photodiode PD and the transfer transistor TX are not shared by the two pixels PX (PXA, PXB), but are provided for each pixel PX. In FIGS. 2 and 3, n indicates the row of the pixel block BL. For example, the pixel block BL of the first row is composed of the pixel PX (PXA) of the first row and the pixel PX (PXB) of the second row, and the pixel block BL of the second row is composed of the pixel PX (PXA) of the third row and the pixel PX (PXB) of the fourth row.

[0035] For example, the transfer transistor TXA(n) of the pixel block BL(n) transfers charges from the photodiode PDA(n) to the first node Pa(n), and the transfer transistor TXB(n) transfers charges from the photodiode PDB(n) to the first node Pa(n). A capacitance (charge-voltage conversion capacitance) is formed between the first node Pa(n) and a reference potential, and this capacitance converts the charges transferred to the first node Pa(n) into a voltage. The amplification transistor AMP(n) outputs a signal corresponding to the potential of the first node Pa(n). These points are similar for the other rows of the pixel block BL.

[0036] In the present invention, for example, a pixel block BL may be configured for every three or more pixels PX in which photodiodes PD are sequentially arranged in the column direction.

[0037] Although not shown in the drawings, in this embodiment, a plurality of types of color filters, each of which transmits light of a different color component, are arranged in a predetermined color array (e.g., a Bayer array) on the light incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

[0038] The first transistor SWA(n) constitutes a first switch unit that electrically connects and disconnects the first node Pa(n) and the corresponding second node Pb(n). Although such a first switch unit can be configured by combining switches such as multiple transistors, it is preferable to configure it with a single first transistor SWA(n) as in this embodiment to simplify the structure. These points also apply to the other first transistors SWA.

[0039] Each second transistor SWB constitutes a second switch unit provided for each pair of pixel blocks BL adjacent to each other in the column direction to electrically connect and disconnect the second node Pb corresponding to the first node Pa of one pixel block BL to the second node Pb corresponding to the first node Pa of the other pixel block BL. As a result, in this embodiment, the first nodes Pa of three or more pixel blocks BL are connected in a daisy-chain fashion by a plurality of the second switch units. While the second switch unit described above can be formed by combining a plurality of switches such as transistors, it is preferable to form it with a single second transistor SWB, as in this embodiment, in order to simplify the structure.

[0040] For example, the second transistor SWB(n) is provided to electrically connect and disconnect the second node Pb(n) corresponding to the first node Pa(n) of the pixel block BL(n) on the nth row and the second node Pb(n-1) corresponding to the first node Pa(n-1) of the pixel block BL(n-1) on the n-1th row, as in the other second transistors SWB.

[0041] The reset transistor RST(n) constitutes a third switch unit that supplies a power supply voltage VDD as a predetermined potential to the second node Pb(n). Although such a third switch unit can be constituted by combining switches such as multiple transistors, it is preferable to constitute it by a single reset transistor RST(n) as in this embodiment in order to simplify the structure. These points also apply to the other reset transistors RST.

[0042] 2 and 3, VDD is a power supply potential. In this embodiment, the transistors TXA, TXB, AMP, RST, SEL, SWA, and SWB are all nMOS transistors.

[0043] The gates of the transfer transistors TXA for each row are connected in common to a control line 26, to which a control signal φTXA is supplied from the vertical scanning circuit 21. The gates of the transfer transistors TXB for each row are connected in common to a control line 25, to which a control signal φTXB is supplied from the vertical scanning circuit 21. The gates of the reset transistors RST for each row are connected in common to a control line 24, to which a control signal φRST is supplied from the vertical scanning circuit 21. The gates of the select transistors SEL for each row are connected in common to a control line 23, to which a control signal φSEL is supplied from the vertical scanning circuit 21. The gates of the first transistors SWA for each row are connected in common to a control line 22, to which a control signal φSWA is supplied from the vertical scanning circuit 21. The gates of the second transistors SWB for each row are connected in common to a control line 27, to which a control signal φSWB is supplied from the vertical scanning circuit 21. For example, a control signal φTXA(n) is supplied to the gate of the transfer transistor TXA(n), a control signal φTXB(n) is supplied to the gate of the transfer transistor TXB(n), a control signal φRST(n) is supplied to the gate of the reset transistor RST(n), a control signal φSEL(n) is supplied to the gate of the select transistor SEL(n), a control signal φSWA(n) is supplied to the gate of the first transistor SWA(n), and a control signal φSWB(n) is supplied to the gate of the second transistor SWB(n).

[0044] The transistors TXA, TXB, RST, SEL, SWA, and SWB are turned on when the corresponding control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB are at high level (H), and turned off when they are at low level (L).

[0045] 1, the vertical scanning circuit 21 outputs control signals φTXA, φTXB, φRST, φSEL, φSWA, and φSWB for each row of the pixel block BL to control the pixel block BL, the first transistor SWA, and the second transistor SWB, thereby realizing still image readout operations, moving image readout operations, and the like. In this control, readout operations in various operation modes, which will be described later, are performed according to, for example, the ISO sensitivity setting. Through this control, signals (analog signals) from the pixels PX in the corresponding column are supplied to each vertical signal line 28.

[0046] In this embodiment, the vertical scanning circuit 21 constitutes a control unit that switches between each operation mode, which will be described later, in response to a command (control signal) from the imaging control unit 5 in FIG.

[0047] The signals read out to the vertical signal lines 28 are amplified by a column amplifier 30 for each column, and then processed by a CDS circuit 31 to obtain the difference between the optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and the dark signal (a difference signal containing a noise component to be subtracted from the optical signal), and then converted into a digital signal by an A / D converter 32, and the digital signal is held in the A / D converter 32. The digital image signals held in each A / D converter 32 are horizontally scanned by a horizontal readout circuit 33, converted into a predetermined signal format as necessary, and output to the outside (digital signal processing unit 6 in FIG. 1).

[0048] The CDS circuit 31 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 30 as a dark signal when φDARKC is at a high level (H), and also receives a light signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in Fig. 1, and samples the output signal of the column amplifier 30 as a light signal when φSIGC is at H. The CDS circuit 31 then outputs a signal corresponding to the difference between the sampled dark signal and light signal, based on the clock and pulses from the timing generation circuit. A known configuration can be adopted for the configuration of this CDS circuit 31.

[0049] Here, the structure of the pixel block BL will be described with reference to Figures 4 and 5. In reality, a color filter, a microlens, etc. are arranged above the photodiode PD, but these are omitted in Figures 4 and 5. Note that in Figures 4 and 5, the layout of the power supply lines, ground lines, control lines 22 to 27, etc. is omitted.

[0050] In this embodiment, a P-type well (not shown) is provided on an N-type silicon substrate (not shown), and elements in the pixel block BL, such as photodiodes PD, are disposed in the P-type well. In Fig. 5, reference numerals 41 to 50 denote N-type impurity diffusion regions that form part of the aforementioned transistors. Reference numerals 61 to 67 denote gate electrodes of the transistors made of polysilicon. The diffusion regions 42 and 50 are regions to which a power supply voltage VDD is applied via a power supply line (not shown).

[0051] The photodiodes PDA(n) and PDB(n) are buried photodiodes consisting of an N-type charge accumulation layer (not shown) provided in the P-type well and a P-type depletion prevention layer (not shown) disposed on the surface side of the N-type charge accumulation layer. The photodiodes PDA(n) and PDB(n) photoelectrically convert incident light and accumulate the generated charges in the charge accumulation layer.

[0052] The transfer transistor TXA(n) is an nMOS transistor with the charge storage layer of the photodiode PDA(n) as its source, the diffusion region 41 as its drain, and the gate electrode 61 as its gate. The transfer transistor TXB(n) is an nMOS transistor with the charge storage layer of the photodiode PDB(n) as its source, the diffusion region 41 as its drain, and the gate electrode 62 as its gate. The diffusion region 41 is provided between the photodiode PDA(n) and the photodiode PDB(n). The diffusion region 41 serves as both the diffusion region that becomes the drain of the transfer transistor TXA(n) and the diffusion region that becomes the drain of the transfer transistor TXB(n). The gate electrode 61 of the transfer transistor TXA(n) is located on the photodiode PDA(n) side of the diffusion region 41. The gate electrode 62 of the transfer transistor TXB(n) is located on the photodiode PDB(n) side of the diffusion region 41.

[0053] The amplification transistor AMP(n) is an nMOS transistor with the diffusion region 42 as its drain, the diffusion region 43 as its source, and the gate electrode 63 as its gate. The selection transistor SEL(n) is an nMOS transistor with the diffusion region 43 as its drain, the diffusion region 44 as its source, and the gate electrode 64 as its gate. The diffusion region 44 is connected to the vertical signal line 28.

[0054] The first transistor SWA(n) is an nMOS transistor with the diffusion region 45 as its source, the diffusion region 46 as its drain, and the gate electrode 65 as its gate. The second transistor SWB(n) is an nMOS transistor with the diffusion region 47 as its drain, the diffusion region 48 as its source, and the gate electrode 66 as its gate. The reset transistor RST(n) is an nMOS transistor with the diffusion region 49 as its source, the diffusion region 50 as its drain, and the gate electrode 67 as its gate.

[0055] The gate electrode 63 and the diffusion regions 41, 45 of the pixel block BL(n) are electrically connected to each other by a wiring 71(n) for conduction. In this embodiment, the first node Pa(n) corresponds to the wiring 71(n) and all of the parts electrically connected to and conducting thereto.

[0056] The drain diffusion region 46 of the first transistor SWA(n), the drain diffusion region 47 of the second transistor SWB(n), the source diffusion region 49 of the reset transistor RST(n), and the source diffusion region 48 of the second transistor SWB(n+1) are electrically connected to one another by a wiring 72(n), providing conduction. The second node Pb(n) corresponds to the wiring 72(n) and all of the locations electrically connected to and conducting thereto. The same applies to the other first transistors SWA, other second transistors SWB, and other reset transistors RST.

[0057] The structure of the pixel blocks BL other than the n-th row is the same as the structure of the pixel block BL(n) in the n-th row described above. The structure of the first transistors SWA other than the first transistor SWA(n) is the same as the structure of the first transistor SWA(n) described above. The structure of the connecting transistors SWB other than the second transistor SWB(n) is the same as the structure of the connecting transistor SWB(n) described above. The structure of the reset transistors RST other than the reset transistor RST(n) is the same as the structure of the reset transistor RST(n) described above.

[0058] 2 to 5, CC(n) is the capacitance between the first node Pa(n) and the reference potential when the first transistor SWA(n) is off. The capacitance value of the capacitance CC(n) is Cfd1. CD(n) is the capacitance between the wiring 72(n) and the reference potential when the first transistor SWA(n), the second transistors SWB(n), SWB(n+1), and the reset transistor RST(n) are off. The capacitance value of the capacitance CD(n) is Cfd2. The same applies to the other first transistors SWA, the other second transistors SWB, and the other reset transistors RST.

[0059] The capacitance CC(n) is composed of the capacitance of the drain diffusion region 41 of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the first transistor SWA(n), the capacitance of the gate electrode 63 of the amplifier transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values ​​is the capacitance value Cfd1 of the capacitance CC(n). This also applies to the rows of the other pixel blocks BL. Note that the drain diffusion region 47 of the second transistor SWB(n) and the source diffusion region 49 of the reset transistor RST(n) are not components of the capacitance CC(n), and therefore the capacitance value Cfd1 of the capacitance CC(n) is smaller accordingly.

[0060] Here, the channel capacitance value of the first transistor SWA when it is on and the channel capacitance value of the second transistor SWB when it is on are both denoted as Csw. Typically, the capacitance value Csw is smaller than the capacitance values ​​Cfd1 and Cfd2.

[0061] Now, focusing on pixel block BL(n), when the first transistor SWA(n) is turned off (i.e., the on-state transistors of each of the first transistors SWA and each of the second transistors SWB are not electrically connected to the first node Pa(n)), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential becomes capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1. This state corresponds to a state other than the reset state of the first node Pa(n) during period T2 in FIG. 6, which shows the first operation mode described below (the state during the period when φSWA(n) is L during period T2 in FIG. 6).

[0062] Furthermore, for pixel block BL(n), when the first transistor SWA(n) is turned on, unless any of the first transistors SWA and second transistors SWB that are turned on except for the first transistor SWA(n) are electrically connected to the first node Pa(n) (specifically, if the second transistors SWB(n) and SWB(n+1) are turned off), the capacitance (charge-voltage conversion capacitance) between the first node Pa(n) and the reference potential is the sum of the capacitance CC(n) and the channel capacitance of the first transistor SWA(n) when it is turned on. Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1 + Cfd2 + Csw ≈ Cfd1 + Cfd2. This state corresponds to the state during period T2 in FIG. 7, which illustrates the second operating mode described below.

[0063] Furthermore, with respect to pixel block BL(n), when the first transistor SWA(n) and the second transistor SWB(n+1) are turned on, unless any of the first transistors SWA and second transistors SWB that are turned on except for the transistors SWA(n) and SWB(n+1) are electrically connected to the first node Pa(n) (specifically, if the transistors SWB(n), SWA(n+1), and SWB(n+2) are turned off), the charge-voltage conversion capacitance of the first node Pa(n) is calculated by adding the capacitances CD(n), CD(n+1), and the channel capacitances of the transistors SWA(n) and SWB(n+1) when they are on to the capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+2×Cfd2+2×Csw ≈ Cfd1+2×Cfd2. This state corresponds to the state of period T2 in FIG. 8, which shows the 3A operation mode described later.

[0064] Furthermore, focusing on pixel block BL(n), when the first transistors SWA(n), SWA(n+1) and second transistor SWB(n+1) are turned on, if none of the first transistors SWA and second transistors SWB that are on, other than transistors SWA(n), SWA(n+1), and SWB(n+1), are electrically connected to the first node Pa(n) (specifically, if transistors SWB(n) and SWB(n+2) are off), then the charge-voltage conversion capacitance of the first node Pa(n) will be calculated by adding capacitance CD(n), capacitance CD(n+1), capacitance CC(n+1), and the channel capacitances of transistors SWA(n), SWA(n+1), and SWB(n+1) when they are on to capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≈2×Cfd1+2×Cfd2. This state corresponds to the state of period T2 in FIG. 9, which shows the third B operation mode described later.

[0065] Furthermore, focusing on pixel block BL(n), when the first transistor SWA(n) and the second transistors SWB(n+1), SWB(n+2) are turned on, if none of the first transistors SWA and second transistors SWB that are on are electrically connected to the first node Pa(n) (specifically, if the transistors SWA(n+1), SWA(n+2), SWB(n), SWB(n+3) are off), then the charge-voltage conversion capacitance of the first node Pa(n) will be calculated by adding the capacitances CD(n), CD(n+1), and CD(n+2) and the channel capacitances of the transistors SWA(n), SWB(n+1), and SWB(n+2) when they are on to the capacitance CC(n). Therefore, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+3×Cfd2+3×Csw≈Cfd1+3×Cfd2. This state corresponds to the state of period T2 in Figure 10, which shows the 3C operation mode described later.

[0066] In this way, if none of the first transistors SWA and second transistors SWB are in an on-state and electrically connected to the first node Pa(n), the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes the minimum capacitance value Cfd1, and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, making it possible to read with the highest signal-to-noise ratio.

[0067] On the other hand, if the number of on-state transistors electrically connected to the first node Pa(n) among the first transistors SWA and second transistors SWB is increased to a desired number equal to or greater than one, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) can be increased to a desired value, allowing a larger amount of signal charge to be handled, thereby increasing the number of saturation electrons and thereby expanding the dynamic range.

[0068] The first node Pa(n) of the pixel block BL(n) has been described above, but the same applies to the first nodes Pa of the other pixel blocks BL.

[0069] 6 is a timing chart illustrating a first operation mode of the solid-state imaging device 4 shown in FIG. 2. In this first operation mode, each pixel block BL is sequentially selected row by row. In a state where none of the first transistors SWA and second transistors SWB are electrically connected to the first node Pa of the selected pixel block BL in an on-state (a state where the charge-voltage conversion capacitance of the first node Pa is minimum), the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out signals from the photodiodes PDA and PDB of the selected pixel block BL row by row. In the example shown in FIG. 6, signals from all pixels PXA and PXB are read out. However, this is not limiting. For example, thinning-out readout, in which pixel rows are thinned out and readout, may also be performed. This also applies to the examples shown in FIGS. 7 to 10, which will be described later.

[0070] 6 shows a situation in which pixel block BL(n-1) in the n-1th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the n+1th row is selected in period T3. Since the operation is the same when pixel block BL in any row is selected, only the operation when pixel block BL(n) in the nth row is selected will be described here.

[0071] Before the start of period T2, the exposure of photodiodes PDA(n), PDB(n) has already been completed during a predetermined exposure period. During normal actual shooting (still image shooting), this exposure is performed by a mechanical shutter (not shown) after a so-called global reset, which resets all pixels simultaneously. In electronic viewfinder mode or video shooting, the exposure is performed by a so-called rolling electronic shutter operation. Immediately before the start of period T2, all transistors SEL, RST, TXA, TXB, SWA, and SWB are off.

[0072] During period T2, φSEL(n) on the nth row is set to H, turning on the select transistor SEL(n) of the nth row pixel block BL(n), and selecting the nth row pixel block BL(n). Also during period T2, φRST(n) on the nth row is set to H, turning on the reset transistor RST(n). However, the reset transistor RST(n) does not necessarily have to be on throughout the entire period T2; φRST(n) may be set to H only when the first node Pa(n) is reset (i.e., during the H period of φSWA(n) in FIG. 6).

[0073] Immediately after the start of period T2, for a certain period of time (when the first node Pa(n) is reset), φSWA(n) is set to H and the first transistor SWA(n) in the nth row is temporarily turned on. At this time, φRST(n) is set to H and the reset transistor RST(n) is on, so the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD via the reset transistor RST(n) in an on state and the first transistor SWA(n) in an on state.

[0074] After that, when the first transistor SWA(n) is turned off, none of the transistors SWA, SWB is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1, which is the minimum.

[0075] After that, from time t1 during the period T2, for a certain period of time, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the first node Pa(n) is amplified by the amplifier transistor AMP(n) on the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28 and is further amplified by the column amplifier 30. The signal is then sampled by the CDS circuit 31 as a dark signal.

[0076] After that, from time t2 during period T2, φTXA(n) is set to H for a fixed period of time, turning on the transfer transistor TXA(n) in the nth row. As a result, the signal charge accumulated in the photodiode PDA(n) in the pixel block BL(n) in the nth row is transferred to the charge-voltage conversion capacitance of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n).

[0077] At a later time point t3 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the amplifier transistor AMP(n) in the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28 and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

[0078] After that, after φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t1 and the optical signal sampled over a fixed period from time t3. The A / D converters 32 convert the signal corresponding to this difference into a digital signal and hold it. The digital image signals held in each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (digital signal processing unit 6 in FIG. 1).

[0079] Then, for a fixed period from time t4 during period T2 (when the first node Pa(n) is reset), φSWA(n) is set to H and the first transistor SWA(n) in the nth row is temporarily turned on. At this time, φSEL(n) is set to H and the reset transistor RST(n) is on, so the potential of the first node Pa(n) is temporarily reset to the power supply potential VDD via the reset transistor RST(n) in the on state and the first transistor SWA(n) in the on state.

[0080] After that, when the first transistor SWA(n) is turned off, none of the transistors SWA, SWB is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1, which is the minimum.

[0081] After that, from time t5 during the period T2, for a certain period of time, the dark signal sampling signal φDARKC is set to H, and the potential appearing at the first node Pa(n) is amplified by the amplifier transistor AMP(n) on the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28. The signal is then amplified by the column amplifier 30 and sampled as a dark signal by the CDS circuit 31.

[0082] From time t6 thereafter during period T2, φTXB(n) is set to H for a fixed period of time, turning on the transfer transistor TXB(n) in the nth row. As a result, the signal charge accumulated in the photodiode PDB(n) in the pixel block BL(n) in the nth row is transferred to the charge-voltage conversion capacitance of the first node Pa(n). The potential of the first node Pa(n), excluding noise components, is proportional to the amount of this signal charge and the reciprocal of the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n).

[0083] At a later time point t7 during the period T2, the optical signal sampling signal φSIGC is set to H, and the potential appearing at the first node Pa(n) is amplified by the amplifier transistor AMP(n) in the nth row, and then passes through the select transistor SEL(n) and the vertical signal line 28 and is further amplified by the column amplifier 30. The signal is then sampled as an optical signal by the CDS circuit 31.

[0084] After that, after φSIGC goes low, the CDS circuit 31 outputs a signal corresponding to the difference between the dark signal sampled over a fixed period from time t5 and the optical signal sampled over a fixed period from time t7. The A / D converters 32 convert the signal corresponding to this difference into a digital signal and hold it. The digital image signals held in each A / D converter 32 are horizontally scanned by the horizontal readout circuit 33 and output as digital image signals to the outside (the digital signal processing unit 6 in FIG. 1).

[0085] In this way, in the first operation mode, since none of the transistors SWA, SWB are electrically connected to the first node Pa of the selected pixel block BL in the on state, the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL is minimized, and the charge-voltage conversion coefficient due to the charge-voltage conversion capacitance is increased, enabling readout with the highest S / N ratio. For example, when the ISO sensitivity setting is highest, the imaging control unit 5 issues a command to perform the first operation mode.

[0086] Fig. 7 is a timing chart showing a second operation mode of the solid-state imaging device 4 shown in Fig. 2. This second operation mode is an example of an operation in which each pixel block BL is selected sequentially row by row, and the transfer transistors TXA, TXB of the selected pixel block BL are selectively turned on sequentially while one of the first transistors SWA and the second transistors SWB that is in an on state is electrically connected to the first node Pa of the selected pixel block BL, thereby sequentially reading out signals of each photodiode PDA, PDB of the selected pixel block BL row by row.

[0087] 7, like Fig. 6, shows a situation in which pixel block BL(n-1) in the (n-1)th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the (n+1)th row is selected in period T3. The second operation mode shown in Fig. 7 differs from the first operation mode shown in Fig. 6 in the following points.

[0088] In the second operation mode shown in FIG. 7, during a period T2 in which the pixel block BL(n) in the nth row is selected, φSWA(n) is set to H, and φSWB(n) and φSWB(n+1) are set to L, turning on the first transistor SWA(n) and turning off the second transistors SWB(n) and φSWB(n+1). As a result, during period T2, one of the transistors SWA and SWB, the first transistor SW (here, the first transistor SWA(n)), is electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is, so to speak, one step larger than that of the first operation mode shown in FIG. 6.

[0089] 7, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while φRST(n) is set to H and the reset transistor RST(n) is turned on only when the first node Pa(n) is reset (for a certain period from immediately after the start of period T2 and for a certain period from time t4 during period T2). This allows the potential of the first node Pa(n) to be properly reset.

[0090] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0091] In this way, in the second operation mode, the first transistor SWA of one of the transistors SWA and SWB that is in the on state is electrically connected to the first node Pa of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by one step, so to speak, and the number of saturation electrons in the charge-voltage conversion capacitance of the first node Pa can be increased by one step. This makes it possible to increase the dynamic range by one step. For example, when the ISO sensitivity setting is one step lower than the highest value, the imaging control unit 5 issues a command to execute the second operation mode.

[0092] 8 is a timing chart showing the 3A operation mode of the solid-state imaging device 4 shown in FIG. The 3A operation mode is one of the third operation modes. The third operation mode is an example of an operation in which each pixel block BL is sequentially selected row by row, and signals from each photodiode PDA, PDB of the selected pixel block BL are sequentially read out row by row by selectively turning on the transfer transistors TXA, TXB of the selected pixel block BL in a state in which the first transistor SWA electrically connecting and disconnecting the first node Pa of the selected pixel block BL to the corresponding second node Pb is turned on, the second transistor SWB electrically connected to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on, and the reset transistor RST supplying the power supply potential VDD to the second node Pb corresponding to the first node Pa of the selected pixel block BL is turned on only when the first node Pa of the selected pixel block BL is reset. The third A operation mode is an example of an operation in which, in the third operation mode, one first transistor SWA in an on state and one second transistor SWB in an on state are electrically connected to the first node Pa of the selected pixel block BL.

[0093] 8, like Fig. 6, shows a situation in which pixel block BL(n-1) in the (n-1)th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the (n+1)th row is selected in period T3. The differences between the 3Ath operation mode shown in Fig. 8 and the first operation mode shown in Fig. 6 are as follows.

[0094] 8, during a period T2 in which the n-th pixel block BL(n) is selected, φSWA(n) and φSWB(n+1) are set to H, and φSWA(n+1), φSWB(n), and φSWB(n+2) are set to L, turning on the first transistor SWA(n) and the second transistor SWB(n+1) and turning off the first transistor SWA(n+1) and the second transistor SWB(n), SWB(n+2). As a result, during the period T2, one of the on-state first transistor SWA (here, the first transistor SWA(n)) and one on-state second transistor SWB (here, the second transistor SWB(n+1)) of the transistors SWA and SWB are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) becomes Cfd1+Cfd2+Csw≈Cfd1+Cfd2, which is two stages larger than that in the first operation mode shown in FIG.

[0095] In the 3A operation mode shown in FIG. 8, φSWA(n) is set to H and the first transistor SWA(n) is turned on, while φRST(n) is set to H and the reset transistor RST(n) is turned on only when the first node Pa(n) is reset (for a certain period from immediately after the start of period T2 and for a certain period from time t4 during period T2). This allows the potential of the first node Pa(n) to be reset appropriately. This also applies to the 3B operation mode shown in FIG. 9 and the 3C operation mode shown in FIG. 10, which will be described later.

[0096] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0097] In this way, in the third operation mode, one of the transistors SWA and SWB, the first transistor SWA in the on state, and one of the second transistors SWB in the on state, are electrically connected to the first node Pa of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by two steps, so to speak, and the number of saturation electrons in the charge-voltage conversion capacitance of the first node Pa can be increased by two steps. This allows the dynamic range to be expanded by two steps. For example, when the ISO sensitivity setting is two steps lower than the highest value, the imaging control unit 5 issues a command to perform the 3A operation mode.

[0098] Fig. 9 is a timing chart showing the 3B operation mode of the solid-state imaging device 4 shown in Fig. 2. The 3B operation mode is an example of an operation in which two first transistors SWA in an on state and one second transistor SWB in an on state are electrically connected to the first node Pa of the selected pixel block BL in the third operation mode.

[0099] 9, like Fig. 4, shows a situation in which pixel block BL(n-1) in the (n-1)th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the (n+1)th row is selected in period T3. The differences between the 3B operation mode shown in Fig. 9 and the first operation mode shown in Fig. 4 are as follows.

[0100] 9 , during a period T2 in which the n-th pixel block BL(n) is selected, φSWA(n), φSWA(n+1), and φSWB(n+1) are set to H, and φSWB(n) and φSWB(n+2) are set to L, so that the first transistors SWA(n), SWA(n+1) and the second transistor SWB(n+1) are turned on, and the second transistors SWB(n), SWB(n+2) are turned off. As a result, during the period T2, two of the transistors SWA and SWB that are in the on state (first transistors SWA(n), SWA(n+1) here) and one of the second transistors SWB that is in the on state (second transistor SWB(n+1) here) are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is 2×Cfd1+2×Cfd2+3×Csw≈2×Cfd1+2×Cfd2, which is three stages larger than the first operation mode shown in FIG. 6.

[0101] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0102] In this way, in the third-order operation mode (3B), two of the transistors SWA and SWB, the first transistor SWA in the on state and one of the second transistors SWB in the on state, are electrically connected to the first node Pa of the selected pixel block BL, so that the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL increases by three steps, and the number of saturation electrons in the charge-voltage conversion capacitance of the first node Pa can be increased by three steps. This allows the dynamic range to be expanded by three steps. For example, when the ISO sensitivity setting is three steps lower than the highest value, the imaging control unit 5 issues a command to execute the third-order operation mode.

[0103] Fig. 10 is a timing chart showing the 3C operation mode of the solid-state imaging device 4 shown in Fig. 2. This 3C operation mode is an example of an operation in which each pixel block BL is selected row by row in sequence, and in a state in which one of the first transistors SWA and the second transistors SWB, that is in an on-state, and two of the second transistors SWB, that are in an on-state, are electrically connected to the first node Pa of the selected pixel block BL, the transfer transistors TXA and TXB of the selected pixel block BL are selectively turned on in sequence, thereby sequentially reading out signals from each photodiode PDA and PDB of the selected pixel block BL row by row.

[0104] 6, Fig. 10 also shows a situation in which pixel block BL(n-1) in the (n-1)th row is selected in period T1, pixel block BL(n) in the nth row is selected in period T2, and pixel block BL(n+1) in the (n+1)th row is selected in period T3. The differences between the 3C operation mode shown in Fig. 10 and the first operation mode shown in Fig. 4 are as follows.

[0105] In the 3C operation mode shown in FIG. 10, during a period T2 in which the pixel block BL(n) in the nth row is selected, φSWA(n), φSWB(n+1), and φSWB(n+2) are set to H, and φSWA(n+1), φSWA(n+2), φSWB(n), and φSWB(n+3) are set to L, so that the first transistor SWA(n) and the second transistors SWB(n+1), SWB(n+2) are turned on, and the first transistors SWA(n+1), SWA(n+2) and the second transistors SWB(n), SWB(n+3) are turned off. As a result, during period T2, one of the transistors SWA, SWB, the first transistor SWA (here, the first transistor SWA(n)), and the two second transistors SWB (here, the second transistors SWB(n+1), SWB(n+2)), are electrically connected to the first node Pa(n) of the selected pixel block BL(n). Therefore, as described above, the capacitance value of the charge-voltage conversion capacitance of the first node Pa(n) is Cfd1+3×Cfd2+3×Csw≈Cfd1+3×Cfd2, which is three stages larger than the first operation mode shown in FIG.

[0106] Here, the period T2 in which the pixel block BL(n) in the nth row is selected has been described, but the same applies to the periods in which other pixel blocks BL are selected.

[0107] In this way, in the third-level operation mode, one of the transistors SWA and SWB, the first transistor SWA, is in an on-state, and the two second transistors SWB are in an on-state. This electrically connects the first node Pa of the selected pixel block BL, increasing the capacitance value of the charge-voltage conversion capacitance of the first node Pa of the selected pixel block BL by three steps, thereby expanding the number of saturation electrons in the charge-voltage conversion capacitance of the first node Pa by three steps. This allows the dynamic range to be expanded by three steps. For example, when the ISO sensitivity setting is three steps lower than the highest value, the imaging control unit 5 issues a command to execute the second operation mode.

[0108] Here, a solid-state imaging device according to a comparative example, which is compared with the solid-state imaging device 4 according to the present embodiment, will be described. FIG. 11 is a circuit diagram showing the vicinity of three pixel blocks BL of the solid-state imaging device according to this comparative example, and corresponds to FIG. 3. FIG. 12 is a schematic plan view showing the vicinity of the three pixel blocks BL shown in FIG. 11, and corresponds to FIGS. 4 and 5. In FIGS. 11 and 12, elements that are the same as or correspond to elements in FIGS. 3, 4, and 5 are given the same reference numerals, and redundant explanations will be omitted. Note that although reference numerals are not given to diffusion regions and gate electrodes in FIG. 12, these reference numerals are the same as those in FIG. 5, so please refer to FIG. 5 as necessary.

[0109] This comparative example differs from the present embodiment in the following respects. In this comparative example, the first and second transistors SWA and SWB and the wirings 71 and 72 are removed, and instead a first coupling transistor SWa, a second coupling transistor SWb, and wirings 97 and 98 are provided. Also, in this comparative example, a node P corresponding to the first node Pa exists, but a node corresponding to the second node Pb does not exist. Furthermore, in this embodiment, the source of the reset transistor RST is not connected to the first node Pa but is connected to the second node Pb, whereas in this comparative example, the source of the reset transistor RST is connected to the node P.

[0110] In this comparative example, for each pair of pixel blocks BL that are adjacent to each other in the column direction among the pixel blocks BL, a first linking transistor SWa and a second linking transistor SWb are provided in series between a node P of one pixel block BL and a node P of the other pixel block BL. For example, a first linking transistor SWa(n) and a second linking transistor SWb(n) are provided in series between a node P(n) of a pixel block BL(n) in the nth row and a node P(n+1) of a pixel block BL in the n+1th row.

[0111] In this comparative example, the gate electrode of the amplifier transistor AMP(n), the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the source diffusion region of the first linking transistor SWa(n), the drain diffusion region of the second linking transistor SWb(n-1), and the source diffusion region of the reset transistor RST(n) of the pixel block BL(n) are electrically connected to one another by a wiring 97(n), thereby providing conduction. A node P(n) corresponds to the wiring 97(n) and all of the locations electrically connected to and conducting thereto. This also applies to the other pixel blocks BL.

[0112] In this comparative example, each pair of linking transistors SWa and SWb arranged in series between each pair of nodes P are connected by a wiring 98. For example, the drain diffusion region of the first linking transistor SWa(n) and the source diffusion region of the second linking transistor SWb(n) are electrically connected by a wiring 98(n).

[0113] 11 and 12, CA(n) is the capacitance between node P(n) and the reference potential when the linking transistors SWa(n) and SWb(n-1) are off. The capacitance value of capacitance CA(n) is Cfd1'. CB(n) is the capacitance between wiring 72(n) and the reference potential when the linking transistors SWa(n) and SWb(n) are off. These points also apply to the other rows of pixel block BL.

[0114] The capacitance CA(n) is composed of the capacitance of the drain diffusion regions of the transfer transistors TXA(n) and TXB(n), the capacitance of the source diffusion region of the reset transistor RST(n), the capacitance of the source diffusion region of the first linking transistor SWa(n), the capacitance of the drain diffusion region of the second linking transistor SWb(n-1), the capacitance of the gate electrode of the amplifier transistor AMP(n), and the wiring capacitance of the wiring 97(n), and the sum of these capacitance values ​​is the capacitance value Cfd1' of the capacitance CA(n). This also applies to the other rows of the pixel block BL.

[0115] In contrast, as described above, the capacitance CC(n) in this embodiment is composed of the capacitance of the drain diffusion regions 41 of the transfer transistors TXA(n), TXB(n), the capacitance of the source diffusion region of the first transistor SWA(n), the capacitance of the gate electrode of the amplification transistor AMP(n), and the wiring capacitance of the wiring 71(n), and the sum of these capacitance values ​​is the capacitance value Cfd1 of the capacitance CC(n).

[0116] Therefore, the capacitance value Cfd1 of the capacitance CC(n) in this embodiment is smaller than the capacitance value Cfd1′ of the capacitance CA(n) in this comparative example by the capacitance of the drain diffusion region of the second link transistor SWb(n-1) and the capacitance of the source diffusion region of the reset transistor RST(n) (i.e., by the amount of two transistor diffusion capacitances).

[0117] In this comparative example, focusing on pixel block BL(n), when both linking transistors SWa(n) and SWb(n-1) are turned off, the capacitance (charge-voltage conversion capacitance) between node P(n) and the reference potential becomes capacitance CA(n), the capacitance value of the charge-voltage conversion capacitance of node P(n) becomes the minimum Cfd1', and the charge-voltage conversion coefficient due to this charge-voltage conversion capacitance becomes large, enabling readout with the highest SNR. Also, in this comparative example, by increasing the number of linking transistors SWa and SWb that are in the on state and electrically connected to node P(n) to a desired number greater than or equal to one, the capacitance value of the charge-voltage conversion capacitance of node P(n) can be increased to a desired value, allowing for the handling of a large amount of signal charge and therefore increasing the number of saturation electrons. This allows for an expanded dynamic range.

[0118] As described above, the minimum capacitance value Cfd1 of the charge-voltage conversion capacitance of the first node Pa(n) in this embodiment is smaller by two transistor diffusion capacitances than the minimum capacitance value Cfd1' of the charge-voltage conversion capacitance of the node P(n) in this comparative example. Therefore, according to this embodiment, the charge-voltage conversion coefficient is even larger than in this comparative example, and readout with an even higher S / N ratio is possible.

[0119] In this embodiment, a second transistor SWB is provided between every two adjacent second nodes Pb in the column direction, but the present invention is not necessarily limited to this. For example, a second transistor SWB may not be provided between a second node Pb arranged every r (r is an integer greater than or equal to 2) in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, and the gap between the second node Pb and the adjacent second node Pb may be always open. In this case, the smaller the value of r, the smaller the maximum value of the predetermined number in the second operating mode, and the degree of expansion of the dynamic range decreases, but the signal-to-noise ratio during high-sensitivity readout can be improved compared to the comparative example. Also, for example, a second transistor SWB may not be provided between a second node Pb arranged every s (s is an integer greater than or equal to 1) in the column direction and a second node Pb adjacent to the second node Pb on the lower side in the figure, and the gap between the second node Pb and the adjacent second node Pb may be electrically shorted. Furthermore, for example, second transistors SWB may be provided only between second nodes Pb arranged every u (u is an integer greater than or equal to 1) in the column direction and second nodes Pb adjacent to the second nodes Pb on the lower side in the figure, while second nodes Pb other than those arranged every u in the column direction may be electrically short-circuited between second nodes Pb adjacent to the second nodes Pb on the lower side in the figure.

[0120] In this embodiment, the capacitance value of the capacitor CD may be set to a value within a range of ±20% of the capacitance value of the capacitor CC, or may be set to a value within a range of ±10% of the capacitance value of the capacitor CC, for example, by providing an adjustment capacitor on the wiring 72. These points also apply to the second embodiment described later.

[0121] 6 to 10 are examples of operations in which the signal charge of the photodiode PD of each pixel PX is read out without being mixed with the signal charge of the photodiode PD of other pixels PX. However, in the present invention, the signal charge of the photodiode PD of each pixel PX may be read out by mixing it with the signal charge of the photodiode PD of other pixels PX of the same color.

[0122] For example, when the first transistors SWA(n-1), SWA(n), SWA(n+1) and the second transistors SWB(n), SWB(n+1) are turned on to interconnect the first nodes Pa(n-1), Pa(n), Pa(n+1), and TXA(n-1), TXA(n), TXA(n+1) are turned on simultaneously, the signal charges of the photodiodes PDA(n-1), PDA(n), PDA(n-1) of the three same-color pixels PXA(n-1), PXA(n), PXA(n-1) in a Bayer array or the like are averaged at the interconnected first nodes Pa(n-1), Pa(n), Pa(n+1), and the same-color three-pixel mixed readout function can be realized. At this time, by turning off the second transistors SWB(n-2), SWB(n+2) and minimizing the number of first or second transistors in the on state that are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) is minimized, and same-color three-pixel mixed readout can be performed with the highest signal-to-noise ratio. On the other hand, if one or more on-state transistors among the first transistors SWA(n-1), SWA(n), SWA(n+1) and second transistors SWB(n), SWB(n+1) are electrically connected to the first nodes Pa(n-1), Pa(n), Pa(n+1), in addition to the first transistors SWA(n-1), SWA(n), SWA(n+1), the charge-voltage conversion capacitance value at the connected first nodes Pa(n-1), Pa(n), Pa(n+1) will increase in accordance with the number of on-state transistors, and the dynamic range of same-color three-pixel mixed readout can be expanded.

[0123] [Second embodiment] Figure 13 is a circuit diagram showing the schematic configuration of a solid-state imaging element 84 of an electronic camera according to a second embodiment of the present invention, and corresponds to Figure 2. In Figure 13, elements that are the same as or correspond to elements in Figure 2 are given the same reference numerals, and redundant explanations will be omitted.

[0124] This embodiment differs from the first embodiment in that in the first embodiment, the photodiodes PDB and transfer transistors TXB are removed from each pixel block BL, and each pixel block BL is replaced with a pixel PXA. However, in the present embodiment, the column density of the photodiodes PDA is double that of the first embodiment, and is the same as the column density of the photodiodes PDA and PDB as a whole in the fourth embodiment. In the present embodiment, n indicates the row of the pixel block BL as well as the row of the pixel PXA.

[0125] In other words, in the first embodiment, each pixel block BL is composed of two pixels PX (PXA, PXB), whereas in this embodiment, each pixel block BL is composed of one pixel PX (PXA). And, in the first embodiment, the two pixels PX (PXA, PXB) belonging to the pixel block BL share a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL, whereas in this embodiment, each pixel PX (only PXA in this embodiment) has a set of the first node Pa, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL.

[0126] Basically, the description of the first embodiment is applicable to this embodiment by replacing pixel blocks BL with pixels PXA, and therefore a detailed description of this embodiment will be omitted here.

[0127] This embodiment also provides the same advantages as the first embodiment.

[0128] Although the embodiments and modifications of the present invention have been described above, the present invention is not limited to these. [Explanation of symbols]

[0129] 4. Solid-state imaging element BL pixel block PX pixels PD photodiode TXA,TXB transfer transistor Pa First Node Pb Second node AMP Amplifying transistor SWA first transistor SWB Second transistor RST Reset transistor (third transistor)

Claims

1. a first photoelectric conversion unit that converts light into electric charges; a second photoelectric conversion unit that converts light into electric charges; a first diffusion section to which the charges converted by the first photoelectric conversion section are transferred; a second diffusion section to which the charges converted by the second photoelectric conversion section are transferred; a first transistor electrically connected to the first diffusion region; a second transistor electrically connected to the second diffusion region, the second transistor being connected in series with the first transistor via a connection path for electrically connecting the first diffusion region and the second diffusion region; a third transistor electrically connected to a supply section to which a predetermined voltage is supplied, the third transistor being connected in series with the first transistor through a connection path for electrically connecting the first diffusion section and the supply section; An imaging element comprising:

2. 2. The imaging device according to claim 1, a gate portion of the third transistor is disposed at a position farther from the first diffusion portion than the gate portion of the first transistor in a connection path for electrically connecting the first diffusion portion and the supply portion; Image sensor.

3. 3. The imaging device according to claim 1, the gate portion of the first transistor and the gate portion of the third transistor are arranged in a connection path for electrically connecting the first diffusion portion and the supply portion, such that the gate portion of the first transistor and the gate portion of the third transistor are disposed in that order farther from the first diffusion portion; Image sensor.

4. 4. The imaging device according to claim 1, the third transistor is used to electrically connect the first transistor and the supply unit in a connection path for electrically connecting the first diffusion unit and the supply unit; Image sensor.

5. 5. The imaging device according to claim 1, the third transistor is used to electrically connect a connection path between the first transistor and the second transistor, which is part of a connection path for electrically connecting the first diffusion region and the second diffusion region, to the supply region; Image sensor.

6. 6. The imaging device according to claim 1, a drain portion of the third transistor electrically connected to the supply portion; Image sensor.

7. 7. The imaging device according to claim 1, a source portion of the third transistor is electrically connected to a drain portion of the first transistor; Image sensor.

8. The imaging device according to any one of claims 1 to 7, a first transfer transistor for transferring the charges converted by the first photoelectric conversion portion to the first diffusion portion; a gate width of the first transistor is smaller than a gate width of the first transfer transistor; Image sensor.

9. 9. The imaging device according to claim 8, a gate width of the third transistor is smaller than a gate width of the first transfer transistor; Image sensor.

10. 10. The imaging device according to claim 8, a second transfer transistor for transferring the charges converted by the second photoelectric conversion unit to the second diffusion unit; a gate width of the second transistor is smaller than a gate width of the second transfer transistor; Image sensor.

11. The imaging device according to claim 10, a gate width of the third transistor is smaller than a gate width of the second transfer transistor; Image sensor.

12. The imaging device according to any one of claims 1 to 11, An imaging element comprising an amplifying transistor having a gate portion electrically connected to the first diffusion portion.

13. The imaging device according to claim 12, a gate portion of the amplification transistor is disposed at a position farther from the first diffusion portion than a gate portion of the first transistor; Image sensor.

14. 14. The imaging device according to claim 12, a gate width of the first transistor is smaller than a gate width of the amplifying transistor; Image sensor.

15. The imaging device according to any one of claims 12 to 14, a gate length of the first transistor is smaller than a gate length of the amplifying transistor; Image sensor.

16. 14. The imaging device according to claim 12, a gate length of the first transistor is smaller than a gate length of the amplifying transistor; Image sensor.

17. The imaging device according to any one of claims 12 to 16, an imaging element comprising a selection transistor electrically connected to the amplification transistor;

18. 18. The imaging device according to claim 17, a gate width of the amplification transistor is larger than a gate width of the selection transistor; Image sensor.

19. 19. The imaging device according to claim 18, The gate length of the amplification transistor is greater than the gate length of the selection transistor. Image sensor.

20. 18. The imaging device according to claim 17, The gate length of the amplification transistor is greater than the gate length of the selection transistor. Image sensor.

21. The imaging device according to any one of claims 17 to 20, the amplification transistor is formed using at least a part of a diffusion portion that forms the selection transistor; Image sensor.

22. 22. The imaging device according to claim 17, the amplification transistor and the selection transistor are formed so as to share at least a part of one diffusion region; Image sensor.

23. 23. The imaging device according to claim 17, one of the drain portion of the amplification transistor and the source portion of the amplification transistor is formed using at least a part of a diffusion portion forming one of the drain portion of the selection transistor and the source portion of the selection transistor; Image sensor.

24. The imaging device according to any one of claims 17 to 23, one of the drain portion of the amplification transistor and the source portion of the amplification transistor forms one of the drain portion of the selection transistor and the source portion of the selection transistor; Image sensor.

25. 25. The imaging device according to claim 1, the first diffusion region and the first transistor are electrically connected via a wiring; Image sensor.

26. 26. The imaging device according to claim 1, the first transistor and the third transistor are electrically connected via a wiring; Image sensor.

27. 27. The imaging device according to claim 1, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit; Image sensor.

28. 28. The imaging device according to claim 27, the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the column direction; Image sensor.

29. 28. The imaging device according to claim 1, a third photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit; The first diffusion unit receives the charges converted by the third photoelectric conversion unit. Image sensor.

30. 30. The imaging device according to claim 29, the first diffusion unit receives charges from three or more photoelectric conversion units including the first photoelectric conversion unit and the third photoelectric conversion unit; Image sensor.

31. 31. The imaging device according to claim 1, a connection path for electrically connecting the first diffusion region and the second diffusion region includes three or more transistors including the first transistor and the second transistor; Image sensor.

32. 32. The imaging device according to claim 31, the three or more transistors arranged on a connection path for electrically connecting the first diffusion region and the second diffusion region are connected in series; Image sensor.

33. 33. The imaging device according to claim 1, a connection path for electrically connecting the first diffusion portion and the supply portion includes three or more transistors including the first transistor and the third transistor; Image sensor.

34. 34. The imaging device according to claim 33, the three or more transistors arranged on a connection path for electrically connecting the first diffusion region and the supply region are connected in series; Image sensor.

35. 35. The imaging device according to claim 1, the first transistor and the second transistor are arranged such that a length from the first diffusion region to the first transistor is shorter than a length from the first transistor to the second transistor in a connection path for electrically connecting the first diffusion region and the second diffusion region; Image sensor.

36. 36. The imaging device according to claim 35, the first transistor and the second transistor are arranged such that a length from the first diffusion portion to a gate portion of the first transistor is shorter than a length from the gate portion of the first transistor to a gate portion of the second transistor in a connection path for electrically connecting the first diffusion portion and the second diffusion portion; Image sensor.

37. 37. The imaging device according to claim 35 or 36, the first transistor and the second transistor are arranged such that a length from the second diffusion region to the second transistor is shorter than a length from the second transistor to the first transistor in a connection path for electrically connecting the first diffusion region and the second diffusion region; Image sensor.

38. 38. The imaging device according to claim 37, the first transistor and the second transistor are arranged such that a length from the second diffusion portion to a gate portion of the second transistor is shorter than a length from the gate portion of the second transistor to a gate portion of the first transistor in a connection path for electrically connecting the first diffusion portion and the second diffusion portion; Image sensor.

39. 39. The imaging device according to claim 35, the first transistor and the second transistor are electrically connected via a wiring; Image sensor.

40. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit controls the first transistor to be turned off and the second transistor to be turned off at the first timing, and controls the first transistor to be turned off and the second transistor to be turned off at the second timing; Image sensor.

41. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing; Image sensor.

42. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing; Image sensor.

43. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing and the first transistor to be off and the second transistor to be on at the second timing. Image sensor.

44. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing. Image sensor.

45. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing and the first transistor to be on and the second transistor to be on at the second timing. Image sensor.

46. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing. Image sensor.

47. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing, and a second mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing. Image sensor.

48. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off at the first timing and the second transistor to be off at the second timing, a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing and the first transistor to be off and the second transistor to be on at the second timing, and a third mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing and the first transistor to be on and the second transistor to be on at the second timing. Image sensor.

49. 40. The imaging device according to claim 1, a control unit that controls a first timing at which charges are transferred from the first photoelectric conversion unit to the first diffusion unit and a second timing at which charges are transferred from the second photoelectric conversion unit to the second diffusion unit to be different timings; the control unit executes one of a first mode in which the control unit controls the first transistor to be off and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be off at the second timing; a second mode in which the control unit controls the first transistor to be on and the second transistor to be off at the first timing, and controls the first transistor to be off and the second transistor to be on at the second timing; and a third mode in which the control unit controls the first transistor to be on and the second transistor to be on at the first timing, and controls the first transistor to be on and the second transistor to be on at the second timing. Image sensor.

50. An imaging device comprising the imaging element according to any one of claims 1 to 49.

51. 51. The imaging device of claim 50, An imaging device comprising an imaging control unit that controls the imaging element.

52. 52. The imaging device of claim 51, the imaging control unit controls an operation of the first transistor and an operation of the second transistor. Imaging device.

53. 53. The imaging device of claim 52, the imaging control unit controls the operation of the first transistor and the operation of the second transistor based on a set ISO sensitivity. Imaging device.

54. 54. The imaging device according to any one of claims 50 to 53, an imaging device including a driving unit for driving a photographing lens that emits light to the imaging element;

55. 55. The imaging device of claim 54, An imaging device comprising the above-mentioned photographic lens.

Images