Semiconductor storage device and method for manufacturing semiconductor storage device

Abstract

To suppress formation defects of a stepped part.SOLUTION: A semiconductor storage device of an embodiment comprises a laminate in which a plurality of first conductive layers and a plurality of first insulation layers are alternately stacked one layer at a time, and a stepped part provided in a part of the laminate, including a plurality of terrace surfaces which are formed of the plurality of first conductive layers and in which the plurality of first conductive layers and the plurality of first insulation layers are processed into a staircase shape, and a plurality of step surfaces connecting the terrace surfaces in a lamination direction of the laminate, and extending in a first direction crossing the lamination direction. At least a part of the layer thickness of the portions forming the terrace surfaces of the plurality of first conductive layers is formed greater than the thicknesses of other portions of the corresponding conductive layers. Among the plurality of first insulation layers, the lowermost first insulation layer of each of the plurality of step surfaces has a tapered portion extending downward toward the terrace surface connected on the lower side of the corresponding step surface. The width in the first direction on the lower surface of the tapered portion is greater than the thickness of the first insulation layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] For example, some 3D nonvolatile memories have a stack of alternating conductive layers and insulating layers, with staircase sections formed at the edges of the stack, where the stack is processed into a staircase shape to extend each conductive layer to the upper wiring.

[0003] As the thickness of the laminated body becomes thinner and the number of layers increases, the processing of the staircase portion becomes more difficult, and poor formation of the staircase portion can degrade the electrical characteristics of the semiconductor memory device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-170447 [Patent Document 2] Japanese Patent Application Laid-Open No. 2018-157169 [Patent Document 3] Special Publication No. 2020-529736 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor memory device capable of suppressing defective formation of a stepped portion, and a method for manufacturing the semiconductor memory device. [Means for solving the problem]

[0006] The semiconductor memory device of one embodiment comprises: a stack of multiple first conductive layers and multiple first insulating layers stacked alternately, and a staircase portion provided in a portion of the stack, the multiple first conductive layers and the multiple first insulating layers being processed into a staircase shape, the staircase portion having multiple terrace surfaces formed by the multiple first conductive layers and multiple step surfaces connecting the multiple terrace surfaces in the stacking direction of the stack, and extending in a first direction intersecting the stacking direction; wherein the thickness of at least a portion of the portion forming the terrace surfaces of the multiple first conductive layers is formed thicker than the thickness of other portions of the corresponding conductive layers; and among the multiple first insulating layers, the lowest first insulating layer of each of the multiple step surfaces has a tapered portion that widens toward the terrace surface connected below the corresponding step surface, and the width in the first direction at the lower surface of the tapered portion is greater than the thickness of the first insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing a detailed configuration example of the semiconductor memory device according to the first embodiment. [Figure 3] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 7] 10A to 10C are diagrams illustrating a part of a procedure of a manufacturing method of a semiconductor memory device according to a comparative example. [Figure 8] FIG. 10 is a diagram showing a detailed configuration example of a semiconductor memory device according to a second embodiment. [Figure 9] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] [Embodiment 1] (Configuration example of semiconductor memory device) FIG. 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to a first embodiment. FIG. 1(a) is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1. However, hatching is omitted in FIG. 1(a) to make the drawing easier to read. Also, some select gate lines and upper layer wiring are omitted in FIG. 1(a).

[0010] In this specification, both the X direction and the Y direction are directions that are parallel to the plane direction of the word lines WL, which will be described later, and are perpendicular to each other. The electrical lead-out direction of the word lines WL, which will be described later, is sometimes referred to as the first direction, and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the second direction, and this second direction is the direction along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing errors, the first direction and the second direction are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1, the semiconductor memory device 1 includes a peripheral circuit CUA, a memory region MR, a through-contact region TP, and a staircase region SR on a substrate SB.

[0012] The substrate SB is a semiconductor substrate such as a silicon substrate. A peripheral circuit CUA including transistors TS and wiring is arranged on the substrate SB. The peripheral circuit CUA contributes to the operation of the memory cells, which will be described later.

[0013] The peripheral circuit CUA is covered with an insulating layer 50. A source line SL is arranged on the insulating layer 50. A plurality of word lines WL are stacked on the source line SL. The plurality of word lines WL is covered with an insulating layer 49. The insulating layer 49 also extends around the plurality of word lines WL.

[0014] A plurality of plate-shaped contacts LI are arranged on the plurality of word lines WL, penetrating the word lines WL in the stacking direction and extending in the X direction, so that the plurality of word lines WL are divided in the Y direction by the plurality of plate-shaped contacts LI.

[0015] A plurality of memory regions MR, staircase regions SR, and through contact regions TP are arranged side by side in the X direction between the plurality of plate-like contacts LI. The plurality of memory regions MR are arranged spaced apart from each other in the X direction, with the staircase regions SR and the through contact regions TP sandwiched therebetween.

[0016] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL in the stacking direction. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0017] The staircase region SR includes a plurality of staircase portions SP formed by digging down the word lines WL in a mortar-like shape in the stacking direction. In one staircase region SR, for example, two staircase portions SP are arranged side by side in the Y direction with one plate-like contact LI interposed therebetween.

[0018] The stepped portion SP forms one side of a mortar-shaped bowl that descends in a stepped manner from both sides in the X direction and one side in the Y direction toward the bottom surface, but the other side in the Y direction of the stepped portion SP is open toward the side surface of the plate-like contact LI.

[0019] Each step of the staircase section SP is composed of word lines WL of each layer. The word lines WL of each layer maintain electrical continuity on both sides of the staircase region SR in the X direction via the staircase portion on one side of the staircase section SP in the Y direction. Contacts CC are arranged on the terrace surface of each step of the staircase section SP, connecting the word lines WL of each layer to the upper layer wiring MX.

[0020] This allows the word lines WL, which are stacked in multiple layers, to be individually drawn out. From these contacts CC, write voltages, read voltages, etc. are applied to memory cells in the memory regions MR on both sides in the X direction via word lines WL located at the same height as the memory cells.

[0021] A through contact region TP is arranged on one side of the staircase region SR in the X direction. Through contacts C4 that penetrate multiple word lines WL are arranged in the through contact region TP. The through contacts C4 connect the peripheral circuit CUA arranged on the substrate SB below with the upper layer wiring MX that is connected to the contacts CC of the staircase section SP. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CUA via the through contacts C4 and the upper layer wiring MX.

[0022] 2A and 2B are diagrams illustrating a detailed configuration example of the semiconductor memory device 1 according to the first embodiment. FIG. 2A is a cross-sectional view of the staircase region SR along the X direction. FIG. 2B is a partially enlarged view illustrating a cross section of a staircase portion SP disposed in the staircase region SR. However, in FIG. 2A, the structure below the insulating layer 50, including the substrate SB and the peripheral circuit CUA, etc., is omitted.

[0023] As shown in FIG. 2(a), in the staircase region SR, a source line SL is disposed on an insulating layer 50, and a stacked body LM is disposed on the source line SL. The stacked body LM has a structure in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked one by one. Each of the plurality of word lines WL is, for example, a tungsten layer or a molybdenum layer. These word lines WL are an example of a first conductive layer. Each of the plurality of insulating layers OL is, for example, a silicon oxide layer.

[0024] A staircase portion SP extending in the X direction is arranged in the laminated body LM. In the staircase portion SP, a plurality of word lines WL and a plurality of insulating layers OL are processed in a staircase shape. The entire staircase region SR including the staircase portion SP is covered with an insulating layer 51, which is, for example, a silicon oxide layer. Insulating layers 52 to 54 are formed on the upper surface of the insulating layer 51. The insulating layers 52 to 54, together with the insulating layer 51, each constitute a part of the insulating layer 49 in FIG. 1.

[0025] Each step of the staircase section SP is composed of one or more pairs of word lines WL and insulating layers OL. In each step, the top layer is the word lines WL and the bottom layer is the insulating layer OL. In the example of Figure 2, each step of the staircase section SP is composed of one pair of word lines WL and insulating layers OL.

[0026] The upper surfaces of the word lines WL constituting each step of the staircase portion SP are called terrace surfaces TR. Also, the end surfaces in the X direction of the word lines WL and insulating layers OL constituting each step of the staircase portion SP are called step surfaces SS. That is, the staircase portion SP has multiple terrace surfaces TR and multiple step surfaces SS.

[0027] Each of the plurality of step surfaces SS connects the plurality of terrace surfaces TR in the stacking direction. Specifically, each of the plurality of step surfaces SS connects to an upper terrace surface TR at its upper end and connects to a lower terrace surface TR at its lower end. The end faces of the lower insulating layer OL that constitutes the step surfaces SS have tapered portions TPa that widen toward the terrace surfaces TR.

[0028] The layer thickness of the portion of the word line WL that forms the terrace surface TR is formed to be thicker than the layer thickness of the other portion of the corresponding word line WL.

[0029] In this specification, the direction in which the terrace surface TR of each step of the staircase portion SP faces is defined as the upward direction.

[0030] Each contact CC penetrates the insulating layers 52 and 51 and reaches the word line WL at each step of the staircase portion SP. The contact CC includes an insulating layer 56 covering the sidewall of the contact CC and a conductive layer 22 filling the inside of the insulating layer 56. The lower end of the conductive layer 22 is connected to the terrace surface TR of the corresponding word line WL. The upper end of the conductive layer 22 is connected to an upper-layer wiring MX arranged in the insulating layer 54 via a plug V0 extending through the insulating layer 53.

[0031] As described above, the semiconductor memory device 1 includes a peripheral circuit CUA (see FIG. 1), and the upper layer wiring MX is electrically connected to the peripheral circuit CUA. The peripheral circuit CUA includes a plurality of transistors TS, which contribute to the electrical operation of the memory cells. Data is written to and read from the memory cells by applying a voltage to the memory cells via the peripheral circuit CUA, the through contact C4, the upper layer wiring MX, the contact CC, and the word line WL.

[0032] The specific positional relationship between the terrace surface TR, the step surface SS, and the tapered portion TPa will be described with reference to FIG. 2(b).

[0033] 2(b) shows, for example, an insulating layer OLm, a word line WLm, an insulating layer OLn, and a word line WLn stacked one layer at a time in this order from the bottom up. The thickness To of the insulating layers OLm and OLn is determined based on the distance between the word lines WL stacked above and below that will not cause problems in device operation due to their mutual electrical influence. In other words, if the distance between the word lines WL is equal to or greater than the thickness To, the word lines WL will not cause problems in device operation due to their mutual electrical influence.

[0034] A terrace surface TRm is formed on the word line WLm, and a terrace surface TRn is formed on the word line WLn. The step surface SSn is connected to the terrace surface TRn above and to the terrace surface TRm below. The insulating layer OLn below the step surface SSn has a tapered portion TPan that widens toward the terrace surface TRm.

[0035] The terrace surface TRm is a portion of the upper surface of the word line WLm that protrudes in the X direction from a position SF that vertically overlaps with the X-direction end SEn of the word line WLn, which is processed into a stepped shape. The terrace surface TRm has a first portion Pam where the word line WLm is formed thick, and a second portion Pbm where the word line WLm is formed thinner than the first portion Pam.

[0036] The first portion Pam is a region of the terrace surface TRm on the end side of the terrace surface TRm in the X direction. The layer thickness Twa of the word line WLm in the first portion Pam is thicker than the layer thickness Twb in the second portion Pbm. A contact CC is connected to the first portion Pam. On the other hand, the second portion Pbm is a region of the terrace surface TRm opposite the end side of the terrace surface TRm in the X direction. The second portion Pbm is a region from a position SG where the first portion Pam overlaps with the end face SNm on the step surface SSn side, as viewed from above, to a position SF. Therefore, the width Wa of the second portion Pbm in the X direction corresponds to the distance between the position SF and the end face SNm of the word line WLm.

[0037] The tapered portion TPan extends along the second portion Pbm, and the end TPas of the tapered portion TPan on the terrace surface TRm side reaches the first portion Pam. That is, the first portion Pam covers the end TPas of the tapered portion TPan on the terrace surface TRm side. As a result, the second portion Pbm is covered by the tapered portion TPan. In this case, the width Wb of the lower surface of the tapered portion TPan in the X direction is slightly larger than the width Wa of the second portion Pbm in the X direction.

[0038] Furthermore, the width Wb in the X direction at the bottom surface of the tapered portion TPan is formed to be equal to or greater than the thickness To of the insulating layer OLn. That is, the distance between the end SEn of the word line WLn and the end surface SNm of the word line WLm is ensured to be equal to or greater than the thickness To. As a result, the word lines WLn and WLm are sufficiently spaced apart in the X direction, preventing problems in device operation due to electrical influence between them.

[0039] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 of embodiment 1 will be described with reference to Figures 3 to 7. Figures 3 to 7 are diagrams sequentially illustrating some of the steps of the method for manufacturing the semiconductor memory device 1 according to embodiment 1. It is assumed that, before the processes shown in Figures 3 to 7, a peripheral circuit CUA has been formed on the substrate SB, and an insulating layer 50 covering the peripheral circuit CUA has already been formed.

[0040] 3 to 6 show how the staircase portion SP is formed in the region that will later become the staircase region SR. Figures 3 to 6 are cross-sectional views along the X direction of the region that will later become the staircase region SR.

[0041] As shown in Fig. 3(a), a source line SL is formed on an insulating layer 50. A laminate LMs is formed on the source line SL, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The bottom layer of the laminate LMs is the insulating layer OL, and the top layer is the insulating layer NL.

[0042] The insulating layers NL are, for example, silicon nitride layers. The insulating layers NL function as sacrificial layers that will later be replaced with word lines WL. These insulating layers NL are an example of a first insulating layer. The insulating layers OL are, for example, silicon oxide layers. These insulating layers OL are an example of a second insulating layer.

[0043] A mask pattern 72 is formed on the laminate LMs to cover a portion of the laminate LMs. The mask pattern 72 is, for example, a carbon-containing layer. Using the mask pattern 72, the exposed portions of the insulating layers NL and OL are removed one by one by etching. Next, the ends of the mask pattern 72 are recessed by a process using oxygen plasma or the like to newly expose the top surface of the laminate LMs, and the insulating layers NL and OL are further removed one by one by etching.

[0044] Such slimming of the mask pattern 72 and etching of the insulating layers NL and OL of the laminated body LMs are repeated multiple times, thereby forming a staircase portion SPa as a first staircase portion as shown in FIG.

[0045] The staircase portion SPa extends in the X direction and has a staircase shape formed by processing the insulating layers NL and OL. The staircase portion SPa has a terrace surface TRa formed by the insulating layers NL and a plurality of step surfaces SSa. The step surfaces SSa connect the terrace surfaces TRa to one another in the stacking direction of the laminated body LMs.

[0046] The terrace surface TRa is the upper surface of the insulating layer NL that constitutes each step of the staircase portion SPa. The step surface SSa is the end surface in the X direction of the insulating layer NL and the insulating layer OL that constitute each step of the staircase portion SPa. The upper layer side of the step surface SSa is the insulating layer NL, and the lower layer side is the insulating layer OL. The step surface SSa is connected to the terrace surface TRa on the upper side of the insulating layer NL and on the lower side of the insulating layer OL. The terrace surface TRa is an example of a first terrace surface. The step surface SSa is also an example of a first step surface.

[0047] Furthermore, when forming the staircase portion SPa, the insulating layer OL below the step surface SSa is processed to have a tapered portion TPa that widens downward toward the terrace surface TRa that connects to the step surface SSa. As a result, the portion of the terrace surface TRa near the step surface SSa is covered by the tapered portion TPa. Furthermore, when processing the tapered portion TPa, the width Wb of the tapered portion TPa in the X direction at the bottom surface is processed to be larger than the layer thickness To of the insulating layer OL.

[0048] After the stepped portion SPa is formed, the mask pattern 72 is removed by ashing using oxygen plasma or the like.

[0049] 4(a), an insulating layer NLa is formed to cover the entire staircase portion SPa so as to follow the shape of the staircase portion SPa, thereby forming a terrace surface TRb above the terrace surface TRa.

[0050] The insulating layer NLa has the same main component as the insulating layer NL. Specifically, the insulating layer NLa is, for example, a silicon nitride layer. The insulating layer NLa is an example of a third insulating layer.

[0051] 4(b), the insulating layer NLa covering the step portion SPa is etched back. At this time, by using anisotropic etching such as RIE (Reactive Ion Etching), the insulating layer NLa covering the step surface SSa can be removed while leaving the insulating layer NLa constituting the terrace surface TRb.

[0052] In addition, the tapered portion TPa formed below the step surface SSa functions as an etching stopper layer when removing the insulating layer NLa covering the step surface SSa. That is, downward etching for removing the insulating layer NLa ends when the tapered portion TPa is reached. This is because the tapered portion TPa, which is a silicon oxide layer or the like, has a certain etching selectivity with respect to the insulating layer NLa, which is a silicon nitride layer or the like. In this way, the tapered portion TPa functions as an etching stopper layer, thereby preventing the terrace surface TRa connected below the step surface SSa from being etched.

[0053] This forms a staircase portion SPc which will later become the staircase portion SP.

[0054] The staircase portion SPc has a plurality of terrace surfaces TRb and a plurality of step surfaces SSc, which are end surfaces in the X direction of the insulating layers OL, NL, and NLa.

[0055] 5(a), an insulating layer 51 is stacked to cover the stepped portion SPc and reach the height position of the upper surface of the unprocessed laminated body LMs. Also, an insulating layer 52 is formed to cover the upper surface of the unprocessed laminated body LMs and the insulating layer 51.

[0056] Although not shown, pillars PL are formed in the laminate LMs by a predetermined method. Note that the pillars PL may be formed before the formation of the staircase region SR.

[0057] The insulating layers NL and NLa of the laminate LMs are removed using an etching solution, and the removed portions are filled with a metal such as a tungsten layer. This results in the word lines WL as shown in Figure 5(b). This process of replacing the insulating layers with word lines WL is sometimes called a replacement process.

[0058] By the above processing, a laminated body LM is formed in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked one by one. Then, a staircase portion SP having a terrace surface TR and a step surface SS is formed in the laminated body LM.

[0059] In the stepped portion SP, the layer thickness of the portion forming the terrace surface TR of the word line WL is made thicker than the layer thickness of the other portion of the corresponding word line WL because the insulating layer NLa is stacked on the terrace surface TRa of the insulating layer NL, and then the insulating layer NL and the insulating layer NLa are replaced with the word line WL.

[0060] Next, the state in which the contact CC is formed is shown in Fig. 6. Like Figs. 3 to 5, Fig. 6 shows a cross section along the X direction of a region including the stepped portion SP.

[0061] 6(a), a plurality of contact holes HLc are formed so as to penetrate the insulating layers 52 and 51 and reach the individual terrace surfaces TR. The contact holes HLc are configured to become contacts CC that will later be connected to the word lines WL.

[0062] These contact holes HLc have different depths, and the contact holes HLc that reach the word lines WL in the upper layers of the laminate LM undergo more excessive over-etching of the word lines WL. However, because the layer thickness of the portions of the word lines WL that form the terrace surfaces TR is formed thicker, even when the contact holes HLc with the deepest depth are processed under etching conditions that allow processing, it is possible to prevent the lower ends of the multiple contact holes HLc from penetrating the terrace surfaces TR.

[0063] 6(b), an insulating layer 56 is formed to cover the sidewalls of the contact holes HLc. A conductive layer 22 such as a tungsten layer is filled into the gaps of the contact holes HLc remaining inside the insulating layer 56. In this way, contacts CC are formed.

[0064] Also, although not shown, after the contact CC is formed, insulating layers 53 and 54 are formed on insulating layer 52, and are connected to conductive layer 22 of contact CC, and a plug V0 extending through insulating layer 53, and an upper layer wiring MX connected to plug V0 and disposed in insulating layer 54 are formed.

[0065] Furthermore, although not shown, after or prior to the formation of the contacts CC, through contacts C4 are formed in the through contact regions TP. Furthermore, plate-like contacts LI are formed before or at the same time as the formation of the through contacts C4. Then, upper layer wiring MX is connected to the through contacts C4, the plate-like contacts LI, and the contacts CC, and bit lines and the like (not shown) are connected to the pillars PL.

[0066] In this manner, the semiconductor memory device 1 of the first embodiment is manufactured.

[0067] (Comparative Example) Next, a method for manufacturing a semiconductor memory device according to a comparative example will be described with reference to Fig. 7. Fig. 7 is a diagram illustrating a part of the procedure for the method for manufacturing a semiconductor memory device according to the comparative example.

[0068] Fig. 7(a) is a cross-sectional view showing a staircase portion SPbx on which an insulating layer NLb is formed in a manufacturing method of a semiconductor memory device according to a comparative example. Fig. 7(b) is a cross-sectional view showing an example of a state in which the insulating layer NLb on the step surface SSbx has been removed, and Fig. 7(c) is a cross-sectional view showing another example of a state in which the insulating layer NLb on the step surface SSbx has been removed. That is, Fig. 7(a) is a view corresponding to Fig. 4(a) of the first embodiment, and Figs. 7(b) and 7(c) are views corresponding to Fig. 4(b) of the first embodiment.

[0069] 7(a), in the manufacturing method of the semiconductor memory device of the comparative example, no tapered portion is formed on the staircase portion SPbx. After forming an insulating layer NLb on such a staircase portion SPbx, the insulating layer NLb is mainly removed from the step surface SSbx by a process such as RIE.

[0070] 7(b), a recess TC may be formed in a part of the terrace surface TRax. This is because the insulating layer NLb to be removed and the insulating layer NL forming the terrace surface TRax are both silicon nitride layers or the like, and therefore, even after the insulating layer NLb is removed, the etching in the downward direction does not finish and reaches the terrace surface TRax.

[0071] If such a recess TC is formed on the terrace surface TRax, it may cause a defective formation of the word line WL during a subsequent replacement process, which may, for example, inhibit the application of voltage to the memory cell via the word line WL, thereby deteriorating the electrical characteristics of the semiconductor memory device.

[0072] On the other hand, in order to avoid the formation of the recess TC, it is possible to shorten the processing time of the RIE, etc. In this case, there is a risk that residues Rd of the insulating layer NLb will be generated on the step surface SSax, as shown in FIG.

[0073] If such residue Rd exists on the step surface SSax, when a replacement process is performed later, the residue Rd will be replaced with a tungsten layer, etc. Such a tungsten layer, etc., spanning multiple word lines may become a leak path, causing a short circuit between multiple word lines.

[0074] (Overview) According to the semiconductor memory device 1 of embodiment 1, in a staircase portion SP provided in a part of a laminate LM in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked one layer at a time, the layer thickness of the portion forming the terrace surface TR of each of the plurality of word lines WL is made thicker than the layer thickness of the other portion of the corresponding word line WL.

[0075] This makes it possible to prevent the contacts CC from penetrating the terrace surface TR when the contacts CC are formed, thereby preventing the electrical characteristics of the semiconductor memory device 1 from deteriorating.

[0076] The insulating layer OL, which is the lowest layer of the plurality of step surfaces SSa of the staircase portion SP, has a tapered portion TPa that widens toward the terrace surface TRa connected to the corresponding step surface SSa on the lower side.

[0077] As a result, the tapered portion TPa protects the terrace surface TRa, and thus when the insulating layer NLa covering the step surface SSa is etched away, it is possible to prevent the formation of recesses TC on the terrace surface TRa. As a result, when a replacement process is performed later, it is possible to prevent the formation of defective word lines WL, and therefore to prevent the deterioration of the electrical characteristics of the semiconductor memory device 1.

[0078] Each of the plurality of terrace surfaces TR has a first portion Pa in which the word line WL has a thick layer thickness, and a second portion Pb in the vicinity of the boundary with the corresponding step surface SS in which the layer thickness is thinner than the first portion Pa, and the first portion Pa covers the end of the tapered portion TPa on the terrace surface TR side.

[0079] As a result, the second portion Pb is entirely covered by the tapered portion Tpa, which more reliably prevents the formation of the recess TC on the terrace surface TRa, thereby more reliably suppressing the deterioration of the electrical characteristics of the semiconductor memory device 1.

[0080] Furthermore, the width Wb of the lower surface of the tapered portion TPa in the X direction is greater than the thickness To of the insulating layer OL.

[0081] This allows the distance between the first portions Pa of the plurality of terrace surfaces TR to be equal to or greater than the distance at which the step surfaces SS of the upper word lines WL and the thickened portions of the lower word lines WL do not electrically affect each other, thereby preventing deterioration of the electrical characteristics of the semiconductor memory device 1.

[0082] [Embodiment 2] (Configuration example of semiconductor memory device) A semiconductor memory device 2 of embodiment 2 will be described with reference to Figure 8. In the semiconductor memory device 2 of embodiment 2, the shape of the tapered portion of the insulating layer OL is different from that of the above-mentioned embodiment 1. Note that, in the following, the same components as those of the above-mentioned embodiment 1 will be denoted by the same reference numerals, and their description may be omitted.

[0083] Fig. 8 is a diagram showing a detailed configuration example of the semiconductor memory device 2 according to the second embodiment. Fig. 8 is a diagram corresponding to Fig. 2(b) of the first embodiment.

[0084] FIG. 8 shows the stack of the second embodiment, in which an insulating layer OLp, a word line WLp, an insulating layer OLq, and a word line WLq are stacked in this order from the bottom.

[0085] A terrace surface TRp is formed on the word line WLp, and a terrace surface TRq is formed on the word line WLq. The step surface SSq is connected to the terrace surface TRq above and to the terrace surface TRp below.

[0086] The insulating layer OLq below the step surface SSq has a tapered portion TPb that widens toward the terrace surface TRp, and extends to a position corresponding to the word line WLq above the step surface SSq.

[0087] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 2 according to the second embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 2 according to the second embodiment. Note that, in the following, the same components as those in the above-described embodiments will be denoted by the same reference numerals, and their description may be omitted.

[0088] Before the process shown in FIG. 9, it is assumed that the peripheral circuit CUA has been formed on the substrate SB, and the insulating layer 50 covering the peripheral circuit CUA has already been formed.

[0089] 9(a), a staircase portion SPd is formed in the same manner as in the above-described embodiment 1. The staircase portion SPd has a staircase shape in which a plurality of insulating layers NL and a plurality of insulating layers OL extend in the X direction. Each step of the staircase portion SPd is composed of one set of insulating layers NL and OL.

[0090] The staircase portion SPd has a terrace surface TRd formed by a plurality of insulating layers OL and a plurality of step surfaces SSd. The step surfaces SSd connect the plurality of terrace surfaces TRd to one another in the stacking direction of the laminated body LMt. The staircase portion SPd is an example of a second staircase portion.

[0091] The terrace surface TRd is the upper surface of the insulating layer OL that constitutes each step of the staircase portion SPd. The step surface SSd is the end surface in the X direction of the insulating layer NL and the insulating layer OL that constitute each step of the staircase portion SPd. The upper layer side of the step surface SSd is the insulating layer OL, and the lower layer side is the insulating layer NL. The terrace surface TRd is an example of a second terrace surface. The step surface SSd is an example of a second step surface.

[0092] As shown in FIG. 9(a), an insulating layer OLa is formed as a fourth insulating layer that covers the entire staircase portion SPd so as to conform to the shape of the staircase portion SPd. The insulating layer OLa has the same main component as the insulating layer OL. Specifically, the insulating layer OLa is, for example, a silicon oxide layer. The insulating layer OLa is an example of a fourth insulating layer.

[0093] As shown in FIG. 9(b), the portions of the insulating layer OLa formed on the terrace surfaces TRd and the portions of the insulating layers OL that form the terrace surfaces TRd are etched. This exposes the terrace surfaces TRe formed by the insulating layers NL. In this way, a staircase portion SPe is formed as a first staircase portion.

[0094] The staircase portion SPe has a plurality of terrace surfaces TRe formed by a plurality of insulating layers NL and a plurality of step surfaces SSe. The plurality of terrace surfaces TRe corresponds to the plurality of terrace surfaces TRa in the first embodiment.

[0095] The terrace surface TRe is the upper surface of the insulating layer NL that constitutes each step of the staircase portion SPe. The step surface SSe is the end surface in the X direction of the insulating layer NL and the insulating layer OL that constitute each step of the staircase portion SPe. The upper layer side of the step surface SSe is the insulating layer NL, and the lower layer side is the insulating layer OL. The step surface SSe is connected to the terrace surface TRe on the upper side of the insulating layer NL and the lower side of the insulating layer OL. The terrace surface TRe is an example of a first terrace surface. The step surface SSe is also an example of a first step surface.

[0096] When forming the staircase portion SPe, the lower insulating layer OL is processed to have a tapered portion TPb that widens toward the terrace surface TRe connected to the lower side of the step surface SSe, so that the portion of the terrace surface TRe near the step surface SSe is covered by the tapered portion TPb.

[0097] When processing the tapered portion TPb, the insulating layer OLa covering the step surface SSd is processed to have a slope continuous with the tapered portion TPb and a tapered portion TPc extending from a position corresponding to the insulating layer NL above the step surface SSe toward the terrace surface TRe. The tapered portion TPc is made of the insulating layer OLa and therefore has the same main component as the insulating layer OL.

[0098] In this way, the tapered portion TPc, which has the same main component as the insulating layer OL, is stacked above the tapered portion TPb, which is made up of the insulating layer OL, thereby increasing the overall height of the tapered portion. This improves the tapered portion's function as an etching stopper layer when the insulating layer NLa is subsequently removed. Furthermore, the increased height of the tapered portion as a whole makes it possible to make the slope of the tapered shape gentler. This allows a wider area of ​​the terrace surface TRe to be covered.

[0099] Although not shown, an insulating layer NLa is deposited on the terrace surface TRe of the stepped portion Spe formed as described above. Thereafter, similar to the first embodiment, insulating layers 51 and 52 are formed, a replacement process is performed, and the insulating layers are replaced with word lines WL. Then, contacts CC, plugs V0, upper layer wiring MX, through contacts C4, etc. are formed, thereby manufacturing the semiconductor memory device of the second embodiment.

[0100] In the method for manufacturing the semiconductor memory device according to the second embodiment, the upper portion of the tapered portion TPb is described as extending to a position corresponding to the upper word line WL, but this is not limited thereto. As long as the tapered portion TPb can function independently as an etching stopper layer for the terrace surface TRe, it does not necessarily have to extend to a position corresponding to the upper word line WL.

[0101] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0102] 1, 2 semiconductor memory device, CC contact, LM, LMs, LMt stack, NL, NLa, OL, OLa insulating layer, SP, SPa, SPc, SPd, SPe staircase portion, SR staircase region, SS, SSa, SSc, SSd, SSe step surface, TPa, TPb, TPc tapered portion, TR, TRa, TRb, TRd, TRe terrace surface, WL word line.

Claims

1. a laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one; a staircase portion provided in a part of the laminate, the plurality of first conductive layers and the plurality of first insulating layers being processed in a staircase shape, the staircase portion having a plurality of terrace surfaces formed by the plurality of first conductive layers and a plurality of step surfaces connecting the plurality of terrace surfaces to each other in a stacking direction of the laminate, the staircase portion extending in a first direction intersecting the stacking direction; Equipped with a thickness of at least a portion of each of the plurality of first conductive layers forming a terrace surface is formed to be thicker than a thickness of the other portion of the corresponding conductive layer; Among the plurality of first insulating layers, a first insulating layer at the bottom of each of the plurality of step surfaces has a tapered portion that widens toward a terrace surface connected to the corresponding step surface below, a width in the first direction of the lower surface of the tapered portion is greater than a thickness of the first insulating layer; Semiconductor memory device.

2. Each of the plurality of terrace surfaces is a first portion in which the first conductive layer is formed to have a large thickness; a second portion in the vicinity of a boundary with a corresponding step surface, the second portion having a thickness thinner than that of the first portion; the first portion covers an end of the tapered portion that extends toward the terrace surface; 2. The semiconductor memory device according to claim 1.

3. forming a laminate in which a plurality of first insulating layers and a plurality of second insulating layers are alternately stacked one by one; a first staircase portion is formed in a part of the laminate by processing the plurality of first insulating layers and the plurality of second insulating layers in a stepped shape, the first staircase portion having a plurality of first terrace surfaces formed by the plurality of first insulating layers and a plurality of first step surfaces connecting the plurality of first terrace surfaces in a stacking direction of the laminate, the first staircase portion extending in a first direction intersecting the stacking direction; When forming the first step portion, Among the plurality of second insulating layers, the second insulating layer at the bottom of each of the plurality of first step surfaces is processed so as to have a tapered portion that widens toward a first terrace surface that is connected to the corresponding first step surface below, and so that the width of the tapered portion in the first direction at the bottom surface is larger than the thickness of the first insulating layer; the first step portion is entirely covered with a third insulating layer having a main component in common with the first insulating layer; removing portions of the third insulating layer that cover the plurality of first step surfaces; A method for manufacturing a semiconductor memory device.

4. When forming the first step portion, a second staircase portion extending in the first direction is formed in a part of the laminate by processing the plurality of first insulating layers and the plurality of second insulating layers in a stepped shape, the second staircase portion having a plurality of second terrace surfaces formed by the plurality of second insulating layers and a plurality of second step surfaces connecting the plurality of second terrace surfaces to each other in the stacking direction of the laminate; the second step portion is entirely covered with a fourth insulating layer having a main component in common with the second insulating layer; etching the portions of the fourth insulating layer formed on the plurality of second terrace surfaces and the portions of the plurality of second insulating layers forming the plurality of second terrace surfaces until the plurality of first terrace surfaces are exposed, thereby processing the tapered portions into the tapered portions including the fourth insulating layer and the second insulating layer that are the lowest second insulating layers of each of the plurality of first step surfaces; 4. The method for manufacturing a semiconductor memory device according to claim 3.

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