Semiconductor storage device

Abstract

To more reliably connect a high-density pillar to a bit line.SOLUTION: A semiconductor storage device of an embodiment comprises: a laminate in which a plurality of conductive layers are stacked spaced apart from each other; a plurality of pillars, each having a semiconductor layer extending in a first direction of the laminate, which is the lamination direction of the laminate, and arranged in (2n+1) columns (where n is an integer equal to or greater than 1) in the second direction crossing the first direction; a plurality of first plugs respectively arranged at the upper ends of the plurality of pillars and electrically connected to the semiconductor layers; and a plurality of bit lines extending in the second direction above the plurality of pillars and electrically connected to corresponding ones of the plurality of first plugs. The plurality of first plugs have a longitudinal direction crossing the second direction when viewed from the first direction.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] As semiconductor memory devices such as 3D non-volatile memories become increasingly highly integrated, the pillars on which memory cells are formed are becoming denser, and how to reliably connect the bit lines corresponding to each pillar is becoming an issue. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0240547 [Patent Document 2] US Patent Application Publication No. 2022 / 0020681 [Patent Document 3] Japanese Patent Publication No. 2022-037583 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device that can more reliably connect high-density pillars to bit lines. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment comprises a stack of multiple conductive layers stacked at a distance from each other, multiple pillars each having a semiconductor layer extending within the stack in a first direction which is the stacking direction of the stack, and arranged in (2n+1) columns (n ​​is an integer greater than or equal to 1) in a second direction intersecting the first direction, multiple first plugs each disposed at an upper end of the multiple pillars and electrically connected to the semiconductor layer, and multiple bit lines extending in the second direction above the multiple pillars and each electrically connected to a corresponding one of the multiple first plugs, wherein the multiple first plugs have a longitudinal direction in a direction intersecting the second direction when viewed from the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 3] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 4] 1A and 1B are schematic diagrams showing an example of the layout of various components in a memory area of ​​a semiconductor memory device according to an embodiment; [Figure 5] 2 is a flow diagram illustrating a part of the procedure of a method for manufacturing the semiconductor memory device 1 according to the embodiment. [Figure 6] FIG. 1 is a schematic diagram showing an example of the layout of various components in a memory area of ​​a semiconductor memory device according to a comparative example. [Figure 7] 10A and 10B are schematic diagrams showing an example of the layout of various components in a memory area of ​​a semiconductor memory device according to a modified example of the embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Configuration example of semiconductor memory device) 1 is a block diagram of a semiconductor memory device 1 according to an embodiment. As shown in FIG. 1, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0009] The input / output circuit 310 controls input and output of a signal DQ to and from an external device such as a memory controller (not shown) that controls the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0010] The input circuit transmits data DAT such as write data WD received from an external device to the data register 540 , transmits an address ADD to the address register 340 , and transmits a command CMD to the command register 350 .

[0011] The output circuit transmits the status information STS received from the status register 330, the data DAT such as the read data RD received from the data register 540, and the address ADD received from the address register 340 to an external device.

[0012] The logic control circuit 320 receives, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from an external device, and controls the input / output circuit 310 and the sequencer 360 in response to the received signals.

[0013] The status register 330 temporarily holds status information STS for, for example, data write, read, and erase operations, and notifies an external device whether the operation has ended normally.

[0014] The address register 340 temporarily holds an address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers a row address RA to the row decoder 520 and a column address CA to the column decoder 550.

[0015] The command register 350 temporarily stores a command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360 .

[0016] The sequencer 360 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 in accordance with the command CMD held in the command register 350, and executes a write operation, a read operation, an erase operation, and the like.

[0017] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360 .

[0018] The voltage generation circuit 380 generates voltages required for write, read, and erase operations under the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0019] The memory cell array 510 includes a plurality of blocks BLK (BLK0 to BLKn), where n is an integer equal to or greater than 2. A block BLK is a set of a plurality of memory cells associated with bit lines and word lines, and serves as, for example, a unit for erasing data. The memory cells are configured as, for example, transistors, and hold non-volatile data.

[0020] By including such memory cells, the semiconductor memory device 1 of the embodiment is configured as, for example, a NAND type nonvolatile memory.

[0021] The row decoder 520 decodes the row address RA, selects one of the blocks BLK based on the decoding result, and applies a required voltage to the block BLK.

[0022] During a read operation, the sense amplifier module 530 senses data read from the memory cell array 510. The sense amplifier module 530 also transmits read data RD to the data register 540. During a write operation, the sense amplifier module 530 transmits write data WD to the memory cell array 510.

[0023] The data register 540 includes a plurality of latch circuits. The latch circuits hold write data WD and read data RRD. For example, in a write operation, the data register 540 temporarily holds the write data WD received from the input / output circuit 310 and transmits it to the sense amplifier module 530. For example, in a read operation, the data register 540 temporarily holds the read data RD received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0024] The column decoder 550 decodes the column address CA during, for example, a write operation, a read operation, or an erase operation, and selects a latch circuit in the data register 540 according to the decoding result.

[0025] The group of circuits arranged around the memory cell array 510 is also called a peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generation circuit 380.

[0026] As described above, the semiconductor memory device 1 of the embodiment includes the memory cell array 510 including a plurality of memory cells, and a peripheral circuit that operates the plurality of memory cells.

[0027] FIG. 2 is an equivalent circuit diagram showing an example of the configuration of the memory cell array 510 included in the semiconductor memory device 1 according to the embodiment.

[0028] As described above, the memory cell array 510 includes a plurality of blocks BLK. Each of the plurality of blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to peripheral circuits such as the sense amplifier module 530 via a bit line BL. The other end of each of the plurality of memory strings MS is connected to the peripheral circuits via a common source line SL.

[0029] The memory string MS includes a drain select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC, and a source select transistor STS. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

[0030] The memory cells MC are, for example, field effect transistors (FETs) that include a charge storage layer in a gate insulating layer. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cells MC may be able to store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one block BLK.

[0031] The select transistors (STD, STS) are, for example, field-effect transistors. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS), respectively. The drain select line SGD connected to the drain select transistor STD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source select line SGS connected to the source select transistor STS is commonly connected to all memory strings MS in one block BLK.

[0032] One end of each of the word lines WL and the select gate lines (SGD, SGS) is connected to a peripheral circuit such as a row decoder 520.

[0033] (Example of physical configuration of semiconductor memory device) Next, the physical configuration of the semiconductor memory device 1 according to the embodiment will be described with reference to FIGS.

[0034] 3A and 3B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 3A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 3B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0035] However, hatching is omitted in Fig. 3(a) for ease of viewing the drawing. Also, Fig. 3(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring and the like are omitted.

[0036] In this specification, the X and Y directions are both directions along the plane of the word lines WL, and are orthogonal to each other. The electrical drawing direction of the word lines WL is sometimes referred to as the third direction, and this third direction is along the X direction. The direction intersecting the third direction is sometimes referred to as the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing errors, the second and third directions are not necessarily orthogonal to each other. The direction in which multiple word lines WL are stacked is sometimes referred to as the first direction, and this first direction corresponds to the vertical direction of the semiconductor memory device 1.

[0037] 3(a), the semiconductor memory device 1 includes a semiconductor substrate SB on which, from the bottom of the page, are provided electrode films EL, source lines SL, a stacked body LM, and a peripheral circuit CBA. In the stacked body LM, one or more select gate lines SGS, a plurality of word lines WL, and one or more select gate lines SGD are stacked and spaced apart from each other.

[0038] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL to form a stacked body LM.

[0039] With the above configuration, the source potential can be applied from the above-mentioned voltage generating circuit 380 (see FIG. 1) to the source line SL via the electrode film EL and the plug PG.

[0040] 3(a) and 3(b), a memory region MR is arranged in the center of the laminate LM in the X direction, and staircase regions SR are arranged at both ends in the X direction. These memory region MR and staircase regions SR are divided into multiple regions by multiple plate-like portions PT that extend in the X direction and penetrate multiple word lines WL, etc.

[0041] The region arranged between adjacent plate-like portions PT in the Y direction and including the memory region MR and the staircase region SR is an example of a physical configuration corresponding to one block BLK (see FIG. 2) described above. As described above, the memory region MR includes multiple memory cells MC (see FIG. 2) that store data in a non-volatile manner, and the block region BLK described above is the unit for erasing this data.

[0042] Furthermore, between plate-like portions PT adjacent in the Y direction, a plurality of isolation layers SHE are arranged, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR and reach parts of the staircase regions SR at both ends in the X direction. The isolation layers SHE are, for example, insulating layers such as silicon oxide layers.

[0043] In this way, the area between the adjacent plate-shaped portions PT, which is partitioned by the separation layer SHE into the pattern of the select gate lines SGD, is an example of a physical configuration corresponding to the above-mentioned string unit SU (see FIG. 2).

[0044] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells MC are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which the memory cells MC are arranged three-dimensionally in the memory region MR.

[0045] Thus, the memory region MR is an example of a physical configuration corresponding to the above-mentioned memory cell array 510 (see FIG. 2). Also, the pillar PL is an example of a physical configuration corresponding to the above-mentioned memory string MS (see FIG. 2) in which memory cells MC and the like are connected in series.

[0046] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0047] The above-mentioned separation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the separation layer SHE penetrates the portion above the multiple word lines WL, thereby dividing the upper portion of the stacked body LM into a pattern of multiple select gate lines SGD.

[0048] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0049] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0050] 3(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0051] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 3(a) belong to different block regions BLK and are not actually located on the same cross section.

[0052] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells MC included in the memory region MR in the center of the word lines WL via word lines WL located at the same height as the memory cells MC.

[0053] In this specification, the direction in which the terrace surfaces of the word lines WL and the like that are processed in a stepped shape face is defined as the upper side of the semiconductor memory device 1.

[0054] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0055] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. On the surface of the semiconductor substrate SB, peripheral circuits CBA such as the row decoder 520 including transistors TR and wiring, and the sense amplifier module 530 (see FIG. 1) are arranged. Various voltages applied to the memory cells MC from the contacts CC are controlled by the peripheral circuits CBA electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cells MC.

[0056] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0057] FIG. 4 is a schematic diagram showing an example of the layout of various components in the memory region MR of the semiconductor memory device 1 according to the embodiment.

[0058] More specifically, Fig. 4(a) is a schematic diagram showing the detailed configuration of a pillar PL. Figs. 4(b) and 4(c) are enlarged views of a portion of the memory region MR, with Fig. 4(b) omitting the bit lines BL and Fig. 4(c) showing the bit lines BL. Fig. 4(d) is a schematic top view showing a portion of the memory region MR.

[0059] As shown in FIG. 4(d) and as described above, the memory region MR between the plate-shaped portions PT adjacent in the Y direction is separated into a plurality of sections by a plurality of separation layers SHE extending along the X direction.

[0060] Furthermore, between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, and between the separation layers SHE adjacent in the Y direction, the pillars PL are arranged in a plurality of rows extending in the X direction. In the rows shown in Fig. 5(d), the pillars PL are arranged in five rows R1 to R5. However, one end side in the Y direction of the pillars PL belonging to rows R1 and R5 adjacent to the separation layer SHE overlaps with the separation layer SHE when viewed from the stacking direction of the laminate LM.

[0061] In the arrangement of these pillars PL, the pillars PL belonging to adjacent columns R1 and R2, columns R2 and R3, columns R3 and R4, and columns R4 and R5 are arranged with their positions in the Y direction shifted so as not to overlap with each other in the Y direction. On the other hand, the pillars PL belonging to adjacent columns R1, R3, and R5, and columns R2 and R4, separated by an adjacent column, are arranged so that their positions in the Y direction coincide with each other. As a result, the multiple pillars PL are arranged in a staggered pattern when viewed from the stacking direction of the laminate LM, for example. More preferably, the multiple pillars PL are arranged at substantially the same pitch.

[0062] As described above, by arranging the pillars PL so as to allow interference between some of the pillars PL and the separation layer SHE, it is possible to maintain a periodic arrangement, such as a staggered arrangement, of the pillars PL. This allows for improved processing accuracy when forming multiple pillars PL at high density. As described above, the separation layer SHE is, for example, an insulating layer, and does not affect the electrical characteristics of the pillars PL even if it comes into contact with the pillars PL.

[0063] Above these pillars PL, for example, a plurality of bit lines BL extending in the Y direction are arranged at predetermined intervals from each other in the X direction. More preferably, the plurality of bit lines BL are arranged at substantially equal intervals in the X direction.

[0064] Each pillar PL is electrically connected to one of these bit lines BL. In this case, in order to enable individual driving of the memory cells MC belonging to each pillar PL, the pillar PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction and between the separation layers SHE adjacent in the Y direction are connected to different bit lines BL.

[0065] Here, the laminate LM has a two-tier structure in which, for example, sacrificial layers corresponding to a plurality of word lines WL are laminated in two separate steps. In the two-tier structure laminate LM, the staircase shapes of the pillars PL and the staircase region SR are also formed in two separate steps.

[0066] As shown in Fig. 4(a), inside the pillar PL, a MANOS structure is formed, which includes a semiconductor layer CN extending in the stacking direction of the laminate LM and an insulating layer ME having a multilayer structure. With this MANOS structure, a memory cell MC is formed at the intersection of the pillar PL and the word line WL, and select gates STD and STS (see Fig. 2) are formed at the intersection of the pillar PL and select gate lines SGD and SGS, respectively.

[0067] Note that the pillars PL, which are arranged in the region between the plate-like portion PT and the isolation layer SHE and belong to column R1, overlap the isolation layer SHE at the height of the select gate line SGD, with one end in the Y direction missing. The select gate lines SGD surrounding the pillars PL of column R1 also overlap the isolation layer SHE, with a missing portion. However, the select transistors STD formed at the intersections of the pillars PL and the select gate lines SGD are adjusted to function as select transistors STD in the pillars PL of column R1 as well. The isolation layer SHE does not reach the height of the word lines WL, so no missing portion occurs in the pillars PL of column R1. Nor does any missing portion occur in the word lines. Therefore, the memory cells MC formed at the intersections of the pillars of column R1 and the word lines WL function as expected.

[0068] Similarly, one end of the pillar PL in the Y direction, which is disposed in the region between the two isolation layers SHE and belongs to column R5, overlaps with the isolation layer SHE at the height of the select gate line SGD, and that portion is missing. Furthermore, the select gate line SGD surrounding the pillar PL of column R5 overlaps with the isolation layer SHE, and that portion is missing. However, the select transistor STD formed at the intersection of the pillar PL and the select gate line SGD is adjusted to function as a select transistor STD in the pillar PL of column R5 as well. The isolation layer SHE does not reach the height of the word line WL, so no missing portion occurs in the pillar PL of column R5. Nor does any missing portion occur in the word line. Therefore, the memory cell MC formed at the intersection of the pillar of column R5 and the word line WL functions as expected.

[0069] Furthermore, for example, in a stack LM having a two-tier structure, the pillar PL includes a lower pillar LMH arranged in a lower layer portion of the stack LM and an upper pillar UMH arranged in an upper layer portion of the stack LM and connected to the lower pillar LMH. At the upper end of the pillar PL, plugs CH and VY are arranged in this order from the pillar PL side, and each pillar PL is connected to an upper bit line BL via these plugs CH and VY.

[0070] 4(b), the pillars PL have, for example, a circular shape when viewed from the stacking direction of the laminate LM, but may also have other shapes such as an oval or elliptical shape.

[0071] The plug CH at the upper end of the pillar PL has, for example, an elliptical shape when viewed from the stacking direction of the laminate LM, so that its longitudinal direction is along the X direction. However, the plug CH may have another shape, such as an oval shape or a rectangle with rounded corners, as long as its longitudinal direction is along the X direction. The longitudinal distance of the plug CH can be, for example, 1.1 times or more and less than 2 times the lateral distance of the plug CH.

[0072] When viewed from the stacking direction of the laminate LM, the outer shape of the plug CH is smaller than the outer shape of the pillar PL and is disposed so as to fit within the range of the upper surface of the pillar PL. Moreover, when viewed from the stacking direction of the laminate LM, the center point of the plug CH substantially coincides with the center point of the corresponding pillar PL.

[0073] On the other hand, the plug VY disposed on the upper surface of the plug CH has an elliptical shape with the longitudinal direction along, for example, the Y direction. That is, the plug VY extends in the direction in which the bit line BL extends.

[0074] Furthermore, the center point of the plug VY as viewed from the stacking direction of the laminate LM substantially coincides with the center points of the corresponding pillar PL and plug CH in the Y direction, but is offset in the X direction. In this case, the amount of offset between the center point of the plug VY and the center points of the corresponding pillar PL and plug CH differs for each pillar PL so that the pillar PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction and between the separation layers SHE adjacent in the Y direction are connected to different bit lines BL.

[0075] As shown in Figure 4(c), when the bit line BL is superimposed on Figure 4(b), it can be seen that, due to the above configuration, the pillars PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, and between the separation layers SHE adjacent in the Y direction, are each connected to a different bit line BL.

[0076] More specifically, the position of each plug VY in the X direction is determined to match the position of the bit line BL to be connected among the multiple bit lines BL in the X direction. Therefore, as described above, the amount of deviation in the X direction between the center point of the plug VY and the center points of the corresponding pillar PL and plug CH varies individually, and such displacement of the center points makes it possible to connect the pillar PL arranged between the plate-like portion PT and the separation layer SHE and between the separation layers SHE to different bit lines BL individually.

[0077] That is, in the example shown in FIG. 4(c), between the plate-like portion PT and the separation layer SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL1, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL4, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL2, is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL5, is connected to bit line BL3 via plugs CH and VY.

[0078] In the example shown in FIG. 4(c), between the separation layers SHE adjacent in the Y direction, a predetermined pillar PL belonging to column R1 is connected to bit line BL5 via plugs CH and VY. A pillar PL belonging to column R2, which is adjacent to the pillar PL of column R1 connected to bit line BL5, is connected to bit line BL2 via plugs CH and VY. A pillar PL belonging to column R3, which is adjacent to the pillar PL of column R2 connected to bit line BL2, is connected to bit line BL4 via plugs CH and VY. A pillar PL belonging to column R4, which is adjacent to the pillar PL of column R3 connected to bit line BL4, is connected to bit line BL1 via plugs CH and VY. A pillar PL belonging to column R5, which is adjacent to the pillar PL of column R4 connected to bit line BL1, is connected to bit line BL3 via plugs CH and VY.

[0079] In this way, the multiple bit lines BL are connected to any of the pillars PL in each of the columns R1 to R5 at intervals of 5. In other words, among the arrangement of the multiple pillars PL, the pillars PL belonging to the same column of the columns R1 to R5 are connected to every fifth bit line BL, the number of which is the same as the number of the pillars PL arranged, among the multiple bit lines BL aligned in the Y direction.

[0080] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is a flow chart illustrating a part of the procedure of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0081] As shown in FIG. 5, lower layer wiring such as source lines SL is formed on a support substrate such as a silicon substrate (step S101).

[0082] Next, a plurality of sacrificial layers such as silicon nitride layers are stacked above the source line SL at a distance from each other to form a lower ONO structure, thereby forming a first-layer stack (step S111). In addition, a part of the first-layer stack is processed into a staircase shape to form a lower-layer staircase, which is then covered with an insulating layer 50 (step S112).

[0083] Furthermore, lower pillars LMH, which will be the lower structure of the pillars PL, are formed in the first layer stack (step S113). However, at this stage, the lower pillars LMH are filled with a sacrificial layer such as an amorphous silicon layer.

[0084] Next, a plurality of sacrificial layers such as silicon nitride layers are stacked on the first stack at a distance from each other to form an upper ONO structure, thereby forming a second stack (step S121). Also, a part of the second stack is processed into a staircase shape to form an upper staircase, which is then buried with an insulating layer 50 (step S122).

[0085] Furthermore, a memory hole that becomes the upper pillar UMH, which is the upper structure of the pillar PL, is formed in the second stack (step S123). Furthermore, the sacrificial layer that fills the lower pillar LMH is removed via the memory hole.

[0086] Next, a MANOS structure is formed in the lower pillar LMH and the upper pillar UMH, and pillars PL are formed (step S131).

[0087] Next, a slit ST is formed through the two-tier structure stack (step S132). A remover such as hot phosphoric acid is introduced through the slit ST to remove the sacrificial layer of the stack (step S133). A source gas such as tungsten is introduced through the slit ST to form a plurality of word lines WL in the portion where the sacrificial layer has been removed (step S134).

[0088] By such a replacement process, a stacked body LM having a two-tier structure in which a plurality of word lines WL and the like are stacked and spaced apart from each other is formed.

[0089] Next, an insulating layer or the like is filled into the slit ST to form a plate-like portion PT (step S135). Also, a separation layer SHE is formed that extends in the memory region MR along the X direction and reaches the staircase region SR (step S136). As a result, one or more selection gate lines SGD are formed in the upper layer portion of the stacked body LM.

[0090] Next, holes that will later become plugs CH are formed in the layer above the laminate LM (step S141). At this time, the holes are formed to have an elliptical shape when viewed from the stacking direction of the laminate LM. Furthermore, a plurality of contact holes that will later become contacts CC are formed in the staircase region SR (step S142).

[0091] Next, a conductive layer such as a tungsten layer is filled into these holes and contact holes, thereby forming plugs CH connected to the pillars PL, respectively, and contacts CC connected to the word lines WL and select gate lines SGD, SGS, respectively (step S143).

[0092] Next, plugs VY and the like connected to the plugs CH and contacts CC are formed in a layer above the plugs CH (step S144). Also, bit lines BL connected to the plugs VY are formed in a layer above the plugs VY (step S145). Also, upper layer wiring connected to the contacts CC via the plugs is formed in the same layer as the bit lines BL (step S146).

[0093] Then, a silicon substrate SB on which a peripheral circuit CBA is formed is bonded to the top surface of a support substrate on which the stacked body LM, pillars PL, plugs CH, VY, bit lines BL, contacts CC, upper layer wiring, etc. are formed (step S151), and the support substrate is removed (step S152).Furthermore, plugs PG and electrode films EL are sequentially formed on the side from which the support substrate has been removed (step S153).

[0094] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0095] 5 is merely an example and can be changed as appropriate. For example, the process of step S112 and the process of step S113 can be interchanged, and the process of step S122 and the processes of steps S123 and S131 can be interchanged. The process of step S141 and the process of step S142 can also be interchanged.

[0096] (Overview) In order to achieve high integration of semiconductor memory devices such as three-dimensional nonvolatile memories, the density of pillars on which memory cells are formed is increasing. For this reason, a plurality of pillars arranged in multiple rows, for example, five rows, may be arranged between a plate-like portion and an isolation layer or between isolation layers. However, when connecting each pillar arranged between a plate-like portion and an isolation layer or between isolation layers to a different bit line, it is becoming difficult to adjust the relative positions of the pillars, plugs, and bit lines.

[0097] 6A and 6B are schematic diagrams showing an example of the layout of various components in a memory region MRx of a semiconductor memory device according to a comparative example. More specifically, Fig. 6A and Fig. 6B are enlarged views of a portion of the memory region MRx, with Fig. 6A omitting the bit lines BL and Fig. 6B showing the bit lines BL.

[0098] 6, the semiconductor memory device of the comparative example includes plugs CHx having, for example, a circular shape when viewed from the stacking direction of the stack. Meanwhile, also in the comparative example, the pillars PL are arranged in a staggered pattern, more specifically, in five rows extending in the X direction between the plate-like portion PT and the isolation layer SHE or in the region between the isolation layers SHE. Also in the comparative example, the center points of the pillars PL and the plugs CHx are approximately the same, and the positions of the plugs VY in the X direction are individually different relative to these pillars PL and plugs CHx.

[0099] This allows each pillar PL arranged in the region between the plate-like portion PT and the separation layer SHE or between the separation layers SHE to be connected to a different bit line BL. That is, the multiple bit lines BL are connected to any of the pillars PL in each of the columns R1 to R5 at intervals of five.

[0100] However, in a certain column among columns R1 to R5, it is difficult to ensure a sufficient connection area between the plug VY, whose position in the X direction is determined in accordance with the position of the bit line BL, and the plug CHx, whose position in the X direction is determined in accordance with the position of the pillar PL. In the example of Fig. 6, in the regions between the plate-like portion PT and the isolation layer SHE and between the isolation layers SHE, the connection area between the plugs CHx and VY on the pillar PL, which belongs to column R5 and is connected to bit line BL3, is insufficient.

[0101] More specifically, in the pillar PL disposed between the plate-like portion PT and the separation layer SHE and belonging to column R5, the plug VY is disposed upward in the plane of the drawing, i.e., extremely to one side in the X direction, relative to the pillar PL and the plug CHx, thereby reducing the connection area between the plugs CHx and VY. Also, in the pillar PL disposed between the separation layers SHE and belonging to column R5, the plug VY is disposed downward in the plane of the drawing, i.e., extremely to the other side in the X direction, relative to the pillar PL and the plug CHx, thereby reducing the connection area between the plugs CHx and VY.

[0102] Such a reduction in the connection area between plugs CHx and VY can occur, for example, when the arrangement of pillars PL between the plate-like portion PT and the isolation layer SHE, and between the isolation layers SHE, is an odd number of columns, and when connecting to the middle bit line BL of the bit lines BL connected to the pillar PL at a period equal to the arrangement of the pillars PL, that is, in the example of Figure 6, the middle bit line BL3 of bit lines BL1 to BL5.

[0103] In contrast, the multiple plugs CH in the embodiment are, for example, elliptical in shape with the longitudinal direction along the X direction as viewed from the stacking direction of the laminate LM. Therefore, as shown in FIG. 4(a) and other figures, even if the plug VY is disposed extremely close to one side in the X direction with respect to the pillar PL and the plug CH in the pillar PL belonging to row R5, a sufficient contact area between the plugs CH and VY is ensured.

[0104] The semiconductor memory device 1 of the embodiment includes a plurality of pillars PL arranged in (2n+1) columns (n ​​is an integer equal to or greater than 1) extending along the X direction, and a plurality of plugs CH disposed at the upper ends of the pillars PL and electrically connected to the channel layers CN of the pillars PL, the longitudinal direction of the plugs CH intersecting the Y direction. This allows the densely packed pillars PL to be more reliably connected to the bit lines BL. This improves the electrical characteristics of the semiconductor memory device 1, thereby increasing reliability.

[0105] According to the semiconductor memory device 1 of the embodiment, the multiple plugs CH have their longitudinal direction aligned with the X direction, which allows the highly dense pillars PL to be more reliably connected to the bit lines BL.

[0106] According to the semiconductor memory device 1 of the embodiment, the plurality of plugs VY have their longitudinal direction along the Y direction and are arranged at positions overlapping with the bit lines BL to be connected among the plurality of bit lines BL in the stacking direction of the laminate LM. As described above, by having the plurality of plugs CH have their longitudinal direction along the X direction, a sufficient contact area with the plugs VY arranged in accordance with the positions of the bit lines BL as described above can be ensured, thereby enabling more reliable connection.

[0107] According to the semiconductor memory device 1 of the embodiment, the multiple plugs CH have an outer shape smaller than that of the multiple pillars PL when viewed from the stacking direction of the laminate LM, and are arranged at positions overlapping with the pillars PL to be connected among the multiple pillars PL in the stacking direction of the laminate LM. As described above, by having the multiple plugs CH have a longitudinal direction along the X direction, as described above, the plugs CH arranged to align with the positions of the pillars PL and the plugs VY arranged to align with the positions of the bit lines BL can be more reliably connected to each other by ensuring a sufficient contact area.

[0108] According to the semiconductor memory device 1 of the embodiment, the pillars PL arranged in (2n+1) columns are disposed in the region between the plate-like portion PT and the separation layer SHE adjacent to each other in the Y direction, or in the region between the separation layers SHE. As described above, even when the pillars PL are arranged in odd columns in the region between the plate-like portion PT and the separation layer SHE, or in the region between the separation layers SHE, these pillars PL can be more reliably connected to the bit lines BL.

[0109] According to the semiconductor memory device 1 of the embodiment, among the plurality of pillars PL, pillars PL belonging to the same arrangement are connected to every (2n+1) bit lines BL among the plurality of bit lines BL aligned in the X direction. In this way, by configuring the pillars PL belonging to the same arrangement to be connected to the bit lines BL in the same number as the arrangement of the pillars PL, it is possible to connect each pillar PL arranged in the region between the plate-like portion PT and the separation layer SHE or in the region between the separation layers SHE to different bit lines BL.

[0110] In the above-described embodiment, the pillars PL are arranged in five rows extending in the X direction in the regions between the plate-like portion PT and the separation layer SHE and between the separation layers SHE. However, the arrangement of the pillars PL may be three rows, or seven or more rows, as long as there is an odd number of rows. As described above, by applying the configuration of the above-described embodiment to pillars PL arranged in such odd rows, it is possible to ensure a sufficient connection area between the plugs CH and VY for any bit line BL connected to the pillars PL at the same period as the arrangement of the pillars PL.

[0111] In the above-described embodiment, the source lines SL are formed on the support substrate before the formation of the laminated body LM. However, the source lines may be formed after bonding with the semiconductor substrate SB and after removing the support substrate.

[0112] In the above embodiment, the laminate LM has a two-tier structure, but the number of tiers in the laminate may be one tier, or three or more tiers.

[0113] In the above-described embodiment, the staircase region SR is arranged at the end of the stack LM in the X direction. However, the staircase region may be arranged in the center of the stack when viewed from the stacking direction by digging out the center of the stack in a staircase shape.

[0114] (Variation) Next, a semiconductor memory device according to a modification of the embodiment will be described with reference to Fig. 7. In the semiconductor memory device according to the modification, the longitudinal direction of the plugs CHa is different from that of the plugs CH in the above-described embodiment.

[0115] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0116] FIG. 7 is a schematic diagram showing an example of the layout of various components in a memory region MRa of a semiconductor memory device according to a modified example of the embodiment.

[0117] More specifically, Figures 7(a) and 7(b) are enlarged views of a portion of memory region MRa, with bit lines BL omitted in Figure 7(a) and bit lines BL shown in Figure 7(b), and Figure 7(c) is a schematic top view showing a portion of memory region MRa.

[0118] 7(c), the layout of the pillars PL and the multiple bit lines BL above the pillars PL in the memory region MRa of the modified example is the same as that of the above-described embodiment. That is, in each region between the plate portion PT and the isolation layer SHE and between the isolation layers SHE, the multiple pillars PL are arranged in an odd number of columns, such as five columns, extending in the X direction, forming a staggered arrangement overall. In addition, multiple bit lines BL extending in the Y direction are arranged above these pillars PL, spaced apart from each other in the X direction.

[0119] 7(a) and 7(b), in the semiconductor memory device of the modified example, the plurality of plugs CHa have, for example, an elliptical shape with the longitudinal direction in a direction intersecting both the X direction and the Y direction. It is preferable that the longitudinal direction of the plurality of plugs CHa forms an angle of 30° or more and 60° or less with respect to the plurality of bit lines BL extending in the Y direction.

[0120] The shape of the plugs CHa is not limited to an elliptical shape, and may be other shapes such as an oval shape or a rectangular shape with rounded corners.

[0121] In this way, even in the semiconductor memory device of the modified example in which the plurality of plugs CHa have longitudinal directions oblique to both the X direction and the Y direction, the pillars PL arranged between the plate-like portion PT and the separation layer SHE adjacent in the Y direction and between the separation layers SHE adjacent in the Y direction can be connected to different bit lines BL, respectively. In addition, in this case, the plurality of bit lines BL are connected to any of the pillars PL in each of the columns R1 to R5 at a cycle of five.

[0122] According to the semiconductor memory device of the modified example, the angle between the longitudinal direction of the plurality of plugs CHa and the plurality of bit lines BL is 30° or more and 60° or less. This allows the distance between adjacent plugs CHa in the X direction to be long, facilitating exposure and etching processes when forming a pattern of the plurality of plugs CHa. Furthermore, by increasing the distance between adjacent plugs CHa in the X direction, delays in the transmission speed of various signals via the plugs CHa can be suppressed.

[0123] In addition, the semiconductor memory device of the modified example has the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0124] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0125] 1...semiconductor memory device, BL...bit line, CH, CHa, VY...plug, CN...channel layer, LM...laminated body, MC...memory cell, MR, MRa...memory region, PL...pillar, PT...plate-shaped portion, SR...staircase region, SGD, SGS...select gate line, SHE...isolation layer, STD, STS...select gate, WL...word line.

Claims

1. a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; a plurality of pillars each having a semiconductor layer extending within the stack in a first direction that is a stacking direction of the stack, and arranged in (2n+1) columns (n ​​is an integer of 1 or more) in a second direction that intersects with the first direction; a plurality of first plugs disposed at upper ends of the plurality of pillars and electrically connected to the semiconductor layer; a plurality of bit lines extending in the second direction above the plurality of pillars and electrically connected to corresponding first plugs among the plurality of first plugs, The plurality of first plugs include: having a longitudinal direction in a direction intersecting the second direction when viewed from the first direction; Semiconductor memory device.

2. an angle formed between the longitudinal direction of the plurality of first plugs and the plurality of bit lines is equal to or greater than 30° and equal to or less than 60°; 2. The semiconductor memory device according to claim 1.

3. the plurality of first plugs are elliptical when viewed from the first direction; 2. The semiconductor memory device according to claim 1.

4. further comprising a plurality of second plugs arranged at upper ends of the plurality of first plugs and connecting corresponding first plugs and bit lines among the plurality of first plugs and the plurality of bit lines, 2. The semiconductor memory device according to claim 1.

5. The plurality of second plugs include: having a longitudinal direction in the second direction; the first bit line is disposed at a position overlapping with a bit line to be connected among the plurality of bit lines in the first direction; 5. The semiconductor memory device according to claim 4.

6. The plurality of first plugs include: When viewed from the first direction, the outer shape is smaller than the outer shape of the plurality of pillars, The pillar is disposed at a position overlapping with a pillar to be connected among the plurality of pillars in the first direction.

6. The semiconductor memory device according to claim 5.

7. a first plate-shaped portion extending within the stacked body in the first direction and a third direction intersecting the first and second directions; a second plate-shaped portion extending within the stack in the first and third directions at a position spaced apart from the first plate-shaped portion in the second direction, The plurality of pillars are disposed in a region between the first and second plate-shaped portions; 2. The semiconductor memory device according to claim 1.

8. a first plate-shaped portion extending within the stacked body in the first direction and a third direction intersecting the first and second directions; a second plate-shaped portion extending within the stack in the first and third directions at a position spaced apart from the first plate-shaped portion in the second direction; a plurality of separation layers that penetrate at least an uppermost conductive layer among the plurality of conductive layers and extend in the third direction at positions spaced apart from each other in the second direction in a region of the stack between the first and second plate-shaped portions, The plurality of pillars are A region between a separation layer of the plurality of separation layers adjacent to the first plate-shaped portion in the second direction and the first plate-shaped portion, or and disposed in a region between two separation layers adjacent to each other in the second direction among the plurality of separation layers.

2. The semiconductor memory device according to claim 1.

9. Among the plurality of pillars, pillars belonging to an arrangement adjacent to the plurality of separation layers in the second direction partially overlap with adjacent separation layers when viewed from the first direction; 9. The semiconductor memory device according to claim 8.

10. The plurality of pillars are arranged in five rows.

9. The semiconductor memory device according to claim 8.

11. The plurality of bit lines are spaced apart from each other in the third direction, Among the plurality of pillars, pillars belonging to the same array are connected to every (2n+1) bit lines among the plurality of bit lines aligned in the third direction; 9. The semiconductor memory device according to claim 8.

12. Among the plurality of bit lines, the (2n+1) bit lines arranged in the third direction are respectively connected to pillars belonging to different arrangements among the plurality of pillars; 12. The semiconductor memory device according to claim 11.

13. Among the plurality of pillars, pillars belonging to adjacent arrays are arranged such that their center points as viewed from the first direction do not overlap with each other in the second direction; 12. The semiconductor memory device according to claim 11.

14. When viewed from the first direction, the plurality of pillars are arranged in a staggered pattern.

14. The semiconductor memory device according to claim 13.

15. a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; a plurality of pillars each having a semiconductor layer extending within the stack in a first direction that is a stacking direction of the stack; a plurality of first plugs disposed at upper ends of the plurality of pillars and electrically connected to the semiconductor layer; a plurality of second plugs respectively disposed at upper ends of the plurality of first plugs and connected to the plurality of first plugs; a plurality of bit lines extending above the plurality of pillars in a second direction intersecting the first direction and electrically connected to corresponding second plugs among the plurality of second plugs; a first plate-shaped portion extending within the laminate in the first direction and a third direction intersecting the first and second directions; a second plate-shaped portion extending within the stack in the first and third directions at a position spaced apart from the first plate-shaped portion in the second direction; a plurality of separation layers that penetrate at least an uppermost conductive layer among the plurality of conductive layers and extend in the third direction at positions spaced apart from each other in the second direction in a region of the laminate between the first and second plate-shaped portions, The plurality of pillars are A region between a separation layer of the plurality of separation layers adjacent to the first plate-shaped portion in the second direction and the first plate-shaped portion, or the plurality of separation layers are arranged in five rows in the second direction in a region between two separation layers adjacent to each other in the second direction, The plurality of first plugs include: having a longitudinal direction in a direction intersecting the second direction when viewed from the first direction; Semiconductor memory device.

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