Semiconductor storage device and method for manufacturing semiconductor storage device

Abstract

To suppress the contact between a contact and other components.SOLUTION: A semiconductor storage device of an embodiment comprises: a first laminate which includes a first stepped part in which a plurality of first conductive layers are stacked spaced apart from each other and processed into a staircase shape; a second laminate arranged above the first laminate and including a second stepped part in which a plurality of second conductive layers are stacked spaced apart from each other and processed into a staircase shape, and extending continuously from the first stepped part; a first insulation layer covering the first and second stepped parts; a first layer interposed in the first insulation layer above the first stepped part, containing a material different from the material of the first insulation layer, and arranged at a height position between the first and second laminates; and a first contact extending downward from above the first stepped part through the first insulation layer and the first layer, and connected to one of the plurality of first conductive layers processed into the staircase shape.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as 3D nonvolatile memories, memory cells are arranged three-dimensionally in a stack of multiple conductive layers spaced apart from one another. These conductive layers are processed into a stepped structure in some areas of the stack, and contacts are connected to each conductive layer. When forming the contacts, the contacts may come into contact with other components, which can degrade the electrical characteristics of the semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-034651 [Patent Document 2] Japanese Patent Publication No. 2022-047595 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-060838 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device that can prevent contact between a contact and other components, and a method for manufacturing the semiconductor memory device. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a first stacked body in which a plurality of first conductive layers are stacked at a distance from each other, and the plurality of first conductive layers have a first staircase portion processed into a staircase shape; a second stacked body arranged above the first stacked body in which a plurality of second conductive layers are stacked at a distance from each other, and the plurality of second conductive layers are processed into a staircase shape, and has a second staircase portion extending continuously from the first staircase portion; a first insulating layer covering the first and second staircase portions; a first layer interposed in the first insulating layer above the first staircase portion and containing a material different from the first insulating layer, and arranged at a height position between the first and second stacked bodies; and a first contact extending downward from above the first staircase portion, penetrating the first insulating layer and the first layer, and connected to any one of the plurality of first conductive layers processed into a staircase shape. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10]1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing an example of a method for forming contact holes according to an embodiment and a comparative example. [Figure 12] FIG. 10 is a diagram showing an example of the configuration of a semiconductor memory device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0010] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0012] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL to form a stacked body LM.

[0013] 1(a) and 1(b), a memory region MR is arranged in the center of the word lines WL in the X direction, and staircase regions SR are arranged at both ends of the word lines WL in the X direction. The memory region MR and staircase region SR are divided into multiple regions by multiple plate-like contacts LI that extend in the X direction and penetrate the word lines WL.

[0014] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0015] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0016] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0017] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0018] The isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0019] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0020] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0021] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0022] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0023] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0024] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0025] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0026] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0027] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0028] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0029] 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS, and FIG. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL.

[0030] Figure 2(d) is a cross-sectional view along the X direction in the staircase region SR of the semiconductor memory device 1. In Figure 2(d), the structure below the insulating layer 60 and above an insulating layer 53, which will be described later, is omitted.

[0031] In this specification, the direction in which the terrace surface of the word line WL of each step in the staircase region SR faces is defined as the upward direction in the semiconductor memory device 1.

[0032] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0033] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0034] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA through the insulating layer 50 on the outside of the laminated body LM.

[0035] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0036] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0037] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0038] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described later, each constitute a part of the insulating layer 50 shown in FIG.

[0039] As described above, the multilayer body LM is divided in the Y direction by the plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0040] In this way, the plate-shaped contact LI extends continuously within the stack LM from one end to the other end in the X direction of the stack LM. The plate-shaped contact LI also penetrates the stack LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0041] The plate-shaped contact LI has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0042] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0043] The insulating layer 54 covers the side walls of the plate contact LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source line BSL. The upper end of the conductive layer 24 is connected to the upper wiring via a plug or the like at a position different from that of the cross section of FIG. 2(a). This allows the plate contact LI to function as a source line contact.

[0044] However, instead of the plate-shaped contacts LI, plate-shaped members filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction. In this case, the plate-shaped contacts do not function as source line contacts.

[0045] Between the plate contacts LI adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, which penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0046] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0047] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0048] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0049] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0050] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0051] 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0052] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL via the memory layer ME. However, a portion of the channel layer CN contacts the intermediate source line BSL on the side, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0053] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0054] 2(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0055] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0056] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0057] 2(b), select gates STD are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGS0 and SGS1 below the word lines WL.

[0058] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0059] As shown in Fig. 2(d), the staircase region SR has a staircase portion SP in which multiple word lines WL and select gate lines SGD, SGS are processed in a staircase shape. The staircase portion SP shown in Fig. 2(d) is a part of the staircase region SR divided into multiple block regions BLK, where contacts CC are arranged and which has the function of drawing out the word lines WL, etc.

[0060] The stepped portion SP is covered with an insulating layer 51. The insulating layer 51 reaches, for example, the height position of the uppermost layer of the laminated body LM, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 also forms part of the insulating layer 50 in FIG.

[0061] A stopper layer STP is disposed above the stepped portion SP where the word lines WL and select gate lines SGS in the stacked body LMa are formed. The stopper layer STP contains a different material from the insulating layer 51 and is interposed in the insulating layer 51 at a height position between the stacked bodies LMa and LMb. While the insulating layer 51 is a silicon oxide layer or the like, the stopper layer STP is, for example, a silicon nitride layer.

[0062] In the staircase region SR, the source lines SL include an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0063] Therefore, in the staircase region SR, the plate-shaped contact LI penetrates the insulating layer 51, the stacked body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0064] Each contact CC (CCs, CCt) penetrates the insulating layer 51 and is connected to a word line WL or a select gate line SGD, SGS immediately below the insulating layer OL that constitutes each step of the staircase portion SP. Of the multiple contacts CCs, CCt, the contact CCs is a contact CC that is connected to one of the multiple word lines WL and select gate lines SGD included in the stacked body LMb. On the other hand, the contact CCt is a contact CC that is connected to one of the multiple word lines WL and select gate lines SGS included in the stacked body LMa.

[0065] Each contact CCs may have a tapered shape in which the diameter and cross-sectional area decrease from the upper end to the lower end. Alternatively, each contact CC may have a bowing shape in which the diameter and cross-sectional area are maximized at a predetermined position between the upper end and the lower end. In either case, the cross-sectional area of ​​the contact CCs changes continuously from the upper end to the lower end.

[0066] Each contact CCt penetrates the insulating layer 51 and the stopper layer STP interposed in the insulating layer 51 to reach the word line WL or the select gate line SGS immediately below the insulating layer OL that constitutes each step of the staircase portion SP. Each of these contacts CCt has a contact portion CCb that is the upper layer portion of the stopper layer STP and a contact portion CCa that is the lower layer portion of the stopper layer STP.

[0067] Each contact portion CCb may have a tapered shape in which the diameter and cross-sectional area decrease from the upper end toward the lower end in contact with the stopper layer STP. Alternatively, each contact portion CCb may have a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper end and the lower end. In either case, the cross-sectional area of ​​the contact portion CCb changes continuously from the upper end to the lower end.

[0068] Each contact portion CCa has a tapered shape in which the diameter and cross-sectional area decrease from the upper end in contact with the stopper layer STP to the lower end in contact with the word line WL to be connected, for example. At this time, the cross-sectional area of ​​the contact portion CCa changes continuously from the upper end to the lower end.

[0069] In one contact CCt, the cross-sectional area of ​​the contact portion CCb along the XY plane is generally larger than the cross-sectional area of ​​the contact portion CCa along the XY plane. More specifically, the cross-sectional area of ​​the contact CCt changes discontinuously above and below the stopper layer STP, and the cross-sectional area of ​​the lower end of the contact portion CCb is larger than the cross-sectional area of ​​the upper end of the contact portion CCa.

[0070] When viewed from the stacking direction of the laminated bodies LMa and LMb, the central axis of the contact portion CCb may be misaligned with the central axis of the contact portion CCa. The reason for this misalignment will be described later.

[0071] Hereinafter, when there is no need to particularly distinguish between these contacts CCs and CCt, they will simply be referred to as contacts CC.

[0072] The contact CC has an insulating layer 55 that covers the outer periphery of the contact CC, and a conductive layer 25 such as a tungsten layer or a copper layer that fills the inside of the insulating layer 55. The conductive layer 25 is connected to an upper layer wiring MX that is arranged in the insulating layer 53 via a plug V0 that is arranged in the insulating layer 52. This upper layer wiring MX is electrically connected to the peripheral circuit CBA (see FIG. 1) described above.

[0073] With this configuration, the word lines WL of each layer and the select gate lines SGD, SGS above and below the word lines WL can be electrically drawn out from one end or the other end in the X direction of the laminated body LM. That is, with the above configuration, a predetermined voltage can be applied to the memory cells MC from the peripheral circuit CBA via the upper layer wiring MX, contacts CC, word lines WL, etc., to operate the memory cells MC as storage elements.

[0074] Furthermore, a plurality of pillars HR are distributed throughout the staircase region SR. As will be described later, these pillars HR serve to support the components of the sacrificial layer and the insulating layer when the laminate LM is formed from the laminate. However, they do not contribute to the function of the semiconductor memory device 1.

[0075] In principle, the multiple columnar portions HR are arranged in, for example, a grid or staggered pattern when viewed from the stacking direction of the laminate LM while avoiding interference with the plate-like contacts LI and contacts CC. Each columnar portion HR has a cross-sectional shape along the XY plane that is, for example, circular, elliptical, or oval.

[0076] The columnar portion HR has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the columnar portion HR has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0077] The entire columnar portion HR is a single insulating layer 57 such as a silicon oxide layer. In other words, the columnar portion HR is composed of an insulating layer 57 made of substantially a single material. Here, being made of substantially a single material may include cases where the element ratios of the constituent components of one columnar portion HR or multiple columnar portions HR are different, and cases where the types and amounts of impurities contained are different, and it also allows for the inclusion of voids in the columnar portion HR made of a single material.

[0078] Since the columnar portion HR is thus a single piece of the insulating layer 57, it cannot have an electrical effect on other components, and interference with adjacent plate-like contacts LI and the like may be permitted within a predetermined range.

[0079] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 3 to 10. Figures 3 to 10 are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0080] First, FIG. 3 shows the laminate LMsa, which is the lower layer portion of the laminate LM before the word lines WL are formed, and how various components are formed on the laminate LMsa.

[0081] FIG. 3 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0082] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a support substrate SS.

[0083] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface side of the support substrate SS.

[0084] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. As described above, the intermediate insulating layer SCO is, for example, a silicon oxide layer or the like.

[0085] Furthermore, a stacked body LMsa is formed on the upper source line DSLb, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become word lines WL or select gate lines SGS.

[0086] 3(b), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. Such processing can be performed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layers NL and OL of the laminate LMsa.

[0087] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are retracted to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the above-mentioned stepped shape is formed.

[0088] 3(c), an insulating layer 51 is formed to cover the step portion and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the laminated body LMsa.

[0089] As shown in FIG. 3(d), a plurality of memory holes MHa and a plurality of holes HLa extending in the stacking direction of the stacked body LMsa are formed, for example, at once. The memory holes MHa are portions that will later become the lower structure of the pillars PL. The holes HLa are portions that will later become the lower structure of the columnar portions HR.

[0090] The memory holes MHa are arranged in a region that will later become the memory region MR, and reach the lower source line DSLa through the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN. The holes HLa are arranged in a region that will later become the staircase region SR, and reach the lower source line DSLa through the insulating layer 51, the stacked body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO.

[0091] As shown in FIG. 3(e), the memory holes MHa and HLa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer.

[0092] As a result, in the region that will later become the memory region MR, pillars PLc are formed in which the sacrificial layer 26 is filled in the plurality of memory holes MHa. Also, in the region that will later become the staircase region SR, columnar portions HRc are formed in which the sacrificial layer 26 is filled in the plurality of holes HLa.

[0093] Next, Figures 4 and 5 show how the laminate LMsb, which is the upper layer part of the laminate LM before the word line WL is formed, is formed with a stopper layer STP interposed in part, and how various structures are further formed in the laminate LMsb.

[0094] 4 and 5 are cross-sectional views along the X direction of the regions that will later become the memory region MR and the staircase region SR, similar to FIG. 3 described above.

[0095] As shown in Fig. 4(a), a stopper layer STPb is formed to cover the laminate LMsa and the insulating layer 51 in the staircase portion. The stopper layer STPb is a layer that covers the entire surface of the laminate LMsa and the insulating layer 51 before they are formed into the pattern shown in Fig. 2(d) above.

[0096] 4(b), the stopper layer STPb is processed into the pattern of the stopper layer STP described above. That is, of the portion covering the insulating layer 51, the portion of the stopper layer STPb covering the stacked body LMsa and the portion covering the insulating layer 51 are removed, leaving the portion where the plurality of contacts CCt will be formed. Furthermore, a plurality of openings CLa are formed in the remaining portion on the insulating layer 51. These openings CLa are portions through which the contacts CCt will later pass. Furthermore, when forming these openings CLa, a mask pattern or the like aligned with the above-mentioned columnar portion HRc is used.

[0097] More specifically, a mark (not shown) is provided in a certain region on the support substrate SS for aligning a mask pattern when forming the columnar portion HRc. A mask pattern having the pattern of the columnar portion HRc is formed on the laminate LMsa using this mark as a reference, and the columnar portion HRc can be formed at a desired position on the laminate LMsa using this mask pattern. A mask pattern having the pattern of the opening CLa to be formed in the stopper layer STP is formed using this same mark as a reference, and the formation position of the opening CLa is aligned with the columnar portion HRc.

[0098] In this way, by aligning the opening CLa with the columnar portion HRc, the opening CLa can be formed while avoiding interference with the columnar portion HRc.

[0099] As a result of the above, the stopper layer STP is formed on the insulating layer 51 which covers the portion of the laminated body LMa which has been processed into a stepped shape.

[0100] As shown in Figure 4(c), a laminate LMsb is formed by covering the laminate LMsa and the stopper layer STP of the staircase portion, and by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL one by one. At this time, the openings CLa formed in the stopper layer STP are filled with, for example, the insulating layer OL. The sacrificial layers NL of the laminate LMsb will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0101] As shown in Fig. 4(d), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the process shown in Fig. 3(b) above.

[0102] At this time, the uppermost step of the staircase portion already formed in the laminate LMsa and the lowermost step of the staircase portion formed in the laminate LMsb are brought close to each other so that they are continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. Also, by removing the laminate LMsb above the staircase portion of the laminate LMsa, the stopper layer STP formed above the staircase portion of the laminate LMsa is exposed again.

[0103] 5(a), an insulating layer 51 is formed to cover the re-exposed upper surface of the stopper layer STP and the newly formed step portion of the laminate LMsb, and to reach the height of the upper surface of the laminate LMsb. The insulating layer 51 is also formed in the outer regions of the laminates LMsa and LMsb. This forms the insulating layer 51 with the stopper layer STP interposed in a part thereof.

[0104] As shown in FIG. 5(b), a plurality of memory holes MHb and a plurality of holes HLb are formed at the height position of the stacked body LMsb in the stacking direction, for example, at the same time. The memory holes MHb are portions that will later become the upper structure of the pillars PL. The holes HLb are portions that will later become the upper structure of the columnar portions HR.

[0105] The memory holes MHb are arranged in a region that will later become the memory region MR, penetrate the stacked body LMsb, and reach the upper ends of the pillars PLc formed in the stacked body LMsa.

[0106] Some of the multiple holes HLb are positioned so as to overlap the staircase portions of the laminates LMsa and LMsb in the stacking direction, and penetrate the insulating layer 51 and the laminate LMsb or the stopper layer STP to reach the upper ends of the columnar portions HRc formed in the laminate LMsa.

[0107] As shown in FIG. 5(c), the sacrificial layer 26 is removed from the pillars PLc and columnar portions HRc at the bottoms of the memory holes MHb and HLb.

[0108] As a result, a plurality of memory holes MH are formed, each of which opens at the bottom of the plurality of memory holes MHb, penetrates the stacked bodies LMsb and LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. Also, a plurality of holes HL are formed, each of which opens at the bottom of the plurality of holes HLb, penetrates the insulating layer 51, the stacked body LMsb or the stopper layer STP, the stacked body LMsa, the upper source line DSLb, and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0109] In addition, if the sacrificial layer 26 filled in the pillars PLc and the columnar portions HRc is a CVD-carbon layer or the like, when the mask pattern or the like used in the processing of FIG. 5(b) described above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed from these pillars PLc and columnar portions HRc all at once.

[0110] Thereafter, an insulating layer 57 is buried in the holes HR formed in the region that will later become the staircase region SR, thereby forming a plurality of pillar portions HR.

[0111] 6 and 7 show how a pillar PL is formed by forming a multilayer structure in the memory hole MH. Figures 6 and 7 are cross-sectional views along the Y direction of a region that will later become the memory region MR.

[0112] As shown in FIG. 6(a), a plurality of memory holes MH are formed in a region that will later become the memory region MR.

[0113] 6(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH, whereby the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0114] The multilayer insulating layer MEb is an insulating layer with a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0115] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminated body LMsb.

[0116] As shown in Figure 6(c), in the region that will later become the memory region MR, the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the top surface of the laminated body LMsb, and a recess DN is formed at the top end of the memory hole MH from which the insulating layer CRb and the semiconductor layer CNb have been removed.

[0117] As a result, the memory layer ME, the channel layer CN, and the core layer CR are formed in the memory hole MH in this order from the outer periphery.

[0118] 7A, in the region that will later become the memory region MR, a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0119] 7(b), in the region that will later become the memory region MR, the semiconductor layer CPb on the top surface of the stacked body LMsb is removed by CMP or the like, and a cap layer CP is formed at the upper end of the memory hole MH. In addition, the insulating layer OL, which is the top layer of the stacked body LMsb that has been thinned by CMP or the like, is added.

[0120] As a result, a pillar PL is formed in which the cap layer CP is buried in the uppermost insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a part of the side surface of the channel layer CN is not exposed from the memory layer ME.

[0121] Next, the formation of the source lines SL and word lines WL will be shown with reference to Figures 8 and 9. Figures 8 and 9 are cross-sectional views along the Y direction of a region that will later become the memory region MR, similar to Figures 6 and 7 described above.

[0122] 8(a), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 54s are formed on the side walls of the slit ST that face each other in the Y direction.

[0123] The slits ST have a tapered or bowed cross section in the Y direction, and extend in the X direction within the stacks LMsa and LMsb. Therefore, in the staircase region SR (not shown), the lower ends of the slits ST reach the intermediate insulating layer SCO.

[0124] As shown in FIG. 8(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0125] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs.

[0126] At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well. In addition, in the staircase region SR (not shown), there is no intermediate sacrificial layer SCN between the lower source line DSLa and the upper source line DSLb, and therefore no gap layer GPs is formed.

[0127] 8(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b) and 2(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0128] 8(d), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0129] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0130] At this time, in the staircase region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb, and no intermediate source line BSL is formed either.

[0131] As shown in FIG. 9(a), the insulating layer 54s on the sidewall of the slit ST is temporarily removed.

[0132] 9(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0133] The stacked bodies LMga and LMgb, each including a plurality of gap layers GP, have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support the fragile stacked bodies LMga and LMgb. On the other hand, in the region that will later become the staircase region SR, a plurality of columnar portions HR support the stacked bodies LMga and LMgb.

[0134] Such a support structure of the pillars PL and the columnar portions HR prevents the remaining insulating layer OL from bending and the laminated bodies LMga and LMgb from being distorted or collapsing.

[0135] 9(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0136] The top layer and the second-top conductive layer of the laminated body LMb will be partitioned into a pattern of a plurality of select gate lines SGD by later forming a separation layer SHE that penetrates them.

[0137] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0138] As described above, the stopper layer STP is formed only in the region where the contact CCt is disposed, which prevents the stopper layer STP, which is, for example, a silicon nitride layer of the same type as the insulating layer NL, from being replaced with a conductive layer by the replacement process.

[0139] Thereafter, an insulating layer 54 is formed on the sidewall of the slit ST, and the insulating layer 54 is filled with the conductive layer 24 to form the plate-like contact LI. However, the slit ST may be filled with the insulating layer 54 or the like without forming the conductive layer 24, to form a plate-like member.

[0140] In addition, a trench is formed through one or more conductive layers including the topmost conductive layer of the laminated body LMb, and an insulating layer 56 is filled in the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0141] Next, a state in which a plurality of contacts CC are formed in the staircase region SR will be shown with reference to Fig. 10. Fig. 10 is a cross-sectional view of the staircase region SR along the X direction.

[0142] As shown in FIG. 10(a), in the staircase region SR, a plurality of pillar portions HR are formed, each having an insulating layer 57 buried in a hole HL.

[0143] Furthermore, a plurality of contact holes CL (CLs, CLt) are formed that penetrate the insulating layer 51 and the like and reach the plurality of word lines WL and select gate lines SGD, SGS of the stacked bodies LMa, LMb, respectively.

[0144] The multiple contact holes CLs are formed to penetrate the insulating layer 51 that covers the stepped portions of the multiple word lines WL and select gate lines SGD of the laminate LMb, and reach these word lines WL and select gate lines SGD, respectively.

[0145] The multiple contact holes CLt are formed to penetrate the insulating layer 51 that covers the stepped portions of the stacked body LMa where the multiple word lines WL and select gate lines SGS are formed, and to reach these word lines WL and select gate lines SGS, respectively.

[0146] At this time, the openings of these contact holes CLt are formed to correspond to the formation positions of openings CLa provided in the stopper layer STP and to be larger than the openings CLa. Furthermore, the etching conditions for forming the contact holes CL (CLs, CTt) are adjusted to have selectivity with respect to the stopper layer STP.

[0147] As a result, the insulating layer 51, which is, for example, a silicon oxide layer, is selectively etched compared to the stopper layer STP, which is, for example, a silicon nitride layer. Then, at the portion of the etched bottom surface of the contact hole CLt, which has an opening larger than the opening CLa of the stopper layer STP, that reaches the stopper layer STP, the etching rate drops extremely or etching stops.

[0148] Furthermore, in the portion of the etched bottom surface of the contact hole CLt that reaches the opening CLa of the stopper layer STP, the etching passes through the opening CLa and progresses to below the stopper layer STP, and can reach the word line WL or the like to be connected.

[0149] As a result, the cross-sectional area of ​​the contact hole CLt along the XY plane below the stopper layer STP is generally smaller than the cross-sectional area of ​​the contact hole CLt along the XY plane above the stopper layer STP. More specifically, the cross-sectional area of ​​the contact hole CLt changes discontinuously above and below the stopper layer STP, and the cross-sectional area of ​​the upper end of the lower portion of the stopper layer STP is smaller than the cross-sectional area of ​​the lower end of the upper portion of the stopper layer STP.

[0150] Although each contact hole CLt is formed at a position corresponding to each opening CLa of the stopper layer STP, there may be a slight misalignment in the formation position of the contact hole CLt. In this case, the central axis of the contact hole CLt seen from the stacking direction of the stacked bodies LMa and LMb will be misaligned between the upper side and the lower side of the stopper layer STP.

[0151] As shown in FIG. 10(b), an insulating layer 55 is formed on the side wall of the contact hole CL.

[0152] As shown in FIG. 10(c), a conductive layer 25 is filled into the gap in the contact hole CL.

[0153] In this way, a plurality of contacts CC (CCs, CCt) are formed.

[0154] Thereafter, an insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the stacked body LM and the staircase region SR, and a plug V0 is formed through the insulating layer 52 to be connected to the contact CC. A plug CH is also formed through the insulating layer 52 to be connected to the pillar PL. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and upper-layer wiring MX and bit lines BL, etc., connected to the plugs V0 and CH are formed. Electrode pads, etc., for electrical conduction with the peripheral circuit CBA are also formed on the upper surface of the insulating layer 53.

[0155] It should be noted that the plugs V0, CH, upper layer wiring MX, bit line BL, etc. may be formed all at once by using, for example, a dual damascene method.

[0156] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0157] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0158] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0159] (Overview) Semiconductor memory devices such as three-dimensional nonvolatile memories are configured by stacking multiple word lines, forming some of them in a stepped shape, and connecting contacts to these stepped portions, making it possible to apply voltage to multiple word lines.

[0160] Furthermore, a stack of multiple word lines, etc., is formed by, for example, stacking multiple sacrificial layers and replacing them with a conductive material. When replacing the sacrificial layers with word lines, etc., a columnar portion penetrating the stack may be formed in the stepped portion of the stack to support the stack, which has a fragile structure. However, the columnar portion may be formed at an angle due to stress generated between various components such as a laminate, or due to oblique ion incidence during etching. The tilt due to oblique ion incidence during etching may also occur in the contact. Furthermore, when forming the columnar portion and the contact, misalignment may occur in the mask pattern used to process them. If at least one of the columnar portion and the contact is tilted or misaligned, the columnar portion and the contact may come into contact with each other.

[0161] By using the manufacturing method of the semiconductor memory device 1 of the embodiment, it is possible to prevent contact between the columnar portion HR and the contact CC, which will be described with reference to FIG.

[0162] 11 is a cross-sectional view showing an example of a method for forming contact holes CLt and CLx according to the embodiment and a comparative example. As shown in FIG.

[0163] 11(a), it is assumed that the columnar portion HRx is tilted. It is also assumed that voids VD are generated in the columnar portion HRx when the insulating layer is embedded. It is also assumed that the mask pattern 70 is misaligned in a direction approaching the already formed columnar portion HRx.

[0164] As shown in FIG. 11(b), when the contact hole CLx of the comparative example is formed, contact with, for example, the tilted columnar portion HRx may occur, and furthermore, the contact hole CLx may be connected to a void VD in the columnar portion HRx, and etching may proceed downwards below the columnar portion HRx via the void VD.

[0165] If a conductive layer is filled into a contact hole CLx in this state, the conductive layer will also fill the void VD that extends downward, which may result in electrical leakage between the adjacent lower word line WLx and the word line WLx to which the contact is connected.

[0166] The contact between the contact hole CLx and the columnar portion HRx is more likely to occur on the lower layer side of the stacked body, that is, contact is more likely to occur between the contact hole CLx, which is connected to the word line WLx in the lower layer of the stacked body, and the vicinity of the lower end of the columnar portion HRx arranged nearby.

[0167] 11(c), the columnar portion HR is tilted, and voids VD are generated within the columnar portion HR when the insulating layer is embedded. Furthermore, the mask pattern 70 is misaligned in a direction approaching the formed columnar portion HR. As a result, the opening of the mask pattern 70 and the opening CLa provided in the stopper layer STP, which should overlap in the vertical direction, do not completely overlap.

[0168] 11(d), when the contact hole CLt of the embodiment is formed, the portion of the etched bottom surface of the contact hole CLt that vertically overlaps with the tilted columnar portion HR is located outside the opening CLa of the stopper layer STP. Therefore, the contact hole CLt reaches the stopper layer STP, and the etching stops there. This makes it possible to prevent contact between the contact hole CLt and the columnar portion HR.

[0169] On the other hand, the portion of the etched bottom of the contact hole CLt that overlaps with the opening CLa in the vertical direction passes through the opening CLa and reaches the word line WL to be connected, thereby enabling the contact CCt formed from the contact hole CLt to be more reliably connected to the word line WL to be connected.

[0170] If the inclination of the columnar portion HR is due to stress or the like generated in the stacked bodies LMga, LMgb, etc. after the formation of the columnar portion HR, the stopper layer STP will also be subjected to the same stress, and therefore the relative positional relationship between the opening CLa provided in the stopper layer STP and the columnar portion HR is maintained substantially as it is.

[0171] As described above, the opening CLa is aligned with the structure below the columnar portion HR and is formed to avoid interference with the structure below the columnar portion HR. Therefore, even if the columnar portion HR is tilted due to stress, the contact hole CLt is formed through the opening CLa whose relative positional relationship with the columnar portion HR is maintained, thereby further suppressing contact between the contact hole CLt and the columnar portion HR.

[0172] The semiconductor memory device 1 of the first embodiment includes a contact CCt that extends downward from above the stepped portion SP provided in the laminate LMa, penetrating the insulating layer 51 and the stopper layer STP, and is connected to one of the plurality of word lines WL and select gate lines SGS that are processed in a stepped shape, thereby making it possible to prevent contact between the contact CCt and other components.

[0173] In the above-described embodiment, the stopper layer STP is, for example, a silicon nitride layer. However, the stopper layer STP may be, for example, a polysilicon layer, an amorphous silicon layer, or a metal oxide layer, as long as it contains a material different from that of the insulating layer 51 and has etching selectivity with respect to the insulating layer 51. The metal oxide layer may be, for example, an aluminum oxide (Al2O3) layer.

[0174] In the above-described embodiment, the opening CLa of the stopper layer STP is smaller than the opening area of ​​the contact hole CLt, for example. However, the opening CLa may be substantially equal to the opening area of ​​the contact hole CLt, for example. In this case, when there is no misalignment with the opening CLa, the diameters of the contact portions CCa and CCb of the contact CCt can be substantially equal.

[0175] However, the area of ​​the opening CLa can be determined based on, for example, the distance between the columnar portion HR and the contact CCt, more preferably, the distance between their bottom ends, and the size of the void VD that may occur in the columnar portion HR.

[0176] (Variation) Next, a semiconductor memory device 2 according to a modification of the embodiment will be described with reference to Fig. 12. The semiconductor memory device 2 according to the modification includes a stopper layer STPp made of a material different from the stopper layer STP described above.

[0177] FIG. 12 is a diagram showing an example of the configuration of a semiconductor memory device 2 according to a modification of the embodiment.

[0178] More specifically, Fig. 12(a) is a cross-sectional view taken along the X direction in the staircase region SR of the semiconductor memory device 2. Fig. 12(b) is a cross-sectional view taken along the XY plane at the height of the select gate line SGD in the staircase region SR of the semiconductor memory device 2. Note that Fig. 12(a) omits the structure below the insulating layer 60 and above an insulating layer 53, which will be described later.

[0179] In FIG. 12, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0180] 12, the semiconductor memory device 2 of the modified example includes a stopper layer STPp instead of the stopper layer STP described above. The stopper layer STPp is a conductive layer such as a metal layer. The metal layer may be, for example, a tungsten layer or a molybdenum layer.

[0181] Since the stopper layer STPp is a conductive layer, the stopper layer STPp is provided separately for each contact CCt in the modified semiconductor memory device 2. Although the contact CCt has the insulating layer 55 on its sidewall, by separating the stopper layer STPp for each contact CCt, it is possible to more reliably prevent conduction between the contacts CCt.

[0182] As shown in Fig. 12(b), the individually separated stopper layers STPp are formed to occupy an area larger than at least the cross section of the contact portion CCb, which is the upper structure of the contact CCt. Fig. 12(b) shows a stopper layer STPp having a circular shape as an example. However, the stopper layer STPp may have other shapes, such as a square or other polygonal shapes.

[0183] Such a stopper layer STPp can be obtained by, for example, performing processing for separating the contacts CCt in parallel with the formation of the opening CLa shown in FIG. 4B in the above-described embodiment.

[0184] According to the semiconductor memory device 2 of the modified example, the stopper layers STPp are distributed at positions corresponding to the plurality of contacts CCt, respectively, thereby making it possible to suppress conduction between the contacts CCt even if the stopper layers STPp are conductive.

[0185] In the semiconductor memory device 2 of the modified example, the stopper layer STPp contains at least one of tungsten and molybdenum as a main component. By using a metal material for the stopper layer STPp in this manner, it is possible to further increase the etching selectivity with respect to the insulating layer 51, which is, for example, a silicon oxide layer.

[0186] In addition, the semiconductor memory device 2 of the modified example has the same effects as the semiconductor memory device 1 of the above-described embodiment.

[0187] (Other variations) In the above-described embodiment and modified examples, the columnar portions HR are formed after the staircase structure is formed. However, the columnar portions HR may be formed before the staircase structure is formed. In this case, when the staircase structure is formed, the upper columnar portions HR are partially lost along with the stacked bodies LMsa and LMsb that are processed into a staircase shape. Even in this case, the lower columnar portions HR remain, and therefore, by applying the above configuration, the risk of contact with the contacts CCt can be reduced.

[0188] In the above-described embodiment and modified examples, in a method of drawing out a plurality of word lines WL etc. on one side, contacts are arranged alternately in the Y direction for every two block regions BLK in the staircase region SR on one side in the X direction. However, in a method of drawing out word lines WL etc. on one side, it is sufficient to arrange contacts on one side in the X direction within the same block region BLK, and the arrangement order is not limited to the above.

[0189] In the above-described embodiment and modified example, the laminate LM has a two-tier structure in which two laminates LMa and LMb are stacked one on top of the other. However, the configuration of the laminate is not limited to two tiers and may be three or more tiers.

[0190] In the above-described embodiment and modified examples, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0191] In the above-described embodiment and modified example, the peripheral circuit CBA is arranged above the stack LM, but the peripheral circuit may be arranged below the stack or on the same layer as the stack.

[0192] When the peripheral circuit is disposed below the stack, the source line and the stack can be formed on an insulating layer of a semiconductor substrate having the peripheral circuit covered with the insulating layer, for example. When the peripheral circuit is disposed on the same layer as the stack, the stack can be formed at a different position from the peripheral circuit on the semiconductor substrate on which the peripheral circuit is formed.

[0193] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0194] 1,2...semiconductor memory device, CC, CCs, CCt...contact, CCa, CCb...contact portion, CLa...opening, HR...columnar portion, LI...plate-shaped contact, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, 51...insulating layer, PL...pillar, SGD, SGS...select gate line, SP...staircase portion, SR...staircase region, ST...slit, STP, STPp...stopper layer, WL...word line.

Claims

1. a first laminate in which a plurality of first conductive layers are laminated and spaced apart from each other, the first conductive layers having a first staircase portion formed by processing the plurality of first conductive layers into a staircase shape; a second laminated body disposed above the first laminated body, in which a plurality of second conductive layers are laminated and spaced apart from one another, and in which the plurality of second conductive layers are processed into a stepped shape to have a second stepped portion extending continuously from the first stepped portion; a first insulating layer covering the first and second step portions; a first layer containing a material different from that of the first insulating layer and disposed in the first insulating layer above the first step portion at a height position between the first and second stacked bodies; a first contact extending downward from above the first step portion through the first insulating layer and the first layer, and connected to any one of the plurality of first conductive layers processed in a stepped shape; Semiconductor memory device.

2. a cross-sectional area of ​​the first contact as viewed in a stacking direction of the first and second stacked bodies varies discontinuously between an upper side and a lower side of the first layer; 2. The semiconductor memory device according to claim 1.

3. a cross-sectional area of ​​the first contact as viewed from the stacking direction at a height position of the upper surface of the first layer is larger than a cross-sectional area of ​​the first contact as viewed from the stacking direction at a height position of the lower surface of the first layer; 3. The semiconductor memory device according to claim 2.

4. a central axis of the first contact, as viewed from a stacking direction of the first and second laminates, is misaligned between an upper side and a lower side of the first layer; 2. The semiconductor memory device according to claim 1.

5. a second contact extending downward from above the second step portion through the first insulating layer and connected to any one of the plurality of second conductive layers processed in a stepped shape; a cross-sectional area of ​​the second contact as viewed in the stacking direction continuously changes from an upper end to a lower end; 3. The semiconductor memory device according to claim 2.

6. a plurality of third contacts extending downward from above the first step portion through the first insulating layer and the first layer and connected to each of the plurality of first conductive layers processed in a stepped shape; the plurality of third contacts include the first contact; 2. The semiconductor memory device according to claim 1.

7. The first layer comprises: continuously extending over the entire area in which the plurality of third contacts are arranged; 7. The semiconductor memory device according to claim 6.

8. The first insulating layer comprises: It contains silicon oxide as its main component, The first layer comprises: Contains at least one of silicon nitride, silicon, and metal oxide as a main component; 8. The semiconductor memory device according to claim 7.

9. The first layer comprises: The third contacts are disposed in a dispersed manner at positions corresponding to the third contacts, respectively.

7. The semiconductor memory device according to claim 6.

10. The first insulating layer comprises: It contains silicon oxide as its main component, The first layer comprises: Contains at least one of tungsten and molybdenum as a main component.

10. The semiconductor memory device according to claim 9.

11. a first laminate including a plurality of first sacrificial layers stacked at intervals from one another, the plurality of first sacrificial layers being processed into a staircase shape to form a first staircase portion; covering the first step portion with a first insulating layer; forming a first layer on the first insulating layer, the first layer including a material different from that of the first insulating layer; a second sacrificial layer is formed on the first stacked body so as to be spaced apart from one another, and the second sacrificial layers are processed into a stepped shape to form a second stacked body having a second stepped portion extending continuously from the first stepped portion; forming an additional first insulating layer to further cover the second step portion and the first layer; replacing the first and second sacrificial layers with a conductive material to form a plurality of first conductive layers included in the first stack and a plurality of second conductive layers included in the second stack; forming a first contact extending downward from above the first step portion through the first insulating layer and the first layer and connected to any one of the plurality of first conductive layers processed in a stepped shape; The first layer comprises: The first contact is formed with an opening at a portion through which the first contact passes, The first contact comprises: a conductive film is formed through the first insulating layer so as to extend in the vertical direction of the first layer through the opening, A method for manufacturing a semiconductor memory device.

12. a columnar portion is further formed on the first step portion, the columnar portion extending to a height position of the first stacked body; The opening is formed in alignment with the post; The method for manufacturing a semiconductor memory device according to claim 11.

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