Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

To provide a semiconductor memory device capable of improving electrical characteristics, and a method of manufacturing a semiconductor memory device.SOLUTION: A semiconductor memory device comprises a first chip and a second chip which is stuck with the first chip. The second chip includes a laminate, a columnar body, a semiconductor layer, a first wire and a second wire. The columnar body includes at least a first end portion arriving at a first end of the laminate. The semiconductor layer includes a first semiconductor part, a second semiconductor part, and a third semiconductor part. The first semiconductor part includes a first portion, which is disposed along the first end of the laminate, and a second portion covering the first end portion of the columnar body. The first semiconductor part and the second semiconductor part contain an impurity forming a p-type semiconductor. The third semiconductor part contains an impurity forming an n-type semiconductor. A first gate electrode layer includes a portion which overlaps the first semiconductor part when viewed in a first direction.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-41054 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor memory device and a method for manufacturing the semiconductor memory device that can improve electrical characteristics. [Means for solving the problem]

[0005] In one embodiment, the semiconductor memory device includes a first chip and a second chip. The second chip is bonded to the first chip. The second chip has a stacked body, a pillar, a semiconductor layer, a first wiring, and a second wiring. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are alternately stacked layer by layer in a first direction. The stacked body has a first end that is an end on a first side in the first direction opposite the first chip. The pillar extends in the first direction within the stacked body. The pillar has a first end that reaches at least the first end of the stacked body. The semiconductor layer has a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion arranged along the first end of the stacked body and a second portion covering the first end of the pillar. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first semiconductor portion and the second semiconductor portion contain impurities that form p-type semiconductors. The third semiconductor portion contains impurities that form n-type semiconductors. Of the multiple gate electrode layers, a first gate electrode layer that is closest to the first end of the stack includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing a part of a semiconductor memory device according to a first embodiment. [Figure 4] 4 is an enlarged cross-sectional view showing a region surrounded by line F4 of the semiconductor memory device shown in FIG. 3. [Figure 5] FIG. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device shown in FIG. 4. [Figure 6]FIG. 4 is a cross-sectional view of the semiconductor memory device shown in FIG. 3 taken along line F6-F6. [Figure 7] FIG. 2 is a cross-sectional view illustrating a semiconductor layer according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view of the configuration shown in FIG. 7 taken along line F8-F8. [Figure 9] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 5A and 5B are diagrams for explaining a read operation of the semiconductor memory device according to the first embodiment. [Figure 13] FIG. 3 is a cross-sectional view illustrating a read operation of the semiconductor memory device according to the first embodiment. [Figure 14] FIG. 3 is a diagram for explaining a write operation of the semiconductor memory device according to the first embodiment. [Figure 15] 5A and 5B are diagrams for explaining an erase operation of the semiconductor memory device according to the first embodiment. [Figure 16] 3 is a cross-sectional view illustrating an erase operation of the semiconductor memory device according to the first embodiment. FIG. [Figure 17] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a second embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing a part of a semiconductor memory device according to a third embodiment. [Figure 19] 19 is a cross-sectional view of the configuration shown in FIG. 18 taken along line F19-F19. [Figure 20] FIG. 10 is a plan view showing a part of a semiconductor memory device according to a fourth embodiment. [Figure 21] FIG. 11 is a plan view showing a part of a semiconductor memory device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A semiconductor memory device and a method for manufacturing the semiconductor memory device according to the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions will be assigned the same reference numerals. Further, duplicate descriptions of those components may be omitted. In the following description, reference numerals ending with a distinguishing number or letter may have the number or letter omitted if they do not need to be distinguished from each other.

[0008] In this application, terms are defined as follows: "Parallel," "orthogonal," or "same" may include the cases of "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. That is, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected via another element interposed therebetween. "Overlapping" is not limited to the case where multiple elements are in contact with each other, but may also include the case where multiple elements are separated (the case where the projected images of multiple elements overlap when viewed from a certain direction).

[0009] The +X direction, −X direction, +Y direction, −Y direction, +Z direction, and −Z direction are defined as follows: The +X direction is the direction in which the word lines WL, which will be described later, extend (see FIG. 3). The −X direction is the opposite direction of the +X direction. When the +X direction and the −X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction that intersects (e.g., is perpendicular to) the X direction. The +Y direction is a direction in which the bit lines BL extend (see FIG. 6). The −Y direction is the opposite direction of the +Y direction. When the +Y direction and the −Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (e.g., is perpendicular to) the X direction and the Y direction. The +Z direction is the direction from the bit lines BL, which will be described later, toward the stack 40 (see FIG. 3). The −Z direction is the opposite direction of the +Z direction. When the +Z direction and the −Z direction are not distinguished, they are simply referred to as the Z direction. In this application, the +Z direction side may be referred to as "upper" and the -Z direction side as "lower." However, these expressions are used for convenience of explanation and do not define the direction of gravity. The Z direction is an example of a "first direction." The Y direction is an example of a "second direction." Furthermore, in the drawings described below, illustrations of configurations that are not relevant to the explanation may be omitted.

[0010] (First embodiment) <1. Configuration of Semiconductor Memory Device> 1 is a block diagram showing a portion of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 1). A block BLK is a collection of memory cell transistors. A block BLK is used as a unit for erasing data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0012] The command register 12 holds the command CMD that the semiconductor memory device 1 receives from the host device. The address register 13 holds address information ADD that the semiconductor memory device 1 receives from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0013] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line and transfers the determination result to the host device as read data DAT.

[0014] 2. Electrical Configuration of Memory Cell Array Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. Fig. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, five strings STR0 to STR4).

[0015] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0016] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to one of word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, thereby retaining data in a non-volatile manner.

[0017] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. The drain-side select transistor STD connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain-side select gate line SGD.

[0018] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to a source line SL. The control gate of the source-side select transistor STS is connected to a source-side select gate line SGS. The source-side select transistor STS connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side select gate line SGS.

[0019] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn. In the same string STR, the control gates of the drain-side select transistors STD are commonly connected to the corresponding drain-side select gate line SGD. The control gates of the source-side select transistors STS are commonly connected to the source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS to which the same column address is assigned in multiple strings STR.

[0020] <3. Structure of semiconductor memory device> Next, the structure of the semiconductor memory device 1 will be described. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0021] <3.1 First Chip> The first chip 2 is a circuit chip including a peripheral circuit, and includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0022] The semiconductor substrate 21 is, for example, a substrate that serves as the base of the first chip 2. At least a portion of the semiconductor substrate 21 is plate-shaped and extends along the X and Y directions. The semiconductor substrate 21 is made of, for example, a semiconductor material such as silicon.

[0023] The peripheral circuit 22 is a circuit for causing the memory cell array 11 to function. The peripheral circuit 22 includes a plurality of transistors 22a and a plurality of wirings 22b. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. An insulating section 23 covers the peripheral circuit 22. A plurality of pads 24 are provided on the surface of the insulating section 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0024] <3.2 Second Chip> The second chip 3 is an array chip including a memory cell array 11. The second chip 3 has, for example, the memory cell array 11, an insulating section 31, a plurality of pads 32, and an insulating section 33. Here, the insulating section 31, the plurality of pads 32, and the insulating section 33 will be described, and the memory cell array 11 will be described later.

[0025] The insulating section 31 covers the memory cell array 11 from the -Z direction side. A plurality of pads 32 are provided on the surface of the insulating section 31. Each pad 32 is electrically connected to a wiring (e.g., wiring 71 or wiring 72) included in a wiring section 70 of the memory cell array 11, which will be described later. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3 face to face. The insulating section 33 covers the memory cell array 11 from the +Z direction side.

[0026] <4. Memory Cell Array> Next, the memory cell array 11 will be described. As shown in FIG. 3 , the memory cell array 11 includes an array region AR and a hook-up region FR. The array region AR is provided with a plurality of memory pillars MH (described later) and is capable of storing data. The hook-up region FR is provided with a plurality of contacts CC (described later) and connects a plurality of conductive layers 41 (described later) to a wiring portion 70. The hook-up region FR is provided, for example, on both sides of the array region AR in the X direction. The hook-up region FR is not provided with memory pillars MH. In the hook-up region FR, for example, the ends of the plurality of conductive layers 41 are arranged in a stepped pattern. Alternatively, the hook-up region FR may have through contacts that penetrate the conductive layers 41 as the contacts CC. Furthermore, the hook-up region FR is provided with a support HR that supports a plurality of insulating layers 42 in a replacement process (described later).

[0027] As shown in FIG. 3, the memory cell array 11 includes, for example, a stack 40, a semiconductor layer 50, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the conductive layer, a wiring portion 70, a support HR, and a plurality of separation portions 80 (see FIG. 6).

[0028] 4.1 Laminate First, the laminate 40 will be described. 4 is an enlarged cross-sectional view of the region surrounded by line F4 of the semiconductor memory device 1 shown in FIG. 3. The stacked body 40 has a first end 40e1. The first end 40e1 is the end on the +Z direction side opposite the first chip 2. For example, the first end 40e1 is the end on the +Z direction side opposite the semiconductor substrate 21. The stacked body 40 also includes, for example, a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating layer 43. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction.

[0029] The conductive layers 41 extend in the X and Y directions. Each conductive layer 41 is made of a conductive material such as tungsten or molybdenum. The conductive layers 41 are an example of a "gate electrode layer."

[0030] Of the multiple conductive layers 41, one or more (for example, multiple) conductive layers 41 located at the bottom function as drain-side select gate lines SGD. The drain-side select gate lines SGD are provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersections between the drain-side select gate lines SGD and channel layers 62 (described later) of each memory pillar MH function as the above-mentioned drain-side select transistors STD.

[0031] Of the multiple conductive layers 41, one or more (for example, multiple) conductive layers 41 located at the top function as source-side select gate lines SGS. The source-side select gate lines SGS are provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersections between the source-side select gate lines SGS and the channel layers 62 of each memory pillar MH function as the source-side select transistors STS described above.

[0032] Of the multiple conductive layers 41, at least some of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain-side select gate lines SGD and the source-side select gate lines SGS function as word lines WL. The word lines WL are provided in common to the multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersections between the word lines WL and the channel layers 62 of each memory pillar MH function as memory cell transistors MT. The memory cell transistors MT will be described in detail later.

[0033] In this embodiment, the plurality of conductive layers 41 include a conductive layer 41A, a conductive layer 41B, and a conductive layer 41C.

[0034] The conductive layer 41A is the uppermost conductive layer 41 among the multiple conductive layers 41. The conductive layer 41A is the conductive layer 41 closest to the first end 40e1 of the stacked body 40 among the multiple conductive layers 41. The conductive layer 41A is an example of a "first gate electrode layer."

[0035] The conductive layer 41B is one of the conductive layers 41 included in the plurality of conductive layers 41. The conductive layer 41B is, for example, a conductive layer that functions as the uppermost word line WL among the plurality of word lines WL. The conductive layer 41B is, for example, a conductive layer 41 that is closest to the source-side select gate line SGS among the plurality of word lines WL. Note that the conductive layer 41B may be a conductive layer 41 that functions as a drain-side select gate line SGD, or a conductive layer 41 that functions as a source-side select gate line SGS. The conductive layer 41B is an example of a "second gate electrode layer."

[0036] The conductive layer 41C is a conductive layer 41 adjacent to the conductive layer 41B in the Z direction. The conductive layer 41C is, for example, a conductive layer 41 located immediately below the conductive layer 41B. The conductive layer 41C is, for example, a conductive layer that functions as a word line WL. Note that the conductive layer 41C may be a conductive layer 41 that functions as a drain-side select gate line SGD, or a conductive layer 41 that functions as a source-side select gate line SGS. The conductive layer 41C is an example of a "third gate electrode layer."

[0037] The insulating layer 42 is an interlayer insulating film provided between two conductive layers 41 adjacent to each other in the Z direction, and insulates the two conductive layers 41 from each other. The insulating layer 42 extends in the X and Y directions. The insulating layer 42 is formed, for example, from a film containing silicon and oxygen. The insulating layer 42 is formed by supplying a raw material gas and depositing it while causing a chemical reaction. The insulating layer 42 is formed, for example, by chemical vapor deposition (CVD). The insulating layer 42 contains carbon and other materials that are mixed in due to a chemical reaction during film formation.

[0038] The multiple insulating layers 42 include an insulating layer 42A. The insulating layer 42A is an interlayer insulating film provided between the conductive layer 41B (second gate electrode layer) and the conductive layer 41C (third gate electrode layer) to insulate the two conductive layers 41B and 41C. The insulating layer 42A is an example of a "first insulating layer."

[0039] The insulating layer 43 is an insulating layer provided above the conductive layer 41A (first gate electrode layer). The insulating layer 43 is an insulating layer disposed between the conductive layer 41A (first gate electrode layer) and the first end 40e1 of the stacked body 40. The end of the insulating layer 43 on the +Z direction side forms the first end 40e1 of the stacked body 40. The insulating layer 43 extends along the X direction and the Y direction. The insulating layer 42 is formed, for example, of a film containing silicon and oxygen.

[0040] The insulating layer 43 is, for example, a thermal oxide film. The insulating layer 43 is a layer formed by heating a silicon layer in an oxygen atmosphere to oxidize part or all of the silicon layer. Compared to the insulating layer 42, the insulating layer 43 has a lower content of materials other than silicon and oxygen (for example, carbon). The insulating layer 43 and the insulating layer 42 have different compositions (for example, film quality). The insulating layer 43 is a film with higher voltage resistance than the insulating layer 42. The insulating layer 43 is an example of a "second insulating layer."

[0041] In this embodiment, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is smaller than the Z-direction thickness (e.g., minimum thickness) T1 of the insulating layer 42. For example, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is half or less of the Z-direction thickness (e.g., minimum thickness) T1 of the insulating layer 42. In this embodiment, the "Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43" corresponds to the Z-direction distance (e.g., the shortest distance) between the conductive layer 41A and a first semiconductor portion 51 described later.

[0042] From another perspective, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is thinner than the Z-direction thickness T3 of the conductive layer 41A. For example, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is half or less of the Z-direction thickness T3 of the conductive layer 41A. From yet another perspective, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is thinner than the Z-direction thickness T4 of the conductive layer 41B. For example, the Z-direction thickness (e.g., minimum thickness) T2 of the insulating layer 43 is half or less of the Z-direction thickness T4 of the conductive layer 41B.

[0043] 4.2 Semiconductor layer (source line) The semiconductor layer 50 is provided on the first end 40e1 of the stacked body 40. The semiconductor layer 50 extends in the X and Y directions. The semiconductor layer 50 is made of a material containing silicon. The semiconductor layer 50 is a layer that functions as a source line SL. The semiconductor layer 50 will be described in detail later.

[0044] <4.3 Memory pillar> The memory pillars MH are aligned in the X and Y directions (see FIG. 3). Each memory pillar MH extends in the Z direction within the stack 40 and penetrates the stack 40. The memory pillar MH is an example of a "columnar body."

[0045] Fig. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device 1 shown in Fig. 4. The memory pillar MH includes, for example, a memory film (multilayer film) 61, a channel layer 62, an insulating portion 63, a cavity portion (air gap) 64, and a cap portion 65 (see Fig. 4).

[0046] The memory film 61 is provided on the outer periphery of the channel layer 62. The memory film 61 is located between the plurality of conductive layers 41 and the channel layer 62. The memory film 61 includes, for example, a block insulating film 61a, a charge trapping film 61b, and a tunnel insulating film 61c.

[0047] The block insulating film 61a is provided between the plurality of conductive layers 41 and the charge trap film 61b. The block insulating film 61a is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 61b. The block insulating film 61a is formed in a ring shape and extends in the Z direction. For example, the block insulating film 61a extends over the entire length of the memory pillar MH in the Z direction except for a first end MHe1 of the memory pillar MH, which will be described later. The block insulating film 61a is a laminated structure film in which a plurality of insulating films, such as a film containing silicon and oxygen or a film containing metal and oxygen, are stacked. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 61a may include a high-dielectric-constant material (high-k material) such as silicon nitride or hafnium oxide.

[0048] The charge trap film 61b is located between the block insulating film 61a and the tunnel insulating film 61c. The charge trap film 61b is formed in a ring shape and extends in the Z direction. For example, the charge trap film 61b extends over the entire length of the memory pillar MH in the Z direction except for the first end MHe1 of the memory pillar MH. The charge trap film 61b is a functional film that has a large number of crystal defects (trap levels) and can trap charges in the crystal defects. The charge trap film 61b is formed of, for example, a film containing silicon and nitrogen. The portions of the charge trap film 61b adjacent to each word line WL are an example of a "charge storage section" that can store information by accumulating charges.

[0049] The tunnel insulating film 61c is provided between the channel layer 62 and the charge trap film 61b. The tunnel insulating film 61c is, for example, annular along the outer peripheral surface of the channel layer 62 and extends in the Z direction along the channel layer 62. The tunnel insulating film 61c extends, for example, over the entire length of the memory pillar MH in the Z direction except for the first end MHe1 of the memory pillar MH. The tunnel insulating film 61c is a potential barrier between the channel layer 62 and the charge trap film 61b. The tunnel insulating film 61c is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0050] The channel layer 62 is provided inside the memory film 61. The channel layer 62 is formed in a ring shape. The channel layer 62 extends in the Z direction. For example, the channel layer 62 covers the entire length of the memory pillar MH in the Z direction. The channel layer 62 is formed of a semiconductor material such as polysilicon. The channel layer 62 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 62 forms a channel to electrically connect the bit line BL and the source line SL.

[0051] As a result, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) memory cell transistor MT is formed by the end of the word line WL adjacent to the memory pillar MH, the block insulating film 61a, the charge trap film 61b, the tunnel insulating film 61c, and the channel layer 62. Note that the memory film 61 may have a floating gate type charge storage portion (floating gate electrode) instead of the charge trap film 61b as the charge storage portion. The floating gate electrode is formed of, for example, polysilicon containing impurities.

[0052] The insulating portion 63 is provided inside the channel layer 62. The insulating portion 63 fills at least a portion of the inside of the channel layer 62. The insulating portion 63 is formed of a film containing silicon and oxygen. In this embodiment, the insulating portion 63 is formed in a ring shape along the inner circumferential surface of the channel layer 62 so as to form a cavity (air gap) 64 inside. Note that the cavity 64 does not necessarily have to exist. The insulating portion 63 extends in the Z direction. For example, the insulating portion 63 spans most of the memory pillar MH in the Z direction except for the lower end of the memory pillar MH (see FIG. 4).

[0053] Returning to FIG. 4, the cap portion 65 will now be described. The cap portion 65 is provided below the insulating portion 63. The cap portion 65 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 65 may be doped with impurities. The cap portion 65 is disposed on the inner periphery side of the lower end portion of the memory film 61, and is formed integrally with the channel layer 62. The cap portion 65, together with the lower end portion of the channel layer 62, forms the lower end portion of the memory pillar MH. A contact CH contacts the cap portion 65 from the -Z direction side.

[0054] Next, the first end MHe1 of the memory pillar MH will be described. In this embodiment, the first end MHe1 of the memory pillar MH protrudes from the first end 40e1 of the stack 40 toward the +Z direction. The first end MHe1 of the memory pillar MH contacts the semiconductor layer 50. At the first end MHe1 of the memory pillar MH, the memory film 61 is not present, and the channel layer 62 is exposed to the outside of the memory pillar MH. At the first end MHe1, the channel layer 62 of the memory pillar MH contacts the semiconductor layer 50 at a position on the +Z direction side of the first end 40e1 of the stack 40. The first end MHe1 of the memory pillar MH is an example of a "first end." Note that the first end MHe1 of the memory pillar MH does not necessarily have to protrude from the first end 40e1 of the stack 40 toward the +Z direction. It is sufficient that the first end MHe1 of the memory pillar MH reaches at least the first end 40e1 of the stack 40. For example, the first end MHe1 of the memory pillar MH may be in contact with the semiconductor layer 50 at the same position as the first end 40e1 of the stack 40.

[0055] 4.4 Bit lines Next, returning to FIG. 3, the bit lines BL will be described. The bit line BL is a wiring for selecting one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below (on the -Z direction side of) the stacked body 40. The multiple bit lines BL are spaced apart in the X direction and lined up in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass below the corresponding multiple memory pillars MH.

[0056] Each bit line BL is connected to the channel layer 62 of the memory pillar MH via a contact VY and a contact CH. This allows any memory cell transistor MT to be selected from multiple memory cell transistors MT arranged three-dimensionally by combining word lines WL and bit lines BL.

[0057] 4.5 Contacts for Conductive Layers 3, the contacts CC are electrical connection parts that electrically connect the conductive layer 41 and wiring 72 (described later) included in the wiring part 70. The multiple contacts CC are arranged, for example, corresponding to the hook-up regions FR of the memory cell array 11. The multiple contacts CC extend in the Z direction and are connected to different conductive layers 41.

[0058] <4.6 Wiring section> Next, the wiring section 70 will be described. The wiring section 70 is disposed, for example, between the stacked body 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, a plurality of wirings 72, a plurality of wirings 75 (only one of which is shown in FIG. 6), and a plurality of wirings 76 (only one of which is shown in FIG. 6). The wirings 75 and the wirings 76 will be described later.

[0059] The wiring 71 is an electrical connection portion that electrically connects the bit line BL and the pad 32. The multiple wirings 71 are arranged, for example, below the multiple bit lines BL. Each wiring 71 extends, for example, in the X direction or the Y direction. A via V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0060] The wiring 72 is an electrical connection portion that electrically connects the conductive layer contact CC and the pad 32. The wiring 72 is electrically connected to the conductive layer 41 via the conductive layer contact CC. A voltage is applied to the wiring 72 to select the conductive layer 41 (word line WL, drain side select gate line SGD, or source side select gate line SGS).

[0061] <4.7 Support> Next, the support HR will be described. The support HR is provided in the hook-up region FR. The support HR penetrates the stack 40 in the Z direction in the hook-up region FR. The support HR is, for example, a columnar body having the same structure as the memory pillar MH. Note that the support HR may be formed of an insulating portion. The support HR supports the multiple insulating layers 42 in the replacement process described below.

[0062] <5. Divided part> Next, the dividing portion 80 will be described. 6 is a cross-sectional view of the semiconductor memory device 1 shown in FIG. 3 taken along line F6-F6. In this embodiment, a plurality of dividing portions 80 are provided in the stacked body 40. The plurality of dividing portions 80 are arranged separately in the Y direction. Each of the plurality of dividing portions 80 extends in the Z direction within the stacked body 40, and divides one or more conductive layers 41, including the lowest layer among the plurality of conductive layers 41, in the Y direction. The plurality of dividing portions 80 includes, for example, a plurality of dividing portions ST and a plurality of dividing portions SHE.

[0063] <5.1 Separation ST> The dividing portions ST are walls that divide the laminate 40 in the Y direction. The dividing portions ST are arranged separately in the Y direction. The dividing portions ST extend in the Z direction, penetrate the laminate 40, and extend in the X direction. That is, the dividing portions ST are walls that extend along the Z direction and the X direction. The dividing portions ST divide all of the conductive layers 41 included in the laminate 40 in the Y direction. The dividing portions ST include, for example, insulating portions STa and conductive portions STb.

[0064] The insulating portions STa extend in the Z direction and penetrate the laminated body 40. The insulating portions STa divide each of the multiple conductive layers 41 included in the laminated body 40 in the Y direction. The insulating portions STa are formed of, for example, a film containing silicon and oxygen.

[0065] The conductive portion STb is provided inside the insulating portion STa. The conductive portion STb extends in the Z direction and penetrates the stack 40. The upper end of the conductive portion STb is in contact with the semiconductor layer 50 (source line SL). The conductive portion STb is made of a conductive material such as tungsten or molybdenum. The conductive portion STb may function as, for example, an electrical connection portion that connects the semiconductor layer 50 (source line SL) and wiring in the memory cell array 11.

[0066] The dividing portion ST may be formed of only one of the insulating portion STa and the conductive portion STb. For example, the dividing portion ST may be formed of only an insulator or only a conductor.

[0067] <5.2 Divided part SHE> The dividing portion SHE is a dividing portion that is shallower in the Z direction than the dividing portion ST, and is a wall portion that divides the lower end portion of the stack 40 in the Y direction. The dividing portions SHE are arranged separately in the Y direction. In this embodiment, a plurality of (for example, four) dividing portions SHE are present between two dividing portions ST adjacent to each other in the Y direction. The dividing portion SHE is provided at the lower end portion of the stack 40, and extends in the Z direction partway through the stack 40, and also extends in the X direction. In other words, the dividing portion SHE is a wall portion that extends along the Z direction and the X direction.

[0068] The dividing portion SHE penetrates some of the conductive layers 41, including the lowest layer, of the plurality of conductive layers 41, and divides the some of the conductive layers 41 in the Y direction. For example, the dividing portion SHE penetrates each of all of the conductive layers 41 that function as drain-side select gate lines SGD. On the other hand, the dividing portion SHE does not reach the conductive layers 41 that function as word lines WL. The dividing portion SHE divides only the conductive layers 41 that function as drain-side select gate lines SGD in the Y direction. The dividing portion SHE is formed, for example, from a film containing silicon and oxygen.

[0069] <6. Structures related to semiconductor layer (source line)> Next, the structure relating to the semiconductor layer 50 will be described. FIG. 7 is a cross-sectional view illustrating the semiconductor layer 50. For ease of explanation, FIG. 7 illustrates only two memory pillars MH between two separating portions ST (ST1, ST2) adjacent to each other in the Y direction. In reality, as shown in FIG. 6, among the multiple separating portions ST, many memory pillars MH exist between two separating portions ST (ST1, ST2) adjacent to each other in the Y direction. Separating portion ST1 is an example of a "first separating portion." Separating portion ST2 is an example of a "second separating portion."

[0070] 7, the semiconductor layer 50 is provided along the first end 40e1 of the stacked body 40. In this embodiment, the semiconductor layer 50 is provided on the first end 40e1 of the stacked body 40. The semiconductor layer 50 includes, for example, a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53.

[0071] <6.1 First Semiconductor Section> The first semiconductor portion 51 is a portion that is connected to first ends MHe1 of the multiple memory pillars MH. The first semiconductor portion 51 extends, for example, in the Y direction so as to cover the first ends MHe1 of the multiple memory pillars MH. In this embodiment, the first semiconductor portion 51 extends linearly in the X direction (see FIG. 8). The first semiconductor portion 51 includes, for example, a first portion 51a and multiple second portions 51b.

[0072] The first portion 51a is provided along the first end 40e1 of the laminate 40. For example, the first portion 51a is provided on the first end 40e1 of the laminate 40. For example, the first portion 51a is a layer extending along the X direction and the Y direction on the first end 40e1 of the laminate 40. The first portion 51a is disposed between the second portions 51b in the X direction and the Y direction, and connects the second portions 51b together. Furthermore, an end portion of the first portion 51a on the +Y direction side is connected to the second semiconductor portion 52 in the Y direction. An end portion of the first portion 51a on the −Y direction side is connected to the third semiconductor portion 53 in the Y direction.

[0073] The multiple second portions 51b are provided in one-to-one correspondence with the multiple memory pillars MH when viewed from the Z direction (see FIG. 8). Each second portion 51b covers a first end MHe1 of the memory pillar MH from the +Z direction side. In this embodiment, the first ends MHe1 of the multiple memory pillars MH protrude from the first end 40e1 of the stack 40 in the +Z direction. In this embodiment, each second portion 51b protrudes from the first portion 51a in the +Z direction and covers the first end MHe1 of the memory pillar MH from the +Z direction side.

[0074] The first semiconductor portion 51 contains impurities (impurities that become acceptors) that form a p-type semiconductor, and is p-type (for example, p- An "acceptor" is an element with fewer valence electrons than a tetravalent element, such as a trivalent element. An example of an acceptor is boron (B).

[0075] <6.2 Second Semiconductor Section> The second semiconductor portion 52 is a portion to which the wiring 75 of the wiring portion 70 is connected. The second semiconductor portion 52 is located, for example, on the +Y direction side with respect to the first semiconductor portion 51. The second semiconductor portion 52 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the second semiconductor portion 52 is provided on the first end 40e1 of the stacked body 40. The second semiconductor portion 52 includes, for example, a first portion 52a and a second portion 52b.

[0076] The first portion 52a is provided along the first end 40e1 of the stacked body 40. For example, the first portion 52a is provided on the first end 40e1 of the stacked body 40. The thickness of the first portion 52a in the Z direction is the same as the thickness of the first portion 51a of the first semiconductor portion 51 in the Z direction.

[0077] The second portion 52b covers the first end STe1 of the first dividing portion ST1 from the +Z direction side. In the present embodiment, the first end STe1 of the first dividing portion ST1 protrudes in the +Z direction from the first end 40e1 of the stacked body 40. In the present embodiment, the second portion 52b protrudes in the +Z direction from the first portion 52a and covers the first end STe1 of the first dividing portion ST1 from the +Z direction side.

[0078] In this embodiment, the second semiconductor portion 52 overlaps at least a part of the dividing portion ST1 when viewed from the Z direction. The second semiconductor portion 52 extends linearly in the X direction along the dividing portion ST1, for example (see FIG. 8).

[0079] The second semiconductor portion 52 contains impurities (impurities that become acceptors) that form a p-type semiconductor, and is p-type (for example, p +In this embodiment, the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51. The impurities that form the second semiconductor portion 52 may be the same as or different from the impurities that form the first semiconductor portion 51.

[0080] <6.3 Third Semiconductor Section> The third semiconductor portion 53 is a portion to which the wiring 76 of the wiring portion 70 is connected. The third semiconductor portion 53 is located, for example, on the -Y direction side with respect to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51 in the Y direction. In this embodiment, the third semiconductor portion 53 is provided on the first end 40e1 of the stacked body 40. The third semiconductor portion 53 has, for example, a first portion 53a and a second portion 53b.

[0081] The first portion 53a is provided along the first end 40e1 of the stacked body 40. For example, the first portion 53a is provided on the first end 40e1 of the stacked body 40. The thickness of the first portion 53a in the Z direction is the same as the thickness of the first portion 51a of the first semiconductor portion 51 in the Z direction.

[0082] The second portion 53b covers the first end STe1 of the second dividing portion ST2 from the +Z direction side. In the present embodiment, the first end STe1 of the second dividing portion ST2 protrudes in the +Z direction from the first end 40e1 of the stacked body 40. In the present embodiment, the second portion 53b protrudes in the +Z direction from the first portion 53a and covers the first end STe1 of the second dividing portion ST2 from the +Z direction side.

[0083] In this embodiment, the third semiconductor portion 53 overlaps at least a part of the dividing portion ST2 when viewed from the Z direction. The third semiconductor portion 53 extends linearly in the X direction along the dividing portion ST2, for example (see FIG. 8).

[0084] The third semiconductor portion 53 contains impurities (donor impurities) that form an n-type semiconductor, and is n-type (for example, n + A "donor" is an element that has more valence electrons than a tetravalent element, such as a pentavalent element. An example of a donor is phosphorus (P).

[0085] 6.4 Inversion Layer In this embodiment, the above-described conductive layer 41A (the uppermost conductive layer 41 among the multiple conductive layers 41) overlaps with the semiconductor layer 50 when viewed from the Z direction. The conductive layer 41A includes, for example, a first portion 41Aa, a second portion 41Ab, and a third portion 41Ac. When viewed from the Z direction, the first portion 41Aa overlaps with the first semiconductor portion 51 of the semiconductor layer 50. When viewed from the Z direction, the second portion 41Ab overlaps with the second semiconductor portion 52 of the semiconductor layer 50. When viewed from the Z direction, the third portion 41Ac overlaps with the third semiconductor portion 53 of the semiconductor layer 50. In this application, "overlapping with XX" is not limited to overlapping with the entire region of XX, and may include overlapping with at least a portion of the region of XX.

[0086] In this embodiment, when a voltage is applied to the conductive layer 41A, an inversion layer 50r is formed in a part of the semiconductor layer 50. The inversion layer 50r is formed, for example, at the end of the first semiconductor portion 51 on the −Z direction side. The inversion layer 50r extends in the X and Y directions along the first end 40e1 of the stacked body 40. The inversion layer 50r is in contact with the channel layer 62 of the memory pillar MH and also in contact with the third semiconductor portion 53. When the inversion layer 50r is formed, electrons can move between the channel layer 62 of the memory pillar MH and the third semiconductor portion 53.

[0087] <6.5 1st wiring> Next, the wiring 75 will be described. For ease of explanation, the wiring 75 will be referred to as the "first wiring 75" below. The first wiring 75 is a wiring that is electrically connected to the second semiconductor portion 52. In this embodiment, the first wiring 75 is provided on the second semiconductor portion 52, and contacts the second semiconductor portion 52 from the +Z direction. For example, the first wiring 75 contacts the first portion 52a and the second portion 52b of the second semiconductor portion 52.

[0088] FIG. 8 is a cross-sectional view taken along line F8-F8 of the configuration shown in FIG. 7. For ease of explanation, FIG. 8 also shows only some of the memory pillars MH between two separating portions ST (ST1, ST2) adjacent in the Y direction. For ease of explanation, FIG. 8 is a schematic diagram in which the insulating portion 33 is omitted and the first semiconductor portion 51, the second semiconductor portion 52, the third semiconductor portion 53, the wiring 75, the wiring 76, and the like are shown by solid lines. This definition also applies to FIGS. 19, 20, and 21.

[0089] 8, the first wiring 75 extends linearly in the X direction along the second semiconductor portion 52. The arrangement of the first wiring 75 is not limited to the above example. For example, the first wiring 75 may be provided below the stacked body 40 and electrically connected to the second semiconductor portion 52 via the conductive portion STb of the separating portion ST1.

[0090] <6.6 2nd wiring> Next, the wiring 76 will be described. For ease of description, the wiring 76 will be referred to as the "second wiring 76" below. The second wiring 76 is a wiring that is electrically connected to the third semiconductor portion 53. In this embodiment, the second wiring 76 is electrically insulated from the first wiring 75. In this embodiment, the second wiring 76 is provided on the third semiconductor portion 53 and contacts the third semiconductor portion 53 from the +Z direction. For example, the second wiring 76 contacts the first portion 53a and the second portion 53b of the third semiconductor portion 53. The second wiring 76 extends linearly in the X direction along the third semiconductor portion 53.

[0091] The arrangement of the second wiring 76 is not limited to the above example. For example, the second wiring 76 may be provided below the stacked body 40 and electrically connected to the third semiconductor portion 53 via the conductive portion STb of the separating portion ST2.

[0092] <6.7 Insulation> 7, the insulating portion 33 will be described. The insulating portion 33 is provided between the first wiring 75 and the second wiring 76, and electrically insulates the first wiring 75 from the second wiring 76. The insulating portion 33 is also provided between the second semiconductor portion 52 and the third semiconductor portion 53, and electrically insulates the second semiconductor portion 52 from the third semiconductor portion 53.

[0093] <7. Manufacturing method> Next, a method for manufacturing the semiconductor memory device 1 will be described. 9 to 11 are cross-sectional views illustrating a manufacturing method of the semiconductor memory device 1. A semiconductor substrate 101 is prepared. The semiconductor substrate 101 is made of silicon. Next, an insulating layer 43 is formed on the surface of the semiconductor substrate 101 (see (a) in FIG. 9). In this embodiment, the insulating layer 43, which is a thermal oxide film, is formed on the surface of the semiconductor substrate 101 by heating the surface of the semiconductor substrate 101 while supplying an oxidizing agent thereto.

[0094] Next, insulating layers 111 and 42 are alternately stacked one by one on the insulating layer 43 (see (b) in FIG. 9). This forms a stacked body 40A. The insulating layer 111 is a sacrificial layer that will be replaced with the conductive layer 41 in a later process. The insulating layer 111 is formed of, for example, a material containing silicon and nitrogen.

[0095] Next, memory pillars MH and separating portions ST are formed in the stacked body 40A (see (c) in FIG. 9). A first end MHe1 of the memory pillar MH and a first end STe1 of the separating portion ST are formed inside the semiconductor substrate 101. In this embodiment, a replacement step is performed through the grooves provided when forming the separating portions ST, and the insulating layer 111 is replaced with the conductive layer 41. In this way, the stacked body 40 is formed from the stacked body 40A.

[0096] The second chip 3 is formed by the above steps. Furthermore, the first chip 2 is formed by a separate step. The second chip 3 is then oriented upside down and bonded to the first chip 2. For example, the pads 32 of the second chip 3 are bonded to the pads 24 of the first chip 2, thereby integrating the first chip 2 and the second chip 3.

[0097] Next, at least a portion of the semiconductor substrate 101 is removed from the second chip 3 by etching and / or another process (see (d) in FIG. 10). In this embodiment, the entire semiconductor substrate 101 is removed except for the insulating layer 43. Furthermore, the memory film 61 is removed by etching at the first end MHe1 of the memory pillar MH. This exposes the channel layer 62 at the first end MHe1 of the memory pillar MH. Furthermore, the insulating portion STa is removed by etching at the first end STe1 of the separating portion ST. This exposes the conductive portion STb at the first end STe1 of the separating portion ST.

[0098] Next, the semiconductor layer 120 is formed on the insulating layer 43 (see (e) in FIG. 10). The semiconductor layer 120 contains impurities that form a p-type semiconductor. In this embodiment, the semiconductor layer 120 is a p - The semiconductor layer 120 is formed as a silicon-type semiconductor. The semiconductor layer 120 is formed of, for example, silicon doped with impurities. Alternatively, the semiconductor layer 120 may be formed by implanting impurities after deposition.

[0099] The semiconductor layer 120 includes a first portion 121, a second portion 122, and a third portion 123. The first portion 121 corresponds to the first semiconductor portion 51 of the semiconductor layer 50. The second portion 122 corresponds to the second semiconductor portion 52 of the semiconductor layer 50. The third portion 123 corresponds to the third semiconductor portion 53 of the semiconductor layer 50.

[0100] Next, a mask M1 is formed by, for example, lithography to cover the first portion 121 and the third portion 123 of the semiconductor layer 120 (see (f) in FIG. 10). Next, with the mask M1 in place, impurities that form a p-type semiconductor are additionally implanted into the second portion 122 of the semiconductor layer 120. As a result, the second portion 122 of the semiconductor layer 120 becomes a p + It is formed as a type semiconductor.

[0101] Next, a mask M2 is formed by, for example, lithography to cover the first portion 121 and the second portion 122 of the semiconductor layer 120 (see (g) in FIG. 11). Next, with the mask M2 in place, impurities that form an n-type semiconductor are additionally implanted into the third portion 123 of the semiconductor layer 120. As a result, the third portion 123 of the semiconductor layer 120 becomes an n-type semiconductor. + It is formed as a type semiconductor.

[0102] Next, annealing (e.g., laser annealing) is performed for activation. As a result, the first portion 121 of the semiconductor layer 120 becomes the first semiconductor portion 51. The second portion 122 of the semiconductor layer 120 becomes the second semiconductor portion 52. The third portion 123 of the semiconductor layer 120 becomes the third semiconductor portion 53.

[0103] Next, a conductive material (e.g., a metal material) is supplied onto the semiconductor layer 50, and a conductive layer 130 is formed on the semiconductor layer 50 (see (h) in FIG. 11). Next, unnecessary portions are removed from the conductive layer 130 by patterning, and a first wiring 75 and a second wiring 76 are formed from the conductive layer 130 (see (i) in FIG. 11). Next, an insulating section 33 is provided so as to fill the gap between the first wiring 75 and the second wiring 76. Thereafter, upper layer wiring included in the wiring section 70 is formed. This completes the semiconductor memory device 1.

[0104] The manufacturing method of the semiconductor memory device 1 is not limited to the above example. For example, the insulating layer 43 may be formed after the first chip 2 and the second chip 3 are bonded together and the semiconductor substrate 101 is removed from the second chip 3. Also, a part or all of the semiconductor layer 50 may be formed before the first chip 2 and the second chip 3 are bonded together. For example, a part or all of the semiconductor layer 50 may be formed as part of the semiconductor substrate 101 before the insulating layer 43 is formed. In this case, for example, the first chip 2 and the second chip 3 may be bonded together and unnecessary portions of the semiconductor substrate 101 may be removed, so that the semiconductor layer 50 is formed from the remaining portion of the semiconductor substrate 101.

[0105] <8. Example of operation> Next, we will explain an example of the operation of the semiconductor memory device 1. The following control is executed by the control circuit (sequencer) 14 unless otherwise specified.

[0106] 8.1 Read operation First, the read operation will be described. 12 is a diagram for explaining a read operation. Here, the memory cell transistor MT from which data is read is referred to as the "selected memory cell transistor MT," and the word line WL corresponding to the selected memory cell transistor MT is referred to as the "selected word line WL." On the other hand, the memory cell transistor MT from which data is not read is referred to as the "unselected memory cell transistor MT," and the word line WL corresponding to the unselected memory cell transistor MT is referred to as the "unselected word line WL." Note that the bit line BL refers to the bit line BL corresponding to the selected memory cell transistor MT.

[0107] As shown in FIG. 12, at time t10, the first wiring 75, the second wiring 76, the source side select gate line SGS, the selected word line WL, the unselected word lines WL, the drain side select gate line SGD, and the bit line BL have the ground potential Vss (e.g., 0V) under the control of the control circuit 14.

[0108] From time t11, the control circuit 14 maintains the voltage of the bit line BL at voltage Vbl. The voltage Vbl is higher than voltage Vss. Also, from time t11, the control circuit 14 maintains the voltage of the second wiring 76 at voltage Vcelsrc. The voltage Vcelsrc is lower than voltage Vbl. The application of voltages Vbl and Vcelsrc continues until, for example, time t15.

[0109] The control circuit 14 applies a voltage Vsgs to the source-side select gate line SGS from time t12. The voltage Vsgs is a voltage that turns on the source-side select transistor STS (conductive state). When the voltage Vsgs is applied to the conductive layer 41A, an inversion layer 50r (see FIG. 13) is formed in the semiconductor layer 50.

[0110] Note that a voltage higher than the voltage applied to the other conductive layers 41 that become the source-side select gate lines SGS may be applied to the conductive layer 41A in order to form an inversion layer 50r in the semiconductor layer 50. In this embodiment, because the insulating layer 43 is thin, even if the voltage applied to the conductive layer 41A is low, the inversion layer 50r can be formed in the semiconductor layer 50. Therefore, the voltage Vsgs applied to the conductive layer 41A is the same as the voltage Vsgs applied to the other conductive layers 41 that become the source-side select gate lines SGS.

[0111] Furthermore, from time t12, the control circuit 14 applies a voltage Vsgd to the drain-side select gate line SGD. The voltage Vsgd is a voltage that turns on (conducts) the drain-side select transistor STD. Furthermore, from time t12, the control circuit 14 applies a voltage Vpass_read to the unselected word lines WL. The voltage Vpass_read is a voltage that turns on (conducts) the unselected memory cell transistors MT regardless of the threshold state of the unselected memory cell transistors MT. The application of the voltages Vsgs, Vsgd, and Vpass_read continues until, for example, time t15.

[0112] The control circuit 14 applies the voltage Vcgr to the selected word line WL between time t13 and time t14. The application of the voltage Vcgr causes the selected memory cell transistors MT having a threshold voltage equal to or greater than the voltage Vcgr to remain in the off state (non-conductive state), while the selected memory cell transistors MT having a threshold voltage less than the voltage Vcgr are turned on (conductive state). In this state, the sense amplifier module 17 determines whether or not a current flows through the channel layer 62 of the memory pillar MH based on the voltage of the bit line BL. This allows a data read operation to be performed.

[0113] 13 is a cross-sectional view illustrating the read operation of the semiconductor memory device 1. In the read operation, as described above, the voltage Vsgs is applied to the conductive layer 41A, and an inversion layer 50r is formed in the semiconductor layer 50. Therefore, when the selected memory cell transistor MT is turned on (conductive), electrons move between the channel layer 62 of the memory pillar MH and the second wiring 76 via the inversion layer 50r and the third semiconductor portion 53, causing a current to flow between the bit line BL and the second wiring 76.

[0114] 8.2 Write operation Next, the write operation will be described. 14 is a diagram for explaining the write operation. Here, the memory cell transistor MT to which data is to be written is referred to as the "selected memory cell transistor MT," and the word line WL corresponding to the selected memory cell transistor MT is referred to as the "selected word line WL." On the other hand, the memory cell transistor MT to which data is not to be written is referred to as the "unselected memory cell transistor MT," and the word line WL corresponding to the unselected memory cell transistor MT is referred to as the "unselected word line WL." Note that the bit line BL refers to the bit line BL corresponding to the selected memory cell transistor MT.

[0115] As shown in FIG. 14, at time t20, the first wiring 75, the second wiring 76, the source side select gate line SGS, the selected word line WL, the unselected word lines WL, the drain side select gate line SGD, and the bit line BL have the ground potential Vss (e.g., 0V) under the control of the control circuit 14.

[0116] The control circuit 14 applies a voltage Vsgd to the drain-side select gate line SGD from time t21. The voltage Vsgd turns on the drain-side select transistor STD (to a conductive state). The application of the voltage Vsgd continues until time t25, for example.

[0117] Starting at time t22, the control circuit 14 applies a voltage Vpass to the selected word line WL and unselected word lines WL. Vpass is a voltage high enough to turn on the memory cell transistors MT, but low enough not to write data to the memory cell transistors MT. The application of the voltage Vpass to the unselected word lines WL continues until, for example, time t25.

[0118] The control circuit 14 applies a voltage Vpgm to the selected word line WL between time t23 and time t24. The voltage Vpgm is higher than the voltage Vpass. The voltage Vpgm is a voltage that writes data to the memory cell transistor MT (changes the threshold state of the memory cell transistor MT). By applying the voltage Vpgm, a large potential difference is formed between the selected word line WL and the channel layer 62 of the memory cell transistor MT due to the voltages Vpgm and Vss. As a result, electrons are injected into the selected memory cell transistor MT, and data is written.

[0119] <8.3 Erase Operation> Next, the erase operation will be described. 15 is a diagram for explaining the erase operation. As shown in Fig. 15, at time t30, the first wiring 75 and the word line WL have the ground potential Vss (e.g., 0 V) ​​under the control of the control circuit 14. Also, the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL are set to a floating state under the control of the control circuit 14.

[0120] The control circuit 14 applies a voltage Vera to the first wiring 75 between time t31 and time t32. The voltage Vera is a voltage greater than the voltage Vss. As a result, the voltages of the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL rise to a voltage close to the voltage Vera (≒Vera). This causes holes to be generated in the second semiconductor portion 52, and the generated holes are supplied to the memory cell transistor MT. This causes electrons to be extracted from the memory cell transistor MT, erasing the data.

[0121] Starting at time t32, the control circuit 14 discharges the first wiring 75. As a result, the voltages of the second wiring 76, the source-side select gate line SGS, the drain-side select gate line SGD, and the bit line BL, which had risen to a voltage close to the voltage Vera (≈Vera), decrease toward the voltage Vss.

[0122] 16 is a cross-sectional view for explaining the erase operation of the semiconductor memory device 1. In the erase operation, as described above, holes are generated in the second semiconductor portion 52, and the generated holes are supplied to the memory cell transistor MT via the first semiconductor portion 51 and the channel layer 62 of the memory pillar MH. As a result, electrons are extracted from the memory cell transistor MT, and data is erased.

[0123] <9. Advantages> As a comparative example, consider a configuration in which holes are supplied by a GIDL (Gate Induced Drain Leakage) current during an erase operation. In this configuration, it is necessary to implant impurities such as phosphorus deep into the channel layer 62 of the memory pillar MH and then perform an annealing process to amorphize it. However, it is not easy to implant impurities deep into the channel layer 62 and then perform an annealing process to amorphize it. This may result in a shortage of GIDL current during an erase operation. As a result, the electrical characteristics of the semiconductor memory device may be degraded.

[0124] On the other hand, the semiconductor memory device 1 of this embodiment has a semiconductor layer 50, a first wiring 56, and a second wiring 57. The semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52, and a third semiconductor portion 53. The first semiconductor portion 51 includes a first portion 51a arranged along the first end 40e1 of the stacked body 40 and a second portion 51b covering the first end MHe1 of the memory pillar MH. The second semiconductor portion 52 is connected to the first semiconductor portion 51. The third semiconductor portion 53 is connected to the first semiconductor portion 51. The first wiring 56 is electrically connected to the second semiconductor portion 52. The second wiring 57 is electrically connected to the third semiconductor portion 53. The first semiconductor portion 51 and the second semiconductor portion 52 contain impurities that form p-type semiconductors. The third semiconductor portion 53 contains impurities that form n-type semiconductors. The conductive layer 41A includes a portion 41Aa that overlaps with the first semiconductor portion 51 when viewed from the Z direction.

[0125] With this configuration, during an erase operation, holes can be generated by the second semiconductor portion 52, which is a p-type semiconductor, and supplied to the memory cell transistor MT. This prevents the erase operation from becoming insufficient, and improves the electrical characteristics of the semiconductor memory device 1.

[0126] In this embodiment, the third semiconductor portion 53 is provided on the first end 40e1 of the stacked body 40. With this configuration, electrons can easily move between the third semiconductor portion 53 and an inversion layer 50r formed in the first semiconductor portion 51 near the first end 40e1 of the stacked body 40. This can further improve the electrical characteristics of the semiconductor memory device 1.

[0127] In this embodiment, the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51. With this configuration, holes can be generated by the second semiconductor portion 52 and supplied to the memory cell transistor MT more easily. For example, if the second semiconductor portion 52 contains more impurities that form a p-type semiconductor than the first semiconductor portion 51, the contact resistance between the second semiconductor portion 52 and the wiring 75 decreases, making it easier to generate holes. This can further improve the electrical characteristics of the semiconductor memory device 1. Note that, when only considering operation, it is not essential that the impurity concentration of the second semiconductor portion 52 be higher than the impurity concentration of the first semiconductor portion 51.

[0128] In this embodiment, the distance in the Z direction between the conductive layer 41A and the first semiconductor portion 51 is smaller than the thickness T1 in the Z direction of the insulating layer 42A. With this configuration, even if the voltage applied to the conductive layer 41A is low, the inversion layer 50r is easily formed in the semiconductor layer 50. This allows the electrical characteristics of the semiconductor memory device 1 to be further improved.

[0129] In this embodiment, the shortest distance between the conductive layer 41A and the first semiconductor portion 51 is equal to or less than half the thickness T1 of the insulating layer 42A in the Z direction. With this configuration, even if a low voltage is applied to the conductive layer 41A, it becomes easier to form the inversion layer 50r in the semiconductor layer 50. This allows for further improvement in the electrical characteristics of the semiconductor memory device 1.

[0130] In this embodiment, the insulating layer 43 and the insulating layer 42 have different compositions. With this configuration, it is easier to ensure the necessary voltage resistance even when the insulating layer 43 is thin. This allows the electrical characteristics of the semiconductor memory device 1 to be further improved.

[0131] In this embodiment, the second semiconductor portion 52 overlaps with at least a portion of the dividing portion ST1 when viewed from the Z direction. With this configuration, the second semiconductor portion 52 is formed using an area where the memory pillars MH are not arranged. This makes it easier to achieve miniaturization and / or high-density packaging of the semiconductor memory device 1.

[0132] In this embodiment, the third semiconductor portion 53 overlaps at least a portion of the dividing portion ST2 when viewed from the Z direction. With this configuration, the third semiconductor portion 53 is formed using an area where the memory pillars MH are not arranged. This makes it easier to achieve miniaturization and / or high-density packaging of the semiconductor memory device 1.

[0133] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the dividing portion ST does not have a conductive portion STb. Note that the configuration other than that described below is the same as the configuration of the first embodiment.

[0134] FIG. 17 is a cross-sectional view showing a portion of a semiconductor memory device 1A of the second embodiment. In this embodiment, the dividing portion ST does not have a conductive portion STb. The entire dividing portion ST is formed by an insulating portion STa. The end of the dividing portion ST on the +Z direction side coincides with the first end 40e1 of the stacked body 40. Therefore, the second semiconductor portion 52 does not have a second portion 52b. The second semiconductor portion 52 is layered along the X direction and the Y direction. Similarly, the third semiconductor portion 53 does not have a second portion 53b. The third semiconductor portion 53 is layered along the X direction and the Y direction.

[0135] According to this configuration, the semiconductor layer 50 can form paths for electrons and holes to move, thereby improving the electrical characteristics of the semiconductor memory device 1A.

[0136] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the second embodiment in that the second semiconductor portion 52 is disposed in a region that does not overlap with the dividing portion ST in the Z direction. Note that the configuration other than that described below is the same as the configuration of the second embodiment.

[0137] 18 is a cross-sectional view showing a part of a semiconductor memory device 1B according to the second embodiment. In this embodiment, the semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52 (see FIG. 19), a semiconductor portion 53A, and a semiconductor portion 53B.

[0138] In this embodiment, each of the semiconductor portions 53A and 53B contains impurities (donor impurities) that form an n-type semiconductor, and is n-type (for example, n + The semiconductor portion 53A has a conductivity type (a conductivity type). Each of the semiconductor portion 53A and the semiconductor portion 53B is an example of a "third semiconductor portion." When viewed from the Z direction, the semiconductor portion 53A overlaps with at least a portion of the separating portion ST1. The semiconductor portion 53A extends linearly in the X direction along the separating portion ST1 (see FIG. 19). When viewed from the Z direction, the other semiconductor portion 53B overlaps with at least a portion of the separating portion ST2. The semiconductor portion 53B extends linearly in the X direction along the separating portion ST2 (see FIG. 19).

[0139] In this embodiment, the wiring portion 70 includes a wiring 76A and a wiring 76B. The wiring 76A is disposed away from the semiconductor portion 53A in the Z direction. For example, the wiring 76A is disposed at a height that does not interfere with the bit line BL. A via 202A is provided between the wiring 76A and the semiconductor portion 53A. The via 202A is a conductive portion that extends in the Z direction. In this embodiment, the via 202A extends in the Z direction and also extends linearly in the X direction along the separating portion ST1. The wiring 76A is electrically connected to the semiconductor portion 53A via the via 202A. Note that, instead of the above example, the via 202A does not have to be provided. The wiring 76A may be provided on the semiconductor portion 53A.

[0140] Similarly, the wiring 76B is arranged apart from the semiconductor portion 53B in the Z direction. For example, the wiring 76B is arranged at a height that does not interfere with the bit line BL. A via 202B is provided between the wiring 76B and the semiconductor portion 53B. The via 202B is a conductive portion that extends in the Z direction. In this embodiment, the via 202B extends in the Z direction and also extends linearly in the X direction along the dividing portion ST2. The wiring 76B is electrically connected to the semiconductor portion 53B via the via 202B. Note that, instead of the above example, the via 202B does not have to be provided. The wiring 76B may be provided on the semiconductor portion 53B.

[0141] FIG. 19 is a cross-sectional view taken along line F19-F19 of the configuration shown in FIG. 18. In this embodiment, the memory cell array 11 includes a first array region AR1 and a second array region AR2 as the array region AR. The memory cell array 11 has a non-array region NAR between the first array region AR1 and the second array region AR2. The non-array region NAR is a region in which no memory pillars MH are arranged. The non-array region NAR is, for example, a region in which no memory pillars MH exist beyond the arrangement interval of the memory pillars MH in the array region AR. The memory cell array 11 may have multiple non-array regions NAR arranged at regular intervals.

[0142] In this embodiment, the semiconductor layer 50 has a second semiconductor portion 52 in at least a part of the non-array region NAR. The wiring 75 is arranged away from the second semiconductor portion 52 in the Z direction. For example, the wiring 75 is arranged at a height that does not interfere with the bit line BL. A via 201 is provided between the wiring 75 and the second semiconductor portion 52. The via 201 is a conductive portion that extends in the Z direction. The wiring 75 is electrically connected to the semiconductor portion 53A through the via 201. Note that, instead of the above example, the via 201 does not have to be provided. The wiring 75 may be provided on the second semiconductor portion 52.

[0143] According to this configuration, the semiconductor layer 50 can form paths for electron and hole movement, thereby improving the electrical characteristics of the semiconductor memory device 1B. In the third embodiment described above, the third semiconductor portion (semiconductor portions 53A, 53B) is arranged in the array region AR, and the second semiconductor portion 52 is arranged in the non-array region NAR. Alternatively, the second semiconductor portion 52 may be arranged in the array region AR, and the third semiconductor portion 53 may be arranged in the non-array region NAR. Furthermore, both the second semiconductor portion 52 and the third semiconductor portion 53 may be arranged in the non-array region NAR.

[0144] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that the second semiconductor portion 52 is disposed in the hook-up region FR. Note that the configuration other than that described below is the same as that of the third embodiment.

[0145] 20 is a plan view showing a part of a semiconductor memory device 1C according to the fourth embodiment. In this embodiment, the semiconductor layer 50 includes a first semiconductor portion 51, a second semiconductor portion 52, a semiconductor portion 53A, and a semiconductor portion 53B.

[0146] At least a portion of the semiconductor portion 53A is arranged in the array region AR. At least a portion of the semiconductor portion 53B is arranged in the array region AR. On the other hand, the second semiconductor portion 52 is provided in the hook-up region FR. The hook-up region FR is a region where no memory pillars MH are arranged. For example, the second semiconductor portion 52 is arranged between two supports HR.

[0147] With this configuration, the semiconductor layer 50 can form paths for electron and hole movement, improving the electrical characteristics of the semiconductor memory device 1C. In this embodiment, the second semiconductor portion 52 is formed in an area where no memory pillars MH are arranged. This facilitates miniaturization and / or high-density packaging of the semiconductor memory device 1C. Alternatively, the third semiconductor portion 53 may be arranged in the hookup region FR, or both the second semiconductor portion 52 and the third semiconductor portion 53 may be arranged in the hookup region FR.

[0148] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment differs from the third embodiment in that the second semiconductor portion 52 overlaps with the dummy memory pillar DMH in the Z direction. Note that the configuration other than that described below is the same as the configuration of the third embodiment.

[0149] 21 is a plan view showing a portion of a semiconductor memory device 1D of the fifth embodiment. In this embodiment, the second semiconductor portion 52 is arranged in a region in the array region AR that overlaps with the dummy memory pillar DMH. The dummy memory pillar DMH is a memory pillar MH that is not used to hold valid data. The dummy memory pillar DMH is arranged, for example, at a position that overlaps with the dividing portion SHE in the Z direction, and is not connected to the bit line BL.

[0150] With this configuration, the semiconductor layer 50 can form paths for electron and hole movement, thereby improving the electrical characteristics of the semiconductor memory device 1D. Furthermore, in this embodiment, the second semiconductor portion 52 is formed using an area where no memory pillars MH are arranged. This facilitates miniaturization and / or high-density packaging of the semiconductor memory device 1C. Note that, instead of the above example, the third semiconductor portion 53 may be arranged in an area overlapping with the dummy memory pillars DMH, or both the second semiconductor portion 52 and the third semiconductor portion 53 may be arranged in an area overlapping with the dummy memory pillars DMH.

[0151] Although several embodiments have been described above, the embodiments are not limited to the above examples. For example, multiple embodiments may be realized in combination with each other.

[0152] According to at least one embodiment described above, the semiconductor memory device includes a first chip and a second chip. The second chip has a stack, a pillar, a semiconductor layer, a first wiring, and a second wiring. The stack includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are alternately stacked layer by layer in a first direction. The stack has a first end that is an end on a first side in the first direction opposite the first chip. The pillar extends in the first direction within the stack. The pillar has a first end that reaches at least the first end of the stack. The semiconductor layer has a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion includes a first portion arranged along the first end of the stack and a second portion covering the first end of the pillar. The second semiconductor portion is connected to the first semiconductor portion. The third semiconductor portion is connected to the first semiconductor portion. The first wiring is electrically connected to the second semiconductor portion. The second wiring is electrically connected to the third semiconductor portion. The first semiconductor portion and the second semiconductor portion contain impurities that form p-type semiconductors. The third semiconductor portion contains impurities that form n-type semiconductors. Of the multiple gate electrode layers, the first gate electrode layer closest to the first end of the stack includes a portion that overlaps with the first semiconductor portion when viewed from the first direction. This configuration can improve the electrical characteristics of the semiconductor memory device.

[0153] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0154] 1, 1A, 1B, 1C, 1D...Semiconductor memory device 2...First chip 3...Second chip 21...Semiconductor substrate 40...Laminate 40e1...first end of stack 41...Conductive layer (gate electrode layer) 41A...conductive layer (first gate electrode layer) 41B...conductive layer (second gate electrode layer) 41C...conductive layer (third gate electrode layer) 42...insulating layer 42A...First insulating layer 43...insulating layer (second insulating layer) 50...Semiconductor layer 51...First semiconductor section 51a…first part 51b…Second part 52...Second semiconductor section 53...Third Semiconductor Department 56…1st wiring 57…Second wiring MH...Memory pillar (columnar body) MHe1: First end of memory pillar

Claims

1. A first chip; a second chip bonded to the first chip; Equipped with The second chip is a stack including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction, and having a first end that is an end on a first side in the first direction opposite to the first chip; a columnar body extending in the first direction within the stack and having a first end portion that reaches at least the first end of the stack; a semiconductor layer including a first semiconductor part including a first portion arranged along the first end of the stacked body and a second portion covering the first end of the columnar body, a second semiconductor part connected to the first semiconductor part, and a third semiconductor part connected to the first semiconductor part; a first wiring electrically connected to the second semiconductor portion; a second wiring electrically connected to the third semiconductor portion; and the first semiconductor portion and the second semiconductor portion contain impurities that form p-type semiconductors, the third semiconductor portion contains impurities that form an n-type semiconductor; a first gate electrode layer among the plurality of gate electrode layers that is closest to the first end of the stacked body includes a portion that overlaps with the first semiconductor portion when viewed from the first direction; Semiconductor memory device.

2. the third semiconductor portion is provided on the first end of the stacked body, 2. The semiconductor memory device according to claim 1.

3. the second semiconductor portion contains a larger amount of impurities forming a p-type semiconductor than the first semiconductor portion; 3. The semiconductor memory device according to claim 1.

4. the plurality of gate electrode layers include a second gate electrode layer and a third gate electrode layer adjacent to the second gate electrode layer in the first direction; the plurality of insulating layers includes a first insulating layer disposed between the second gate electrode layer and the third gate electrode layer; a distance in the first direction between the first gate electrode layer and the first semiconductor portion is smaller than a thickness in the first direction of the first insulating layer; 3. The semiconductor memory device according to claim 1.

5. a distance in the first direction between the first gate electrode layer and the first semiconductor portion is equal to or less than half a thickness in the first direction of the first insulating layer; 5. The semiconductor memory device according to claim 4.

6. the stack includes a second insulating layer disposed between the first gate electrode layer and the first end of the stack, the second insulating layer and the first insulating layer having different compositions.

5. The semiconductor memory device according to claim 4.

7. the first insulating layer is an insulating layer formed by supplying a raw material gas, the second insulating layer is a thermal oxide film; 7. The semiconductor memory device according to claim 6.

8. a first dividing portion extending in the first direction within the stacked body and dividing each of the plurality of gate electrode layers in a second direction intersecting the first direction, the second semiconductor portion overlaps with at least a portion of the first dividing portion when viewed from the first direction; 3. The semiconductor memory device according to claim 1.

9. a second dividing portion extending in the first direction within the stacked body and dividing each of the plurality of gate electrode layers in a second direction intersecting the first direction, the third semiconductor portion overlaps with at least a portion of the second dividing portion when viewed from the first direction; 3. The semiconductor memory device according to claim 1.

10. forming a stack by alternately stacking first layers and second layers in a first direction above a semiconductor substrate; forming a columnar body including a first end portion extending in the first direction within the stacked body and reaching the semiconductor substrate; removing at least a portion of the semiconductor substrate; supplying an impurity to form a p-type semiconductor into a portion of the semiconductor layer covering the first end of the columnar body; supplying an impurity to form an n-type semiconductor in another part of the semiconductor layer; A method for manufacturing a semiconductor memory device.

Images