Memory device

Abstract

To suppress the manufacturing cost of a memory device.SOLUTION: A memory device includes a substrate W1, a plurality of conductor layers 22, a plurality of pillars MP, and a plurality of first contacts CC. The plurality of conductor layers are arranged in a first direction above the substrate. Each of the plurality of pillars is provided so as to extend in the first direction. A portion at which the plurality of pillars intersect the plurality of conductor layers functions as a memory cell. Each of the plurality of first contacts is electrically connected to a corresponding one of the plurality of conductor layers. Each of the plurality of first contacts has a first conductive member 50 which is provided so as to extend in the first direction and is electrically connected, at a local portion BP, to a corresponding one of the conductor layers while being surrounded by the corresponding conductor layer on a cross section parallel to a surface of the substrate.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-192646 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-056452 [Patent Document 3] Japanese Patent Publication No. 2021-150408 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce manufacturing costs of memory devices. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a substrate, a plurality of conductive layers, a plurality of pillars, and a plurality of first contacts. The plurality of conductive layers are aligned in a first direction above the substrate. Each of the plurality of pillars extends in the first direction. A portion where each of the plurality of pillars intersects with the plurality of conductive layers functions as a memory cell. The plurality of first contacts are electrically connected to a corresponding one of the plurality of conductive layers. Each of the plurality of first contacts extends in the first direction, and in a cross section parallel to the surface of the substrate including the corresponding conductive layer, has a first conductive member whose outer edge is surrounded by the corresponding conductive layer and electrically connected to the corresponding conductive layer at a local portion of the outer edge. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the embodiment. [Figure 3] FIG. 1 is a perspective view showing an example of the appearance of a memory device according to an embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the embodiment. [Figure 5] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure in a memory region of a memory cell array included in the memory device according to the embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the embodiment. [Figure 7] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure in a contact region and a PN contact region of a memory cell array included in a memory device according to the embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a contact before conduction that is provided in the memory device according to the embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 7, showing an example of a cross-sectional structure of a PN contact included in the memory device according to the embodiment. [Figure 10] FIG. 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to an embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure of a contact after conduction, which is provided in the memory device according to the embodiment. [Figure 12] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 13] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 14] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 15] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 16] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 17] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 18] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 19] 1A to 1C are cross-sectional views showing an example of a cross-sectional structure of a memory cell array included in a memory device according to an embodiment during a manufacturing process. [Figure 20] 10 is a flowchart showing an example of a method for electrically connecting a contact to a stacked wiring included in a memory device according to the embodiment. [Figure 21] 5A and 5B are schematic diagrams showing specific examples of conduction processing between stacked wiring and contacts included in the memory device according to the embodiment. [Figure 22] 5A and 5B are schematic diagrams showing specific examples of conduction processing between stacked wiring and contacts included in the memory device according to the embodiment. [Figure 23] 5A and 5B are schematic diagrams showing specific examples of conduction processing between stacked wiring and contacts included in the memory device according to the embodiment. [Figure 24] FIG. 4 is a schematic diagram showing an example of voltages applied to stacked wiring, contacts, and PN contacts in a read operation of the memory device according to the embodiment. [Figure 25] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a contact region of a memory cell array according to a first modification. [Figure 26] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure in a contact region and a PN contact region of a memory cell array according to a second modification. [Figure 27]FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a third modification. [Figure 28] FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fourth modification. [Figure 29] FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fifth modification. [Figure 30] FIG. 13 is a cross-sectional view showing an example of a detailed cross-sectional structure of a memory pillar at a boundary portion between two layers included in a memory device according to a fifth modification. [Figure 31] FIG. 2 is a cross-sectional view showing an example of a detailed cross-sectional structure of the vicinity of two bond pads arranged opposite to each other in a memory device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate devices and methods for embodying the technical ideas of the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components are omitted as appropriate. Hatching added to plan views does not necessarily relate to the material or characteristics of the components. In this specification, components having substantially the same functions and configurations are assigned the same reference symbols. Numbers and letters added to reference symbols are used to refer to the same reference symbols and to distinguish between similar elements.

[0008] <1> composition First, the configuration of a memory device 1 according to the embodiment will be described.

[0009] <1-1> Overall configuration of memory device 1 1 is a block diagram showing an example of the overall configuration of a memory system including a memory device 1 according to an embodiment. As shown in FIG. 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0010] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes a plurality of pages. A page corresponds to a unit in which data is read and written. Although not shown, the memory cell array 10 is provided with a plurality of bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and a plurality of word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0011] The input / output circuit 11 is an interface circuit that controls transmission and reception of input / output signals to and from the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, commands, etc. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0012] The logic controller 12 controls each of the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is a command, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0013] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated under the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes a block address, a page address, a column address, etc. The commands include instructions for various operations of the memory device 1.

[0014] The sequencer 14 controls the overall operation of the memory device 1. Based on the command and address information stored in the register circuit 13, the sequencer 14 executes read operations, write operations, erase operations, and the like.

[0015] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, etc.

[0016] The row decoder module 16 is a circuit used to select a block BLK to be operated and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively, and are used to select the blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0017] The sense amplifier module 17 is a circuit used to transfer voltages to each bit line BL and to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, a latch circuit for temporarily holding data, and the like.

[0018] The combination of the memory device 1 and the memory controller 2 may constitute one semiconductor device. TM Examples include memory cards and solid state drives (SSDs).

[0019] <1-2> Circuit configuration of memory cell array 10 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in a memory device 1 according to the embodiment. Fig. 2 shows two blocks BLK0 and BLK1 among a plurality of blocks BLK included in the memory cell array 10. As shown in Fig. 2, in the memory cell array 10, select gate lines SGD and SGS and word lines WL0 to WL(N-1) (N is an integer of 2 or more) are provided for each block BLK. Bit lines BL0 to BLm and source lines SL are shared by, for example, a plurality of blocks BLK.

[0020] Each block BLK includes multiple NAND strings NS. The multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. In other words, each bit line BL is shared among multiple blocks BLK by NAND strings NS assigned the same column address. Each NAND string NS is connected between the associated bit line BL and source line SL. Each NAND string NS includes, for example, N memory cell transistors MT0 to MT(N-1) and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and retains (stores) data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the block BLK.

[0021] In each NAND string NS, a select transistor ST1, memory cell transistors MT(N-1) to MT0, and a select transistor ST2 are connected in series in this order. Specifically, the drain and source terminals of the select transistor ST1 are connected to the associated bit line BL and the drain terminal of the memory cell transistor MT(N-1), respectively. The drain and source terminals of the select transistor ST2 are connected to the source terminal of the memory cell transistor MT0 and the source line SL, respectively. The memory cell transistors MT0 to MT(N-1) are connected in series between the select transistors ST1 and ST2.

[0022] Each select gate line SGD is connected to the gate terminal of each of the select transistors ST1 included in the associated block BLK. Each select gate line SGS is connected to the gate terminal of each of the select transistors ST2 included in the associated block BLK. Word lines WL0 to WL(N-1) are connected to the control gate terminals of each of the memory cell transistors MT0 to MT(N-1) included in the associated block BLK. A "page" corresponds to a set of memory cell transistors MT connected to a common word line WL within the same block BLK. A set of memory cell transistors MT connected to a common word line WL within the same block BLK can have a storage capacity of two or more pages of data depending on the number of bits stored in the memory cell transistors MT.

[0023] The memory cell array 10 may have other circuit configurations. For example, each block BLK may be provided with a plurality of independently controllable select gate lines SGD. In this case, each block BLK is configured to be selectable in units of a plurality of units each associated with a plurality of select gate lines SGD.

[0024] In the following, the memory device 1 according to the embodiment will be described taking as an example a case where each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7, respectively (that is, a case where N=8).

[0025] <1-3> Structure of memory device 1 The structure of the memory device 1 according to the embodiment will be described below.

[0026] In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the reference semiconductor substrate. "Up and down" are defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the reference semiconductor substrate. The XY plane (cross section) corresponds to a plane (cross section) parallel to each of the X and Y directions. The YZ cross section corresponds to a cross section parallel to each of the Y and Z directions. The XZ cross section corresponds to a cross section parallel to each of the X and Z directions.

[0027] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the embodiment will be described. The memory device 1 according to the embodiment is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. That is, the memory device 1 according to the embodiment includes a structure formed by bonding semiconductor substrates W1 and W2 together. Each of the semiconductor substrates W1 and W2 is a silicon substrate. Below, a case will be described in which the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a portion of the semiconductor substrate W2 may remain after the semiconductor substrates W1 and W2 are bonded together.

[0028] 3 is a perspective view showing an example of the appearance of the memory device 1 according to the embodiment. As shown in Fig. 3, the memory device 1 has a structure in which, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300 are stacked in this order from the bottom.

[0029] The CMOS layer 100 includes a CMOS circuit (control circuit) formed using a semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions and the like according to the design of the CMOS circuit. The CMOS layer 100 includes control circuits such as an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0030] The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to a CMOS circuit provided in the CMOS layer 100 and form part of the semiconductor circuit. The bonding layer B2 is formed using a semiconductor substrate W2 (not shown). The bonding layer B2 includes a plurality of bonding pads that are electrically connected to a memory cell array 10 provided in the memory layer 200 and form part of the semiconductor circuit. The plurality of bonding pads included in the bonding layer B1 are respectively connected to the plurality of bonding pads included in the bonding layer B2. The space between the bonding layers B1 and B2 corresponds to the boundary between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2 (not shown).

[0031] The memory layer 200 includes a memory cell array 10 formed using a semiconductor substrate W2. The wiring layer 300 is formed after bonding the semiconductor substrates W1 and W2 together. The wiring layer 300 includes wiring connected to a semiconductor circuit provided in the memory layer 200 and a plurality of pads PD. The plurality of pads PD are exposed on the surface of the memory device 1. The plurality of pads PD are used to connect the memory device 1 to a memory controller 2, etc.

[0032] (2: Planar layout of memory cell array 10) 4 is a plan view showing an example of a planar layout of a memory cell array 10 included in a memory device 1 according to the embodiment. As shown in FIG. 4, the memory cell array 10 includes a plurality of slits SLT, a plurality of memory pillars MP, a plurality of contacts CC, and a plurality of PN contacts PNC. The memory cell array 10 also includes, for example, a memory region MA, a contact region CA, and a PN contact region PNA aligned in the X direction.

[0033] Each slit SLT is a plate-like member extending along the X direction. Each slit SLT has a portion extending along the X direction and crosses the memory region MA, contact region CA, and PN contact region PNA along the X direction. Multiple slits SLT are aligned in the Y direction. Each slit SLT separates adjacent wirings (e.g., word lines WL0 to WL7 and select gate lines SGD and SGS) through the slit SLT. In each slit SLT, a conductor with an insulating spacer on its sidewall may be arranged insulated from the wirings, or an insulator may be embedded. In the memory cell array 10, each of the regions partitioned along the Y direction by the slits SLT corresponds to one block BLK.

[0034] The memory area MA is an area used for storing data. A plurality of memory pillars MP are arranged in the memory area MA. Each memory pillar MP is, for example, a pillar-shaped component that functions as one NAND string NS. The plurality of memory pillars MP are arranged in a grid pattern for each block BLK. At least one bit line BL is arranged to overlap each memory pillar MP. Each of the plurality of bit lines BL has a portion extending in the Y direction and is aligned in the X direction. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The associated memory pillar MP and bit line BL are electrically connected via contacts CV.

[0035] The contact area CA is an area used for connecting stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) included in the memory cell array 10 to the row decoder module 16. In the contact area CA, a plurality of contacts CC are arranged for each block BLK. For each block BLK, each of the plurality of contacts CC is electrically connected to an associated one of the stacked wirings. In each block BLK, at least one contact CC is electrically connected to each of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. Note that in the contact area CA, the plurality of contacts CC in each block BLK are not limited to being arranged in a line in the X direction as shown in FIG. 4, but may be arranged in a grid pattern for each block BLK.

[0036] The PN contact area PNA is an area including contacts used in a conduction process for electrically connecting the stacked wiring of the memory cell array 10 to the plurality of contacts CC. At least one PN contact PNC is arranged in each block BLK in the PN contact area PNA. The PN contact PNC is configured so that a voltage can be applied thereto by, for example, the row decoder module 16. The PN contact PNC and the stacked wiring are connected via a PN junction. Details of the conduction process will be described later.

[0037] (3: Cross-sectional structure of memory area MA of memory cell array 10) 5 is a cross-sectional view showing an example of the cross-sectional structure of a memory region MA of a memory cell array 10 included in a memory device 1 according to the embodiment. Fig. 5 shows an example of the structure of the memory cell array 10 formed on a semiconductor substrate W2 before being bonded to the semiconductor substrate W1, and indicates coordinate axes based on the semiconductor substrate W2. As shown in Fig. 5, the memory cell array 10 includes, in the memory region MA, for example, conductor layers 21-25, insulator layers 31-35, an insulating member 36, and contacts CV, V1, and V2.

[0038] A conductor layer 21 is provided on a semiconductor substrate W2. An insulator layer 31 is provided on the conductor layer 21. Conductor layers 22 and insulator layers 32 are alternately provided on the insulator layer 31. That is, a plurality of conductor layers 22 are arranged side by side in the Z direction. The number of conductor layers 22 corresponds to the number of layers of stacked wiring (select gate lines SGS, word lines WL, and select gate lines SGD). An insulator layer 33, a conductor layer 23, an insulator layer 34, and an insulator layer 35 are provided in this order on the uppermost conductor layer 22. Each of the conductor layers 21 and 22 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 23 has, for example, a portion formed in a line shape extending in the Y direction. The conductor layer 21 is used as a source line SL. In this example, ten conductive layers 22 arranged in the Z direction are used as select gate lines SGS, word lines WL0 to WL7, and select gate lines SGD, in that order from the source line SL side. Conductor layers 23 are used as bit lines BL.

[0039] A conductive layer 24 is provided above the conductive layer 23. The conductive layer 24 is a wiring that relays the connection between the bit line BL and the sense amplifier module 17. The conductive layer 23 and the conductive layer 24 are connected via a contact V1. A conductive layer 25 is provided above the conductive layer 24. The conductive layer 25 corresponds to a bond pad. The conductive layer 26 includes, for example, copper. The conductive layer 24 and the conductive layer 25 are connected via a contact V2. Side surfaces of the conductive layer 24 and the contacts V1 and V2 are covered with an insulator layer 34. The insulator layer 34 may be composed of multiple insulating films. Side surfaces of the conductive layer 25 are covered with an insulator layer 35. The insulator layer 35 and the conductive layer 25 are included in the junction layer B2. The memory cell array 10 may include multiple conductive layers 24 and multiple conductive layers 25.

[0040] The slits SLT separate the insulating layer 31 from the alternately arranged conductive layers 22 and insulating layers 32. In this example, an insulating member 36 is embedded in the slits SLT. The insulating member 36 has a plate-shaped portion extending along the XZ plane. A conductor having an insulating spacer on its side wall may be arranged in the slits SLT while being insulated from these wirings.

[0041] Each memory pillar MP extends along the Z direction and penetrates the insulator layer 31 and the alternating conductor layers 22 and insulator layers 32. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is an insulator that extends along the Z direction. The semiconductor layer 41 covers the core member 40. The lower part of the semiconductor layer 41 is in contact with, for example, the conductor layer 21. The stacked film 42 covers the side surface of the semiconductor layer 41. The associated semiconductor layer 41 (memory pillar MP) and conductor layer 23 (bit line BL) are connected via a contact CV.

[0042] The portion where the conductive layer 22 used as the select gate line SGS intersects with the memory pillar MP functions as a select transistor ST2. The portion where the conductive layer 22 used as the word line WL intersects with the memory pillar MP functions as a memory cell transistor MT. The portion where the conductive layer 22 used as the select gate line SGD intersects with the memory pillar MP functions as a select transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2 included in the NAND string NS.

[0043] (4: Cross-sectional structure of memory pillar MP) FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of a memory pillar MP included in the memory device 1 according to the embodiment. FIG. 6 illustrates a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. As shown in FIG. 6, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 contains, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 contains, for example, silicon nitride (SiN).

[0044] (5: Cross-sectional structure of the contact region CA and the PN contact region PNA of the memory cell array 10) FIG. 7 is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA and the PN contact region PNA of the memory cell array 10 included in the memory device 1 according to the embodiment. FIG. 7 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in FIG. 7, the memory cell array 10 includes conductor layers 21-25, insulator layers 31-35, and contacts V0, V1, and V2 in the contact region CA and the PN contact region PNA. The conductor layers 21 and 22 and the insulator layers 31-35 are each continuously provided from the memory region MA to the contact region CA and the PN contact region PNA. The contact region CA and the PN contact region PNA do not include a stepped stacked wiring (conductor layer 22). The memory cell array 10 further includes a plurality of conductor layers 26 and a plurality of contacts V0 in the contact region CA, and a conductor layer 27 and a contact V0 in the PN contact region PNA.

[0045] In the contact region CA, the lengths of the contacts CC in the Z direction are approximately equal. Each contact CC penetrates multiple insulator layers 32 and two or more conductor layers 22 and is in contact with multiple conductor layers 22, including the topmost conductor layer 22 and the bottommost conductor layer 22. In this example, the bottom surface of each contact CC is in contact with the bottommost conductor layer 22. Note that each contact CC may also penetrate the bottommost conductor layer 22. In the contact region CA, the stacked wiring (conductor layers 22) is not processed in a stepped shape, so each contact CC is provided by penetrating the same number of conductor layers 22. Each contact CC includes a conductive member 50 and an insulating film 51. The conductive member 50 is provided extending in the Z direction. The insulating film 51 covers the side and bottom surfaces of the conductive member 50. The conductive member 50 has portions facing each of the multiple conductor layers 22, with the insulating film 51 interposed therebetween.

[0046] The plurality of conductive layers 26 are wirings provided corresponding to the plurality of contacts CC. Each conductive layer 26 is disposed, for example, at the same height (layer) as the conductive layer 23. The bottom of each conductive layer 26 is connected to the conductive member 50 in the corresponding contact CC via a contact V0. The top of each conductive layer 26 is connected to the conductive layer 25 via contacts V1 and V2 and the conductive layer 24.

[0047] In the PN contact region PNA, the height of the upper surface of the PN contact PNC (the end farther from the source line SL) is aligned with the height of the upper surface of the contact CC (the end farther from the source line SL). The PN contact PNC penetrates multiple insulating layers 32 and two or more conductor layers 22, and is in contact with multiple conductor layers 22, including the uppermost conductor layer 22 and the lowermost conductor layer 22. In this example, the bottom surface of the PN contact PNC is in contact with the lowermost conductor layer 22. The PN contact PNC may also penetrate the lowermost conductor layer 22. The PN contact PNC also has recess portions RP corresponding to each of the multiple conductor layers 22. The diameter of the PN contact PNC is larger at the recess portions RP. That is, the side surface of the PN contact PNC has a step. Furthermore, the PN contact PNC includes a conductive member 60, a P-type semiconductor layer 61, and an N-type semiconductor layer 62. The conductive member 60 is provided to extend in the Z direction. The P-type semiconductor layer 61 covers the side and bottom surfaces of the conductive member 50. The N-type semiconductor layer 62 covers the side surfaces of the P-type semiconductor layer 61 in each recess portion RP of the PN contact PNC. The conductive member 60 has portions that face each of the multiple conductor layers 22, with the P-type semiconductor layer 61 and the N-type semiconductor layer 62 interposed therebetween.

[0048] The conductive layer 27 is a wiring provided corresponding to the PN contact PNC. The conductive layer 27 is disposed, for example, at the same height (layer) as the conductive layer 23. The bottom of the conductive layer 27 is connected to the conductive member 60 in the associated PN contact PNC via a contact V0. The top of the conductive layer 27 is connected to the conductive layer 25 via contacts V1 and V2 and the conductive layer 24.

[0049] (6: Cross-sectional structure of contact CC before conduction) FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure of a contact CC included in the memory device 1 according to the embodiment before electrical connection. FIG. 8 illustrates a cross section including the contact CC and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2 before the contact CC and the conductive layer 22 are electrically connected. As shown in FIG. 8, in the contact CC, an insulating film 51 surrounds the side surface of the conductive member 50. The conductive layer 22 surrounds the side surface of the insulating film 51. Thus, before the contact CC and the conductive layer 22 are electrically connected, each conductive layer 22 is separated and insulated from the conductive member 50 in the contact CC via the insulating film 51. The conductive member 50 includes, for example, tungsten (W). The insulating film 51 includes, for example, silicon oxide (SiO2).

[0050] (7: Cross-sectional structure of PN contact PNC) FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7 , showing an example of the cross-sectional structure of the PN contact PNC included in the memory device 1 according to the embodiment. FIG. 9 shows a cross section including the PN contact PNC and the conductive layer 22 and parallel to the surface of the semiconductor substrate W2. As shown in FIG. 9 , in the PN contact PNC, the P-type semiconductor layer 61 surrounds the side surface of the conductive member 60. The N-type semiconductor layer 62 surrounds the side surface of the P-type semiconductor layer 61. The conductive layer 22 surrounds the side surface of the N-type semiconductor layer 62. As such, the conductive member 60 and the conductive layer 22 in the PN contact PNC are connected via the P-type semiconductor layer 61 and the N-type semiconductor layer 62. In other words, the conductive member 60 and the conductive layer 22 in the PN contact PNC are connected via a PN junction made up of the P-type semiconductor layer 61 and the N-type semiconductor layer 62. In this example, the direction from the conductive member 60 of the PN contact PNC toward the conductive layer 22 corresponds to the forward direction of the PN junction. The conductive member 60 includes, for example, tungsten (W). The P-type semiconductor layer 61 includes, for example, silicon doped with boron (B). The N-type semiconductor layer 62 includes, for example, silicon doped with phosphorus (P).

[0051] (8: Cross-sectional structure of memory device 1) FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the embodiment. FIG. 10 shows the state after the contacts CC and the conductive layer 22 are electrically connected, and shows coordinate axes based on the semiconductor substrate W1. As shown in FIG. 10, the memory device 1 according to the embodiment has a configuration in which the structure of the memory cell array 10 described with reference to FIGS. 5 and 7 is inverted upside down, except that the state after the contacts CC and the conductive layer 22 are electrically connected in the memory layer 200. Note that in this example, the semiconductor substrate W2 is removed after the bonding process of the semiconductor substrates W1 and W2. The memory cell array 10 includes an insulator layer 70, multiple conductive layers 72, and multiple contacts C1 in the CMOS layer 100, an insulator layer 71 and multiple conductive layers 73 in the bonding layer B1, and an insulator layer 80 in the wiring layer 300. Transistors TR1 to TR3 are provided on the semiconductor substrate W1. The transistor TR1 corresponds to an element included in the sense amplifier module 17. Each of the transistors TR2 and TR3 corresponds to an element included in the row decoder module 16.

[0052] The insulator layer 70 is provided on the semiconductor substrate W1. The insulator layer 70 may be composed of multiple insulating films. Inside the insulator layer 70, at least one contact C1 and at least one conductor layer 72 are connected in series on each of the transistors TR1, TR2, and TR3.

[0053] The insulator layer 71 is provided on the insulator layer 70. The conductor layers 73 correspond to bond pads formed using the semiconductor substrate W1 and are in contact with the tops of the associated contacts C1. For example, the conductor layer 73 in the memory region MA is connected to the transistor TR1 via at least one contact C1 and at least one conductor layer 72. The conductor layer 73 in the contact region CA is connected to the transistor TR2 via at least one contact C1 and at least one conductor layer 72. The conductor layer 73 in the PN contact region PNA is connected to the transistor TR3 via at least one contact C1 and at least one conductor layer 72. Each conductor layer 73 is in contact with an associated conductor layer 25 (bond pad).

[0054] The insulating layer 80 is provided on the conductive layer 21. The insulating layer 80 includes, for example, the pads PD described with reference to FIG. 3 and wiring for connecting the pads PD to the input / output circuit 11 provided on the semiconductor substrate W1 (not shown).

[0055] After the conduction process described below is performed, each contact CC electrically connects one of the plurality of conductive layers 22 that it contacts to its own conductive member 50 via a dielectric breakdown portion BP. The dielectric breakdown portion BP is formed by the conduction process causing dielectric breakdown of a localized portion (one location) of the annular insulating film 51 in the XY cross section. The position of the conductive layer 22 to which each contact CC is electrically connected by the conduction process may differ for each block BLK. That is, in the memory device 1 according to the embodiment, the memory cell array 10 includes a plurality of blocks BLK, each of which includes a plurality of conductive layers 22, a plurality of memory pillars MP, and a plurality of contacts CC, and the connection relationship between the plurality of conductive layers 22 and the plurality of contacts CC may differ for each block BLK.

[0056] (9: Cross-sectional structure of contact CC after conduction) FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 , showing an example of the cross-sectional structure of a contact CC included in the memory device 1 according to the embodiment after conduction. FIG. 11 illustrates a cross section parallel to the surface of the semiconductor substrate W1, including the electrically connected contact CC and conductive layer 22, after the contact CC and conductive layer 22 are electrically connected. As shown in FIG. 11 , after the conduction process, the conductive member 50 in the contact CC and one of the conductive layers 22 are electrically connected via a dielectric breakdown portion BP. In this example, a state is shown in which a portion of the insulating film 51 is broken down by dielectric breakdown, and a portion of the conductive member 50 has moved toward the conductive layer 22. Therefore, in the XY cross section, the conductive layer 22 and the conductive member 50 in the contact CC are locally connected at one location. In other words, in the cross section parallel to the surface of the semiconductor substrate W1, the outer edge of the conductive member 50 is surrounded by the corresponding conductive layer 22, and is electrically connected to the corresponding conductive layer 22 at one location on the outer edge (the local dielectric breakdown portion BP). The insulating film 51 covers the side surface of the conductive member 50 except for the connection portion (dielectric breakdown portion BP) between the conductive member 50 and the corresponding conductor layer 22. The dielectric breakdown portion BP contains, for example, tungsten (W) like the conductive member 50.

[0057] <2> Manufacturing method Next, a manufacturing method of the memory device 1 according to the embodiment will be described. In this specification, the term "stacked wiring section" refers to a structure (stacked body) used to form stacked wiring including a plurality of word lines WL aligned in the Z direction.

[0058] <2-1> Method for forming memory cell array 10 12, 13, 14, 15, 16, 17, 18, and 19 are cross-sectional views showing an example of a cross-sectional structure in a manufacturing process of the memory cell array 10 included in the memory device 1 according to the embodiment. Each of Fig. 12 to Fig. 19 shows a process of forming three contacts CC in the contact region CA shown in Fig. 7 and one PN contact PNC in the PN contact region PNA using a semiconductor substrate W2.

[0059] First, as shown in Fig. 12, a plurality of sacrificial members SM corresponding to the stacked wiring portion are formed. Specifically, first, a conductor layer 21 and an insulator layer 31 are provided in this order on the semiconductor substrate W2. Then, sacrificial members SM and insulator layers 32 are alternately stacked on the insulator layer 31. The number of sacrificial members SM corresponds to the number of conductor layers 22. Then, an insulator layer 331 is provided on the uppermost sacrificial member SM. The insulator layer 331 corresponds to a portion of the insulator layer 33 shown in Fig. 7.

[0060] Next, as shown in FIG. 13, a plurality of holes H1 and H2 are formed. Each hole H1 is provided corresponding to one contact CC. Each hole H2 is provided corresponding to one PN contact PNC. Each hole H1 and H2 penetrates the insulator layer 331, the plurality of insulator layers 32, and the plurality of sacrificial members SM. In this example, the bottom of each of the holes H1 and H2 reaches the lowest sacrificial member SM. The lowest sacrificial member SM is exposed at the bottom of each of the holes H1 and H2. Note that each of the holes H1 and H2 may penetrate the lowest sacrificial member SM. In this process, for example, RIE (Reactive Ion Etching) is used.

[0061] Next, as shown in FIG. 14, a plurality of recesses RP are formed in the hole H2. Specifically, first, a mask MK1 is formed to cover the contact region CA. The mask MK1 is, for example, a photoresist. Then, a portion of the sacrificial material SM exposed in the hole H2 is selectively removed by an isotropic etching process. As a result, a plurality of recesses RP are formed in the hole H2 corresponding to the plurality of sacrificial materials SM, respectively. The isotropic etching process used in this step is, for example, wet etching.

[0062] 15, an N-type semiconductor layer 62 is formed in the hole H2. Specifically, first, the N-type semiconductor layer 62 is formed in the hole H2 so as to fill each recess portion RP. The N-type semiconductor layer 62 is formed by, for example, CVD (Chemical Vapor Deposition). Then, the N-type semiconductor layer 62 in the hole H2 is separated into each recess portion RP and removed so as to remain in each recess portion RP.

[0063] 16, a P-type semiconductor layer 61 is formed in the hole H2. For example, CVD is used to form the P-type semiconductor layer 61. The P-type semiconductor layer 61 formed in the hole H2 is in contact with the N-type semiconductor layer 62 in each recess portion RP. As a result, a PN junction is formed in each recess portion RP in the hole H2. Then, after the P-type semiconductor layer 61 is formed, the mask MK1 is removed.

[0064] 17, an insulating film 51 is formed in each hole H1. Specifically, first, a mask MK2 is formed to cover the PN contact region PNA. The mask MK2 is, for example, a photoresist. Then, the insulating film 51 is provided on the side and bottom surfaces of each hole H1 so as to contact all of the stacked sacrificial members SM. Then, after the insulating film 51 is formed, the mask MK2 is removed.

[0065] 18, a conductor is filled into each of the holes H1 and H2. The conductor filled into the hole H1 corresponds to the conductive member 50, and the conductor filled into the hole H2 corresponds to the conductive member 60. As a result, a structure corresponding to the contact CC is formed in each of the holes H1, and a structure corresponding to the PN contact PNC is formed in each of the holes H2.

[0066] Next, a replacement process is performed. Specifically, first, slits SLT are formed in an area not shown in the figure, dividing the multiple sacrificial members SM into blocks BLK. Then, the multiple sacrificial members SM are selectively removed through the slits SLT by wet etching using hot phosphoric acid or the like. Then, a conductor is embedded through the slits SLT into the spaces where the sacrificial members SM have been removed. CVD, for example, is used to form the conductor in this process. Then, the conductor formed in the slits SLT is removed by an etch-back process or the like, and the conductor formed in adjacent spaces is separated into multiple layers. As a result, multiple conductor layers 22 are formed that function as the select gate line SGS, word lines WL0 to WL7, and select gate line SGD, as shown in FIG. 19.

[0067] The combination of functions of the stacked wiring formed by the replacement process is not limited to the above-described multiple conductive layers 22 (select gate lines SGS and SGD and word lines WL). Depending on the structure of the memory cell array 10, the source lines SL (conductive layers 21) may be formed by the replacement process, similar to the conductive layers 22. In this case, the sacrificial member SM in the lowest layer corresponds to the conductive layer 21.

[0068] <2-2> Conduction method between laminated wiring and contact CC 20 is a flowchart showing an example of a method for electrically connecting the contacts CC to the stacked wiring included in the memory device 1 according to the embodiment. Hereinafter, with reference to FIG. 20, the method for electrically connecting the contacts CC to the stacked wiring will be described with a focus on one block BLK.

[0069] First, a block BLK in which the conduction between the contacts CC and the conductive layers 22 is not yet completed is selected (step S11). Next, a contact CC is selected from the selected block BLK (step S12). Next, a conduction process is performed on the selected contact CC (step S13). Through the conduction process, the selected contact CC is electrically connected to one of the conductive layers 22 included in the stacked wiring.

[0070] Next, it is confirmed whether the conduction process for all contacts CC in the selected block BLK has been completed (step S14). If the conduction process for all contacts CC in the selected block BLK has not been completed (step S14: NO), the next contact CC is selected (step S15), and the process proceeds to step S13. That is, the conduction process for selecting the next contact CC is executed. When the conduction process is executed, the next contact CC is electrically connected to any of the conductive layers 22 in the stacked wiring that has not been electrically connected to the contact CC by the conduction process up to this point. When the conduction process for all contacts CC in the selected block BLK has been completed (step S14: YES), the series of processes shown in FIG. 20 is completed. Then, the series of processes shown in FIG. 20 is executed for each of all blocks BLK.

[0071] 21, 22, and 23, a case where conduction processing is performed sequentially on three contacts CC will be described below. Each of FIGS. 21, 22, and 23 is a schematic diagram showing a specific example of conduction processing between the stacked wiring and the contacts CC included in the memory device 1 according to the embodiment. Each of FIGS. 21, 22, and 23 shows stacked wiring (i.e., multiple conductor layers 22) corresponding to the contact region CA and the PN contact region PNA shown in FIG. 19, three contacts CC, and a PN contact PNC, and voltages applied to each of the three contacts CC and the PN contact PNC. Note that, hereinafter, the three contacts CC shown in the figure will be referred to as contacts CC1, CC2, and CC3, respectively, from the left side of the page.

[0072] 21 corresponds to a state before all contacts CC in a selected block BLK are electrically connected to the stacked wiring. As shown in FIG. 21, in this example, contact CC1 is selected as a target for the conduction process, and the other contacts CC are unselected. In this case, the row decoder module 16 applies, for example, a voltage Vp to the selected contact CC1, a voltage Vp / 2 to the unselected contacts CC2 and CC3, and a voltage of 0 V to the PN contact PNC. Vp is a high voltage that can cause dielectric breakdown of the insulating film 51 based on the difference between Vp and the voltage applied to each conductive layer 22 via the PN contact PNC.

[0073] A forward bias is applied to the PN junctions provided in the respective recess portions RP by the voltage applied to the PN contacts PNC. As a result, the voltage of each conductive layer 22 becomes 0 V. When Vp is applied to the selected contact CC1, a high electric field is generated between the conductive member 50 in the contact CC1 and each conductive layer 22 via the insulating film 51. This causes dielectric breakdown in the insulating film 51 of the contact CC1 at a location with the lowest breakdown voltage (in this example, at a location at the intersection of the conductive layer 22 corresponding to the word line WL5 and the contact CC1).

[0074] This electrically connects the contact CC1 to the conductive layer 22 corresponding to the word line WL5. After the breakdown occurs, the voltage of the word line WL5 rises. However, because Vp / 2 is applied to the unselected contacts CC2 and CC3, the electric field applied to the insulating film 51 of each of the unselected contacts CC2 and CC3 remains small. This prevents secondary breakdown of the insulating film 51 of each of the unselected contacts CC2 and CC3. Furthermore, as the voltage of the word line WL5 rises, a reverse bias voltage is applied to the PN junction at the intersection of the word line WL5 and the PN contact PNC. This prevents the voltage of the word line WL5 from affecting the PN contact PNC.

[0075] 22 shows how the conduction process for contact CC2 is executed after the conduction process for contact CC1 shown in FIG. 21. As shown in FIG. 22, in this example, contact CC2 is selected as the target for the conduction process, and the other contacts CC1 and CC3 are unselected. In this case, the row decoder module 16 applies, for example, a voltage Vp to the selected contact CC2, a voltage Vp / 2 to the unselected contacts CC1 and CC3, and a voltage of 0 V to the PN contact PNC.

[0076] The voltage applied to the PN contact PNC causes the voltage of each conductive layer 22 to become 0V. When Vp / 2 is applied to the already-conductive contact CC1, the voltage of the word line WL5 rises to Vp / 2. At this time, a reverse bias is applied to the PN junction of the recess portion RP at the intersection of the word line WL5 and the PN contact PNC, so the effect on the PN contact PNC is suppressed. Then, when Vp is applied to the selected contact CC2, a high electric field is generated via the insulating film 51 between the conductive member 50 in the contact CC2 and each conductive layer 22 except for the word line WL5. This causes dielectric breakdown in the insulating film 51 of the contact CC2 at a location with the lowest withstand voltage excluding the intersection with the word line WL5 to which Vp / 2 is applied (in this example, one location at the intersection of the conductive layer 22 corresponding to the word line WL3 and the contact CC2).

[0077] This electrically connects contact CC2 to the conductive layer 22 corresponding to word line WL3. After breakdown occurs, the voltage of word line WL3 rises. However, because Vp / 2 is applied to unselected contacts CC1 and CC3, the electric field applied to the insulating film 51 of each of unselected contacts CC1 and CC3 remains small. As a result, secondary breakdown of the insulating film 51 of each of unselected contacts CC1 and CC3 is suppressed. Furthermore, as the voltage of word line WL3 rises, a reverse bias voltage is applied to the PN junction at the intersection of word line WL3 and contact PNC. This suppresses the effect of the voltage of word line WL3 on PN contact PNC.

[0078] 23 shows how the conduction process for contact CC3 is performed after the conduction process for contact CC2 shown in FIG. 22. As shown in FIG. 23, in this example, contact CC3 is selected as the target for the conduction process, and the other contacts CC1 and CC2 are unselected. In this case, the row decoder module 16 applies, for example, a voltage Vp to the selected contact CC3, a voltage Vp / 2 to the unselected contacts CC1 and CC2, and a voltage of 0 V to the PN contact PNC.

[0079] The voltage applied to the PN contact PNC reduces the voltage of each conductive layer 22 to 0V. When Vp / 2 is applied to the already-conductive contacts CC1 and CC2, the voltage of the word lines WL3 and WL5 rises to Vp / 2. At this time, a reverse bias is applied to the PN junctions of the recessed portion RP at the intersections of the word lines WL3 and WL5 and the PN contact PNC, suppressing the effect on the PN contact PNC. When Vp is applied to the selected contact CC3, a high electric field is generated via the insulating film 51 between the conductive member 50 in the contact CC3 and each conductive layer 22 other than the word lines WL3 and WL5. This causes dielectric breakdown in the insulating film 51 of the contact CC3 at a location with the lowest breakdown voltage excluding the intersections with the word lines WL3 and WL5 to which Vp / 2 is applied (in this example, one location at the intersection of the conductive layer 22 corresponding to the word line WL0 and the contact CC3).

[0080] This electrically connects contact CC3 to the conductive layer 22 corresponding to word line WL0. After breakdown occurs, the voltage of word line WL0 rises. However, because Vp / 2 is applied to unselected contacts CC1 and CC2, the electric field applied to the insulating film 51 of each of contacts CC1 and CC2 remains small. As a result, secondary breakdown of the insulating film 51 of each of unselected contacts CC1 and CC2 is suppressed. Furthermore, as the voltage of word line WL0 rises, a reverse bias voltage is applied to the PN junction at the intersection of word line WL0 and contact PNC. This suppresses the effect of the voltage of word line WL0 on PN contact PNC.

[0081] As described above, the conduction process is performed by selecting the contacts CC one by one in order. The conduction process is performed, for example, during testing before shipping the memory device 1. Without being limited to this, the conduction process may be performed using the semiconductor substrate W2 before the bonding process of the semiconductor substrates W1 and W2, as long as it is possible to apply the voltages described above. Note that, in the conduction process, the voltage applied to the unselected contacts CC is not limited to Vp / 2, and may be any other voltage as long as it is possible to suppress dielectric breakdown in the insulating film 51 of the unselected contacts CC. Also, in the conduction process, the voltage applied to the PN contacts PNC is not limited to 0 V. The voltage applied to the unselected contacts CC is at least higher than the voltage applied to the PN contacts PNC and lower than Vp.

[0082] <3> operation Next, the operation of the memory device 1 according to the embodiment will be described. As an example of the operation of the memory device 1, a read operation will be described below.

[0083] 24 is a schematic diagram showing an example of voltages applied to the stacked wiring, contacts CC, and PN contacts PNC during a read operation of the memory device 1 according to the embodiment. Fig. 24 shows voltages applied to the stacked wiring (i.e., the multiple conductor layers 22), two contacts CC1 and CC2, and the PN contact PNC.

[0084] 24, in this example, memory cell transistor MT3 (not shown) connected to word line WL3 is selected as a read target. In this case, in a read operation, the row decoder module 16 applies a voltage VSG to each of select gate lines SGD and SGS, applies a read voltage VCG to the selected word line WL3 (i.e., contact CC2 connected to the selected word line WL3), applies a read pass voltage VREAD to unselected word lines WL (e.g., contact CC1 connected to unselected word line WL5), and applies a voltage VPNC to the PN contact PNC.

[0085] VSG is a voltage capable of turning on the select transistors ST1 and ST2. VREAD is a high voltage capable of turning on the memory cell transistor MT regardless of the data stored in the memory cell transistor MT. VCG is a read voltage used to determine the threshold voltage of the memory cell transistor MT. VREAD is higher than both VSG and VCG. VPNC is a voltage that reverse-biases the voltage applied to each PN junction formed in the PN contact PNC, regardless of the voltage applied to the stacked wiring. Specifically, VPNC is a voltage equal to or lower than the voltage applied to each of the multiple conductive layers 22, e.g., the ground voltage VSS (0V).

[0086] As a result, the voltage applied to each PN junction of the PN contact PNC during a read operation is reverse biased. Therefore, the influence of the voltage applied to the PN contact PNC on each conductive layer 22 during a read operation can be suppressed. Then, by applying the above-described voltage, each of the select transistors ST1 and ST2 is turned on. The memory cell transistors MT connected to any of the unselected word lines WL0 to WL2 and WL4 to WL7 are turned on regardless of the data to be stored. The memory cell transistor MT3 connected to the selected word line WL3 is turned on or off depending on the data to be stored. As a result, the voltage of the bit line BL fluctuates depending on the threshold voltage of the memory cell transistor MT3 connected to the selected word line WL3. Then, the sense amplifier module 17 can determine the data stored in the memory cell transistor MT3 connected to the selected word line WL3 based on the voltage of the bit line BL.

[0087] In addition, the voltage applied to the PN contact PNC in the write operation is set to a voltage such that the voltage applied to each PN junction formed in the PN contact PNC is reverse biased, as in the read operation. This allows the memory device 1 to perform the write operation without being affected by the voltage applied to the PN contact PNC.

[0088] <4> Effects of the embodiment The memory device 1 according to the embodiment described above makes it possible to reduce the manufacturing cost of the memory device 1. The effects of the embodiment will be described in detail below.

[0089] A memory device with three-dimensionally stacked memory cells has memory pillars MP that penetrate a stacked wiring (stacked body) in which conductor layers (conductive films) and insulator layers (insulating films) are alternately stacked. In such a memory device, contacts CC to the stacked wiring are connected, for example, to staircase sections processed in a staircase pattern at the ends of the stacked wiring. However, when staircase sections are formed, the area of ​​the staircase sections increases as the number of layers in the stacked wiring increases. In other words, this can be a factor in increasing the chip area. Furthermore, an increase in the number of layers in the stacked wiring increases the difficulty of contact processing to different depths, which can be a factor in increasing manufacturing costs.

[0090] Therefore, the memory device 1 according to the embodiment uses contacts CC that penetrate the stacked wiring and are electrically connected only to a specific conductive layer 22. Specifically, the memory device 1 according to the embodiment has multiple contacts CC formed at the same height in a contact region CA that is not processed in a stepped shape. Because multiple holes H1 for forming the contacts CC are processed to the same depth, it is easier than processing holes to different depths. Then, the contacts CC and the specific conductive layer 22 are electrically connected by causing dielectric breakdown of a portion of the insulating film 51 of the contacts CC through a conduction process.

[0091] As described above, the memory device 1 according to the embodiment uses an antifuse-type contact structure for electrical connection between the contacts CC and the conductive layer 22. As a result, in the memory device 1 according to the embodiment, the area of ​​the contact region CA can be reduced by omitting step processing. Also, the difficulty of contact processing for forming the contacts CC can be reduced. Therefore, the memory device 1 according to the embodiment can reduce the chip area and process development costs, thereby reducing the manufacturing costs of the memory device 1.

[0092] <5> Variations, etc. The memory device 1 described above can be modified in various ways.

[0093] (First Modification) FIG. 25 is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA of the memory cell array 10 according to the first modification. FIG. 25 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in FIG. 25, the insulating film 51 included in the contact CC according to the first modification is formed so as to become thinner toward the bottom side (semiconductor substrate W2 side). In other words, the film thickness of the insulating film 51 becomes thicker from the bottom side to the top side of the contact CC. Specifically, the film thickness TH1 of the bottom side of the contact CC is thinner than the film thickness TH2 of the middle portion of the contact CC. The film thickness TH2 of the middle portion of the contact CC is thinner than the film thickness TH3 of the top side of the contact CC. The breakdown voltage of the insulating film 51 increases as the film thickness of the insulating film 51 increases. Therefore, in the first modification, in the conduction process described in the embodiment, it is expected that dielectric breakdown of the insulating film 51 will occur sequentially from the bottom. As a result, in the first modification, the combination of the electrically connected contacts CC and the conductive layers 22 can be controlled to be approximately constant.

[0094] (Second Modification) FIG. 26 is a cross-sectional view showing an example of the cross-sectional structure of the contact region CA and the PN contact region PNA of the memory cell array 10 according to the second modification. FIG. 26 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding to the semiconductor substrate W1, and displays coordinate axes based on the semiconductor substrate W2. As shown in FIG. 26, in the second modification, the contact region CA and the PN contact region PNA are provided with stopper layers 81 instead of the conductor layers 21 used as the source lines SL. In this example, the stopper layers 81 are, for example, silicon layers, and separate and insulate the conductive members 50 of the plurality of contacts CC from the source lines SL (the conductor layers 21) (not shown). The bottoms of the contacts CC and the PN contacts PNC reach the stopper layer 81 through the lowest conductor layer 22. In this case, all the conductor layers 22 contact the sidewalls of the contacts CC. As in the second modification, stopper layers 81 may be provided to control the positions of the bottoms of the contacts CC and the PN contacts PNC. The position of the stopper layer 81 may be different from the height of the source line SL (conductive layer 21) as long as it is provided further away from the bottom side of the contact CC than the lowermost conductive layer 22. When the source line SL (conductive layer 21) is formed by the same replacement process as the conductive layer 22, the stopper layer 81 may be provided further away from the bottom side of the contact CC than the conductive layer 21.

[0095] (Third Modification) FIG. 27 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1A according to a third modification. FIG. 27 shows the same region as FIG. 10 and displays coordinate axes based on the semiconductor substrate W1. The third modification corresponds to a case where, in the memory device 1 according to the embodiment, hole formation processes corresponding to the memory pillar MP, the contact CC, and the PN contact PNC are performed simultaneously. In this example, as in the second modification, a stopper layer 81 is provided in each of the contact region CA and the PN contact region PNA. When hole formation processes corresponding to the memory pillar MP, the contact CC, and the PN contact PNC are performed simultaneously, the heights of the lower end of the memory pillar MP (the end farther from the source line SL), the lower end of the contact CC (the end farther from the source line SL), and the lower end of the PN contact PNC (the end farther from the source line SL) are aligned. When hole formation processes corresponding to the memory pillar MP, the contact CC, and the PN contact PNC are performed simultaneously as in the third modification, the number of manufacturing steps can be reduced. Therefore, the memory device 1A according to the third modification can reduce the manufacturing cost of the memory device 1A compared to the embodiment. In the third modified example, the case where the processing of the contacts CC and PN contacts PNC and the processing of the memory pillars MP are integrated has been illustrated, but the present invention is not limited to this. The processing of the contacts CC and PN contacts PNC and the processing of the slits SLT, etc. may also be integrated. Even in such a case, the manufacturing cost of the memory device 1A can be reduced.

[0096] (Fourth Modification) FIG. 28 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1B according to a fourth modification. As shown in FIG. 28, the fourth modification corresponds to a case where the memory device 1B is formed using a single semiconductor substrate SUB, and a CMOS circuit is disposed below the stacked wiring that constitutes the memory cell array 10. In this case, in the memory device 1B, the source line SL (the conductive layer 21) is located between the semiconductor substrate SUB and the stacked wiring (the plurality of conductive layers 22). Even in such a case, the memory device 1B may have a configuration in which contacts CC and PN contacts PNC are formed, as in the embodiment, and the contacts CC and the stacked wiring are electrically connected by performing a conduction process. As a result, the memory device 1B according to the fourth modification can reduce the manufacturing cost of the memory device 1B, as in the embodiment.

[0097] (Fifth Modification) Fig. 29 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1C according to a fifth modification. Fig. 29 shows an example of the structure of the memory cell array 10 after the semiconductor substrates W1 and W2 are bonded, and displays coordinate axes based on the semiconductor substrate W1. Note that in this example, the semiconductor substrate W2 is removed after the bonding process of the semiconductor substrates W1 and W2, and a wiring layer 300 is formed. As shown in Fig. 29, the memory device 1C includes, for example, conductor layers 21, 22a, 22b, 23, 24 to 27, insulator layers 31, 32a, 32b, 33 to 35, and 82, a memory pillar MPa, contacts CC, CV, V0 to V2, and a PN contact PNC.

[0098] The memory cell array 10 in the fifth modification differs from the memory cell array 10 in the embodiment in the structure between the insulator layer 31 and the insulator layer 33. Specifically, insulator layers 32a and conductor layers 22a are alternately provided below the insulator layer 31. An insulator layer 82 is provided below the lowermost conductor layer 22a. A conductor layer 22b and an insulator layer 32b are alternately provided below the insulator layer 82. An insulator layer 33 is provided on the lowermost conductor layer 22b.

[0099] Each of the conductive layers 22a and 22b is formed, for example, in a plate shape extending along the XY plane. For example, the nine stacked conductive layers 22a are used, in order from the conductive layer 21 side, as select gate lines SGS and eight word lines WL, respectively. For example, the nine stacked conductive layers 22b are used, in order from the conductive layer 21 side, as eight word lines WL and select gate lines SGD, respectively. Each of the conductive layers 22a and 22b contains, for example, tungsten (W). Hereinafter, a division unit in the process of forming holes for forming the memory pillars MPa is referred to as a tier TI. In this example, the memory device 1C includes tiers TI1 and TI2. The tier TI1 includes nine conductive layers 22a. The tier TI2 includes nine conductive layers 22b.

[0100] The memory pillar MPa has a structure in which multiple pillars, each extending along the Z direction, are connected to one another. In this example, the memory pillar MPa includes two pillars connected in the Z direction. Hereinafter, these two pillars are referred to as the lower pillar LMP and the upper pillar UMP based on their positional relationship during memory hole formation. The lower pillar LMP corresponds to the level TI1. The lower pillar LMP is provided to penetrate the insulator layers 31, 32a, and 82 and the multiple conductor layers 22a. The upper pillar UMP is provided below the lower pillar LMP and corresponds to the level TI2. The upper pillar UMP is provided to penetrate the multiple insulator layers 32b and the multiple conductor layers 22b. The connecting portion between the lower pillar LMP and the upper pillar UMP is included in the layer at the height where the insulator layer 82 is provided.

[0101] The lower pillar LMP and the upper pillar UMP share the core member 40, the semiconductor layer 41, and the stacked film 42. That is, the core member 40, the semiconductor layer 41, and the stacked film 42 included in the memory pillar MPa are each continuously provided between the lower pillar LMP and the upper pillar UMP. In this example, the lower pillar LMP and the upper pillar UMP each have a tapered shape. In this case, the XY cross-sectional area of ​​the lower end of the lower pillar LMP is larger than the XY cross-sectional area of ​​the upper end of the upper pillar UMP. Intersections between the lower pillar LMP and each of the nine conductive layers 22a function as a select transistor ST2 and eight memory cell transistors MT, in order from the conductive layer 21 side. Intersections between the upper pillar UMP and each of the nine conductive layers 22b function as eight memory cell transistors MT and a select transistor ST1, in order from the conductive layer 21 side.

[0102] The contacts CC and PN contacts PNC in the fifth modification each contact all of the conductive layers 22a and 22b. Specifically, in this example, the side surfaces of the contacts CC and PN contacts PNC each contact the conductive layers 22a and 22b. The heights (lengths in the Z direction) of the contacts CC are substantially the same. In the fifth modification, the contacts CC associated with a block BLK are electrically connected to different conductive layers 22a or 22b via dielectric breakdown parts BP, as in the embodiment. Note that the contacts CC and PN contacts PNC may each penetrate the uppermost conductive layer 22a. The memory device 1C according to the fifth modification may have a configuration in which the contacts CC and stacked wiring are electrically connected, as in the embodiment.

[0103] FIG. 30 is a cross-sectional view showing an example of a detailed cross-sectional structure of a memory pillar MPa at the boundary between two layers TI1 and TI2 included in a memory device 1C according to a fifth modification. In FIG. 30, the boundary between the layers TI1 and TI2 is shown upside down compared to FIG. 29. As shown in FIG. 30, for example, in a YZ cross-section, the upper end of the lower pillar LMP may have a rounded shape rather than an angular shape. In this case, it cannot be said that the XY cross-sectional area of ​​the upper end of the lower pillar LMP is clearly larger than the XY cross-sectional area of ​​the lower end of the upper pillar UMP. However, the shape of the side surface of the memory pillar MPa is discontinuous at the boundary between the lower pillar LMP and the upper pillar UMP. Specifically, for example, in a YZ cross-section, the side surface SLMP of the lower pillar LMP is offset from the extension line of the side surface SUMP of the upper pillar UMP, which is indicated by a dashed line in FIG. 30. The offset between the two side surfaces SLMP and SUMP can occur in any cross-section including the Z direction, such as an XZ cross-section. In this specification, the boundary portion of the memory pillar MP in two adjacent layers TI in the Z direction can be identified based on the discontinuous portion in the shape of the side surface of the memory pillar MP. The memory pillar MPa may have a structure in which three or more pillars, each extending along the Z direction, are connected. Even in such a case, the memory pillar MPa may have a structure such as that shown in FIG. 30 at the boundary portion of the adjacent layers TI.

[0104] (others) FIG. 31 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bond pads in a memory device 1 according to the embodiment. FIG. 31 shows a conductive layer 73 (bond pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 25 (bond pad) formed using a semiconductor substrate W2 (not shown), and some of the contacts C1, V2, and conductive layers 72 and 24 connected thereto. As shown in FIG. 31, the two opposing bond pads may have different tapered shapes based on the etching direction during their formation. Specifically, the conductive layer 73 formed using the semiconductor substrate W1 has, for example, an inverse tapered shape. The conductive layer 25 formed using the semiconductor substrate W2 has, for example, a tapered shape. Therefore, the cross-sectional shape along the Z direction at the bonded portion of the conductive layer 73 and the conductive layer 25 may not have linear sidewalls but may be non-rectangular. Furthermore, the pair of opposing bond pads may be bonded with a misalignment depending on the alignment during the bonding process. Therefore, a step may be formed between the upper surface of the conductive layer 73 and the lower surface of the conductive layer 25. The pair of opposing bond pads may have a boundary or may be integrated. The bond pads and the contacts C1, V2 connected to the bond pads may be integrally formed. A plurality of corresponding contacts C1, V2 may be connected to the bond pads. For example, the conductive layer 73 may be connected to the conductive layer 72 via a plurality of contacts C1. Similarly, the conductive layer 25 may be connected to the conductive layer 24 via a plurality of contacts V2.

[0105] In the embodiments, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be modified as appropriate. The PN contact region PNA may be removed after the conduction process described in the embodiments is performed. The memory pillar MP may have a structure in which a pillar corresponding to the select gate line SGD is connected to a pillar corresponding to the word line WL. The memory pillar MP and the bit line BL may be connected by multiple contacts connected in the Z direction. A conductive layer may be inserted at the connection portion of the multiple contacts. The number of wiring layers and contacts included in the memory device 1 may be modified as appropriate depending on the circuit design. The memory pillar MP may have a tapered shape, an inverse tapered shape, or a bowing shape. The slit SLT may have a tapered shape, an inverse tapered shape, or a bowing shape. The top, middle, and bottom of the columnar components described in the embodiments are based on their positional relationship during hole processing. In other words, the portion corresponding to the bottom of the hole corresponds to the bottom, the portion corresponding to the middle of the hole corresponds to the middle, and the portion corresponding to the opening of the hole corresponds to the top. The XY cross-sectional structure of the memory pillars MP and the support pillars HR may be circular or elliptical. In this specification, the "XY cross-sectional area" corresponds to the cross-sectional area in a cross section parallel to the semiconductor substrate W1 or W2. Each wiring in the stacked wiring may include a metal oxide film around a conductor such as tungsten. In the stacked wiring, the conductor layers alternately stacked with the insulator layers may be considered to have such a configuration including a metal oxide film.

[0106] The manufacturing processes described in the embodiments are merely examples. For example, other processes may be inserted between each manufacturing process, and the order of manufacturing processes may be changed as long as no problems arise. In this specification, "connected" refers to being electrically connected and does not exclude, for example, the use of another element between them. "Electrically connected" may also refer to an insulator being used as long as it can operate in the same way as an electrically connected structure. "Tapered shape" refers to a shape that becomes thinner as it moves away from a reference member. "Inverse tapered shape" refers to a shape that becomes thicker as it moves away from a reference member. "Columnar" refers to a structure provided in a hole formed during the manufacturing process of the memory device 1. "Diameter" refers to the inner diameter of a hole or the outer diameter of a pillar in a cross section parallel to the surface of the substrate (XY cross section). A "semiconductor substrate" may simply be referred to as a "substrate." A "semiconductor layer" may also be referred to as a "conductor layer." A "region" may be considered a structure contained within a substrate. For example, if the semiconductor substrate W1 is defined as including a memory region MA and a contact region CA, the memory region MA and the contact region CA are respectively associated with different regions above the semiconductor substrate W1. "Height" corresponds to, for example, the distance in the Z direction between the structure to be measured and the semiconductor substrate W1. A structure other than the semiconductor substrate W1 may be used as the basis for "height." "Top (planar) view" corresponds, for example, to viewing the surface of the semiconductor substrate W1 from the vertical direction of the semiconductor substrate W1.

[0107] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0108] 1, 1A, 1B, 1C... memory device, 2... memory controller, 10... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21 to 27, 22a, 22b, 72, 73... conductive layer, 31 to 35, 32a, 32b, 70, 71, 80, 82, 331... insulating layer, 36... insulating member, 40... core member, 41... semiconductor layer, 42... stacked film, 43... tunnel insulating film, 44... insulating film, 45... block insulating film, 50, 60... conductive member, 51... insulating film, 61... P-type semiconductor layer, 62... N-type semiconductor Body layer, 81...stopper layer, 100...CMOS layer, 200...memory layer, 300...wiring layer, B1, B2...junction layer, MP, MPa...memory pillar, LMP...lower pillar, UMP...upper pillar, BL...bit line, WL...word line, SGS, SGD...select gate line, RD...row decoder, SAU...sense amplifier unit, BLK...block, MT...memory cell transistor, ST1, ST2...select transistor, CC, CC1, CC2, CC3, C1, V0, V1, V2...contact, H1, H2...hole, TR, TR1, TR2, TR3...transistor, MK1, MK2...mask, TI1, TI2...layer, W1, W2...semiconductor substrate

Claims

1. A substrate; a plurality of conductive layers arranged in a first direction above the substrate; a plurality of pillars each extending in the first direction, the portions of which intersect with the plurality of conductive layers functioning as memory cells; a plurality of first contacts each electrically connected to a corresponding one of the plurality of conductive layers; each of the plurality of first contacts is provided extending in the first direction, and has a first conductive member whose outer edge is surrounded by the corresponding conductive layer and electrically connected to the corresponding conductive layer at a local portion of the outer edge in a cross section parallel to a surface of the substrate including the corresponding conductive layer; Memory device.

2. Each of the plurality of first contacts further includes a first insulating film covering a side surface of the first conductive member except for the portion. The memory device of claim 1 .

3. A substrate; a plurality of conductive layers arranged in a first direction above the substrate; a plurality of pillars each extending in the first direction, the portions of which intersect with the plurality of conductive layers functioning as memory cells; a plurality of first contacts each extending in the first direction, provided through the plurality of conductive layers, and electrically connected to a corresponding one of the plurality of conductive layers; Memory device.

4. each of the plurality of first contacts is provided extending in the first direction and includes a first conductive member electrically connected to the corresponding conductive layer, and a first insulating film covering a side surface of the first conductive member except for a connection portion between the first conductive member and the corresponding conductive layer; The memory device of claim 3 .

5. the first contacts are provided to penetrate the same number of the conductive layers as each other; The memory device of claim 3 .

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