Semiconductor storage device

Abstract

To suppress short circuits between wiring layers.SOLUTION: A semiconductor device of an embodiment comprises: a laminate in which a plurality of first conductive layers and a plurality of insulation layers are alternately stacked in a first direction; a second conductive layer extending in a first direction in a region outside the laminate; a third conductive layer extending in the position surrounding the laminate in the first direction when viewed from the first direction of the laminate; a first wiring layer provided above the laminate and extending in a second direction crossing the first direction; a second wiring layer provided above the laminate and spaced apart from the first wiring layer in the second direction; an electrode layer provided above the first and second wiring layers, and connected to the upper parts of the second and third conductive layers in a region between the first and second wiring layers; and a pad part provided in the electrode layer and supplying external power to the second and third conductive layers via the electrode layer. A first region including the first wiring layer, the pad part, and the second conductive layer, and a second region including the second wiring layer and the third conductive layer are adjacent to each other in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices, an edge seal is sometimes placed outside the element region to protect the elements. An insulating layer is filled around the element region and the edge seal. Source lines connected to the elements and electrode layers that penetrate between the source lines and connect to the elements and the edge seal are placed above the insulating layer. The electrode layer connected to the elements and the electrode layer connected to the edge seal are electrically isolated.

[0003] However, various heat treatments during the manufacturing process of a semiconductor memory device can deform the source lines between the electrode layers, which can lead to poor formation of the electrode layers and short circuits between electrically isolated electrode layers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-88563 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor memory device that can suppress short circuits between electrode layers. [Means for solving the problem]

[0006] The semiconductor device of the embodiment includes a stacked body in which a plurality of first conductive layers and a plurality of insulating layers are alternately stacked in a first direction; a second conductive layer extending in the first direction of the stacked body in an area outside the stacked body; a third conductive layer extending in the first direction at a position surrounding the stacked body when viewed from the first direction of the stacked body; a first wiring layer provided above the stacked body and extending in a second direction intersecting the first direction; and a second wiring layer provided above the stacked body and spaced apart from the first wiring layer in the second direction. an electrode layer provided above the first wiring layer and the second wiring layer and connected to the upper parts of the second conductive layer and the third conductive layer, respectively, in a region between the first wiring layer and the second wiring layer; and a pad portion provided in the electrode layer and supplying external power to the second conductive layer and the third conductive layer via the electrode layer, wherein a first region including the first wiring layer, the pad portion, and the second conductive layer and a second region including the second wiring layer and the third conductive layer are adjacent to each other in the second direction. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment. [Figure 2] 5A and 5B are diagrams illustrating the positional relationship of components in a peripheral region and an outer peripheral region according to an embodiment. [Figure 3] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] FIG. 1 is a diagram illustrating a semiconductor memory device according to a comparative example. [Figure 15] FIG. 1 is a diagram illustrating a semiconductor memory device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] (Configuration example of semiconductor memory device) FIG. 1 is a diagram illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. Specifically, FIG. 1(a) is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1(b) is a top view schematically illustrating the semiconductor memory device 1. FIG. 1(a) is also a cross-sectional view taken along line AA in FIG. 1(b). However, hatching is omitted in FIG. 1(a) to facilitate clarity of the drawing. Furthermore, for ease of explanation, FIG. 1(b) also illustrates components that are not necessarily visible when viewed from above, such as an edge seal ES.

[0010] In this specification, both the X direction and the Y direction are directions along the plane direction of a plurality of word lines WL, which will be described later, and are perpendicular to each other. The X direction and the Y direction are directions that intersect with the stacking direction of the plurality of word lines WL. The stacking direction of the plurality of word lines WL is an example of a first direction, and the X direction is an example of a second direction.

[0011] 1(a), the semiconductor memory device 1 includes a peripheral circuit CBA, a plurality of word lines WL, a source-side wiring layer BSL, and an electrode layer MA, in this order, above a semiconductor substrate SB. In the following description, the side on which the semiconductor substrate SB is arranged is referred to as the lower side of the semiconductor memory device 1.

[0012] The semiconductor substrate SB is, for example, a silicon substrate, etc. A peripheral circuit CBA including a plurality of transistors TR, etc. is arranged on the semiconductor substrate SB. The peripheral circuit CBA contributes to the operation of the memory cells, which will be described later.

[0013] The peripheral circuit CBA is covered with an insulating layer 40. An edge seal ESc is disposed in the insulating layer 40 around the peripheral circuit CBA, extending through the insulating layer 40 from the semiconductor substrate SB side to the front surface side of the insulating layer 40. A plurality of word lines WL are stacked above the insulating layer 40.

[0014] The word lines WL are alternately stacked with the insulating layers one by one to form a laminated body LM. The word lines WL are an example of a first conductive layer. Each of the insulating layers is an example of a first insulating layer. The word lines WL are covered with an insulating layer 50 and are connected to an insulating layer 40 that covers the peripheral circuit CBA via the insulating layer 50. The insulating layer 50 also extends around the word lines WL. A memory region MR is arranged in the word lines WL, and a staircase region SR is arranged at the end of the word lines WL.

[0015] Although not shown, a plurality of plate-shaped contacts are arranged on the plurality of word lines WL, penetrating the word lines WL in the stacking direction and extending in the X direction. The plurality of word lines WL are divided in the Y direction by a plurality of plate-shaped contacts. The insulating layer 50 covering the plurality of word lines WL is also divided in the Y direction by a plurality of plate-shaped contacts. A plurality of memory regions MR, staircase regions SR, and peripheral regions PR, which will be described later, are arranged side by side in the X direction between the plurality of plate-shaped contacts.

[0016] In the memory region MR, pillars PL are arranged as a plurality of semiconductor layers penetrating the laminate LM in a stacking direction, which is a first direction. Memory cells are formed as memory layers at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0017] In the staircase region SR, the end of the laminated body LM is processed in a staircase shape. As a result, the ends of the word lines WL expand outward as they go upward. Contacts CC are connected to each of the staircase-shaped layers of the word lines WL.

[0018] These contacts CC individually connect the word lines WL, which are stacked in multiple layers. These contacts CC apply write and read voltages to memory cells included in the memory region MR at the center of the word lines WL via the word lines WL at the same height as the memory cells. The various voltages applied to the memory cells from the contacts CC are controlled by peripheral circuits CBA electrically connected to these contacts CC.

[0019] The area outside the staircase region SR is the peripheral region PR. A contact C3 is arranged in the peripheral region PR. The contact C3 extends in the insulating layer 50 in the stacking direction of the multiple word lines WL. The contact C3 is electrically connected to an electrode layer MA (described later) on its upper surface and to a peripheral circuit CBA at its lower end via a plug V0 (described later). External power applied to the electrode layer MA is supplied to the peripheral circuit CBA via the contact C3. The contact C3 is an example of a second conductive layer.

[0020] The memory region MR, staircase region SR, and peripheral region PR described above constitute part of the element region 11 shown in FIG. 1(b). The frame line La shown in FIG. 1(b) indicates the outermost periphery of the element region 11, and the frame line Lb indicates the outermost periphery of the semiconductor memory device 1. The area outside the element region 11, i.e., the area between the frame lines La and Lb, is the outer periphery region 12. In other words, the element region 11 and the outer periphery region 12 are adjacent to each other via the frame line La. The element region 11 is an example of a first region, and the outer periphery region 12 is an example of a second region.

[0021] More specifically, in FIG. 1(b), if the side of the outer peripheral region 12 indicated by line AA is referred to as the outer peripheral region 12a, an edge seal ES extending along the Y direction is disposed in the outer peripheral region 12a. Furthermore, if the portion of the outer peripheral region 12 facing the outer peripheral region 12a in the X direction across the element region 11 is referred to as the outer peripheral region 12b, an edge seal ES as a fourth conductive layer extending along the Y direction is also disposed in the outer peripheral region 12b. The outer peripheral region 12b is an example of a fourth region. Furthermore, the edge seal ES is an example of a third conductive layer.

[0022] The edge seal ES is configured to include an edge seal ESm that extends in the stack direction through the insulating layer 50 and the above-mentioned edge seal ESc that extends through the insulating layer 40. The edge seal ESm is an example of a third conductive layer. However, the third conductive layer may also include the edge seal ESc.

[0023] When viewed from the stacking direction, the edge seal ESm is disposed at a position that surrounds the laminate LM and the wiring and the like associated with the laminate LM. The edge seal ESm is connected at its upper surface to an electrode layer MA, which will be described later. That is, the edge seal ESm is disposed over the entire height of the pillars PL and contacts CC in the insulating layer 50, and the multiple plugs CH, V2, bit lines BL, and wiring layers MX, M2 connected to their lower ends.

[0024] The edge seal ESc is disposed in a position overlapping the above-mentioned edge seal ESm in the vertical direction and surrounds the peripheral circuit CBA. That is, the edge seal ESc is disposed over the entire height of the multiple wiring layers D0, D1, and D2, as well as the contacts CS and vias C1 and C2 in the insulating layer 40. The edge seal ESc may be connected to the edge seal ESm via each wiring layer.

[0025] The edge seal ES is adjusted to a predetermined potential by external power supplied from the electrode layer MA. This electrically shields the element region 11 surrounded by the edge seal ES from the outside. The edge seal ES also serves as a physical shielding structure, preventing impurities from entering the element region 11 from the outside. The edge seal ES also prevents cracks and chips from forming in the element region 11 when the semiconductor memory device 1 is separated into individual pieces by dicing or the like in the final stage of the manufacturing process.

[0026] A source-side wiring layer BSL and an insulating layer 60 made of silicon oxide or the like are formed in this order on the insulating layer 50. The source-side wiring layer BSL is connected to the upper surfaces of the pillars PL in the memory region MR and functions as a source line of the memory cell. The source-side wiring layer BSL is also provided on the upper surface of the insulating layer 50.

[0027] As described above, the insulating layer 50 is divided in the Y direction by a plurality of plate-like contacts extending in the X direction. Therefore, the source-side wiring layer BSL also extends in the X direction and is provided divided in the Y direction.

[0028] The source-side wiring layer BSL is also provided separately in the X direction. Specifically, the source-side wiring layer BSL includes a source-side wiring layer BSL1 and a source-side wiring layer BSL2 provided on the upper surface of the insulating layer 50 at positions spaced apart in the X direction. More specifically, as shown in FIG. 1(a), the source-side wiring layer BSL is not formed in an area BA on the upper surface of the insulating layer 50, and is thereby provided separately on the element region 11 side and the periphery region 12a side. The source-side wiring layer BSL provided on the element region 11 side is the source-side wiring layer BSL1 as a first wiring layer, and the source-side wiring layer BSL provided on the periphery region 12a side is the source-side wiring layer BSL2 as a second wiring layer.

[0029] An area BA is provided between the source-side wiring layer BSL1 and the source-side wiring layer BSL2. The area BA is provided so as to separate at least the element area 11 and the peripheral area 12a. The detailed configuration of the area BA will be described later.

[0030] The source-side wiring layer BSL has a layered structure in which a source line layer BSLa and an insulating layer BSLb are stacked in this order from below. The source line layer BSLa is, for example, a conductive polysilicon layer in which impurities are diffused, and the insulating layer BSLb is, for example, a silicon oxide layer.

[0031] An electrode layer MA is disposed on the insulating layer 60. The electrode layer MA is provided above the source-side wiring layer BSL, penetrates the insulating layer 60 in the stacking direction in a region BA between the source-side wiring layer BSL1 and the source-side wiring layer BSL2, and connects to the contact C3 and the upper portion of the edge seal ESm. This allows the electrode layer MA to supply applied external power to the contact C3 and the edge seal ESm. The electrode layer MA is, for example, an aluminum layer.

[0032] Specifically, the electrode layer MA includes an electrode layer MA1 connected to the contact C3 and an electrode layer MA2 connected to the edge seal ESm, and the electrode layer MA1 is configured to have a pad portion PD.

[0033] The electrode layer MA1 and the electrode layer MA2 are provided so as to be electrically separated. The electrode layer MA1 is provided mainly in the peripheral region PR and is connected to the contact C3. The electrode layer MA2 is provided mainly in the outer circumferential region 12a and is connected to the edge seal ESm. This electrically separates the contact C3 arranged in the peripheral region PR from the edge seal ESm arranged in the outer circumferential region 12a. The electrode layer MA1 is an example of a first electrode layer, and the electrode layer MA2 is an example of a second electrode layer.

[0034] Specifically, the electrode layer MA1 is configured to have an electrode portion MA11 as a first portion, an electrode portion MA12 as a second portion, and an electrode portion MA13 as a third portion. The electrode portion MA11 and the electrode portion MA12 are portions provided above the source-side wiring layer BSL1. The electrode portion MA13 is located below the electrode portions MA11 and MA12 and is a portion connected to the contact C3. The electrode portion MA11 is also a pad portion PD.

[0035] The electrode layer MA2 is configured to have an electrode portion MA21 as a fourth portion, an electrode portion MA22 as a fifth portion, and an electrode portion MA23 as a sixth portion. The electrode portion MA21 and the electrode portion MA22 are portions provided above the source-side wiring layer BSL2. The electrode portion MA23 is located below the electrode portion MA21 and the electrode portion MA22 and is a portion connected to the edge seal ESm.

[0036] The electrode portions MA13 and MA23 are located above the uppermost word line WL among the word lines WL. An insulating layer 60 is provided as a second insulating layer between the electrode portion MA12 and the electrode portion MA21.

[0037] The electrode layer MA, except for the pad portion PD, is covered with an insulating layer 70 such as polyimide. A bonding TV is provided on the pad portion PD. The bonding TV supplies external power to the contact C3 via the electrode layer MA.

[0038] 1(a) shows an example in which the pad portion PD is provided on the electrode layer MA1 and external power is supplied to the contact C3 via the electrode layer MA1, but this is not the only example. A plurality of pad portions are provided on the electrode layers MA1 and MA2, and some of the plurality of pad portions supply external power to the edge seal ESm via the electrode layer MA2.

[0039] A plurality of wiring layers that electrically connect various components on the laminate LM side to the peripheral circuit CBA are arranged in the insulating layers 40, 50 between the peripheral circuit CBA and the laminate LM. The plurality of wiring layers as metal wiring layers are provided below the laminate LM and are arranged at positions that overlap with the laminate LM in the stacking direction.

[0040] For example, below the laminate LM in the insulating layer 50, a plug V0, a ​​wiring layer M0, a plug V1, a wiring layer M1, a plug V2, a wiring layer M2, and the like are arranged in this order from the word line WL side toward the surface side of the insulating layer 50, and various components on the word line WL side are electrically connected to an electrode pad PDm arranged on the surface of the insulating layer 50. In addition, the insulating layer 50 also includes a plug CH arranged in the same layer as the plug V0, a ​​wiring layer MX and a bit line BL arranged in the same layer as the wiring layer M0, and the like. The plug V0, wiring layer M0, plug V1, wiring layer M1, plug V2, wiring layer M2, and electrode pad PDm described above are examples of metal wiring layers.

[0041] For example, in the insulating layer 40 below the insulating layer 50, a contact CS, a wiring layer D0, a via C1, a wiring layer D1, a via C2, a wiring layer D2, and the like are arranged in this order from the transistor TR side of the peripheral circuit CBA toward the surface side of the insulating layer 40, and the transistor TR and the like are electrically connected to the electrode pad PDc arranged on the surface of the insulating layer 40. The electrode pad PDc is connected to the above-mentioned electrode pad DPm on the surface of the insulating layer 50. This electrically connects the plugs and wiring layers on the side of the above-mentioned word lines WL to the peripheral circuit CBA.

[0042] Here, with reference to FIG. 2, a detailed description will be given of an example of the configuration of the peripheral region PR and the outer circumferential region 12a.

[0043] Fig. 2 is a diagram illustrating the positional relationship of each component in the peripheral region PR and the outer peripheral region 12a according to the embodiment. More specifically, Fig. 2(a) is an XY cross-sectional view taken along line L1-L1 in Fig. 1(a), Fig. 2(b) is an XY cross-sectional view taken along line L2-L2 in Fig. 1(a), and Fig. 2(c) is an XY cross-sectional view taken along line L3-L3 in Fig. 1(a). For ease of explanation, Fig. 2(b) also illustrates some components of the electrode layer MA that are not necessarily visible when viewed in cross section along line L2-L2.

[0044] 2(a), the top surface of the semiconductor memory device 1, except for the pad portion PD, is covered with an insulating layer 70. The pad portion PD is formed in a substantially rectangular shape when viewed from the stacking direction, and has a bonding TV in its substantially central portion.

[0045] 2(b), the area BA is provided in the pad area PA including the pad portion PD provided in the peripheral area PR, the edge seal area EA including the edge seal ES provided in the outer peripheral area 12a, and the boundary between the peripheral area PR and the outer peripheral area 12a. The source-side wiring layer BSL is provided in a distributed manner in the area excluding the area BA. That is, the peripheral area PR and the outer peripheral area 12a are adjacent to each other without the source-side wiring layer BSL interposed therebetween.

[0046] The width L in the X direction of the gap GA provided between the pad area PA and the edge seal area EA is, for example, 2 um or less.

[0047] 2(c), the contact C3 is disposed at a position overlapping the pad region PA in the stacking direction, and has an insulating layer 57 covering the outer periphery of the contact C3, and a conductive layer 27 such as a tungsten layer filled inside the insulating layer 57. This allows the contact C3 to supply external power supplied from the electrode layer MA1 to the peripheral circuit CBA.

[0048] The edge seal ESm also has an insulating layer 58 that covers the sidewall of the edge seal ESm, and a conductive layer 28 such as a tungsten layer that fills the inside of the insulating layer 58. This allows the edge seal ESm to receive external power from the electrode layer MA2.

[0049] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 of the embodiment will be described with reference to FIGS.

[0050] 3 to 13 are diagrams sequentially illustrating some steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment. In each of the drawings, the processed surface of the semiconductor memory device 1 in each step is shown facing upward on the paper. In the following description of the method for manufacturing the semiconductor memory device 1, for convenience of explanation, the direction in which the processed surface faces in each step is referred to as the upward side.

[0051] First, the formation of the portion that will later become the staircase portion SP arranged in the staircase region SR is shown in Fig. 3. Fig. 3 shows a cross section along the X direction of the staircase region SR and the peripheral region PR during manufacturing.

[0052] As shown in FIG. 3(a), an insulating layer 51 is formed on a support substrate SS such as a silicon substrate. A stacked body LMs is formed by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL one by one on the insulating layer 51. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that will later be replaced with the word line WL.

[0053] A mask pattern (not shown) is formed on the laminate LMs to cover a portion of the laminate LMs. The mask pattern is used to etch the insulating layers NL and OL of the laminate LMs. Next, the mask pattern is slimmed back using oxygen plasma or the like, and the newly exposed insulating layers NL and OL of the laminate LMs are etched.

[0054] In this way, slimming of the mask pattern and etching of the insulating layers NL and OL of the laminated body LMs are repeated multiple times.

[0055] As a result, staircase portions SPs, which will later become staircase portions SP, are formed as shown in Fig. 3(b) After the staircase portions SPs are formed, the mask pattern is removed by ashing using oxygen plasma or the like.

[0056] 3(c), an insulating layer 51 is stacked to cover the staircase portion SPs and reach the height position of the upper surface of the unprocessed laminated body LMs. Also, an insulating layer 52 is formed to cover the upper surface of the unprocessed laminated body LMs and the insulating layer 51 of the staircase portion SPs.

[0057] Next, the formation of the pillars PL is shown in Fig. 4. Fig. 4 shows a cross section of the memory region MR in the Y direction during manufacturing.

[0058] 4(a), an insulating layer 51, a stacked body LMs, and an insulating layer 52 are formed in this order on the support substrate SS in an area that will later become the memory region MR by the process shown in Fig. 3. Next, a plurality of memory holes MH are formed that penetrate the insulating layer 52, the stacked body LMs, and the insulating layer 51 and reach the support substrate SS.

[0059] As shown in Figure 4(b), a channel layer CN such as a polysilicon layer or amorphous silicon layer is formed as a semiconductor layer on the sidewall and bottom surface of the memory hole MH, with the memory layer ME interposed therebetween. Furthermore, a core layer CR such as a silicon oxide layer is filled into the void of the memory hole MH remaining inside the channel layer CN. This process forms multiple pillars PL.

[0060] Next, the formation of the word lines WL is shown in Figures 5 and 6. Figures 5 and 6(a) show cross sections along the Y direction of the memory region MR during manufacture, and Figure 6(b) shows cross sections along the X direction of the staircase region SR, peripheral region PR, and outer peripheral region 12a during manufacture.

[0061] 5(a), a plurality of slits ST are formed that reach the support substrate SS by penetrating the insulating layer 52, the laminated body LMs, and the insulating layer 51. The plurality of slits ST also extend in the X direction within the laminated body LMs.

[0062] 5(b), a remover for the insulating layer NL, such as hot phosphoric acid, is poured into the laminate LMs through a slit ST penetrating the laminate LMs to remove the insulating layers NL of the laminate LMs, thereby forming a laminate LMg having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0063] 6(a), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminate LMg through the slits ST to fill the gap layer GP of the laminate LMg with the conductive material, thereby forming a laminate LM in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked one by one.

[0064] At this time, by the process shown in Figure 5(a) above, as shown in Figure 6(b), multiple slits ESa are formed in the peripheral region 12a during manufacturing, penetrating the insulating layer 52 and the insulating layer 51 and reaching the support substrate SS.

[0065] Furthermore, by the process shown in Figure 5(b) above, the insulating layer NL is replaced with word lines WL in the staircase region SR during manufacturing, as shown in Figure 6(b), and a staircase portion SP in which multiple word lines WL are processed into a staircase shape is formed.

[0066] Next, the formation of the plate-like contacts LI and the edge seal ESm is shown in Figure 7. Figure 7(a) shows a cross section along the Y direction of the memory region MR during manufacture. Figure 7(b) shows a cross section along the X direction of the staircase region SR, the peripheral region PR, and the outer peripheral region 12a during manufacture.

[0067] An insulating layer 58 is formed on the side walls of the slit ST and the slit ESa, and a conductive layer 28 is filled in the insulating layer 58 to form the plate-like contact LI that serves as the source line contact and the edge seal ESs that is a part of the edge seal ESm, as shown in Figures 7(a) and 7(b). At this time, unfilled portions may occur in the conductive layer 28 filled in the slits ST and ESa, and voids may be formed in the plate-like contact LI or the edge seal ESs.

[0068] Next, the formation of the contact CC and the contact C3 is shown in Fig. 8. Fig. 8(a) and (b) show cross sections along the X direction of the staircase region SR, the peripheral region PR, and the outer periphery region 12a during manufacturing.

[0069] 8(a), a plurality of contact holes HLc are formed so as to penetrate the insulating layers 52 and 51 and reach the upper surfaces of the individual word lines WL processed in a stepped shape. The contact holes HLc are configured to become contacts CC that will be connected to the word lines WL later.

[0070] In parallel with the formation of the contact hole HLc, a contact hole HLt is formed in the region corresponding to the peripheral region PR, penetrating the insulating layers 52 and 51 to reach the support substrate SS. The contact hole HLt is configured to later become the contact C3.

[0071] 8(b), insulating layers 56 and 57 are formed to cover the side walls of the contact holes HLc and HLt, respectively. For ease of explanation, the insulating layers 56 and 57 are given different reference numerals, but these insulating layers 56 to 57 may be formed collectively in the contact holes HLc and HLt.

[0072] Furthermore, conductive layers 26, 27 such as tungsten layers are filled into the gaps of the contact holes HLc, HLt remaining inside the insulating layers 56, 57. For ease of explanation, different reference numerals are assigned to the conductive layers 26, 27, but these conductive layers 26 to 27 may be formed collectively in the contact holes HLc, HLt. In this manner, contacts CC and C3 are formed.

[0073] Next, the formation of the plugs V0 connected to the contacts C3 and CC is shown in Figure 9. Figures 9(a) and 9(b) show cross sections along the X direction of the staircase region SR, the peripheral region PR, and the outer periphery region 12a during manufacturing.

[0074] 9(a), an insulating layer 53 is formed on the insulating layer 52. Next, a plurality of through holes THv are formed that penetrate the insulating layer 53 and reach the upper surfaces of the plurality of contacts CC and the contact C3, and a recess RCe is formed that penetrates the insulating layer 53 and reaches the upper surface of the edge seal ESs.

[0075] 9(b), a tungsten layer or the like is filled in the through hole THv to form a plurality of plugs V0 connected to the conductive layers 26, 27 of the plurality of contacts CC, C3, respectively. At this time, the tungsten layer or the like is also filled in the recess RCe, and the upper surface of the edge seal ESs, which is a part of the edge seal ESm, extends to the upper surface of the insulating layer 53.

[0076] Thereafter, an insulating layer 54 is further formed on the insulating layer 53, and then the bit lines BL, wiring layers MX, M0, M1, M2, etc., plugs CH, V0, V1, V2, etc., and electrode pads PDm, etc. are formed in sequence. These insulating layers 51 to 54 constitute a part of the insulating layer 50 in Fig. 1. At this time, a configuration corresponding to these wiring layers and plugs, etc., is also formed on the upper surface of the edge seal ESs, and an edge seal ESm is formed that reaches approximately the same height as the wiring layers and plugs associated with the laminate LM.

[0077] Next, the manner in which the support substrate SS on which the laminated body LM and the like are formed is bonded to the semiconductor substrate SB on which the peripheral circuit CBA and the like are formed is shown in Fig. 10. Figs. 10(a) and 10(b) show cross sections along the X direction of the support substrate SS on which the laminated body LM and the like are formed and the semiconductor substrate SB on which the peripheral circuit CBA and the like are formed.

[0078] 10(b), a peripheral circuit CBA including a transistor TR is formed on a semiconductor substrate SB separate from the support substrate SS. An insulating layer 40 covering the peripheral circuit CBA is formed on the semiconductor substrate SB, and wiring layers D0, D1, D2, etc., contacts CS and vias C1, C2, etc., and electrode pads PDc are sequentially formed.

[0079] As shown in Figures 10(a) and (b), various components are formed in the laminate LM, and the surface of the support substrate SS on which the electrode pads PDm are formed, on which the bit lines BL, wiring layers MX, M0, M1, M2, plugs CH, V0, V1, V2, and electrode pads PDm are formed, is opposed to the surface of the semiconductor substrate SB on which the electrode pads PDc are formed.

[0080] Furthermore, the insulating layer 54 on the support substrate SS side and the insulating layer 40 on the semiconductor substrate SB side are bonded together. These insulating layers 54, 40 can be bonded together by activating them in advance, for example, by plasma treatment. Furthermore, when bonding the insulating layers 54, 40 together, the support substrate SS and the semiconductor substrate SB are aligned so that the electrode pads PDm formed on the insulating layer 54 and the electrode pads PDc formed on the insulating layer 40 overlap each other.

[0081] After bonding the insulating layers 54 and 40, annealing is performed to bond the electrode pads PDm and PDc, thereby bonding the support substrate SS and the semiconductor substrate SB together.

[0082] 11 to 13 show the process up to the formation of pad parts PD for supplying external power to the semiconductor memory device 1. Similar to the above-mentioned FIG. 10, FIGS. 11 to 13 show cross sections along the X direction of the staircase region SR, the peripheral region PR, and the outer periphery region 12a during manufacturing.

[0083] First, the formation of the source-side wiring layer BSL above the laminated body LM is shown in Fig. 11. In the steps shown in Fig. 11 and thereafter, various processes are performed with the support substrate SS (see Fig. 10) side facing upward, using the surface on the support substrate SS side as the processing surface.

[0084] Prior to the process of FIG. 11(a), the entire support substrate SS above the laminated body LM and part of the insulating layer 51 are removed by CMP (Chemical Mechanical Polishing) or the like to expose the upper surfaces of the contact C3 and the edge seal ESm.

[0085] As shown in FIG. 11(a), a source line layer BSLa and an insulating layer BSLb are laminated in this order on the insulating layer 51 from which the upper surfaces of the contact C3 and the edge seal ESm are exposed.

[0086] Next, a mask pattern (not shown) having an opening corresponding to the region BA is formed on the insulating layer BSLb. The mask pattern is used to sequentially etch the insulating layer BSLb and the source line layer BSLa. After the insulating layer BSLb and the source line layer BSLa are removed from the region BA, the mask pattern is removed. As a result, a plurality of source-side wiring layers BSL are formed dispersedly on the insulating layer 51.

[0087] As described above, voids Vd extending in the stacking direction may be formed in the conductive layer 28 of the edge seal ESm. Such voids Vd may expand in the X direction due to various heat treatments in the processes shown in FIG. 11 and subsequent steps. As the voids Vd expand, the insulating layer 51 near the edge seal ESm may also be compressed in the X direction, which may apply stress to the layers above the insulating layer 51. As described above, removing the source-side wiring layer BSL near the edge seal ESm prevents the source-side wiring layer BSL from peeling off from the insulating layer 51 due to the influence of stress from the insulating layer 51. The voids Vd are an example of an air gap.

[0088] Next, FIG. 12 shows how electrode layers MA1 and MA2 are formed above the plurality of source-side wiring layers BSL.

[0089] First, an insulating layer 60 is formed to cover the entire upper surface of the insulating layer 51 on which the source-side wiring layer BSL is formed. Next, as shown in Fig. 12(a), a recess Hc is formed in the region BA, penetrating the insulating layer 60 to reach the upper surface of the contact C3, and a recess He is formed in the region BA, penetrating the insulating layer 60 to reach the upper surface of the edge seal ESm.

[0090] An aluminum layer, which will later become the electrode layer MA, is formed on the upper surface of the insulating layer 60 and on the sidewalls and bottom surfaces of the recesses Hc and He. The aluminum layer is formed by, for example, a vapor deposition method.

[0091] Next, a mask pattern (not shown) having the patterns of the electrode layers MA1 and MA2 is formed. Furthermore, using the mask pattern, the aluminum layer is etched until the insulating layer 60 is exposed. This forms the electrode layers MA1 and MA2. The electrode layers MA1 and MA2 are electrically isolated from each other by having gaps GA or the like in some parts, and are formed into a predetermined pattern with gaps GB also in the electrode layer MA1. After the electrode layers MA1 and MA2 are formed, the mask pattern is removed. The electrode layers MA1 and MA2 have recesses Hx and Hy, respectively, at the positions where the recesses Hc and He were formed. This connects the electrode layer MA1 to the contact C3, and the electrode layer MA2 to the edge seal ESm.

[0092] Next, FIG. 13 shows how pad portions PD are formed on the electrode layer MA.

[0093] First, an insulating layer 70 is formed to fill the recesses Hx and Hy and cover the entire upper surface of the insulating layer 60. Next, as shown in Fig. 13, a recess is formed that penetrates the insulating layer 70 above the electrode layer MA1 and reaches the upper surface of the electrode layer MA, and a bonding TV is formed on the bottom of the recess where the electrode layer MA is exposed. In this way, the pad portion PD is formed.

[0094] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0095] (Comparative Example) 14 and 15 are diagrams illustrating a semiconductor memory device according to a comparative example. More specifically, FIGS. 14(a) to 14(c) and 15(a) to 15(c) are enlarged cross-sectional views along the X direction illustrating a part of the process of forming the electrode layer MAx. FIGS. 14 and 15 respectively show some adverse effects that may occur due to the source-side wiring layer BSLx in the semiconductor memory device according to the comparative example.

[0096] As shown in Figure 14(a), in the manufacturing process of the semiconductor memory device of the comparative example, when the source side wiring layer BSLx is removed from the pad region and the edge seal region and etched into a predetermined pattern, the source side wiring layer BSLx remains without being removed in the region between, for example, the pad region having the contact C3 and the edge seal region having the edge seal ESm.

[0097] As described above, voids Vd may be formed in the process of forming the edge seal ESm, and these voids Vd may expand in the X direction due to various heat treatments. As a result, the insulating layer 51 near the edge seal ESm may also be compressed in the X direction as the voids Vd expand. Compression of the insulating layer 51 in the X direction may apply stress to the layers above the insulating layer 51. As a result, as shown in FIG. 14(b), the source-side wiring layer BSLx may peel off from the insulating layer 51.

[0098] 14(c), when an attempt is made to form an insulating layer 60 and an electrode layer MAx on such a source-side wiring layer BSLx, the source line layer BSLax and the insulating layer BSLbx peeled off from the insulating layer 51 may prevent the insulating layer 60 and the electrode layer MAx from being properly formed, and MA1x and MA2x may become conductive across a gap GAx, etc. This may cause a short circuit between the contact C3 and the edge seal ESm.

[0099] Incidentally, in order to suppress the expansion of the void Vd, a technique has been proposed in which a bridging film is provided at the lower end of the edge seal ESm to connect the insulating layers 51 on both sides of the edge seal ESm in the X direction. While this makes it possible to suppress the expansion of the void Vd, it does not yet completely prevent short circuits between the contact C3 and the edge seal ESm.

[0100] 15(a), when a source-side wiring layer BSLx is formed on the upper surface of the insulating layer 51 between the pad region and the edge seal region, the insulating layer 60 formed to cover the source-side wiring layer BSLx may rise by the height of the source-side wiring layer BSLx, and a step Ld recessed in the stacking direction may be formed in the shoulder portion of the insulating layer 60. When an electrode layer MAx is formed on the upper surface of the insulating layer 60 having such a step Ld, a step Lm is also formed in the portion of the electrode layer MAx covering the step Ld, as shown in FIG.

[0101] 15(c), if a gap GAx is formed between the electrode layer MAx and the electrode layers MAX1 and MAx2 at such a step Lm, a residue Rd of the electrode layer MAx may remain at the step Lm. Such residue Rd may cause a short circuit between the electrode layer MAx1 and the electrode layer MAx2.

[0102] According to the embodiment, the semiconductor memory device includes a plurality of source-side wiring layers BSL distributed over the laminate LM, an electrode layer MA provided over the source-side wiring layers BSL and connected to the contacts C3 and the upper portions of the edge seal ESm in an area BA between the plurality of source-side wiring layers BSL, and a pad portion provided over the electrode layer MA and supplying external power to the contacts C3 and the edge seal ESm via the electrode layer MA. The pad portion PD and the contacts C3 are provided in the element region 11, and the edge seal ESm is provided in the peripheral region 12a. The element region 11 and the peripheral region 12a are in contact with each other without the source-side wiring layer BSL interposed therebetween.

[0103] In this way, since the source-side wiring layer BSL is not formed in the region BA, film peeling of the source-side wiring layer BSL does not occur, and therefore, defective formation of the electrode layers MA1 and MA2 can be suppressed, and thus short circuits between the electrode layers MA1 and MA2 can be suppressed.

[0104] Furthermore, since the thickness of the insulating layer 60 in the region BA can be made uniform, the gap GA can be more reliably formed without residue Rd, thereby more reliably suppressing short circuits between the electrode layer MA1 and the electrode layer MA2.

[0105] In the above-described embodiment, the source-side wiring layer BSL is formed on the laminate LM by a backside process after bonding to the semiconductor substrate SB. However, the source-side wiring layer may be formed in a process on the support substrate SS. In this case, after a conductive polysilicon layer or the like that will become the source-side wiring layer BSL is formed on the support substrate SS, the laminate LMs or the like can be formed sequentially. After that, bonding to the semiconductor substrate SB is performed, and the conductive polysilicon layer is processed into the pattern of the source-side wiring layer.

[0106] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0107] 1...semiconductor memory device, 11...element region, 12, 12a, 12b...peripheral region, 40, 50, 60, 70...insulating layer, BSL...source side wiring layer, BSLa...source line layer, BSLb...insulating layer, C3, CC...contact, ES, ESm, ESc...edge seal, BA...region, EA...edge seal region, GA, GB...gap, LM, LMg, LMs...laminated body, MA, MA1, MA2...electrode layer, MR...memory region, NL, OL...insulating layer, PA...pad region, PD...pad portion, PR...peripheral region, SB...semiconductor substrate, SS...support substrate, SR...staircase region, TR...transistor, Vd...void, WL...word line.

Claims

1. a laminate in which a plurality of first conductive layers and a plurality of insulating layers are alternately stacked in a first direction; a second conductive layer extending in the first direction of the stack in an area outside the stack; a third conductive layer extending in the first direction at a position surrounding the stacked body when viewed from the first direction of the stacked body; a first wiring layer provided above the stacked body and extending in a second direction intersecting the first direction; a second wiring layer provided above the stacked body and spaced apart from the first wiring layer in the second direction; an electrode layer provided above the first wiring layer and the second wiring layer, and connected to an upper portion of the second conductive layer and an upper portion of the third conductive layer in a region between the first wiring layer and the second wiring layer; a pad portion provided on the electrode layer and configured to supply external power to the second conductive layer and the third conductive layer via the electrode layer; Equipped with A first region including the first wiring layer, the pad portion, and the second conductive layer and a second region including the second wiring layer and the third conductive layer are adjacent to each other in the second direction. Semiconductor memory device.

2. a semiconductor layer that penetrates the stacked body in the first direction and is connected to a part of the first wiring layer; 2. The semiconductor memory device according to claim 1.

3. the electrode layer includes a first electrode layer provided in the first region and a second electrode layer provided in the second region, and the first electrode layer and the second electrode layer are separated from each other; 3. The semiconductor memory device according to claim 2.

4. the third conductive layer has a gap extending in the vertical direction of the laminate; 2. The semiconductor memory device according to claim 1.

5. a plurality of transistors provided below the stacked body and electrically connected to the electrode layer via the third conductive layer; Further provided with 2. The semiconductor memory device according to claim 1.

6. a first region including a stack of a plurality of first conductive layers and a plurality of first insulating layers alternately stacked in a first direction, and a second conductive layer extending in the first direction; a second region provided adjacent to the first region in a second direction intersecting the first direction and including a third conductive layer extending in the first direction; a first wiring layer provided above the stacked body; a first electrode layer including a first portion and a second portion provided above the first wiring layer, and a third portion provided between the first portion and the second portion, positioned below the first portion and the second portion, and connected to the second conductive layer; a second electrode layer including a fourth portion and a fifth portion provided above the first wiring layer, and a sixth portion provided between the fourth portion and the fifth portion, positioned below the fourth portion and the fifth portion, and connected to the third conductive layer; a second insulating layer provided between the second portion and the fourth portion; A semiconductor memory device comprising:

7. The first portion is a pad portion including a bonding.

7. The semiconductor memory device according to claim 6.

8. The third portion and the sixth portion are located above the uppermost first conductive layer of the plurality of first conductive layers.

7. The semiconductor memory device according to claim 6.

9. a fourth region located opposite the second region and the first region in the second direction, including a fourth conductive layer extending in the first direction, and connected to the third conductive layer; The semiconductor memory device according to claim 6 , further comprising:

10. a semiconductor layer that penetrates the stacked body and extends in the first direction; and a memory layer that is provided between the semiconductor layer and the first conductive layer; The semiconductor memory device according to claim 6 , further comprising:

11. the third conductive layer has a void extending in the first direction; 7. The semiconductor memory device according to claim 6.

12. a plurality of transistors provided below the stacked body and electrically connected to the second electrode layer via the third conductive layer; Further provided with 7. The semiconductor memory device according to claim 6.

13. the second insulating layer is provided above the first wiring layer; 7. The semiconductor memory device according to claim 6.

14. the first wiring layer and a second wiring layer provided apart in the second direction, the first electrode layer and the second electrode layer being provided between the first wiring layer and the second wiring layer; 7. The semiconductor memory device according to claim 6.

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