Semiconductor memory device

Abstract

To improve a yield.SOLUTION: A semiconductor memory device includes: a first semiconductor layer 32; a plurality of first wiring layers 35; a plurality of second wiring layers 35; a third wiring layer 35; a third memory pillar MP; a first support pillar LHR1 passing the plurality of first wiring layers in a first region; a second support pillar UHR1 passing at least the plurality of second wiring layers and the third wiring layer in the first region; a third support pillar LHR2 which passes at least one layer in the plurality of first wiring layers in a second region and of which the diameter is larger than the first and second support pillars; and a fourth support pillar UHR2 which is provided on the third support pillar in the second region and passes the plurality of second wiring layers and the third wiring layer and of which the diameter is larger than the first and second support pillars.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as one type of semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,978,766 [Patent Document 2] Japanese Patent Publication No. 2020-145311 [Patent Document 3] Japanese Patent Publication No. 2020-126943 [Patent Document 4] Japanese Patent Application Publication No. 2019-057623 [Patent Document 5] U.S. Patent No. 9,768,233 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor memory device that can improve yield. [Means for solving the problem]

[0005] The semiconductor memory device according to the embodiment includes a first semiconductor layer provided above a substrate, a plurality of first wiring layers stacked above the first semiconductor layer and spaced apart from each other in a first direction, a plurality of second wiring layers stacked above the plurality of first wiring layers and spaced apart from each other in the first direction, a third wiring layer provided above the plurality of second wiring layers, a first memory pillar passing through the plurality of first wiring layers in the first direction, and a third memory pillar including a second memory pillar provided on the first memory pillar and passing through the plurality of second wiring layers and the third wiring layer in the first direction, and a first contact plug provided on the third wiring layer. the second region in which second contact plugs are provided on each of the plurality of second wiring layers; a first support pillar passing through the plurality of first wiring layers in the first region; a second support pillar passing through at least the plurality of second wiring layers and the third wiring layer in the first region; a third support pillar passing through at least one of the plurality of first wiring layers in the second region and having a diameter larger than the first support pillar and the second support pillar; and a fourth support pillar provided on the third support pillar in the second region and having a diameter larger than the first support pillar and the second support pillar. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 4] Enlarged view of region ER in Figure 3 . [Figure 5] FIG. 5 is a cross-sectional view of the memory cell array taken along line XI-XI in FIG. 4. [Figure 6] FIG. 12 is a cross-sectional view of the memory cell array taken along line XII-XII in FIG. [Figure 7] XY-plane cross-section of the memory pillar along line VI-VI in Figure 6. [Figure 8]3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 9] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 10] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 11] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 12] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 13] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 14] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 15] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 16] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 17] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 18] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 19] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 20] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 21]3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 22] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 23] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 24] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 25] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 26] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 27] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 28] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 29] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 30] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 31] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 32] 3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 33] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 34]3A to 3C are plan views of a memory cell array included in the semiconductor memory device according to the first embodiment, illustrating manufacturing processes of the memory cell array. [Figure 35] 3A to 3C are cross-sectional views of a memory cell array illustrating a manufacturing process of the memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 36] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to a second embodiment. [Figure 37] FIG. 37 is a cross-sectional view of the memory cell array taken along line XI-XI in FIG. [Figure 38] 10A to 10C are plan views of a memory cell array included in a semiconductor memory device according to a second embodiment, illustrating a manufacturing process of the memory cell array. [Figure 39] 10A to 10C are cross-sectional views of a memory cell array included in a semiconductor memory device according to a second embodiment, illustrating a manufacturing process of the memory cell array. [Figure 40] 10A to 10C are plan views of a memory cell array included in a semiconductor memory device according to a second embodiment, illustrating a manufacturing process of the memory cell array. [Figure 41] 10A to 10C are cross-sectional views of a memory cell array included in a semiconductor memory device according to a second embodiment, illustrating a manufacturing process of the memory cell array. [Figure 42] FIG. 11 is a plan view showing an example of a planar layout of a memory cell array included in a semiconductor memory device according to a third embodiment. [Figure 43] FIG. 43 is a cross-sectional view of the memory cell array taken along line XI-XI in FIG. 42. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Here, subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] 1. First embodiment A semiconductor memory device 1 according to the first embodiment will be described below. In the following, the semiconductor memory device 1 will be described by taking as an example a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally on a semiconductor substrate.

[0009] 1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of a semiconductor memory device 1. Note that in Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0010] As shown in FIG. 1, the semiconductor memory device 1 includes a memory core unit 10 and a peripheral circuit unit 20.

[0011] The memory core unit 10 includes a memory cell array 11, a row decoder 12, and a sense amplifier 13.

[0012] The memory cell array 11 is an area in which nonvolatile memory cell transistors are arranged three-dimensionally. The memory cell array 11 includes multiple blocks BLK. In the example shown in FIG. 1, the memory cell array 11 includes four blocks BLK0 to BLK3. The blocks BLK are, for example, a collection of multiple memory cell transistors from which data is erased collectively. The blocks BLK include multiple memory cell transistors associated with rows and columns. Each block BLK includes multiple string units SU. In the example shown in FIG. 1, the block BLK includes six string units SU0, SU1, SU2, SU3, SU4, and SU5. The string unit SU includes, for example, a collection of multiple NAND strings NS that are selected collectively in a write operation or a read operation. The NAND string NS includes a collection of multiple memory cell transistors connected in series. The number of blocks BLK in the memory cell array 11 and the number of string units SU in each block BLK are arbitrary. Details of the memory cell array 11 will be described later.

[0013] The row decoder 12 is a circuit that decodes row addresses. The row decoder 12 receives row addresses input from an external controller. Based on the results of decoding the row addresses, the row decoder 12 selects row-direction wiring (word lines and select gate lines, which will be described later) in the memory cell array 11. The row decoder 12 supplies a voltage to the selected row-direction wiring.

[0014] The sense amplifier 13 is a circuit that writes and reads data. When reading data, the sense amplifier 13 reads data from memory cell transistors in one of the blocks BLK. When writing data, the sense amplifier 13 supplies a voltage based on the write data to the memory cell array 11.

[0015] The peripheral circuit section 20 includes a sequencer 21 and a voltage generating circuit 22 .

[0016] The sequencer 21 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generation circuit 22, the row decoder 12, the sense amplifier 13, etc. during write, read, and erase operations.

[0017] The voltage generating circuit 22 generates voltages used in the write operation, read operation, and erase operation, and supplies them to the row decoder 12, the sense amplifier 13, and the like.

[0018] 1.2 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell array 11. Note that the example shown in Fig. 2 shows one block BLK, and the other blocks BLK also have the same configuration.

[0019] The block BLK includes, for example, six string units SU0 to SU5. The number of string units SU included in the block BLK is arbitrary. The string unit SU is, for example, a set of multiple NAND strings NS that are collectively selected in a write operation or a read operation.

[0020] Next, the internal configuration of the string unit SU will be described. The string unit SU includes a plurality of NAND strings NS. The NAND string NS is a collection of a plurality of memory cell transistors connected in series. Each of the plurality of NAND strings NS in the string unit SU is connected to one of bit lines BL0 to BLm (m is an integer equal to or greater than 1).

[0021] Next, the internal configuration of the NAND strings NS will be described. Each NAND string NS includes multiple memory cell transistors MC, one or more select transistors ST1, and one or more select transistors ST2. In the example shown in Figure 2, the NAND string NS includes eight memory cell transistors MC0 to MC7, one select transistor ST1, and one select transistor ST2.

[0022] The memory cell transistor MC is a memory element that stores data in a nonvolatile manner. The memory cell transistor MC includes a control gate and a charge storage film. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that uses an insulator for the charge storage film, or an FG (Floating Gate) type that uses a conductor for the charge storage film. The following describes the case where the memory cell transistor MC is a MONOS type.

[0023] The selection transistors ST1 and ST2 are switching elements and are used to select the string units SU during various operations.

[0024] The current paths of the select transistor ST2, memory cell transistors MC0 to MC7, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0025] The control gates of the memory cell transistors MC0 to MC7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. More specifically, for example, the block BLK includes six string units SU0 to SU5. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for the memory cell transistors MC1 to MC7.

[0026] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3. The gates of the multiple select transistors ST1 in the string unit SU4 are commonly connected to a select gate line SGD4. The gates of the multiple select transistors ST1 in the string unit SU5 are commonly connected to a select gate line SGD5.

[0027] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, like the select gate lines SGD, the select gate line SGS may be provided for each string unit SU.

[0028] The word lines WL0 to WL7, the select gate lines SGD0 to SGD5, and the select gate line SGS are connected to a row decoder 12, respectively.

[0029] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. Each bit line BL is connected to a sense amplifier 13.

[0030] The source line SL is shared among, for example, a plurality of blocks BLK.

[0031] A set of memory cell transistors MC connected to a common word line WL within one string unit SU is referred to as, for example, a "cell unit CU." In other words, a cell unit CU is a set of memory cell transistors MC selected collectively in a write or read operation. A page is a unit of data that is collectively written (or collectively read) to a cell unit CU. For example, when a memory cell transistor MC stores one bit of data, the memory capacity of the cell unit CU is one page. Note that a cell unit CU may have a memory capacity of two or more pages depending on the number of bits of data stored in the memory cell transistor MC.

[0032] 1.3 Planar layout of memory cell array Next, an example of a planar layout of the memory cell array 11 will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view showing an example of a planar layout of the memory cell array 11. FIG. 4 is an enlarged view of an area ER in FIG. 3. The example shown in FIG. 3 shows areas corresponding to four blocks BLK0 to BLK3 included in the memory cell array 11. Note that in the examples shown in FIGS. 3 and 4, some interlayer insulating films are omitted. Note that hatching is added appropriately in the plan views to make the views easier to see. The hatching added in the plan views does not necessarily relate to the materials or properties of the components to which the hatching is added. In the cross-sectional views, illustration of the configuration may be omitted appropriately to make the views easier to see.

[0033] In the following description, the direction parallel to the substrate and in which the word lines WL extend is referred to as the X direction, the direction parallel to the substrate and intersecting the X direction is referred to as the Y direction, and the direction intersecting the X and Y directions and perpendicular to the substrate is referred to as the Z direction.

[0034] 3, the memory cell array 11 includes a terrace region TR1, a cell region CR, and a terrace region TR2. Hereinafter, when there is no need to specify either the terrace region TR1 or TR2, it will be referred to as a "terrace region TR."

[0035] The cell region CR is a region where memory cell transistors MC are arranged.

[0036] The terrace region TR is a connection region between the word lines WL and the select gate lines SGD and SGS and a plurality of corresponding contact plugs. The terrace regions TR1 and TR2 are provided at both ends of the cell region CR in the X direction. The terrace region TR may also be provided within the cell region CR. In the terrace region TR, both ends of the word lines WL and the select gate lines SGD and SGS extending in the X direction are drawn out in a stepped manner. Hereinafter, the stepped drawn portions of the word lines WL and the select gate lines SGD and SGS will be referred to as "terraces." In the following description, when limiting the area of ​​the terrace region TR where the terrace of the select gate line SGD is provided, it will be referred to as the "terrace region TR of the select gate line SGD." The same applies to the other word lines WL0 to WL7 and the select gate line SGS. In the terrace region TR, the word lines WL and the select gate lines SGD and SGS do not have to be drawn out in a stepped manner. Even in this case, contact plugs can be formed that are electrically connected to the target wiring layer but not to other wiring layers.

[0037] Moreover, the memory cell array 11 includes, for example, a plurality of members SLT and a plurality of members SHE.

[0038] The member SLT extends in the X direction and crosses the terrace region TR1, the cell region CR, and the terrace region TR2. Multiple members SLT are arranged in the Y direction. The member SLT has a structure in which an insulator is embedded, for example. The member SLT may include a conductor connected to the source line SL. The member SLT separates adjacent wiring layers (for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS) via the member SLT. Each of the regions separated by the member SLT corresponds to one block BLK.

[0039] The member SHE extends in the X direction and crosses the cell region CR. A plurality of members SHE are arranged in the Y direction. In this embodiment, five members SHE are arranged between two members SLT adjacent to each other in the Y direction. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent wiring layers (selection gate lines SGD) via the member SHE. In the memory cell array 11, each of the regions separated by the members SLT and SHE corresponds to one string unit SU.

[0040] The number of SHE members disposed between two adjacent SLT members can be designed to be any number, and the number of SHE members disposed between two adjacent SLT members is based on the number of string units SU included in each block BLK.

[0041] Next, the planar configuration of the region ER will be described in detail.

[0042] For example, in each block BLK, the select gate line SGS, word lines WL0 to WL7, and select gate line SGD are stacked in order from the substrate side at intervals in the Z direction. The select gate line SGS, word lines WL0 to WL7, and select gate line SGD extend in the X direction, and in the terrace region TR, their respective ends (terraces) are drawn out in a stepped shape.

[0043] As shown in FIG. 4, terraces corresponding to the select gate line SGD, word line WL7, and word line WL6 are provided in the terrace region TR2 from left to right on the page. The same applies to the word lines WL0 to WL5 and select gate line SGS (not shown). For example, in the terrace region TR2, terraces are provided in the order of the select gate line SGD, word lines WL7 to WL0, and select gate line SGS from the cell region CR toward the end in the X direction. Members SLT are provided on each of the two side surfaces of one block BLK facing the Y direction. The members SLT extend in the X and Z directions. The members SLT divide the stacked and spaced select gate line SGS, word lines WL0 to WL7, and select gate line SGD into blocks BLK. Within a block BLK, the select gate line SGD is divided in the Y direction by members SHE. The members SHE extend in the X direction. In the example shown in FIG. 4, the select gate line SGD is divided into six parts by five members SHE. Each of the regions separated by the members SLT and SHE corresponds to one string unit SU. In the example shown in Fig. 4, the six separated regions correspond to string units SU0 to SU5 in order from the top of the page. In other words, the select gate lines SGD0 to SGD5 are arranged in the Y direction in order from the top of the page.

[0044] A plurality of memory pillars MP are provided in the cell region CR. The memory pillars MP are pillars corresponding to the NAND strings NS. The structure of the memory pillars MP will be described in detail later. The memory pillars MP extend in the Z direction. The memory pillars MP penetrate (pass through) the select gate lines SGS, word lines WL0 to WL7, and select gate lines SGD stacked in the Z direction.

[0045] In the example shown in Figure 4, multiple memory pillars MP in the cell region CR are arranged in a staggered pattern in the X direction. The arrangement of the memory pillars MP can be designed as desired. For example, the arrangement of the memory pillars MP does not have to be a staggered pattern. Hereinafter, the diameter (size) of the top surface of a memory pillar MP will be referred to as "diameter Dmp." The top surface (shape of the opening) of a memory pillar MP does not have to be a perfect circle. The pitch between two adjacent memory pillars MP (the distance between the central axes of the two pillars extending in the Z direction) will be referred to as "pitch P1."

[0046] The terrace regions TR1 and TR2 include a plurality of contact plugs CC and a plurality of support pillars HR.

[0047] One end of the contact plugs CC is connected to a terrace of a wiring layer corresponding to any one of the select gate lines SGS, word lines WL0 to WL7, and select gate line SGD. The contact plugs CC are not electrically connected to other wiring layers. For example, the contact plugs CC connected to the terrace of the select gate line SGD are not electrically connected to the select gate line SGS and word lines WL0 to WL7. The other end of the contact plugs CC is electrically connected to the row decoder 12. In the example shown in FIG. 4, five contact plugs CC are connected to the select gate lines SGD0 to SGD5, respectively, three contact plugs CC are connected to the word line WL7, and three contact plugs CC are connected to the word line WL6. The number of contact plugs CC connected to each wiring layer may be one or more. In this embodiment, the diameter (size) of the top surface of the contact plugs CC connected to any one of the select gate lines SGD is approximately the same as the diameter (size) of the top surface of the contact plugs CC connected to any one of the word lines WL0 to WL7 and the select gate line SGS. Note that when these are said to be approximately the same, variations due to the manufacturing process may be included. Hereinafter, the diameter of the upper surface of the contact plug CC in this embodiment will be referred to as "diameter Dcc." Note that the upper surface of the contact plug CC (the shape of the opening) does not have to be a perfect circle. For example, the diameter Dcc of the contact plug CC is larger than the diameter Dmp of the memory pillar MP.

[0048] One method for forming the word lines WL and select gate lines SGD and SGS is to first form a structure corresponding to each wiring layer using a sacrificial film, then replace the sacrificial film with a conductive material to form the wiring layer (hereinafter referred to as "replacement"). In replacement, the sacrificial film is removed to form a void, which is then filled with a conductive material.

[0049] The support pillars HR function as pillars that support the interlayer insulating film having voids during replacement. For example, the support pillars HR have a generally cylindrical structure with an insulator embedded therein. The support pillars HR are not electrically connected to the source lines, word lines WL, and select gate lines SGD and SGS. The support pillars HR extend in the Z direction. In the terrace region TR, the support pillars HR penetrate (pass through) the select gate line SGS, word lines WL0 to WL7, and select gate line SGD stacked in the Z direction. The arrangement of the support pillars HR is arbitrary.

[0050] The support pillar HR includes a lower support pillar LHR and an upper support pillar UHR provided on the lower support pillar LHR. The support pillar HR may include three or more pillars. That is, the support pillar HR may have a structure in which three or more pillars are stacked. Hereinafter, when limiting the lower support pillar LHR and upper support pillar UHR provided in the terrace region TR of the select gate line SGD, they will be referred to as "lower support pillar LHR1" and "upper support pillar UHR1," respectively. When limiting the lower support pillar LHR and upper support pillar UHR provided in the terrace region TR of the word line WL (and the select gate line SGS, not shown), they will be referred to as "lower support pillar LHR2" and "upper support pillar UHR2," respectively.

[0051] As shown in FIG. 4 , in the terrace region TR of the select gate line SGD, the lower support pillars LHR1 and the upper support pillars UHR1 are arranged in a staggered pattern. The diameter and layout of the upper surface of the lower support pillar LHR1 are different from those of the upper support pillar UHR1. The diameter of the upper surface of the lower support pillar LHR1 is denoted as “diameter Dlhr1,” and the diameter of the upper surface of the upper support pillar UHR1 is denoted as “diameter Duhr1.” Note that the upper surfaces (shapes of the openings) of the lower support pillar LHR1 and the upper support pillar UHR1 do not have to be perfect circles. For example, the diameter Dlhr1 of the lower support pillar LHR1 is approximately the same as the diameter Dmp of the memory pillar MP. The diameter Duhr1 of the upper support pillar UHR1 is larger than the diameter Dlhr1 of the lower support pillar LHR1. That is, the diameter Duhr1 of the upper support pillar UHR1 is larger than the diameter Dmp of the memory pillar MP. For example, the diameter Dcc of the contact plug CC is equal to or greater than the diameter Duhr1 of the upper support pillar UHR1.

[0052] The pitch between two adjacent lower support pillars LHR1 is referred to as "pitch P2," and the pitch between two adjacent upper support pillars UHR1 is referred to as "pitch P3." For example, the pitch P2 of the lower support pillars LHR1 is approximately the same as the pitch P1 of the memory pillars MP. The pitch P3 of the upper support pillars UHR1 is larger than the pitch P2 of the lower support pillars LHR1. For example, the pitch P3 of the upper support pillars UHR1 is set to twice the pitch P2 of the lower support pillars LHR1. It is then preferable to position the upper support pillar UHR1 at the center of the three lower support pillars LHR1 arranged in a triangle when viewed in a plan view from the Z direction.

[0053] In the terrace region TR of each select gate line SGD, the contact plug CC is arranged so as to replace, for example, the layout position of the upper support pillar UHR1.

[0054] In the terrace region TR of the word line WL and the select gate line SGS, the lower support pillars LHR2 and the upper support pillars UHR2 are arranged in a matrix, respectively. The diameter and layout of the upper surface of the lower support pillar LHR2 are the same as those of the upper surface of the upper support pillar UHR2. The upper support pillar UHR2 is provided on the lower support pillar LHR2. The diameter of the upper surfaces of the lower support pillar LHR2 and the upper support pillar UHR2 is denoted as "diameter Dhr2". Note that the upper surfaces (the shape of the openings) of the lower support pillar LHR2 and the upper support pillar UHR2 do not have to be perfect circles. The diameter Dhr2 of the lower support pillar LHR2 and the upper support pillar UHR2 is larger than the diameter Duhr1 of the upper support pillar UHR1. Therefore, in this embodiment, the diameters Dmp, Dlhr1, Duhr1, and Dhr2 are in the relationship of Dmp = Dlhr1 < Duhr1 < Dhr2.

[0055] Also, the pitch between two adjacent lower support pillars LHR2 or two adjacent upper support pillars UHR2 is denoted as "pitch P4". The pitch P4 is larger than the pitch P3 of the upper support pillar UHR1. Therefore, in this embodiment, the pitches P1 to P4 are in the relationship of P1 = P2 < P3 < P4.

[0056] In the terrace region TR of the word line WL (and a select gate line SGS not shown), the contact plug CC is arranged, for example, at the centers of four upper support pillars UHR2 arranged in a square in a top view seen from the Z direction.

[0057] 1.4 Cross-sectional structure of the memory cell array Next, an example of a cross-sectional configuration of the memory cell array 11 will be described with reference to FIGS. 5 to 7. FIG. 5 is a cross-sectional view of the memory cell array 11 taken along line XI-XI in FIG. 4. FIG. 6 is a cross-sectional view of the memory cell array 11 taken along line XII-XII in FIG. 4. FIG. 7 is a cross-sectional view of the memory pillar MP in the XY plane taken along line VI-VI in FIG. 6. Note that in the example shown in FIG. 5, for the sake of simplicity, the memory pillar MP, contact plug CC, and conductors (contact plugs, wiring layers, bit lines, etc.) provided on the member SLT are omitted.

[0058] As shown in FIG. 5, the memory cell array 11 includes a semiconductor layer 32, insulating layers 33 and 34, a wiring layer 35, conductors 36 and 42, insulators 37, 38, 40, and 41, and memory pillars MP.

[0059] An insulating layer 31 is provided on the semiconductor substrate 30. For example, the insulating layer 31 includes silicon oxide. Note that circuits such as a row decoder 12 or a sense amplifier 13 may be provided in the region where the insulating layer 31 is provided, i.e., between the semiconductor substrate 30 and the semiconductor layer 32.

[0060] A semiconductor layer 32 functioning as a source line SL is provided on the insulating layer 31. The semiconductor layer 32 extends in the X and Y directions. The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. The semiconductor layer 32a is provided on the insulating layer 31. The semiconductor layer 32b is provided on the semiconductor layer 32a. The semiconductor layer 32c is provided on the semiconductor layer 32b. In the example shown in FIG. 5, the semiconductor layer 32b is provided in the cell region CR, but not in the terrace region TR. The semiconductor layer 32b may also be provided in the terrace region TR. The semiconductor layer 32b is formed, for example, by replacing the insulating layer 33 provided between the semiconductor layer 32a and the semiconductor layer 32c. The semiconductor layers 32a to 32c contain, for example, silicon. The semiconductor layers 32a to 32c also contain, for example, phosphorus (P) as an n-type semiconductor impurity.

[0061] An insulating layer 34 is provided on the semiconductor layer 32. The insulating layer 34 includes, for example, silicon oxide.

[0062] Within the insulating layer 34, for example, ten wiring layers 35 are stacked above the semiconductor layer 32 at intervals in the Z direction. In other words, a plurality of insulating layers 34 and a plurality of wiring layers 35 are stacked alternately. For example, the ten wiring layers 35 function, from the bottom up, as the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD. Note that a plurality of wiring layers 35 functioning as the select gate lines SGS and SGD may be provided. For example, a titanium nitride (TiN) / tungsten (W) stacked structure is used as the conductive material for the wiring layer 35. In this case, the titanium nitride is formed to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten when forming a tungsten film by, for example, chemical vapor deposition (CVD), or as an adhesion layer to improve the adhesion of the tungsten. The wiring layer 35 may also contain a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed so as to cover the conductive material. For example, in each of the wiring layers 35, the high-dielectric-constant material is provided so as to be in contact with the insulating layers 34 and the side surfaces of the memory pillars MP provided above and below the wiring layer 35. Titanium nitride is then provided so as to be in contact with the high-dielectric-constant material. Furthermore, tungsten is provided so as to be in contact with the titanium nitride and to fill the interior of the wiring layer 35. For example, when aluminum oxide is provided as the high-dielectric-constant material, the memory cell transistor MC is also referred to as a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type.

[0063] Next, the internal structure of the member SLT will be described.

[0064] As shown in FIGS. 5 and 6, the member SLT includes a lower member LSLT and an upper member USLT disposed on the lower member LSLT. That is, the member SLT is processed in two separate steps. The member SLT may be processed collectively without being divided, or may be processed in three or more separate steps. The member SLT extends in the X and Z directions. The member SLT penetrates (passes through) ten wiring layers 35 and eleven insulating layers 34. More specifically, for example, the lower member LSLT passes through five wiring layers 35 that function as the select gate lines SGS and word lines WL0 to WL3. For example, the upper member USLT passes through five wiring layers 35 that function as the word lines WL4 to WL7 and the select gate line SGD. The lower end of the member SLT (the lower end of the lower member LSLT) reaches the semiconductor layer 32b. In the following description, the multiple wiring layers 35 corresponding to the select gate lines SGS and word lines WL0 to WL3, respectively, are also referred to as the "lower layer." The plurality of wiring layers 35 corresponding to the word lines WL4 to WL7 and the select gate line SGD are also referred to as "upper layers." The member SLT includes a conductor 36 and an insulator 37. The conductor 36 and the insulator 37 are each formed as a continuous film within the lower member LSLT and the upper member USLT, for example.

[0065] The conductor 36 extends in the X and Z directions. The conductor 36 functions as a contact plug LI. The side surface of the conductor 36 contacts the insulator 37. The bottom surface of the conductor 36 contacts the semiconductor layer 32.

[0066] The insulator 37 is provided to surround the side surfaces of the conductor 36. The insulator 37 prevents the conductor 36 from being electrically connected to the wiring layer 35. For example, the insulator 37 includes silicon oxide.

[0067] Next, the internal configuration of the memory pillar MP will be described.

[0068] As shown in FIG. 6 , the memory pillar MP includes a lower memory pillar LMP, a joint portion JT, and an upper memory pillar UMP. For example, the lower memory pillar LMP passes through five wiring layers 35 that function as select gate lines SGS and word lines WL0 to WL3, i.e., a lower level. For example, the upper memory pillar UMP passes through five wiring layers 35 that function as word lines WL4 to WL7 and select gate lines SGD, i.e., an upper level. The joint portion JT is formed on the lower memory pillar LMP and electrically connects the lower memory pillar LMP and the upper memory pillar UMP. That is, the memory pillar MP is processed in two separate steps. The memory pillar MP may be processed all at once without being divided, or may be processed in three or more separate steps.

[0069] The memory pillars MP extend in the Z direction and pass through the ten wiring layers 35 and the insulating layers 34. The bottoms of the memory pillars MP reach the semiconductor layer 32a. The lower memory pillars LMP and the upper memory pillars UMP have, for example, tapered shapes. The diameter of the joint portion JT along the XY plane is, for example, larger than the diameters of the lower memory pillars LMP and the upper memory pillars UMP at the contact portions with the joint portion JT.

[0070] The memory pillar MP includes a block insulating film 51, a charge storage film 52, a tunnel insulating film 53, a semiconductor film 54, and a core film 55. Each of the block insulating film 51, the charge storage film 52, the tunnel insulating film 53, the semiconductor film 54, and the core film 55 is formed as a continuous film, for example, in the lower memory pillar LMP, the joint part JT, and the upper memory pillar UMP.

[0071] A block insulating film 51, a charge storage film 52, and a tunnel insulating film 53 are stacked, in this order from the outside, on a portion of the side surface of the memory pillar MP and on the bottom surface in contact with the semiconductor layer 32. More specifically, the block insulating film 51, the charge storage film 52, and the tunnel insulating film 53 provided on the side surface of the memory pillar MP are removed in the same layer as the semiconductor layer 32b and in the vicinity thereof. A semiconductor film 54 is provided so as to be in contact with the side surface and bottom surface of the tunnel insulating film 53 and the semiconductor layer 32b. The semiconductor film 54 is a region where the channels of the memory cell transistor MC and the select transistors ST1 and ST2 are formed. The semiconductor film 54 extends in the Z direction. The interior of the semiconductor film 54 is filled with a core film 55.

[0072] For example, the block insulating film 51, the tunnel insulating film 53, and the core film 55 contain silicon oxide. For example, the charge storage film 52 contains silicon nitride (SiN). For example, the semiconductor film 54 contains silicon.

[0073] The cross-sectional structure of the memory pillar MP along the XY plane will be described.

[0074] 7, in a cross section including the wiring layer 35, the core film 55 is provided, for example, in the center of the memory pillar MP. The semiconductor film 54 surrounds the side surfaces of the core film 55. The tunnel insulating film 53 surrounds the side surfaces of the semiconductor film 54. The charge storage film 52 surrounds the side surfaces of the tunnel insulating film 53. The block insulating film 51 surrounds the side surfaces of the charge storage film 52. The wiring layer 35 surrounds the side surfaces of the block insulating film 51.

[0075] 6, the semiconductor film 54 is used as the channels (current paths) of the memory cell transistors MC0 to MC7 and the select transistors ST1 and ST2. The intersection of the memory pillar MP and the wiring layer 35 functioning as the select gate line SGS functions as the select transistor ST2. The intersection of the memory pillar MP and the eight wiring layers 35 functioning as the word lines WL0 to WL7 functions as the memory cell transistors MC0 to MC7. The intersection of the memory pillar MP and the wiring layer 35 functioning as the select gate line SGD functions as the select transistor ST1.

[0076] Next, the member SHE will be described.

[0077] The member SHE separates the wiring layers 35 that function as select gate lines SGD. In other words, the member SHE separates at least the wiring layer 35, among the multiple wiring layers 35, that is located farthest from the semiconductor layer 32. The upper end of the member SHE is located on the uppermost wiring layer 35. The lower end of the member SHE is located in a layer between the wiring layer 35 that functions as the select gate line SGD and the wiring layer 35 that functions as the word line WL. The total number of wiring layers 35 separated by the member SHE increases depending on the number of wiring layers 35 that function as the select gate line SGD. For example, the member SHE is embedded with an insulator 38. The insulator 38 includes, for example, silicon oxide. The upper end of the member SHE and the upper end of the member SLT may or may not be aligned. Furthermore, the upper end of the member SHE and the upper end of the memory pillar MP may or may not be aligned.

[0078] Next, the support pillar HR will be described.

[0079] As shown in FIG. 5, in the terrace region TR of the select gate line SGD, the lower support pillar LHR1 is provided extending in the Z direction. The lower support pillar LHR1 has, for example, a tapered shape. The lower support pillar LHR1 passes through, for example, five wiring layers 35 that function as the select gate line SGS and the word lines WL0 to WL3, i.e., the lower hierarchy. The lower end (bottom) of the lower support pillar LHR1 reaches the semiconductor layer 32a. The upper end of the lower support pillar LHR1 is located, for example, between the wiring layer 35 that functions as the word line WL3 and the wiring layer 35 that functions as the word line WL4. The lower support pillar LHR1 is filled with an insulator 40. The insulator 40 includes, for example, silicon oxide.

[0080] In the terrace region TR of the select gate line SGD, the upper support pillar UHR1 is provided extending in the Z direction. The upper support pillar UHR1 has, for example, a tapered shape. For example, the upper support pillar UHR1 is provided at a different position in the XY plane from the lower support pillar LHR1. In other words, the position of the central axis of the upper support pillar UHR1 extending in the Z direction is different in the X and Y directions from the position of the central axis of the lower support pillar LHR1 extending in the Z direction. The upper support pillar UHR1 passes through, for example, seven wiring layers 35 and insulating layers 34 that function as word lines WL2 to WL7 and the select gate line SGD. In other words, the upper support pillar UHR1 passes through an upper tier and some of the wiring layers 35 in a lower tier. The lower end of the upper support pillar UHR1 is located, for example, between the wiring layer 35 that functions as the word line WL2 and the wiring layer 35 that functions as the word line WL1. The lower end of the upper support pillar UHR1 is located below (closer to the semiconductor layer 32) the upper end of the lower support pillar LHR1, with one or more wiring layers 35 sandwiched between them. The upper support pillar UHR1 contacts the lower support pillar LHR1 and penetrates (passes through) a portion near the upper end of the lower support pillar LHR1 and at least one of the wiring layers 35 in the lower layer. The upper end of the upper support pillar UHR1 is located above the uppermost wiring layer 35 that functions as the select gate line SGD. The upper support pillar UHR1 is embedded with an insulator 41. The insulator 41 includes, for example, silicon oxide. Note that the insulators 40 and 41 may be made of the same material.

[0081] In the terrace region TR of the word line WL and the select gate line SGS, the lower support pillar LHR2 is provided extending in the Z direction. The lower support pillar LHR2 has, for example, a tapered shape. The lower support pillar LHR2 passes through a lower layer. More specifically, the lower support pillar LHR2 provided in the terrace region TR of the select gate line SGS passes through the wiring layer 35 that functions as the select gate line SGS. The lower support pillar LHR2 provided in the terrace region TR of the word line WL0 passes through two wiring layers 35 that function as the select gate line SGS and the word line WL0, respectively. The lower support pillar LHR2 provided in the terrace region TR of the word line WL1 passes through three wiring layers 35 that function as the select gate line SGS and the word lines WL0 and WL1, respectively. The lower support pillar LHR2 provided in the terrace region TR of the word line WL2 passes through four wiring layers 35 that function as the select gate line SGS and the word lines WL0 to WL2, respectively. The lower support pillar LHR2 provided in the terrace region TR of the word lines WL3 to WL7 passes through five wiring layers 35 that function as the select gate line SGS and the word lines WL0 to WL3, respectively. The lower end of each lower support pillar LHR2 reaches the semiconductor layer 32. In the example shown in FIG. 5, the lower end of the lower support pillar LHR2 contacts the insulating layer 33 located between the semiconductor layer 32a and the semiconductor layer 32c, but this is not limiting. For example, the lower end of the lower support pillar LHR2 may reach the semiconductor layer 32a. Like the lower support pillar LHR1, the upper end of the lower support pillar LHR2 is located, for example, between the wiring layer 35 that functions as the word line WL3 and the wiring layer 35 that functions as the word line WL4. Like the lower support pillar LHR1, the lower support pillar LHR2 is buried in an insulator 40.

[0082] In the terrace regions TR of the word lines WL and select gate lines SGS, the upper support pillars UHR2 are provided extending in the Z direction. The upper support pillars UHR2 have, for example, a tapered shape. The upper support pillars UHR2 pass through the upper tier. More specifically, the upper support pillars UHR2 provided in the terrace regions TR of the select gate line SGS and word lines WL0 to WL3 do not pass through the wiring layer 35. The upper support pillars UHR2 provided in the terrace region TR of the word line WL4 pass through the wiring layer 35 that functions as the word line WL4. The upper support pillars UHR2 provided in the terrace region TR of the word line WL5 pass through two wiring layers 35 that function as the word lines WL4 and WL5, respectively. The upper support pillars UHR2 provided in the terrace region TR of the word line WL6 pass through three wiring layers 35 that function as the word lines WL4 to WL6, respectively. The upper support pillar UHR2 provided in the terrace region TR of the word line WL7 passes through four wiring layers 35 that function as the word lines WL4 to WL7. The bottom end of each upper support pillar UHR2 contacts the top end of the lower support pillar LHR2. The upper support pillar UHR2 barely penetrates the lower support pillar LHR2. The upper support pillar UHR2 does not pass through the lower wiring layer 35. Like the upper support pillar UHR1, the top end of the upper support pillar UHR2 is located above the topmost wiring layer 35 that functions as the select gate line SGD. Like the upper support pillar UHR1, the upper support pillar UHR2 is buried in an insulator 41.

[0083] In the terrace region TR, contact plugs CC are provided on each terrace. The contact plugs CC are provided extending in the Z direction. The contact plugs CC have, for example, a tapered shape. The lower ends of the contact plugs CC contact the corresponding wiring layers 35. The upper ends of the contact plugs CC are located above the uppermost wiring layer 35 that functions as the select gate lines SGD. The height of the contact plugs CC varies depending on the position of the terrace to which they are connected. The contact plugs CC are buried with conductors 42. The conductors 42 include, for example, tungsten or copper.

[0084] 1.5 Memory cell array manufacturing method Next, an example of a manufacturing method of the memory cell array 11 will be described with reference to FIGS. 8 to 35. FIGS. 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, and 34 are plan views of the memory cell array 11 illustrating the manufacturing process of the memory cell array 11. FIGS. 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, and 35 are cross-sectional views of the memory cell array 11 illustrating the manufacturing process of the memory cell array 11. The following description focuses on the manufacturing process of the support pillar HR. In this embodiment, a case will be described in which the slits corresponding to the members SLT, the holes corresponding to the memory pillars MP (also referred to as "memory holes"), and the holes corresponding to the support pillars HR are each formed in two separate steps. Each of the member SLT, memory pillar MP, and support pillar HR may be formed by one etching step, or may be formed by three or more etching steps.

[0085] As shown in FIGS. 8 and 9, first, an insulating layer 31 is formed on a semiconductor substrate 30. A semiconductor layer 32a is formed on the insulating layer 31. An insulating layer 33 is formed on the semiconductor layer 32a. More specifically, the insulating layer 33 includes, for example, three insulating layers 33a, 33b, and 33c. For example, the insulating layers 33a and 33c include silicon oxide. The insulating layer 33b includes silicon nitride. Note that the insulating layer 33b is formed in the cell region CR where the insulating layer 33 will be replaced in a process described later, but is not formed in the terrace region TR where the replacement will not be performed. A semiconductor layer 32c is formed on the insulating layer 33. Six insulating layers 34 and five sacrificial films 60 are alternately stacked on the semiconductor layer 32c. The five sacrificial films 60 correspond to a lower layer and are replaced with five wiring layers 35 that function as select gate lines SGS and word lines WL0 to WL3 in a process described later. For example, the sacrificial film 60 is made of silicon nitride.

[0086] In this state, memory holes LMH corresponding to the lower memory pillars LMP and joint parts JT and holes corresponding to the lower support pillars LHR1 are formed. The bottom ends of the memory holes LMH and holes corresponding to the lower support pillars LHR1 reach the semiconductor layer 32a.

[0087] 10 and 11, the holes corresponding to the memory holes LMH and the lower support pillars LHR1 are filled with a sacrificial film 61. The sacrificial film 61 may contain carbon, silicon, or a metal material such as tungsten or titanium nitride.

[0088] 12 and 13, after the insulating layer 34 is formed to protect the upper surface of the sacrificial film 61, the slits corresponding to the lower member LSLT and the holes corresponding to the lower support pillars LHR2 are processed all at once. The lower ends of the slits corresponding to the lower member LSLT and the holes corresponding to the lower support pillars LHR2 reach the insulating layer 33.

[0089] 14 and 15, the slits corresponding to the lower member LSLT and the holes corresponding to the lower support pillars LHR2 are filled with a sacrificial film 62. The sacrificial film 62 may contain carbon, silicon, or a metal material such as tungsten or titanium nitride.

[0090] As shown in FIGS. 16 and 17, in the terrace region TR, the sacrificial film 61 in the hole corresponding to the lower support pillar LHR1 and the sacrificial film 62 in the hole corresponding to the lower support pillar LHR2 are removed, and each hole is filled with the insulator 40.

[0091] 18 and 19, five sacrificial films 60 and five insulating layers 34 are alternately stacked one by one. The five sacrificial films 60 correspond to the upper layers, and in a process described later, are replaced with five wiring layers 35 that function as word lines WL4 to WL7 and select gate lines SGD. The sacrificial films 60 in the terrace regions TR are processed into a stepped shape to form regions corresponding to the terraces of the wiring layers 35. Thereafter, the insulating layers 34 are formed, and the entire surface is planarized by, for example, CMP (Chemical Mechanical Polishing).

[0092] As shown in FIGS. 20 and 21 , the memory hole UMH corresponding to the upper memory pillar UMP and the hole corresponding to the upper support pillar UHR1 are formed at the same time. The lower end of the memory hole UMH reaches the sacrificial film 61 that fills the memory hole LMH. The diameter Duhr1 of the upper support pillar UHR1 is larger than the diameter Dmp of the memory pillar MP. Therefore, when the holes corresponding to the memory hole UMH and the upper support pillar UHR1 are processed at the same time, the depth of the hole corresponding to the upper support pillar UHR1 is deeper than that of the memory hole UMH. That is, the position of the lower end of the hole corresponding to the upper support pillar UHR1 is lower than the position of the lower end of the memory hole UMH (it is closer to the semiconductor layer 32). Therefore, the hole corresponding to the upper support pillar UHR1 penetrates (passes through) a portion near the upper end of the lower support pillar LHR1 and at least one of the multiple sacrificial films 60 corresponding to the lower layer. In the example shown in FIG. 21, the bottom end of the hole corresponding to upper support pillar UHR1 reaches between the sacrificial film 60 corresponding to word line WL1 and the sacrificial film 60 corresponding to word line WL2.

[0093] As shown in FIGS. 22 and 23 , holes corresponding to the upper support pillars UHR1 are filled with a sacrificial film 63. For example, the sacrificial film 63 includes silicon. More specifically, the memory holes UMH and holes corresponding to the upper support pillars UHR1 are filled with the sacrificial film 63. Next, memory pillars MP are formed. More specifically, the sacrificial film 61 in the memory holes LMH and the sacrificial film 63 in the memory holes UMH are removed. Then, a block insulating film 51, a charge storage film 52, a tunnel insulating film 53, a semiconductor film 54, and a core film 55 are formed in this order to fill the memory holes LMH and UMH. The block insulating film 51, the charge storage film 52, the tunnel insulating film 53, the semiconductor film 54, and the core film 55 on the insulating layer 34 are removed to form the memory pillars MP.

[0094] 24 and 25, after an insulating layer 34 is formed to protect the top surfaces of the memory pillars MP, a slit corresponding to the upper member USLT and a hole corresponding to the upper support pillar UHR2 are processed at the same time. The bottom end of the slit corresponding to the upper member USLT reaches the sacrificial film 62 in which the lower member LSLT is embedded. The bottom end of the hole corresponding to the upper support pillar UHR2 reaches the insulator 40 in which the lower support pillar LHR2 is embedded.

[0095] 26 and 27, the slits corresponding to the upper member USLT and the holes corresponding to the upper support pillars UHR2 are filled with a sacrificial film 64. For example, the sacrificial film 64 includes silicon.

[0096] 28 and 29, in the terrace region TR, the sacrificial film 63 in the hole corresponding to the upper support pillar UHR1 and the sacrificial film 64 in the hole corresponding to the upper support pillar UHR2 are removed. Next, the holes corresponding to the upper support pillars UHR1 and UHR2 are filled with an insulator 41.

[0097] As shown in Figures 30 and 31, the sacrificial films 62 and 64 in the slits corresponding to the component SLT are removed, and an insulator 65 is formed on the side surfaces of the slits. For example, the insulator 65 includes silicon oxide. Next, the insulating layer 33 in the cell region CR is replaced with a semiconductor layer 32b. At this time, in the memory pillar MP, the block insulating film 51, the charge storage film 52, and the tunnel insulating film 53, which are in the same layer as the semiconductor layer 32b, are removed. More specifically, the insulating layer 33b is removed from the side surfaces of the slits corresponding to the component SLT by wet etching. For example, if the insulating layer 33b is silicon nitride, wet etching using hot phosphoric acid is performed. Next, the insulating layers 33a and 33c are removed from the side surfaces of the slits corresponding to the component SLT by wet etching. For example, if the insulating layers 33a and 33c are silicon oxide, wet etching using hydrofluoric acid is performed. As a result, the insulating layers 33 (33a, 33b, and 33c) are removed from the cell region CR where the insulating layer 33b is formed. At this time, the block insulating film 51, the charge storage film 52, and the tunnel insulating film 53, which are located in the same layer as the insulating layer 33, are also removed at the same time. Next, the semiconductor layer 32b is formed to fill the region from which the insulating layer 33 has been removed. Next, the excess semiconductor layer 32b on the side surfaces of the slits corresponding to the member SLT and on the insulating layer 34 is removed, thereby forming the semiconductor layer 32b between the semiconductor layers 32a and 33c.

[0098] As shown in FIGS. 32 and 33, the sacrificial film 60 is replaced with the wiring layer 35. More specifically, first, the insulator 65 in the slit corresponding to the member SLT is removed. Next, the sacrificial film 60 is removed from the side surface of the slit corresponding to the member SLT by wet etching. For example, if the sacrificial film 60 is silicon nitride, wet etching is performed using hot phosphoric acid. Next, the wiring layer 35 is formed.

[0099] 34 and 35, the member SLT is filled with a conductor 36 and an insulator 37. Next, the member SHE is formed.

[0100] As shown in FIGS. 4 and 5, contact plugs CC are formed.

[0101] 1.6 Effects of this embodiment The configuration according to this embodiment can provide a semiconductor memory device 1 that can suppress a decrease in yield. This effect will be described in detail.

[0102] For example, in the manufacturing process of a semiconductor memory device, when the wiring layer 35 functioning as the word line WL and the select gate lines SGD and SGD is formed by replacement, removing the sacrificial film 60 corresponding to the wiring layer 35 may cause voids to cause bending of the insulating layer 34. Support pillars HR are provided to suppress bending of the insulating layer 34. For example, holes corresponding to the support pillars HR are processed together with the memory holes LMH and UMH. To suppress variations in the etching rate of these holes, the diameter and pitch of the support pillars HR are set to be approximately the same as those of the memory pillars MP. That is, the support pillars HR are formed with a relatively narrow pitch. As the number of stacked wiring layers 35 increases, the volume of the insulating layer 34 in the terrace region TR increases. This increases compressive stress due to the insulating layer 34 in the terrace region TR. The increased compressive stress can cause distortion, such as the support pillars HR collapsing toward the cell region CR, or bending (buckling) of the insulating layer 34 when the sacrificial film is removed, resulting in a decrease in manufacturing yield. The distortion of the support pillars HR tends to be stronger toward the ends of the memory cell array 11. If the size of the support pillars HR is increased to suppress distortion of the support pillars HR and bending of the insulating layer 34, simultaneous processing with the memory pillars MP becomes impossible, and the number of steps in HARC (High Aspect Ratio Contact) processing for processing high-aspect-ratio contact holes increases. This increases manufacturing costs. Furthermore, because the terrace regions TR of the select gate lines SGD are divided by the members SHE, if the diameter of the support pillars HR is made too large, it becomes impossible to ensure an area for providing contact plugs CC. Alternatively, the area of ​​the terrace regions TR of the select gate lines SGD increases in order to ensure an area for providing contact plugs CC. In other words, the chip area increases.

[0103] In contrast, in this embodiment, the semiconductor memory device 1 can form multiple support pillars HR of multiple sizes in the terrace region TR. More specifically, support pillars HR with a larger diameter and pitch can be provided in the terrace region TR of the word lines WL and select gate lines SGS than the support pillars HR provided in the terrace region TR of the select gate lines SGD. This makes it possible to suppress distortion of the support pillars HR and bending of the insulating layer 34. Therefore, a decrease in the yield of the semiconductor memory device 1 can be suppressed.

[0104] Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can simultaneously process the support pillars HR in the terrace regions TR of the word lines WL and the select gate lines SGS and process the members SLT. As a result, the support pillars HR are formed in a size larger than the memory pillars MP. Even in this case, an increase in the number of steps in the HARC processing can be suppressed, and therefore an increase in the manufacturing cost of the semiconductor memory device 1 can be suppressed.

[0105] Furthermore, with the configuration according to this embodiment, the diameter and pitch of the lower support pillars LHR1 provided in the terrace regions TR of the select gate lines SGD can be made approximately the same as those of the memory pillars MP in the semiconductor memory device 1. This allows the lower memory pillars LMP and the lower support pillars LHR1 to be processed collectively in the manufacturing process of the semiconductor memory device 1.

[0106] Furthermore, with the configuration according to this embodiment, the diameter and pitch of the upper support pillars UHR1 provided in the terrace region TR of the select gate line SGD in the semiconductor memory device 1 can be made larger than the diameter and pitch of the lower support pillars LHR1 (memory pillars MP). At this time, the lower ends of the upper support pillars UHR1 can be located lower than the top surfaces of the lower support pillars LHR1. This makes it possible to suppress distortion of the support pillars HR and deflection of the insulating layer 34. Furthermore, in the manufacturing process of the semiconductor memory device 1, the upper memory pillars UMP and the upper support pillars UHR1 can be processed collectively. This makes it possible to suppress an increase in the number of steps in HARC processing.

[0107] Furthermore, with the configuration according to this embodiment, the diameter and pitch of the upper support pillars UHR1 in the semiconductor memory device 1 can be approximately twice the diameter and pitch of the lower support pillars LHR1. This allows the area for the contact plugs CC to be secured in the terrace region TR of the select gate line SGD. This prevents an increase in chip area.

[0108] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, the size and layout of the support pillars HR, which are different from those in the first embodiment, will be described. The following description will focus on the differences from the first embodiment.

[0109] 2.1 Planar layout of memory cell array First, an example of a planar layout of the memory cell array 11 will be described with reference to Fig. 36. Fig. 36 is a plan view showing an example of a planar layout of the memory cell array 11.

[0110] As shown in FIG. 36, the planar layout of the cell region CR is the same as that of FIG. 4 of the first embodiment.

[0111] In this embodiment, the lower support pillars LHR1 and the upper support pillars UHR1 are arranged in a staggered pattern in the terrace region TR of the select gate line SGD. The diameter and layout of the upper surface of the lower support pillar LHR1 are the same as those of the upper support pillar UHR1. For example, the diameter Dlhr1 of the lower support pillar LHR1, the diameter Duhr1 of the upper support pillar UHR1, and the diameter Dcc of the contact plug CC are approximately the same. Furthermore, the diameter Dlhr1 of the lower support pillar LHR1, the diameter Duhr1 of the upper support pillar UHR1, and the diameter Dcc of the contact plug CC are larger than the diameter Dmp of the memory pillar MP. The upper support pillar UHR1 is provided on the lower support pillar LHR1.

[0112] The diameters and layout of the lower support pillars LHR2, upper support pillars UHR2, and contact plugs CC in the terrace regions TR of the word lines WL and select gate lines SGS are the same as those in FIG. 4 of the first embodiment.

[0113] 2.2 Cross-sectional structure of memory cell array Next, an example of a cross-sectional configuration of the memory cell array 11 will be described with reference to Fig. 37. Fig. 37 is a cross-sectional view of the memory cell array 11 taken along line XI-XI in Fig. 36. Note that, in the example shown in Fig. 37, for the sake of simplicity, the memory pillars MP, contact plugs CC, and conductors (contact plugs, wiring, bit lines BL, etc.) provided on the members SLT are omitted.

[0114] As shown in FIG. 37, the structures of the member SLT, memory pillar MP, lower support pillar LHR2, upper support pillar UHR2, and contact plug CC are similar to those in FIG. 5 of the first embodiment.

[0115] In the terrace region TR of the select gate line SGD, an etch stop layer ESL is provided below the lower support pillar LHR1. The etch stop layer ESL functions as a stopper when processing the hole corresponding to the lower support pillar LHR1. In this embodiment, the diameter Dlhr1 of the lower support pillar LHR1 is larger than the diameter Dmp of the memory pillar MP. Therefore, when the hole corresponding to the lower support pillar LHR1 and the memory hole LMH are processed simultaneously, the etching rate of the hole corresponding to the lower support pillar LHR1 is faster than the etching rate of the memory hole LMH. However, providing the etch stop layer ESL prevents the hole corresponding to the lower support pillar LHR1 from penetrating the semiconductor layer 32. The etch stop layer ESL is buried by a member 70. The member 70 may be made of a material that provides a sufficient etching selectivity when processing the lower support pillar LHR1. The member 70 may contain, for example, carbon or metal.

[0116] As in the first embodiment, the upper support pillar UHR1 passes through, for example, seven wiring layers 35 and insulating layers 34 that function as word lines WL2 to WL7 and select gate line SGD. The lower end of the upper support pillar UHR1 is located, for example, between the wiring layer 35 that functions as word line WL2 and the wiring layer 35 that functions as word line WL1. Therefore, the lower end of the upper support pillar UHR1 is located below (closer to the semiconductor layer 32) the upper end of the lower support pillar LHR1, with one or more wiring layers 35 sandwiched between them. The upper support pillar UHR1 pierces (passes through) a portion near the upper end of the lower support pillar LHR1 and at least one of the wiring layers 35 in the lower hierarchy.

[0117] 2.3 Memory cell array manufacturing method Next, an example of a manufacturing method of the memory cell array 11 will be described with reference to Figures 38 to 41. Figures 38 and 40 are plan views of the memory cell array 11 showing the manufacturing process of the memory cell array 11. Figures 39 and 41 are cross-sectional views of the memory cell array 11 showing the manufacturing process of the memory cell array 11. The following description will focus on the manufacturing process of the etch stop layer ESL.

[0118] First, as shown in FIGS. 38 and 39 , the semiconductor layer 32c is formed using the same procedure as in the first embodiment, and then a member 70 that functions as an etch stop layer ESL is formed. The diameter of the upper surface of the member 70 only needs to be larger than the diameter of the lower end of the lower support pillar LHR1. In the example shown in FIG. 39 , the member 70 is formed after the semiconductor layer 32c is formed. However, if the member 70 is an insulator, the member 70 may be formed after the insulating layer 34 is formed on the semiconductor layer 32c. Furthermore, the lower end of the member 70 may or may not reach the insulating layer 31.

[0119] Next, as shown in FIGS. 40 and 41, six insulating layers 34 and five sacrificial films 60 are alternately stacked one by one. In this state, memory holes LMH corresponding to the lower memory pillars LMP and joint parts JT, and holes corresponding to the lower support pillars LHR1 are formed. The bottom ends of the holes corresponding to the lower support pillars LHR1 are located within the etch stop layer ESL. In this way, the memory pillars MP and the lower support pillars LHR1, which have a different diameter, can be processed at the same time. The subsequent manufacturing processes are the same as those in the first embodiment.

[0120] 2.4 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0121] Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can have an etch stop layer ESL at the bottom of the lower support pillar LHR1 in the terrace region TR of the select gate line SGD. This allows the depth of the hole corresponding to the lower support pillar LHR1 to be controlled. Therefore, even if the size of the lower support pillar LHR1 is made larger than the size of the memory pillar MP, the memory pillar MP and the lower support pillar LHR1, which have different diameters, can be processed together.

[0122] Furthermore, with the configuration according to this embodiment, the diameter and pitch of the lower support pillars LHR1 and upper support pillars UHR1 provided in the terrace region TR of the select gate line SGD in the semiconductor memory device 1 can be made larger than the diameter and pitch of the memory pillars MP, thereby suppressing distortion of the support pillars HR and bending of the insulating layer 34.

[0123] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, the size and layout of the support pillars HR, which are different from those of the first and second embodiments, will be described. The following description will focus on the differences from the first and second embodiments.

[0124] 3.1 Planar layout of memory cell array First, an example of a planar layout of the memory cell array 11 will be described with reference to Fig. 42. Fig. 42 is a plan view showing an example of a planar layout of the memory cell array 11.

[0125] As shown in FIG. 42, the planar layout of the cell region CR is the same as that of the first embodiment shown in FIG.

[0126] In this embodiment, a lower support pillar LHR1, an upper support pillar UHR1, and a contact plug CC, each having the same size as the diameter Dmp of the memory pillar MP, are provided in the terrace region TR of the select gate line SGD. Hereinafter, when limiting the contact plug CC provided in the terrace region TR of the select gate line SGD, it will be referred to as a "contact plug CC1."

[0127] The diameter Dmp of the memory pillar MP, the diameter Dlhr1 of the lower support pillar LHR1, the diameter Duhr1 of the upper support pillar UHR1, and the diameter Dcc1 of the contact plug CC1 are all approximately the same. Furthermore, the planar layout of the memory pillar MP is approximately the same as the planar layouts of the lower support pillar LHR1 and the upper support pillar UHR1. Therefore, the pitch P1 of the memory pillar MP, the pitch P2 of the lower support pillar LHR, and the pitch P3 of the upper support pillar UHR1 are all approximately the same. The upper support pillar UHR1 and contact plug CC1 are formed on the lower support pillar LHR1.

[0128] In this embodiment, the diameter Dcc2 of the contact plug CC (hereinafter referred to as "contact plug CC2") in the terrace region TR of the word line WL and the select gate line SGS is larger than the diameter Dcc1 of the contact plug CC1 in the terrace region TR of the select gate line SGD and is smaller than the diameter Dhr2 of the lower support pillar LHR2 and the upper support pillar UHR2. The planar layout of the terrace region TR of the word line WL and the select gate line SGS is the same as that of FIG. 4 of the first embodiment.

[0129] In this embodiment, the support pillars HR (LHR1 and UHR1) provided in the terrace regions TR of the select gate lines SGD may have the same structure as the memory pillars MP. That is, the support pillars HR provided in the terrace regions TR of the select gate lines SGD may have a structure embedded with a block insulating film 51, a charge storage film 52, a tunnel insulating film 53, a semiconductor film 54, and a core film 55.

[0130] 3.2 Cross-sectional structure of memory cell array Next, an example of a cross-sectional configuration of the memory cell array 11 will be described with reference to Fig. 43. Fig. 43 is a cross-sectional view of the memory cell array 11 taken along line XI-XI in Fig. 42. Note that, in the example shown in Fig. 43, for the sake of simplicity, the memory pillar MP, contact plugs CC1 and CC2, and conductors (contact plugs, wiring, bit lines BL, etc.) provided on the member SLT are omitted.

[0131] As shown in FIG. 43, the structures of the member SLT, memory pillar MP, lower support pillar LHR2, upper support pillar UHR2, and contact plug CC2 are similar to those in FIG. 5 of the first embodiment.

[0132] In the terrace region TR of the select gate line SGD, the diameter Duhr1 of the upper support pillar UHR1 in this embodiment is approximately the same as the diameter Dmp of the memory pillar MP. Therefore, the etching rate of the memory hole UMH corresponding to the upper memory pillar UMP is approximately the same as the etching rate of the hole corresponding to the upper support pillar UHR1. Therefore, when the lower surface of the upper support pillar UHR1 is provided on the upper surface of the lower support pillar LHR1, the upper support pillar UHR1 hardly penetrates through the upper end of the lower support pillar LHR1. In other words, unless a misalignment occurs between the upper support pillar UHR1 and the lower support pillar LHR1 during the manufacturing process of the semiconductor memory device 1, causing the lower surface of the upper support pillar UHR1 to miss the upper surface of the lower support pillar LHR1, the upper support pillar UHR1 hardly penetrates through the upper end of the lower support pillar LHR1. However, if the lower surface of the upper support pillar UHR1 misses the upper surface of the lower support pillar LHR1, i.e., if there is a misalignment between the upper support pillar UHR1 and the lower support pillar LHR1, the upper support pillar UHR1 may pass through the upper end of the lower support pillar LHR1.

[0133] 3.3 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0134] Furthermore, with the configuration according to this embodiment, the semiconductor memory device 1 can make the diameters and pitches of the lower support pillars LHR1 and upper support pillars UHR1 and contact plugs CC1 in the terrace region TR of the select gate line SGD the same as the diameters and pitches of the memory pillars MP.

[0135] 4. Modifications, etc. The semiconductor memory device according to the above embodiment includes a first semiconductor layer (32) provided above a substrate (30), a plurality of first wiring layers (35, WL0 to WL3) stacked above the first semiconductor layer and spaced apart from each other in a first direction (Z direction), a plurality of second wiring layers (35, WL4 to WL7) stacked above the plurality of first wiring layers and spaced apart from each other in the first direction, a third wiring layer (35, SGD) provided above the plurality of second wiring layers, a third memory pillar (MP) including a first memory pillar (LMP) passing through the plurality of first wiring layers in the first direction and a second memory pillar (UMP) provided on the first memory pillar and passing through the plurality of second wiring layers and the third wiring layer in the first direction, and a first wiring layer (35, SGD) provided above the third wiring layer. The semiconductor device includes a first region (TR) in which a contact plug (CC) is provided, a second region (TR) in which the second contact plug (CC) is provided on each of a plurality of second wiring layers, a first support pillar (LHR1) that passes through the plurality of first wiring layers in the first region, a second support pillar (UHR1) that passes through at least a plurality of second wiring layers and a third wiring layer in the first region, a third support pillar (LHR2) that passes through at least one of the plurality of first wiring layers in the second region and has a larger diameter than the first support pillar and the second support pillar, and a fourth support pillar (UHR2) that is provided on the third support pillar in the second region and has a larger diameter than the first support pillar and the second support pillar.

[0136] The configuration according to the above embodiment can provide a semiconductor device that can improve yield.

[0137] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0138] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0139] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0140] 1...semiconductor memory device, 10...memory core section, 11...memory cell array, 12...row decoder, 13...sense amplifier, 20...peripheral circuit section, 21...sequencer, 22...voltage generation circuit, 30...semiconductor substrate, 31, 33, 33a, 33b, 34...insulating layer, 32, 32a to 32c...semiconductor layer, 35...wiring layer, 36, 42...conductor, 37, 38, 40, 41, 65...insulator, 51...block insulating film, 52...charge storage film, 53...tunnel insulating film, 54...semiconductor film, 55...core film, 60 to 64...sacrificial film, 70... Member, BL, BL0 to BLm... bit lines, BLK, BLK0 to BLK3... blocks, CC, CC1, CC2... contact plugs, LHR1... lower support pillar, LHR2... lower support pillar, MC, MC0 to MC7... memory cell transistors, SGD, SGD0 to SGD5... select gate lines, ST1, ST2... select transistors, SU, SU0 to SU5... string units, TR1, TR2... terrace regions, UHR1... upper support pillar, UHR2... upper support pillar, WL, WL0 to WL7... word lines

Claims

1. a first semiconductor layer provided above a substrate; a plurality of first wiring layers stacked above the first semiconductor layer and spaced apart from each other in a first direction; a plurality of second wiring layers stacked above the plurality of first wiring layers and spaced apart from each other in the first direction; a third wiring layer provided above the plurality of second wiring layers; a third memory pillar including a first memory pillar passing through the plurality of first wiring layers in the first direction and a second memory pillar provided on the first memory pillar and passing through the plurality of second wiring layers and the third wiring layer in the first direction; a first region in which a first contact plug is provided on the third wiring layer; a second region in which second contact plugs are provided on each of the plurality of second wiring layers; a first support pillar passing through the plurality of first wiring layers in the first region; a second support pillar passing through at least the plurality of second wiring layers and the third wiring layer in the first region; a third support pillar that passes through at least one of the plurality of first wiring layers in the second region and has a diameter larger than the first support pillar and the second support pillar; a fourth support pillar disposed on the third support pillar in the second region and having a diameter larger than the first support pillar and the second support pillar; A semiconductor memory device comprising:

2. The diameter and pitch of the first support pillars are the same as the diameter and pitch of the third memory pillars.

2. The semiconductor memory device according to claim 1.

3. the diameter and pitch of the second support pillars are greater than the diameter and pitch of the first support pillars; 3. The semiconductor memory device according to claim 2.

4. The diameter and pitch of the second support pillars are the same as the diameter and pitch of the first support pillars.

3. The semiconductor memory device according to claim 2.

5. the pitch of the second support pillars is twice the pitch of the first support pillars; 4. The semiconductor memory device according to claim 3.

6. the second support pillar passes through at least one of the plurality of first wiring layers and contacts the first support pillar; 2. The semiconductor memory device according to claim 1.

7. a central axis of the second support pillar is disposed at a position different from a central axis of the first support pillar in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction; 7. The semiconductor memory device according to claim 6.

8. one ends of the first memory pillar and the first support pillar reach into the first semiconductor layer; 2. The semiconductor memory device according to claim 1.

9. further comprising an etch stop layer provided in the same layer as the first semiconductor layer; the first support pillar is disposed on the etch stop layer; the second support pillar is disposed on the first support pillar; a diameter and pitch of the first support pillars and a diameter and pitch of the second support pillars are larger than a diameter and pitch of the third memory pillars; 2. The semiconductor memory device according to claim 1.

10. a diameter of the upper surface of the etch stop layer is greater than a diameter of the lower surface of the first support pillar; 10. The semiconductor memory device according to claim 9.

11. the second support pillar passes through at least one of the plurality of first wiring layers and contacts the first support pillar; 2. The semiconductor memory device according to claim 1.

12. The diameter of the first contact plug is smaller than the diameter of the second contact plug.

2. The semiconductor memory device according to claim 1.

13. a diameter of the first contact plug is equal to or greater than a diameter of the third memory pillar; 12. The semiconductor memory device according to claim 11.

14. the third memory pillar extends in the first direction and includes a second semiconductor film connected to the first semiconductor layer and a charge storage film; 2. The semiconductor memory device according to claim 1.

15. the first support pillar and the third support pillar are electrically disconnected from the first semiconductor layer and the plurality of first wiring layers; the second support pillar and the fourth support pillar are electrically disconnected from the plurality of second wiring layers and the third wiring layer; 2. The semiconductor memory device according to claim 1.

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