Three-dimensional nor memory string array of thin-film ferroelectric transistor

Abstract

To solve such a problem that ferroelectric field effect transistors of the prior art have low endurance.SOLUTION: A memory structure 10 includes storage transistors 20 organized as horizontal NOR memory strings, and the storage transistors are thin-film ferroelectric field-effect transistors having a ferroelectric gate dielectric layer 26 formed adjacent a semiconductor channel region 25. The semiconductor channel region is formed by an oxide semiconductor material, and the ferroelectric storage transistors are junctionless transistors with no p / n junction in a channel. The ferroelectric storage transistors 20 in each NOR memory string share a first conductive layer 16a as a common source line and a second conductive layer 18 as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to high density memory structures. In particular, the present invention relates to high density, low read latency memory structures formed by interconnected thin film memory elements (e.g., three-dimensional arrays of thin film storage transistors), including those configured as NOR type memory strings ("NOR memory strings"). [Background technology]

[0002] A NOR memory string includes storage transistors that share a common source region and a common drain region, and each storage transistor can be individually addressed and accessed. U.S. Pat. No. 10,121,553, entitled "Capacitively Coupled Nonvolatile Thin-Film Transistor NOR String in a Three-Dimensional Array," issued on November 6, 2018, discloses storage or memory transistors configured as a three-dimensional array of NOR memory strings formed above a plane of a semiconductor substrate. U.S. Pat. No. 10,121,553 is incorporated herein by reference in its entirety for all purposes. In U.S. Pat. No. 10,121,553, the NOR memory string includes multiple thin-film storage transistors that share a common bit line and a common source line. In particular, U.S. Pat. No. 10,121,553 discloses a NOR memory string that includes (i) common source and drain regions extending longitudinally along a horizontal direction and (ii) a gate electrode of each storage transistor extending along a vertical direction. In U.S. Pat. No. 10,121,553, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to a direction parallel to the surface of the semiconductor substrate. In a three-dimensional array, NOR memory strings are arranged in multiple planes (e.g., 8 or 16 planes) on a semiconductor substrate, with the NOR memory strings on each plane arranged in a column. For charge-trapping storage transistors, data is stored in a charge storage layer within each storage transistor. For example, the charge storage layer may be implemented as a multilayer structure consisting of silicon oxide, silicon nitride, and silicon oxide, in that order, and includes a tunnel dielectric layer, a charge trapping layer, and a blocking layer, referred to as an ONO layer. An electric field applied across the charge storage layer adds or removes charge from the charge traps in the charge trapping layer, shifting the threshold voltage of the storage transistor and encoding a given logic state into the storage transistor.

[0003] Advances in electrically polarizable materials ("ferroelectric materials"), especially those used in semiconductor manufacturing processes, suggest new possibilities for ferroelectric memory circuits. For example, "Ferroelectricity in Hafnium Oxide: CMOS Compatible Ferroelectric Field Effect Transistors," by T.S. Boscke et al., published in the 2011 International Electron Devices Meeting (IEDM), pp. 24.5.1-24.5.4, discloses a ferroelectric field-effect transistor (FeFET) using hafnium oxide as the gate dielectric material. By controlling the polarization direction of the ferroelectric gate dielectric layer, the FeFET can be programmed to have one of two threshold voltages. Each threshold voltage of the FeFET constitutes a state representing a specified logic value, such as a "programmed" state or an "erased" state. Such FeFETs can be applied to high-density memory circuits. For example, U.S. Patent Application No. 13 / 897,037 (U.S. Patent No. 9,281,044), entitled "Apparatus Having Ferroelectric Field Effect Transistor Memory Array and Related Methods," filed May 17, 2013, discloses a three-dimensional array of FeFETs.

[0004] However, conventional FeFETs have a problem of low durability. For example, in the paper "Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory," by K. Florent et al., published in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 2.5.1-2.5.4, it is stated that the durability is 10 4 Such low endurance makes the memory circuit substantially unsuitable for many memory applications. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 10,121,553 [Patent Document 2] U.S. Patent No. 9,281,044 Summary of the Invention [Means for solving the problem]

[0006] According to the present disclosure, there is provided a three-dimensional memory structure formed on a plane of a semiconductor substrate, the memory structure including a plurality of stacks of thin-film ferroelectric field effect transistors (FeFETs) arranged as a plurality of stacks of NOR memory strings extending along a first direction substantially parallel to the plane of the semiconductor substrate, the stacks of NOR memory strings being stacked along a second direction substantially perpendicular to the plane, and the thin-film ferroelectric field effect transistors (FeFETs) of each NOR memory string sharing a common source layer and a common drain layer extending along the first direction.

[0007] In some embodiments, each stack of NOR memory strings includes multiple memory string pairs stacked along the second direction, each memory string pair insulated from other memory string pairs by a first insulating layer. Each memory string pair includes a first common drain layer, a first common source layer, and a second common drain layer, each layer spaced apart from each other in the second direction by a second insulating layer. Each memory string pair includes a first NOR memory string formed by the first common drain layer and the first common source layer, and a second NOR memory string formed by the second common drain layer and the first common source layer.

[0008] The memory structure of the present disclosure further includes a semiconductor layer adjacent to each stack of the NOR memory string and in contact with the common source layer and common drain layer of each stack. The semiconductor layer between adjacent common source layers and common drain layers in the second direction forms a channel region for a thin-film ferroelectric field effect transistor (FeFET) of each NOR memory string. The memory structure of the present disclosure also includes a ferroelectric gate dielectric layer adjacent to the semiconductor layer and along the second direction. The memory structure of the present disclosure also includes a plurality of conductors adjacent to the ferroelectric gate dielectric layer between adjacent stacks of the NOR memory string and along the second direction. Each conductor functions as a common gate electrode for each thin-film ferroelectric field effect transistor (FeFET) of the NOR memory strings in adjacent stacks. In some embodiments, the memory structure of the present disclosure further includes an interface layer between the ferroelectric gate dielectric layer that forms a channel and the semiconductor layer.

[0009] In some embodiments, the ferroelectric gate dielectric layer includes a ferroelectric polarization layer provided as a continuous layer adjacent each conductor in the second direction.

[0010] In yet another embodiment, it is provided as a continuous layer along the sidewall of each stack of a NOR memory string.

[0011] In some embodiments, the ferroelectric gate dielectric layer is formed from a doped hafnium oxide material and the semiconductor layer forming the channel region is an oxide semiconductor layer formed from an amorphous oxide semiconductor material.

[0012] In some embodiments, the first common drain layer, the second common drain layer, and the first common source layer are formed partially or substantially from a metallic conductor material.

[0013] These and other advantages, aspects and novel features of the present invention, as well as details of illustrated embodiments thereof, will be more fully understood by reference to the following description and accompanying drawings. [Brief explanation of the drawings]

[0014] Various embodiments of the present invention are disclosed in the following detailed description and the accompanying drawings, which depict various embodiments of the present invention, but which are not intended to be limiting. It should be understood that like reference numerals indicate like structural elements in the drawings, and that the depictions in the figures are not necessarily drawn to scale.

[0015] [Figure 1] FIG. 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. [Figure 2] FIG. 2 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in accordance with another embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view of a portion of the memory structure of FIG. 1 including a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. [Figure 4] FIG. 4 is a circuit representation of a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. [Figure 5] FIG. 5 illustrates an erase operation that can be performed on a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. [Figure 6] FIG. 6 illustrates a program operation that can be performed on a three-dimensional array of NOR memory strings following the erase operation of FIG. 5 in accordance with an embodiment of the present invention. [Figure 7] FIG. 7 illustrates a read operation that can be performed on a three-dimensional array of NOR memory strings following the write operations of FIGS. 5 and 6 in accordance with an embodiment of the present invention. [Figure 8] FIG. 8 illustrates a bit line selector that can be implemented in a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. [Figure 9A] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9B] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9C] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9D] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9E] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9F] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9G] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9H] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9I] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9J]9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9K] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9L] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9M] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 9N] 9A-9N illustrate a fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. [Figure 10A] 10A and 10B illustrate another fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors, according to an embodiment of the present invention. [Figure 10B] 10A and 10B illustrate another fabrication process for a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors, according to an embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings isolated by air gap cavities in accordance with an embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings in which ferroelectric transistors are isolated by air gap cavities in another embodiment of the present invention. [Figure 13]FIG. 13 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings in which ferroelectric transistors are isolated by air gap cavities in another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] According to embodiments of the present invention, the disclosed memory structure includes storage transistors configured as a horizontal NOR memory string, the storage transistors being thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent to an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors, lacking a p / n junction in the channel, in which the mobile carrier density in the channel is modulated by the polarization of the ferroelectric gate dielectric layer. In embodiments of the present invention, the ferroelectric storage transistors in each NOR memory string share a first conductive layer that functions as a common source line and a second conductive layer that functions as a common bit line, the first conductive layer and the second conductive layer being electrically connected to the oxide semiconductor channel region. The ferroelectric storage transistors in the NOR memory string are controlled by individual control gate electrodes, allowing each storage transistor to be individually addressed and accessed. In some embodiments, the ferroelectric gate dielectric layer is formed from a doped hafnium oxide material, and the oxide semiconductor channel region is formed from an amorphous oxide semiconductor material.

[0017] In some embodiments, the memory structure of the present disclosure includes a plurality of NOR memory strings arranged in a three-dimensional array to form a high-density memory structure. The three-dimensional array of NOR memory strings is arranged as a stack of NOR memory strings in a first direction, where the NOR memory strings are formed on top of each other within the stack in the first direction. The three-dimensional array of NOR memory strings is also arranged as a column of NOR memory strings in a second direction forming a plane, where the columns of NOR memory strings are arranged in one or more parallel planes in the first direction. In some embodiments, adjacent pairs of NOR memory strings in the stack share a common source line. The voltage on each shared common source line can be applied directly from one or both ends of each source line separately in the three-dimensional structure. In some embodiments, the shared common source line is electrically floating, and the source voltage is applied from the common bit line using a precharge transistor to reduce congestion of connector lines at the end steps of the bit line / source line in the three-dimensional structure. Furthermore, in some embodiments, an oxide semiconductor channel region is formed as a continuous layer across the plurality of NOR memory strings formed in the stack in at least the first direction. In this manner, NOR memory strings can be constructed using simplified manufacturing process steps with reduced aspect ratios for anisotropic etching of trenches through multiple layers of the memory string, resulting in compact dimensional and high density memory structures.

[0018] The ferroelectric storage transistors described herein provide high endurance, long data retention, and relatively low voltage operation during both erase (below 5.0 volts) and programming (e.g., below -5.0 volts) operations. By combining ferroelectric or polarization properties with three-dimensional structures (e.g., as thin-film NOR memory strings described herein), the ferroelectric storage transistor memory structures of the present invention can achieve the low read latency advantages of high-speed random access memory circuits and the additional advantages of high-density, low-cost memory arrays. These and other advantages of the memory structures of the present invention are further described below.

[0019] In this description, for ease of reference to the drawings, a Cartesian coordinate reference system is used in which the Z direction is orthogonal to the plane of the semiconductor surface, and the X and Y directions are orthogonal to the Z direction, as shown in the figures.

[0020] Additionally, the drawings provided herein are idealized depictions for purposes of illustrating embodiments of the present disclosure and are not intended to be actual depictions of particular components, structures, or devices. The drawings are not drawn to scale, and thicknesses and dimensions of some layers may be exaggerated for clarity. Variations from the shapes shown are expected. For example, regions shown as box-shaped may generally have rough and / or non-linear features. Sharp angles shown may be rounded. Like reference characters refer to like components throughout.

[0021] Memory Structures

[0022] FIG. 1 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings according to an embodiment of the present invention. The memory structure of the present disclosure can be used to implement a portion of a semiconductor memory device, in some examples. Referring to FIG. 1 , the memory structure 10 includes multiple alternating conductive and insulating layers formed on a planar surface of a semiconductor substrate 12. For example, in some embodiments, the insulating layer can be an insulating dielectric layer. The combination of a pair of conductive layers and the insulating layer sandwiched therebetween is referred to herein as an active layer 11. A buffer layer 14 may be provided between the semiconductor substrate 12 and the active layer 11 formed on the semiconductor substrate 12. In some implementations, the buffer layer 14 can be a silicon oxide carbide (SiOC) layer or a silicon oxide (SiO2) layer. The active layer 11, including the alternating conductive and insulating layers, is stacked in the Z direction (i.e., along a direction perpendicular to the plane of the semiconductor substrate 12). The active layer 11 is divided in the X direction into narrow strips ("active strips") 24, which are stacked to form a stack of active strips ("active stack") extending in the Y direction. Each active strip 24 thus formed forms a NOR memory string of ferroelectric storage transistors 20 extending in the Y direction.

[0023] Each active layer 11 includes a first conductive layer 16 that functions as a common bit line for the NOR memory string and a second conductive layer 18 that functions as a common source line for the NOR memory string. The first conductive layer 16 and the second conductive layer 18 are separated by an insulating layer 17, which in some embodiments may be a dielectric layer. For example, in some embodiments, the insulating layer 17 may be a silicon oxide layer. In the memory structure shown in FIG. 1, eight active layers 11 (11-0 through 11-7) are provided. A notable feature of the memory structure 10 of the present disclosure is that in a memory structure having N active layers, adjacent pairs of active layers 11 share a common source line 18. As a result, a memory structure having N active layers includes N common bit lines but only N / 2 common source lines. For example, a pair of adjacent active layers 11-0 and 11-1 includes (i) a first conductive layer 16a forming a common bit line of the first NOR memory string, (ii) an insulating layer 17a, (iii) a second conductive layer 18 forming a common source line of the first NOR memory string and the second NOR memory string, (iv) an insulating layer 17b, and (v) a first conductive layer 16b forming a common bit line of the second NOR memory string. With this configuration, in the memory structure 10 of the present disclosure, the pair of adjacent active layers forms a pair of NOR memory strings that share the common source line 18. The pair of adjacent active layers is separated from other pairs of active layers by an insulating layer 15, such as an insulating dielectric layer.

[0024] Subsequent processing steps form an oxide semiconductor channel region 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28 in the narrow trenches 22 between the isolated active stacks. Another distinctive feature of the memory structure 10 of the present disclosure is that each oxide semiconductor channel region 25 is formed as a continuous layer along the sidewalls of an active stack, sandwiching the NOR memory strings of the active stack in the X-direction. In some implementations, each oxide semiconductor channel region 25 is a continuous layer along the sidewalls of a pair of adjacent active stacks that share a narrow trench 22. The oxide semiconductor channel region 25 is isolated from other oxide semiconductor channel regions 25 formed in other narrow trenches 22.

[0025] In an embodiment of the present invention, the gate electrode 28 and the ferroelectric gate dielectric layer 26 are formed as pillar-shaped structures extending in the Z direction. In this example, the ferroelectric gate dielectric layer 26 surrounds the gate electrode 28 to form the pillar-shaped structures. In this specification, the gate electrode 28 is also referred to as a "local word line," and the combination of the gate electrode 28 and the surrounding ferroelectric gate dielectric layer 26 is collectively referred to as a "local word line (LWL) structure." The local word line structures (LWL structures) formed in each trench 22 are insulated from each other by a dielectric material 23. Ferroelectric storage transistors 20 are formed at intersections of the active strips 24, the oxide semiconductor channel regions 25, and the LWL structures. Thus, ferroelectric storage transistors 20 are formed on both sides of the active strips 24. In the memory structure shown in FIG. 1, the LWL structures are staggered in adjacent trenches 22 such that the ferroelectric storage transistors 20 formed on both sides of the active strips are offset from each other in the Y direction along the NOR memory string. In particular, the insulating layer 15 between a pair of NOR memory strings (active strips 24) and the insulating layers 17a and 17b between adjacent common source lines 18 and common bit lines 16 provide insulation to separate the ferroelectric storage transistors 20 formed on both sides of the same active strip 24. With this configuration, the ferroelectric storage transistors 20 sharing the common source line 18 and common bit line 16 form a NOR memory string (also referred to as a "horizontal NOR memory string" or "HNOR memory string") along each active strip 24 (in the Y direction).

[0026] In the three-dimensional array of NOR memory strings thus formed, the ferroelectric storage transistors 20 are junctionless transistors that do not include p / n junctions as drain or source regions in their channels. Instead, the first conductive layer 16 (common bit line) functions as the drain region of the ferroelectric storage transistors 20, and the second conductive layer 18 functions as the source region of the ferroelectric storage transistors 20. Thus, the NOR memory string includes ferroelectric storage transistors 20 that share a common drain region (common bit line 16) and a common source region (common source line 18).

[0027] In some implementations, first conductive layer 16 and second conductive layer 18 are each formed using a metal layer or low-resistivity metal conductive material, such as molybdenum (Mo), tungsten (W), tungsten nitride (WN), ruthenium, or titanium-tungsten alloy (TiW). In some implementations, insulating layer 15 and insulating layer 17 can be formed as silicon oxide (SiO2). In other embodiments, insulating layer 15 can be formed of other insulating dielectric materials, such as silicon nitride. In some implementations, the ferroelectric gate dielectric layer can be formed from a doped hafnium oxide material, such as zirconium-doped hafnium oxide (HfZrO or "HZO"). In some implementations, the hafnium oxide can be doped with silicon (Si), iridium (Ir), or lanthanum (La). In some implementations, the oxide semiconductor channel region is formed from an amorphous oxide semiconductor material, such as indium gallium zinc oxide (IGZO).

[0028] To complete the memory circuit, various types of circuitry are formed within or on the semiconductor substrate 12 to support memory operations of the HNOR memory string. Such circuitry is referred to as "under-array circuitry" ("CuA") and may include analog and digital circuitry. For example, memory operations may include read and write operations. As used herein, write operations to a memory circuit include erase and program operations and refer to changing the polarization state or polarization direction of the ferroelectric gate dielectric layer 26 from one polarization state to another. Additionally, in some embodiments, memory operations include refresh operations. In some embodiments, the under-array circuitry supports memory operations of the memory circuit, such as erase, program, read, and refresh operations.

[0029] In some embodiments, the array-under-circuitry includes various voltage sources or voltage generators for generating operating voltages such as power supply voltages, ground voltages, programming voltages, erase voltages, read voltages, or reference voltages. The array-under-circuitry may further include word line driver circuits, bit line driver circuits, and input / output driver circuits. The array-under-circuitry may further include address decoders for decoding address signals to select specified storage transistors, sense amplifiers for reading stored data from selected storage transistors, latches and registers such as shift registers, or other memory elements. The array-under-circuitry may further include various logic circuits such as inverters, NAND, NOR, exclusive-OR, and other logic gates. In some embodiments, the array-under-circuitry includes state machines, microsequencers, and data processing circuits. For example, in one embodiment, the array-under-circuitry includes a state machine for managing memory operations (e.g., read operations, erase operations, program operations, and refresh operations) in the memory circuit.

[0030] In some embodiments, other conductive layers may be disposed above or below the memory structure 10 to provide control signals, such as word line signals, to the array of ferroelectric storage transistors 20. In some embodiments, conductive layers may be disposed to connect under-array circuitry to common bit lines of the NOR memory strings and local word lines supporting memory operations. In one embodiment, conductive layers may be provided to route control and data signals between the NOR memory strings and under-array circuitry. In this configuration, the under-array circuitry supports memory operations for the NOR memory strings and autonomously performs erase, program, and read operations for the NOR memory strings in response to erase, program, and read commands provided to the memory structure 10. In one example, a write operation to the ferroelectric storage transistors 20 includes an erase operation followed by a program operation.

[0031] In some embodiments, memory structure 10 is connected to a memory controller, which is a separate semiconductor substrate, and electrically connected using one or more integration techniques, such as hybrid bonding, TSVs, exposed contacts, and other suitable interconnect techniques. The memory controller provides commands such as erase, program, and read to the under-array circuitry, typically along with accompanying information such as memory cell addresses and write data for write operations. Memory structure 10 uses the under-array circuitry to autonomously perform memory operations in response to received commands.

[0032] In an embodiment of the present disclosure, the memory structure 10 represents modular memory units referred to as "tiles," and the memory device is formed using an array of modular memory units. In an exemplary embodiment, the memory device is configured as a two-dimensional array of tiles, each including a three-dimensional array of ferroelectric storage transistors with support circuitry for each tile formed thereunder. More specifically, the support circuitry for the ferroelectric storage transistors of each tile is provided for modularization in a portion of a semiconductor substrate below each tile. In this manner, each modular memory unit (or tile) operates semi-autonomously to perform memory operations such as erase, program, read, and refresh operations. As a result, the memory device includes an array of tiles, each of which can be individually addressed and controlled by under-array circuitry (CuA) formed below each tile. In particular, the tile-based CuA provided in each tile allows each tile in the tile array to simultaneously perform memory operations on multiple tiles and to be accessed independently of one another. In some embodiments, tile-based under-array circuitry (CuA) is formed in a semiconductor substrate using a first fabrication process, and then the semiconductor substrate with the tile-based support circuitry formed thereon is subjected to a second fabrication process to form thin-film storage transistors.

[0033] Memory devices are connected to a memory controller to form a memory module. The memory controller may be a controller integrated circuit, also referred to as a "chiplet." Alternatively, the memory controller may be integrated into or implemented in a general-purpose integrated circuit (e.g., a central processing unit (CPU) or a graphics processing unit (GPU)). The memory controller implements management functions for the memory device. In some embodiments, the memory controller provides commands, such as power up, read, erase, program, commit, and refresh, and associated command information, such as memory addresses and write data, to the memory device. The memory controller may also provide host interface functionality, where applicable, implementing a memory interface for host access and other system functions. The memory controller operates in cooperation with the under-array circuitry of each tile, enabling semi-autonomous memory operations in each tile and simultaneous memory operations for multiple tiles. The memory device formed by the tile array provides high-speed, high-capacity memory with parallel access to storage transistors in multiple tiles.

[0034] In the embodiment shown in FIG. 1, the memory structure 10 includes an oxide semiconductor channel region 25 formed as a continuous layer in the Y direction along the sidewalls of the active stacks of the NOR memory strings (active strips 24). In other embodiments, the oxide semiconductor channel region 25 may be isolated from each other between adjacent local word line (LWL) structures, as shown in FIG. 2. FIG. 2 is a perspective view of a memory structure including a three-dimensional array of NOR memory strings in another embodiment of the present invention. Similar elements in FIGS. 1 and 2 are labeled with similar reference numerals for ease of explanation. Referring to FIG. 2, the memory structure 30 is configured substantially similarly to the memory structure 10 of FIG. 1, except for the formation of the oxide semiconductor channel region 25. In the memory structure 30, the oxide semiconductor channel region 25 formed in the narrow trench 22 is isolated or unified in each LWL structure, as indicated by the dotted circle 32. That is, the oxide semiconductor channel region 25 is provided adjacent only to a columnar structure consisting of a ferroelectric gate dielectric layer 26 and a gate electrode 28. The oxide semiconductor channel region 25 is removed between adjacent LWL structures, thereby eliminating parasitic devices that may form in the regions between the LWL structures.

[0035] FIG. 3 is a cross-sectional view of a portion of the memory structure of FIG. 1 including a three-dimensional array of NOR memory strings in an embodiment of the present invention. Similar elements in FIGS. 1 and 3 are labeled with similar reference numerals for simplicity. Referring to FIG. 3, the memory structure 10 includes a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed on a semiconductor substrate (omitted in FIG. 3 for simplicity). In this embodiment, the active stacks of a pair of NOR memory strings (active strips 24) adjacent to the same narrow trench 22 share a common oxide semiconductor channel region 25, ferroelectric gate dielectric layer 26, and gate electrode 28 in each local word line (LWL) structure. That is, the oxide semiconductor channel region 25 is continuous along the bottom of the narrow trench 22. In adjacent narrow trenches 22, the oxide semiconductor channel region 25 formed in one narrow trench 22 is insulated from the oxide semiconductor channel region 25 formed in the other narrow trench 22. Each active stack 24 has ferroelectric storage transistors 20 formed on both sides of the active stack 24. When the LWL structures are staggered in the Y direction, the ferroelectric storage transistors 20 are formed in adjacent narrow trenches 22 offset from one another in the Y direction so as not to face one another in the X direction. Dielectric material 23 is formed in the trenches 22 between the LWL structures.

[0036] The oxide semiconductor channel region provides many advantages in the three-dimensional array of NOR memory strings of the present invention. First, oxide semiconductor channel regions generally have high mobility, high switching performance, and are free from electron or hole tunneling concerns. Second, the storage transistors of NOR memory strings with oxide semiconductor channel regions are junctionless transistors, thereby eliminating the need for polysilicon source-drain layers in the memory structure. As a result, the stack height of the three-dimensional array of NOR memory strings is significantly reduced compared to conventional memory arrays with the same number of planes or layers of NOR memory strings. Furthermore, in embodiments of the present invention, the stack height of the NOR memory strings is further reduced by sharing a common source line between adjacent active layers. This results in a high-density, compact memory structure.

[0037] In memory structure 10, each pair of active layers (in the Z direction) includes a first common bit line (first conductive layer 16a) and a common source line (second conductive layer 18) separated from each other by insulating layer 17a, and a second common bit line (first conductive layer 16b) separated from the common source line 18 by insulating layer 17b, thereby forming a first NOR memory string and a second NOR memory string. Each pair of first and second NOR memory strings is separated from other pairs in the Z direction by insulating layer 15.

[0038] In this embodiment, the insulating layer 15 has a thickness d1 in the Z direction, and the insulating layers 17a and 17b have a thickness d2 in the Z direction. The thickness d1 is selected to sufficiently insulate adjacent common bit lines of the active stack. The thickness d2 between the common bit line and the common source line defines the channel length of the ferroelectric storage transistor 20. In this embodiment, the first conductive layer 16 and the second conductive layer 18 have the same thickness d3 in the Z direction. In other embodiments, the first conductive layer 16 and the second conductive layer 18 have different thicknesses in the Z direction. Furthermore, in this embodiment, the oxide semiconductor channel region 25 has a thickness d4 in the X direction between the ferroelectric gate dielectric layer 26 and the source line / bit line of the active stack 24, and the thickness d4 defines the depth of the channel region.

[0039] In some embodiments, thickness d1 is in the range of 30 to 50 nm, and in one example, has a value of 30 nm. In some embodiments, thickness d2 is in the range of 30 to 80 nm, and in one example, has a value of 50 nm. In some embodiments, thickness d3 is in the range of 30 to 40 nm, and in one example, has a value of 40 nm. In one embodiment, the stack height of a pair of adjacent NOR memory strings is 250 nm. A memory structure including a stack of eight NOR memory strings can be formed with a stack height of only 1000 nm, a significant reduction in stack height compared to conventional memory structures formed using, for example, polysilicon channels. The reduced stack height has the effect of reducing the aspect ratio of the etching process used to form narrow trenches between active stacks during the manufacturing process, as described in more detail below.

[0040] In some embodiments, the oxide semiconductor channel region 25 has a thickness d4 of 8 to 15 nm in the X direction. In one example, the oxide semiconductor channel region 25 has a thickness of 10 nm. In some embodiments, the ferroelectric gate dielectric layer 26 has a thickness of 3 to 7 nm in the X direction. In one example, the ferroelectric gate dielectric layer 26 has a thickness of 4 nm. In some embodiments, the active stack 24 has a width of 60 nm in the X direction, and the narrow trench in which the LWL structure is formed has a width of 70 nm in the X direction. In some embodiments, the gate electrode has a thickness of about 55 nm in the X direction. Dimensions provided herein are for illustrative purposes only and are not intended to be limiting. In actual implementations, any suitable thickness or dimension may be used.

[0041] In the memory structure 10 of FIG. 3 , the three-dimensional array of NOR memory strings includes ferroelectric storage transistors 20 formed at both ends along the length (Y direction) of each active strip 24, with vertical local word lines 28 staggered in the Y direction along both ends. High density is achieved by sharing each vertical local word line 28 between adjacent active stacks. Each vertical local word line 28 functions as a gate electrode for the vertically aligned ferroelectric storage transistor 20 in the active strip 24 of each active stack. The vertical local word lines 28 may be connected to each other by interconnect conductors 42 (also referred to as “global word lines”) located above or below the three-dimensional array of NOR memory strings. In one embodiment, the global word lines 42 extend in a lateral direction (X direction) perpendicular to the length (Y direction) of the connected active strips 24. The global word lines 42 connect the local word lines 28 to support circuitry, such as word line driver circuitry, formed in the under-array circuitry (CuA) of the semiconductor substrate 12.

[0042] Memory Circuit and Operation

[0043] FIG. 4 is a circuit diagram of a three-dimensional array of NOR memory strings in an embodiment of the present invention. In particular, FIG. 4 illustrates a portion of a NOR memory string that can be constructed from the memory structure described with reference to FIGS. 1-3. Referring to FIG. 4, a memory array 90 includes ferroelectric storage transistors 92 arranged in NOR memory strings 95, including NOR memory strings 95-0 through 95-5. Each NOR memory string 95 includes ferroelectric storage transistors 92 connected across a common bit line BL94 (e.g., BLk through BLk+5) and a common source line SL96 (e.g., SLm through SLm+2), and each ferroelectric storage transistor 92 in each NOR memory string 95 is controlled by a respective word line WL98 (e.g., WLn through WLn+6). More specifically, each ferroelectric storage transistor 92 in the NOR memory string 95 has a gate terminal connected to a word line WL98, a drain terminal connected to a bit line BL94, and a source terminal connected to a source line SL96.

[0044] The memory array 90 includes NOR memory strings formed in an active stack, with each NOR memory string 95-0 through 95-5 located on a different plane of a three-dimensional memory structure. Ferroelectric storage transistors 92 in a column across multiple NOR memory strings are controlled by a common word line WL98, also referred to as a local word line or LWL. FIG. 4 shows a portion of a NOR memory string including ferroelectric storage transistors 92 connected to word lines WLn through WLn+6. In practice, a memory array may have thousands of word lines (e.g., 4096 word lines), resulting in thousands of randomly accessible ferroelectric storage transistors in a NOR memory string. The memory array 90 includes control circuitry for controlling read, write, and refresh operations of the memory array. For example, the control circuitry may be formed in the semiconductor substrate 12 below the memory array, as shown in FIG. 1, and referred to as circuit-under-array, or CuA.

[0045] In the memory array 90, adjacent NOR memory strings 95 share a common source line SL. For example, NOR memory strings 95-0 and 95-1 share a common source line SLm, and NOR memory strings 95-2 and 95-3 share a common source line SLm+1. Sharing a common source line between adjacent pairs of NOR memory strings reduces the number of conductive layers required to form the active stack compared to when each NOR memory string has its own common source line. In other embodiments, a memory array may be constructed with each NOR memory string 95 having its own common source line and common bit line, without sharing a common source line with other NOR memory strings.

[0046] In some embodiments, the memory array 90 may be organized into memory pages, which refers to a group of storage transistors that are accessed together for read and write operations. In this embodiment, a memory page 97 includes storage transistors arranged in columns across multiple planes of the memory array 90 and sharing a common word line 98. That is, a memory page 97 includes storage transistors in the active stacks of NOR memory strings 95-0 through 95-5 that are connected to the same word line 98 (e.g., word line WLn). In actual implementations, a memory page may include ferroelectric storage transistors 92 in one or more columns across multiple planes of NOR memory strings that are associated with the same continuous oxide semiconductor channel and share the same word line.

[0047] In the memory array 90, the source lines 96 are electrically floating, i.e., they are not directly connected to any potential. In practice, the source lines 96 maintain a relatively constant voltage through the parasitic capacitance of their source terminals, such as the parasitic capacitance between the source terminal and the gate terminal of the storage transistor. More specifically, the parasitic capacitance inherent in each NOR memory string (e.g., the distributed capacitance between the common source terminal of the NOR memory string and its multiple local word lines) may be used as a virtual voltage source to provide a common power supply voltage under certain operating conditions. In this description, the source lines 96 may be referred to as being connected to a virtual ground. In some examples, the power supply voltage may be set to a desired voltage value through a precharge operation, or the source lines may be left floating after the precharge operation. In one embodiment, the precharge operation sets the common bit lines to a desired voltage and then momentarily turns on the precharge transistors to short the common bit lines to the common source lines and transfer the bit line voltage to the source lines. As a result, the common source lines are charged from the common bit line voltage to a voltage equal to the voltage supplied to the bit lines. When the precharge operation is complete, the precharge transistor is turned off. The common source line maintains a relatively constant voltage through the parasitic capacitance of the source terminal, for example, the parasitic capacitance between the source terminal and the gate terminal of the storage transistor of the NOR memory string. In other embodiments, the source line 96 may be supplied with a predetermined potential, such as ground, by a voltage source.

[0048] In embodiments of the present invention, the ferroelectric storage transistor 92 is a thin-film ferroelectric field-effect transistor. More specifically, a ferroelectric field-effect transistor (also referred to as an FeFET) is formed by using a ferroelectric material as a gate dielectric layer between a gate conductor (usually a metal layer) and the channel of the field-effect transistor. In some embodiments, the ferroelectric storage transistor may further include an interfacial dielectric layer adjacent to the channel and the ferroelectric gate dielectric layer. The ferroelectric storage transistor achieves memory functionality by storing data as polarization states in the ferroelectric gate dielectric layer. In particular, a voltage applied between the gate conductor and the channel induces an electric polarization in the ferroelectric gate dielectric layer, which can be reversed by applying a voltage of opposite polarity. The ferroelectric gate dielectric layer retains the induced polarization state after the applied gate voltage is removed, thereby achieving the memory functionality of the ferroelectric storage transistor. For example, the ferroelectric storage transistor can be applied to form a non-volatile memory cell in which data is stored in the ferroelectric gate dielectric layer as two stable remanent polarization states.

[0049] The induced polarization state in the ferroelectric gate dielectric layer changes the threshold voltage of the ferroelectric storage transistor. The change or shift in the threshold voltage of the ferroelectric storage transistor due to the different polarization states can be used to represent different logic states of data. For example, two induced electric polarization states in the ferroelectric gate dielectric layer can result in two logic states (e.g., "0" and "1") represented by a high and a low threshold voltage of the ferroelectric storage transistor. In other embodiments, two or more polarization states can be induced in the ferroelectric gate dielectric layer, such as by applying two or more different ranges of voltage to the ferroelectric gate dielectric layer. In this manner, the ferroelectric storage transistor can be operated to store data in two or more logic states. For example, tri-states provide three threshold voltage states corresponding to 1.5 bits stored in each cell, or a continuum of analog states, such as quad-states (00, 01, 10, and 11) corresponding to two bits stored in a single ferroelectric memory cell. This continuum of analog states may be advantageous for artificial intelligence and machine learning applications.

[0050] In embodiments of the present invention, a three-dimensional array of NOR memory strings of ferroelectric storage transistors can be applied to implement non-volatile or quasi-non-volatile memory devices. For example, quasi-volatile memory has an average retention time of 100 milliseconds or more, e.g., about 10 minutes, or even several hours, while non-volatile memory devices may have minimum data retention times of days to years. In one embodiment, the ferroelectric storage transistors have a data retention time of more than 1 hour or even 10 8 For example, a ferroelectric storage transistor has a data retention time of several hours and a program / erase cycle endurance of approximately 10 11The use of such ferroelectric storage transistors allows for the creation of semi-volatile memory devices with refresh intervals on the order of hours, which are significantly longer than the refresh intervals of DRAMs, which require more frequent refreshes, e.g., tens of milliseconds. In some embodiments, multiple three-dimensional arrays of ferroelectric storage transistors ("tiles") can be used to create semi-volatile memory devices with high storage capacities.

[0051] A ferroelectric storage transistor stores data in a ferroelectric gate dielectric layer. In operation, when a voltage of a first polarity is applied to the gate terminal, e.g., relative to the source terminal, an applied electric field of the first polarity induces the ferroelectric gate dielectric layer to assume a first polarization state. Conversely, when a voltage of a second polarity is applied to the gate terminal, e.g., relative to the source terminal, an electric field of a second polarity opposite to the first polarity induces the ferroelectric gate dielectric layer to assume a second polarization state. The first polarization state is determined by a threshold voltage V of the ferroelectric storage transistor. t to a lower value and can be used to encode a first logic state, such as a logic "1" state. Alternatively, the second polarization state can be shifted to a lower value than the threshold voltage V of the ferroelectric storage transistor. t to a higher value, which can be used to encode a second logic state, such as a "0" state. Shifting the threshold voltage Vt of the ferroelectric storage transistor to a higher value (logic "0") is referred to herein as a programming operation, and shifting the threshold voltage Vt of the ferroelectric storage transistor to a higher value (logic "0") is referred to herein as a programming operation. t to a lower value (logic "1") is called an erase operation.

[0052] In some embodiments, the precharge operation described above can be used to set the source and bit line voltages of a NOR memory string to a more negative voltage than the local word line voltage (e.g., during an erase operation) or to a more positive voltage than the local word line voltage (e.g., during a program operation), thereby reversing the erased or programmed polarization state of the ferroelectric storage transistor with the voltage at one of the source and drain terminals as an electrode and the voltage at the local word line as a second electrode, thereby providing some contrast and advantage in that the polarization of the cell can be easily reversed. In some embodiments, each string of ferroelectric storage transistors is a thin-film transistor, as opposed to a single-crystal transistor formed in a semiconductor substrate, and therefore does not require a hardwired connection to the semiconductor substrate ground potential for either the common source, common drain, or common channel. Instead, applying only positive voltages (or only negative voltages) to the local word line or common source / common drain can impart both polarization states to the FeFET. This single voltage polarity feature simplifies the process flow for the control / logic transistors formed in the substrate and also allows for optimized operation since the ferroelectric polarization state typically has voltage hysteresis, changing from a negative voltage (erased state) to a positive voltage (programmed state).

[0053] In embodiments of the present invention, a ferroelectric storage transistor is formed using an oxide semiconductor channel. For example, the oxide semiconductor channel can be formed using an amorphous oxide semiconductor material such as indium gallium zinc oxide (InGaZnO or "IGZO"). An oxide semiconductor channel region has the advantage of having high mobility, which improves switching performance, without concerns about electron and hole tunneling. For example, the electron mobility of an IGZO film is between 10.0 and 100.0 cm, depending on the relative composition of indium, gallium, and zinc. 2 / V. The oxide semiconductor channel forms an N-type unipolar channel region, and the conductive layers 16a, 18, and 16b (FIG. 1) that form the source and drain terminals directly contact the channel region. The ferroelectric storage transistor thus formed is a depletion-mode device that is normally on and can be turned off by depleting the channel region of N-type carriers. The threshold voltage of the ferroelectric storage transistor is a function of the thickness d4 of the oxide semiconductor channel region 25 (FIG. 3). That is, the threshold voltage of the ferroelectric storage transistor is the amount of voltage required to deplete the thickness d4 of the oxide semiconductor channel region, thereby turning off the ferroelectric storage transistor.

[0054] 5-7, exemplary operating conditions for a three-dimensional NOR memory string of ferroelectric storage transistors are described. In an embodiment of the present invention, a write operation to the NOR memory string is performed by first performing an erase operation and then performing a program operation. In this embodiment, an erase operation is applied to all storage transistors in a memory page to set all storage transistors to a first logic state, and a subsequent program operation is applied to selected storage transistors in the memory page to program selected memory storage transistors to a second logic state.

[0055] 5 illustrates an erase operation that can be performed on a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention. Referring to FIG. 5, a memory array 50 is shown that includes a first portion of a set of NOR memory strings belonging to a selected global word line (GWL) 42a and a second portion of the same set of NOR memory strings belonging to an unselected global word line (GWL) 42b. In an actual implementation, the first and second portions of the NOR memory strings would be formed on the same set of NOR memory strings (the same set of active stacks), but would exhibit ferroelectric storage transistors associated with different local word lines 28. That is, the first and second portions of the NOR memory strings would exhibit ferroelectric storage transistors located at different positions in the Y-direction along the NOR memory strings.

[0056] As described above, the global word lines 42a, 42b are interconnect conductors that connect word line signals to one or more local word lines 28 coupled to NOR memory strings formed in one or more active stacks. A first portion of the NOR memory strings corresponds to the selected global word line 42a and includes ferroelectric storage transistors arranged in the same plane in the X direction. The ferroelectric storage transistors of the first portion correspond to memory pages 52a and 54a, which are formed in the same plane but at different positions in the X direction. A second portion of the NOR memory string corresponds to the unselected global word line 42b and includes ferroelectric storage transistors arranged in the same plane in the X direction. The ferroelectric storage transistors of the second portion correspond to memory pages 52b and 54b, which are formed in the same plane but at different positions in the X direction. In particular, the ferroelectric storage transistors of page 52b correspond to an unselected page in the same NOR memory string as the selected page 52a. That is, memory page 52a and memory page 52b belong to the same set of NOR memory strings but are located at different positions in the Y direction. Therefore, the bit lines and source lines of pages 52a and 52b are biased to the same voltage level, but page 52b is associated with unselected global word line 42b. Meanwhile, memory pages 54a and 54b are associated with the same NOR memory string but are located at different positions in the Y direction. Memory page 54a is connected to selected global word line 42a, and memory page 54b is connected to unselected global word line 42b.

[0057] In this embodiment, a memory page includes ferroelectric storage transistors in two adjacent stacks of NOR memory strings that share a common word line and also share the same continuous oxide semiconductor channel region. In one embodiment, memory array 50 includes eight layers of NOR memory strings, and a memory page includes at least 16 ferroelectric storage transistors (or 16 bits) across two adjacent active stacks of NOR memory strings. In other embodiments, the oxide semiconductor channels can be separated at the bottom of each narrow trench 22. In that case, the ferroelectric storage transistors in each stack of NOR memory strings form their own memory page. For example, if the oxide semiconductor channels are separated at the bottom of a narrow trench, memory array 50 may include a memory page of eight ferroelectric storage transistors (or 8 bits) across one active stack of eight layers of NOR memory strings.

[0058] In this embodiment, an erase operation erases a memory page of ferroelectric storage transistors. In some examples, this is referred to as a block erase operation. For example, an erase operation erases all ferroelectric storage transistors associated with a selected global word line 42a in a selected page 52a. To erase the ferroelectric storage transistors in the selected page 52a, a word line voltage that is more positive than the source line and bit line voltages is used. In some embodiments, the source line voltage and bit line voltage are both set to 0V, and the selected global word line 42a is driven to 2-3V. In this example, the selected global word line 42a is driven to 2.2V. To inhibit erasure of other unselected ferroelectric storage transistors, an unselected global word line 42b is biased to a more positive voltage than the voltage of the selected global word line 42a. For example, the unselected global word line 42b is biased to half the voltage of the selected global word line 42a, e.g., 1.1V. The source line voltage and bit line voltage of the unselected pages 54a, 54b are driven to the same voltage (e.g., 1.1V) as the unselected global word line 42b, resulting in a gate-to-source voltage of 0V for these unselected ferroelectric storage transistors. For the ferroelectric storage transistors in page 52b, the source line and bit line are biased to 0V because they belong to the same set of NOR memory strings as the selected page 52a. However, these unselected ferroelectric storage transistors are not erased because their gate terminals are biased to the unselected global word line voltage (e.g., 1.1V), and the gate-to-source voltage across these unselected ferroelectric storage transistors is not sufficient to reverse the polarization state of the transistors. As a result, only the ferroelectric storage transistors of page 52a are erased. In the present disclosure, erased ferroelectric storage transistors retain a first logic state "1."

[0059] 6 illustrates a program operation that may be performed in a three-dimensional array of NOR memory strings following the erase operation of FIG. 5 in an embodiment of the present invention. Referring to FIG. 6, after the ferroelectric storage transistors in a selected page 52a are erased (to a logic state "1"), a portion of the ferroelectric storage transistors in the page will be programmed to a second logic state "0" based on the write data. In FIG. 6, it is assumed that the transistors indicated by the dashed box 44 are programmed. The other transistors are not programmed and retain the logic state associated with the erased state ("1").

[0060] To program the selected ferroelectric storage transistor in the selected page 52a, a word line voltage that is more negative than the source line and bit line voltages is used. Alternatively, the source line and bit line voltages of the ferroelectric storage transistor to be programmed may be more positive than the word line voltage. In an embodiment of the present disclosure, the program operation of the ferroelectric storage transistor achieves asymmetric programming. Asymmetric programming refers to using different source line and bit line voltages for the program operation. In this embodiment, to program the selected ferroelectric storage transistor (represented by the dashed box 44) in the selected page 52a, the selected global word line 42 is set to 0V. The bit line voltage of the selected ferroelectric storage transistor to be programmed is set to 1.8V, and the bit line voltage of the unselected ferroelectric storage transistors is set to 0.8V. The source line voltages of all ferroelectric storage transistors are also set to 0.8V. In this configuration, only ferroelectric storage transistors with a negative gate-source voltage (e.g., 0.8V) and a sufficiently negative gate-drain voltage (e.g., −1.8V) will have a high enough electric field at their drain terminal to flip the polarization state of the transistor to the programmed state (logic “0”). The other ferroelectric storage transistors in the selected page 52a will have a gate-drain voltage of only −0.8V and will retain their previously erased state (e.g., logic “1”).

[0061] To inhibit programming of other unselected ferroelectric storage transistors, the unselected global word lines 42b are biased to a more positive voltage than the voltage of the selected global word line 42a. For example, the unselected global word lines 42b are biased to 0.8V. The source line voltage and bit line voltage of the unselected pages 54a and 54b are driven to the same voltage (e.g., 0.8V) as the unselected global word lines 42b. As a result, a gate-source voltage of 0V is applied across the unselected ferroelectric storage transistors in the unselected page 54b, and these transistors are not programmed. The ferroelectric storage transistors in the unselected page 54a have a negative gate-source voltage of −0.8V, but the gate-drain voltage is only −0.8V, which is insufficient to change the polarization state of these ferroelectric storage transistors. For the unselected ferroelectric storage transistors in page 52b, because they belong to the same set of NOR memory strings as the selected page 52a, the source line and bit line voltages are biased to the same values ​​as the transistors in page 52a. However, these unselected ferroelectric storage transistors are not programmed because their gate terminals are biased to the unselected global word line voltage (e.g., 0.8V), and the gate-to-source voltage across these unselected ferroelectric storage transistors is 0V, keeping them off. As a result, only the selected ferroelectric storage transistors (shown by box 44) in page 52a are programmed.

[0062] In the memory array 50 of FIG. 6 , a continuous channel forms a parasitic transistor device in the region between two bit lines of two ferroelectric storage transistors adjacent to each other in the Z direction, as indicated by dashed ellipses 45a-45f in FIG. 6 . Each of these parasitic transistor devices includes a ferroelectric gate dielectric layer, a channel region, and two bit lines functioning as conductive source / drain terminals. Although the memory array 50 includes such parasitic transistor devices, they do not affect memory operations. In particular, the parasitic transistor devices 45a-45f are erased during an erase operation. During a program operation, a parasitic transistor device (e.g., 45d) located between two unselected ferroelectric storage transistors is not programmed, while parasitic transistor devices (e.g., 45a-c and 45e-f) having at least one adjacent ferroelectric storage transistor selected for programming are simultaneously programmed. Meanwhile, programming the parasitic transistor device increases the threshold voltage of the parasitic transistor device, which has the effect of turning off the programmed parasitic transistor device for a read operation. Therefore, incidental programming of the parasitic transistor devices during the program operation does not affect the operation of memory array 50.

[0063] FIG. 7 illustrates a read operation that can be performed in a three-dimensional array of NOR memory strings in accordance with an embodiment of the present invention, following the write operations of FIGS. 5 and 6. Referring to FIG. 7, to read the ferroelectric storage transistors from the selected page 52a, a small positive gate-source voltage and a small positive bit line voltage are applied. In this embodiment, the read operation is performed by setting the selected global word line 42a to a positive voltage of 0.7V, the source line voltage to 0V, and the bit line voltage to 0.5V. With this biasing, ferroelectric storage transistors in the erased state are conductive, and an "on" current, Ion, flows between the bit line and the source line of the erased storage transistor. Meanwhile, ferroelectric storage transistors in the programmed state are non-conductive, and no current flows between the bit line and source line of the programmed storage transistor, except for a small leakage current, referred to as the "off" current, Ioff.

[0064] During a read operation, the unselected global word lines 42b are set to 0V. The bit line and source line voltages of the unselected memory pages 54a, 54b are also set to 0V. For unselected ferroelectric storage transistors in page 52b that belong to the same NOR memory string as the selected page 52a, the source line and bit line voltages are biased to the same values ​​as the transistors in page 52a. However, because these unselected ferroelectric storage transistors have their gate terminals biased to the unselected global word line voltage (e.g., 0V) and the gate-to-source voltage across them is 0V, these transistors are kept off and therefore not read.

[0065] When biased in this manner, the ferroelectric storage transistors of the selected erased page 52a conduct a current Ion, while the programmed ferroelectric storage transistors of the selected programmed page 52a conduct a current Ioff. The bit lines of the ferroelectric storage transistors are connected to a sense amplifier, which senses the cell current and generates an output logic value indicative of the cell current. The parasitic transistor devices between the two bit lines do not affect the read operation, even when the parasitic devices are erased or programmed. This is because the source / drain terminals of the parasitic transistor devices are biased to the same bit line voltage (0.5V), so no current flows through these parasitic transistor devices.

[0066] In some embodiments, the ferroelectric storage transistors of the three-dimensional array of NOR memory strings may be induced to store multi-state data, i.e., to store data in two or more polarization states corresponding to two or more logic states. In one embodiment, the ferroelectric storage transistors are operated to store multi-state or multi-level data by erasing the ferroelectric storage transistors to a low threshold voltage level representing one polarization state and then programming the ferroelectric storage transistors to two or more intermediate states, each state having a different threshold voltage level above the threshold voltage level associated with the erased state.

[0067] In some embodiments, the ferroelectric storage transistor is erased using the bias conditions described above with reference to Figure 5. For example, the selected global word line is driven to 2.2V, and the selected bit line and source line are driven to 0V. The unselected global word lines, unselected bit lines, and unselected source lines are driven to 1.1V. This bias condition erases the selected ferroelectric storage transistor to a first threshold voltage, which is the lower or lowest threshold voltage of the ferroelectric storage transistor.

[0068] In some embodiments, ferroelectric storage transistors within the same page (e.g., page 52a) are programmed to multiple logic states in a single program operation. That is, the threshold voltages of ferroelectric storage transistors within the same page are raised from an erased threshold voltage level to different, higher threshold voltage levels in the same program operation. Thus, only two write cycles (one erase and one program) are required to store multiple (or more than two) logic states in the ferroelectric storage transistors.

[0069] In one example, bias conditions used to program all ferroelectric storage transistors in the same page to two program states include driving a selected global word line to 0V and driving a selected bit line to 1.6V or 2V, depending on the desired program state of each ferroelectric storage transistor. In this manner, the selected ferroelectric storage transistors can be programmed to two program states having different program threshold voltage levels with a single program operation, resulting in three logical states, together with the erased state, stored in the ferroelectric storage transistors of the selected page. In another example, bias conditions used to program all ferroelectric storage transistors in the same page to three program states include driving a selected global word line to 0V and driving a selected bit line to 1.6V, 1.8V, or 2V, depending on the desired program state of each ferroelectric storage transistor. In this manner, the selected ferroelectric storage transistors can be programmed to three program states having different program threshold voltage levels with a single program operation, resulting in four logical states, together with the erased state, stored in the ferroelectric storage transistors of the selected page. In this example, all source lines, unselected bit lines, and unselected global word lines may be set to 0.8V during a multi-state program operation. In another example, selected ferroelectric storage transistors in a memory page may be programmed to any number of program states in the same program operation by applying different program voltages to the bit lines, e.g., voltage values ​​between 1.6V and 2.0V. Selected ferroelectric storage transistors in a memory page are programmed to successive threshold voltage values ​​by applying program voltages across a successive voltage range, such as successive program voltage values ​​between 1.6V and 2.0V.

[0070] In another embodiment, ferroelectric storage transistors within the same page (e.g., page 52a) are programmed to multiple logic states in separate program operations. That is, after an erase operation, selected ferroelectric storage transistors are programmed to increase their threshold voltages to different levels in separate program operations. In one example, selected global word lines are driven to 0V. Then, in a first program operation, a first group of selected bit lines are driven to 1.6V (VPP voltage) to program the associated ferroelectric storage transistors to a second logic state (the erased state is the first logic state). All source lines, unselected bit lines, and unselected global word lines are driven to a voltage value of 0.44V. * VPP, i.e., 0.7V. To program another logic state with a second program operation, a second group of selected bit lines are driven to 2.0V (VPP voltage), programming the associated ferroelectric storage transistors to a third logic state. All source lines, unselected bit lines, and unselected global word lines are driven to a voltage value of 0.44V. * VPP, i.e., 0.88 V. By performing successive program operations using different VPP voltage values, it is possible to program a selected ferroelectric storage transistor to any number of logic states.

[0071] The above description describes voltage bias conditions and provides exemplary voltage values ​​to describe erase, program, and read operations of a memory array of ferroelectric storage transistors. The voltages listed above are for illustrative purposes only and are not intended to be limiting. In other embodiments, other voltage values ​​may be used to implement the voltage bias conditions for erase, program, and read operations.

[0072] As mentioned above, in embodiments of the present disclosure, the common source line of a memory structure may be left floating or not electrically connected to any potential. Instead, the common source line may be precharged with one or both of the bit lines of a NOR memory string pair prior to erase, program, and read operations. In one embodiment, the precharge operation sets the bit line to a desired voltage via a precharge transistor, and then the source line is charged from the bit line to a voltage equal to the bit line voltage.

[0073] Sense amplifier bit line selection

[0074] Returning to FIG. 1 , the memory structure 10 is shown as including four active stacks with four bit lines on each layer or plane of an eight-layer, three-dimensional memory structure. Ferroelectric storage transistors 20 are formed on either side of each active stack, forming a NOR memory string along each active strip. In an actual implementation, the memory structure 10 may be formed with thousands of bit lines (e.g., 2048 bit lines) per layer, with each bit line coupled to thousands of LWL structures to form thousands of ferroelectric storage transistors 20 (e.g., 4096 transistors) along the active strip as a NOR memory string.

[0075] In some embodiments, storage transistors in memory structure 10 are accessed in units of memory pages having a given byte size, and support circuitry formed in semiconductor substrate 12 below the memory array includes sense amplifier circuitry for outputting byte-sized read data for the memory pages. In one example, memory structure 10 may be accessed with a memory page size of 64 bytes or 512 bits. In that case, support circuitry below the memory array may include 512 sense amplifiers to output the 512-bit read data. In some embodiments, bit line selectors are used to multiplex thousands of bit lines in the memory structure to a given number of sense amplifiers, thereby enabling access to a page of memory data. For example, bit line selectors may be used to multiplex 16k bit lines to 512 sense amplifiers.

[0076] 8 is a diagram illustrating a bit line selector that can be implemented in a three-dimensional array of NOR memory strings in an embodiment of the present invention. In the embodiments described above, the ferroelectric storage transistors formed in the active stacks belong to the same memory page and are accessed together. Referring to FIG. 8, a bit line selector circuit 80 is configured to enable selection of bit lines across all layers of the memory array that belong to the same active stack, thereby selecting storage transistors that belong to the same memory page.

[0077] In this embodiment, the bit line selector circuit 80 includes multiple bit line selectors SEL0 to SEL31. For simplicity, only two selectors, SEL0 and SEL31, are shown in this diagram. Each bit line selector SELn includes a multiplexer 82 (e.g., multiplexer circuits 82-1, 82-2, etc.), and each multiplexer 82 selects one bit line from 32 columns. The multiplexers 82 may be referred to as a 32:1 multiplexer (mux) or a 32:1 selector. In this embodiment, the multiplexers 82 receive selection signals S0 to S31 and select or activate one output terminal 88 from 32 output terminals. For example, the multiplexer 82-1 selects one output terminal from 32 output terminals 88-0 to 88-31. Meanwhile, the multiplexer 82-31 selects one output terminal from 32 output terminals 88-992 to 88-1023. Each output terminal 88 is coupled to a gate terminal of a bank of pass transistors. Each bank of pass transistors receives at a first terminal a bit line signal for the same column across all layers of the memory array. When a pass transistor is activated by output terminal 88, the bit line signal is passed to a second terminal of each of the banks of pass transistors. The second terminals of the banks of pass transistors are connected to respective sense amplifier circuits, such as via metal interconnects.

[0078] For example, in bit line selector SEL0, each output terminal 88-0 through 88-31 is connected to a bank of pass transistors, and the pass transistors of each bank are connected to a respective sense amplifier circuit SA00 through SA07. Each output terminal 88-0 through 88-31 is connected to a different page of ferroelectric storage transistors. For example, output terminal 88-0 is connected to bit line B0 across layers L0 through L7 of the memory array, and output terminal 88-31 is connected to bit line B31 across layers L0 through L7 of the memory array. Meanwhile, bit line selector SEL31 includes a 32:1 multiplexer 82-31 having output terminals 88-992 through 88-1023, and the pass transistors of each bank are connected to a respective sense amplifier circuit SA248 through SA255. Each output terminal 88-992 through 88-1023 is connected to a different page of ferroelectric storage transistors. For example, output terminal 88-992 is connected to bit line B992 that traverses layers L0 to L7 of the memory array, and output terminal 88-1023 is connected to bit line B1023 that traverses layers L0 to L7 of the memory array.

[0079] As configured in this manner, in bit line selectors SEL0-SEL31, multiplexers 82-0-82-31 select one output terminal 88 in response to select signals S0-S31. As a result, one column of bit lines associated with each multiplexer is selected, and each selected column includes bit lines from all layers of the array. Thus, a total of 32 columns of bit lines are selected, each column being coupled to a respective sense amplifier circuit. In this example, the selected 32 columns of bit lines are connected to 256 sense amplifier circuits SA0-SA255, providing 256 bits of read data.

[0080] The bit line selector circuit 80 described herein is for purposes of example only and is not intended to be limiting. While various circuit configurations can be used to implement the bit line selection described herein, bit line selector circuit 80 is disclosed herein as one exemplary embodiment.

[0081] Manufacturing Process

[0082] 9A-9N illustrate a process for fabricating a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors according to an embodiment of the present invention. 9A-9H illustrate vertical cross-sectional views (i.e., in the X-Z plane) of a portion of the three-dimensional array of NOR memory strings. 9I-9N each include two views. View (i) is a horizontal cross-sectional view (i.e., in the X-Y plane) taken along line AA' shown in view (ii). View (ii) is a vertical cross-sectional view (i.e., in the X-Z plane) taken along line AA' in view (i).

[0083] Referring to FIG. 9A , the memory structure 100 is first formed by sequentially depositing (i) an insulating dielectric layer 104 and (ii) a sacrificial layer 106 over a planar surface of a semiconductor substrate 101 to form a multilayer structure. In some embodiments, a buffer layer 102 may be provided over the surface of the semiconductor substrate 101 before the insulating dielectric layer 104 and the sacrificial layer 106 are formed over the surface of the substrate 101. In some embodiments, the buffer layer 102 may be a silicon oxycarbide (SiOC) layer or a silicon oxide (SiO ) layer. In this embodiment, the insulating dielectric layer 104 is a silicon oxide layer and may have a thickness of 30 nm. The sacrificial layer 106 is a silicon nitride layer and may have a thickness of 40 nm. The sacrificial layer 106 is replaced with a conductive layer in a metal replacement process in subsequent processing. FIG. 9A illustrates the memory structure 100 after deposition of the initial layers of thin films. As noted above, the dimensions in this description are provided for illustrative purposes and are not intended to be limiting. In actual implementations, any suitable thicknesses and dimensions may be used. Also, the figures are not necessarily to scale.

[0084] Referring to FIG. 9B, a first set of trenches 108 are formed in the memory structure 100 using, for example, anisotropic etching after a photolithographic patterning step. In some examples, the width of each trench 108 may be 70 nm, and the spacing between them may be 190 nm. Referring to FIG. 9C, an amorphous metal oxide semiconductor layer 120 is conformally deposited on the exposed sidewalls of the trenches 108. The amorphous metal oxide semiconductor layer 120 ("oxide semiconductor layer 120") may be deposited using, for example, atomic layer deposition (ALD) techniques, plasma-enhanced ALD techniques, or physical vapor deposition (PVD). Notably, the oxide semiconductor layer 120 can be formed at low processing temperatures, such as below 400°C. In this embodiment, the oxide semiconductor layer 120 is an indium gallium zinc oxide (InGaZnO, or "IGZO") layer. For example, IGZO deposition using thermal ALD or plasma-enhanced ALD can be performed at processing temperatures as low as 200°C. Other oxide semiconductor materials that may be used include indium zinc oxide (InZnO, or "IZO"), indium aluminum zinc oxide (IAlZnO), or indium tin zinc oxide (ITZO). In one embodiment, the oxide semiconductor layer 120 has a thickness of 10 nm. The oxide semiconductor layer 120 forms the channel region of the ferroelectric storage transistor.

[0085] In this embodiment, the deposited oxide semiconductor layer 120 is a continuous layer along the exposed sidewalls of the trenches 108. In some embodiments, after the oxide semiconductor layer 120 is deposited, an etching process can be performed to etch away the oxide semiconductor layer 120 at the bottom of the trenches 108, thereby isolating the oxide semiconductor layer formed on the sidewalls of the trenches. Etching the oxide semiconductor layer 120 from the bottom of the trenches 108 is optional and may be included if a particular memory page size is desired, as discussed above.

[0086] 9D, trench 108 is then filled with dielectric material 110. In some embodiments, dielectric material 110 is a silicon oxide material, such as SiO. Excess dielectric material may be removed from the top of memory structure 100 using, for example, chemical mechanical polishing (CMP). FIG. 9D illustrates the resulting memory structure 100.

[0087] Referring to FIG. 9E, a second set of trenches 109 are then cut using substantially the same technique as described above with reference to FIG. 9B, with mechanical support from the dielectric material 110. In some examples, the width of the trenches 109 may be 70 nm. Each of the second set of trenches 109 is cut between adjacent pairs of trenches 108 in the first set, and each of the second set of trenches 109 is cut substantially equidistant from adjacent pairs of trenches 108 in the first set. Cutting the trenches 108 and 109 between each other within the multilayer structure results in the formation of a stack within the multilayer structure, referred to herein as an "active stack." In some examples, the width of each active stack is approximately 60 nm. The resulting narrow strips of layers 104 and 106 within the active stack are referred to herein as "active strips."

[0088] The sacrificial silicon nitride layer 106 is then removed, for example, using a wet etch, thereby forming a cavity between the insulating dielectric layers 104, as shown in FIG. 9F. The cavity is then filled with a conductive layer 112, as shown in FIG. 9G. In some embodiments, the conductive layer 112 is a refractory metal layer such as molybdenum (Mo) or tungsten (W). In other embodiments, the conductive layer 112 may be a metal layer selected from molybdenum, titanium, tungsten, lanthanum, tantalum, ruthenium, any silicide thereof, any nitride thereof, and any combination thereof. For example, the conductive layer 112 may be formed using, for example, atomic layer deposition (AED) techniques. An etching step removes any deposited material from the sidewalls of the trench 109. In some examples, an isotropic wet etch is used to remove the deposited material from the sidewalls of the trench 109. In this embodiment, the conductive layer 112 is a molybdenum layer and forms the source and drain terminals of the ferroelectric storage transistor that is being formed.

[0089] An amorphous metal oxide semiconductor layer 120 is then conformally deposited on the exposed sidewalls of trench 109 using, for example, an ALD process. The oxide semiconductor layer 120 may have a thickness of 10 nm. The trench 109 is then filled with a dielectric material 110, such as SiO. Excess deposited material may be removed from the top of memory structure 100, such as by CMP. The resulting memory structure 100 is shown in FIG. 9H.

[0090] Referring to FIG. 9I, vias 114 are then patterned and the dielectric material 110 exposed by the vias 114 is etched, for example, using an anisotropic etch. The vias 114 are masked in an elliptical shape, as shown in horizontal cross section (i) of FIG. 9I. In some examples, the elliptical mask openings may have a major axis of 100 nm along the X direction and a minor axis of 60 nm along the Y direction. The vias 114 are later filled with a dielectric material to isolate adjacent storage transistors in the resulting NOR memory string.

[0091] 9J, via 114 is then filled with a sacrificial silicon nitride liner 115 and a sacrificial amorphous silicon layer 116. Excess material on memory structure 100 may be removed, for example, using CMP. Once via 114 is filled, the remainder of dielectric material 110 in trenches 108 and 109 is removed, for example, using a wet etching step, as shown in FIG. 9K. This results in a cavity 118 in trenches 108 and 109 outside via 114, which is then filled with a sacrificial layer of silicon nitride liner 115 and amorphous silicon layer 116.

[0092] Referring to FIG. 9L, a ferroelectric gate dielectric layer 122 is then conformally deposited on the exposed sidewalls of the cavity 118. In some embodiments, the ferroelectric gate dielectric layer 122 is deposited by any one of a variety of suitable deposition methods, including, but not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Other deposition methods, such as evaporation and electrodeposition, may also be used. In some embodiments, the ferroelectric gate dielectric layer 122 is a doped hafnium oxide (HfO) layer. In one embodiment, hafnium oxide is doped with zirconium oxide (ZrO) to form a hafnium zirconium oxide layer (HfZrO or “HZO”). In other embodiments, the hafnium oxide is doped with silicon (Si), iridium (Ir), and lanthanum (La). In some embodiments, the ferroelectric gate dielectric layer 122 is a material selected from zirconium doped hafnium oxide (HZO), silicon doped hafnium oxide (HSO), aluminum zirconium doped hafnium oxide (HfZrAlO), aluminum doped hafnium oxide (HfO2:Al), lanthanum doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

[0093] In one embodiment, the ferroelectric gate dielectric layer 122 has a thickness of 4 nm. In some embodiments, an interfacial dielectric layer (also referred to as an "interfacial layer") is formed between the oxide semiconductor layer 120 and the ferroelectric gate dielectric layer 122. In some embodiments, the interfacial dielectric layer is formed using a material having a high dielectric constant (K) (also referred to as a "high X" material). In one example, the interfacial dielectric layer, if provided, may be a silicon nitride (Si3N4) layer and have a thickness of 1 nm. The ferroelectric gate dielectric layer 122 may be deposited and then annealed to form a ferroelectric phase in the ferroelectric material. The ferroelectric gate dielectric layer 122 forms the gate dielectric layer of the ferroelectric storage transistor.

[0094] After annealing the deposited ferroelectric gate dielectric layer 122, the cavities 118 are then filled with a conductive layer 124 comprising a successively deposited titanium nitride (TiN) liner and a tungsten (W) layer. The TiN liner may be formed, for example, using atomic layer deposition (ALD) techniques. In each of the cavities 118, the conductive layer 124 provides a vertical local word line (LWL) for adjacent vias 114 (filled with sacrificial materials 115, 116) that serves as the gate electrode for each vertically aligned ferroelectric storage transistor in the same active stack. The structure resulting from the combination of the ferroelectric gate dielectric layer 122 and the conductive layer 124 is referred to herein as a local word line (LWL) structure. Excess deposited material may be removed from the top of the memory structure 100, such as by CMP. Figure 9L illustrates the resulting memory structure 100.

[0095] Advantageously, memory structure 100 includes a regular-sized cavity 118a in the central portion of the memory structure and an expanded-sized cavity 118b at the end of the memory structure (FIG. 9K). As a result, memory structure 100 includes LWL structures formed in regular-sized cavity 118a that are used to form the ferroelectric storage transistors of a NOR memory string. The structures formed in the expanded-sized cavity 118b at the end of memory structure 100 may be dummy structures or, if applicable, may be converted into non-memory transistors, such as precharge transistors. The detailed configuration of memory structure 100 at the end of the memory string is not important to the practice of the present invention.

[0096] 9M, after the LWL structure is formed, the sacrificial material formed in the via 114 is then removed to form the cavity 126. In this embodiment, the amorphous silicon layer 116 is removed, for example, by using a wet etching step. The silicon nitride liner 115 remains in the cavity 126. In other embodiments, the silicon nitride liner 115 may also be removed, for example, by using a wet etching step.

[0097] Referring to FIG. 9N, a dielectric material 130 then fills the exposed vias 126. In some embodiments, the dielectric material 130 is silicon oxide, such as SiO . Excess material on the memory structure 100 may be removed by CMP. The resulting memory structure 100 includes NOR memory strings of ferroelectric storage transistors formed in multiple active stacks in multiple layers, achieving a high-capacity memory device. In particular, the ferroelectric storage transistors in the NOR memory strings are formed by a conductive layer 112 that functions as a source terminal and a drain terminal, an oxide semiconductor layer 120 that functions as a channel region, a ferroelectric gate dielectric layer 122 that functions as a gate dielectric layer, and a conductive layer 124 that functions as a gate terminal or gate conductor. The memory structure 100 includes the oxide semiconductor layer 120, which is a continuous layer across all layers of the active stacks in the Z direction. Furthermore, the conductive layer 112 is arranged so that pairs of NOR memory strings share a common source line.

[0098] In the memory structure 100 of Figure 9N, the oxide semiconductor layer 120 is formed as a continuous layer across the active stack and also along the NOR memory string in the Y direction. Because the areas between the LWL structures are filled with dielectric material only, leaving the oxide semiconductor layer 120 between the LWL structures does not affect the memory device. However, in some embodiments, the oxide semiconductor layer 120 may be separated between the LWL structures, as illustrated by the memory structure 30 of Figure 2.

[0099] 10A-10B illustrate another process for fabricating a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors, according to an embodiment of the present invention. Referring to FIG. 10A, a memory structure 200 is constructed in a manner similar to that described above with reference to FIGS. 9A-9H, with the resulting structure including active stacks of alternating insulating dielectric layers 104 and conductive layers 112, lined with oxide semiconductor layers 120, and separated by trenches filled with dielectric material 110, as shown in FIG. 9H.

[0100] The vias 114 are then patterned, and the dielectric material 110 exposed by the vias 114 is etched, for example, using anisotropic etching. In this embodiment, after the dielectric material 110 is removed from the vias 114, the exposed oxide semiconductor layer 120 within the vias 114 is then also removed, for example, by performing an anisotropic dry or wet etching process. As a result, the oxide semiconductor layer 120 remains only outside the vias 114, and each segment of the oxide semiconductor layer 120 is separated in the Y direction along the NOR memory strings to be formed. Subsequent processing steps described above with reference to FIGS. 9J-9N are performed to complete the fabrication of the memory structure 200. Referring to FIG. 10B, an LWL structure is formed in the cavity between the vias 114. The LWL structure includes a ferroelectric gate dielectric layer 122 and a conductive layer 124. The sacrificial material formed within the vias 114 is replaced with a dielectric material 130, such as silicon oxide. As shown in the horizontal view (i) of FIG. 10B, the oxide semiconductor layer 120 is separated in the Y direction along the NOR memory string, and is provided only in the portions adjacent to each LWL structure.

[0101] In embodiments of the present invention, a memory structure can be constructed using air gaps as insulators disposed between pairs of NOR memory strings sharing a common source line. The air gap has a dielectric constant of approximately 1.0, which is significantly lower than most dielectric materials, effectively reducing parasitic capacitance between bit lines of adjacent NOR memory string pairs in the Z direction. The air gap improves isolation between adjacent pairs of NOR memory strings, thereby improving the performance of the resulting memory device. FIG. 11 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings isolated by air gap cavities in embodiments of the present invention. For ease of explanation, similar elements in FIGS. 1, 3, and 11 are labeled with similar reference numerals. Referring to FIG. 11, a memory structure 300 includes a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed above a semiconductor substrate (not shown in FIG. 11). In this embodiment, active stack pairs of NOR memory strings 24 bordering the same narrow trench 22 share a common oxide semiconductor channel region 25, ferroelectric gate dielectric layer 26, and gate electrode 28. The oxide semiconductor channel region 25 formed in one narrow trench 22 is insulated from the oxide semiconductor channel region 25 formed in the other narrow trench 22. Each active stack 24 has ferroelectric storage transistors formed on both sides of the stack. When the LWL structures are staggered in the Y direction, adjacent narrow trenches 22 have storage transistors formed offset from each other in the Y direction, so that the active stack 24 does not include storage transistors formed directly across the active stack in the X direction. The local word line structures formed in each trench 22 are insulated from each other by dielectric material 23.

[0102] In the memory structure 300, each pair of active layers includes a first common bit line (first conductive layer 16a) and a common source line (second conductive layer 18) separated by an insulating layer 17a, and a second common bit line (third conductive layer 16b) separated from the common source line 18 by an insulating layer 17b, forming first and second NOR memory strings. In embodiments of the present disclosure, each pair of first and second NOR memory strings is separated from the other pair in the Z direction by an air gap or cavity 315, also referred to herein as an “air gap cavity.” In this manner, the air gap 315 isolates adjacent bit lines from each other within each active stack of the memory structure. The three-dimensional array of NOR memory strings may include a bottom insulating layer 305 formed at the bottom of the memory array to isolate the first conductive layer 16a from the semiconductor substrate. The three-dimensional array of NOR memory strings may further include an upper insulating layer 325 formed over the three-dimensional array to insulate the memory array from conductive connectors formed above the memory array.

[0103] As used herein, an air gap refers to a cavity formed within a memory structure that is free of any material. In some embodiments, the air gap 315 can be formed by replacing a portion of an insulating dielectric layer with an air gap sacrificial layer during a multilayer sequential deposition process such as that shown in FIG. 9A . For example, in the multilayer structure of FIG. 9A , every third insulating dielectric layer 140, except for the bottom insulating dielectric layer, can be replaced with an air gap sacrificial layer. In some embodiments, the air gap sacrificial layer is a material that has high etch selectivity to the conductive material used to form the source and bit lines 16 a, 16 b, 18, and also to the insulating material 17 a, 17 b used to insulate the source and bit lines from the memory strings. In some embodiments, the air gap sacrificial layer can be a material selected from germanium (Ge), silicon germanium (SiGe), or carbon (C).

[0104] Subsequently, after forming local word line structures in the trenches 22, for example, after the process of FIG. 9N, which forms a memory structure 300 including an oxide semiconductor channel 25, a ferroelectric gate dielectric layer 26, and a gate electrode 28, the air gap sacrificial layer can then be etched away, such as through one or more shafts formed at designated locations within the narrow trenches 22. The air gap sacrificial layer can be etched away using an isotropic dry or wet etch, or, in the case of a carbon sacrificial layer, ashing. The dielectric material 23 formed within the trenches 22 between the local word line structures and the active stack 24 supports the active stack 24. The air gap sacrificial layer along the Y-direction length of the NOR memory string is etched away to form elongated cavities 315, referred to herein as “air gaps” or “air gap cavities,” bounded by adjacent bit line conductors. When formed in this manner, the memory structure 300 includes periodic air gaps 315 formed in the array between each adjacent pair of bit line conductors 16b and 16a. These periodic air gaps 315 have a dielectric constant of approximately 1.0, which is much lower than the dielectric constant of the insulating dielectric material used to isolate the bit lines. For example, silicon dioxide (SiO2) has a dielectric constant of 4.0, while the air gaps have a dielectric constant of 1.0. By using the cavities or air gaps 315 as an insulating layer between adjacent bit lines, the parasitic capacitance between pairs of adjacent bit lines in the Z direction is significantly reduced.

[0105] In some embodiments, after the air gap sacrificial layer is removed, an air gap liner layer may be deposited to seal the surfaces exposed by the air gap 315. For example, the air gap liner layer may be employed to seal the exposed conductive material forming the common bitlines 16a and 16b and the exposed surfaces of the oxide semiconductor channel region 25. In some embodiments, the air gap liner layer is a dielectric material, and in some examples, the air gap liner layer is a silicon nitride layer or a silicon oxide layer that lines the exposed surfaces formed by the air gap cavity 315.

[0106] In other embodiments, cavities or air gaps 315 may be advantageously employed to segment the oxide semiconductor channel 25 in the region between adjacent pairs of NOR memory strings. Furthermore, in some embodiments, cavities or air gaps 315 may be further employed to segment the ferroelectric gate dielectric layer 26, thereby isolating the ferroelectric gate dielectric layer for each pair of NOR memory strings. FIG. 12 is a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings in another embodiment of the present invention, in which the ferroelectric transistors are isolated from each other by air gap cavities. For ease of illustration, similar elements in FIGS. 11 and 12 are numbered with similar reference numerals. Referring to FIG. 12, a memory structure 400 is formed in substantially the same manner as the memory structure 300 of FIG. 11 and includes air gaps or air gap cavities 315 between adjacent pairs of NOR memory strings. In the memory structure 400, the formation of the air gap cavities 315 provides access for further etching away exposed sidewalls of the oxide semiconductor channel 25. In some embodiments, the air gap 315 is further used to etch away the exposed sidewalls of the ferroelectric gate dielectric layer 26. In some embodiments, the oxide semiconductor channel sidewalls and the ferroelectric gate dielectric layer sidewalls are etched or removed by wet etching or isotropic dry etching. The etching process for the oxide semiconductor channel sidewalls and the ferroelectric gate dielectric layer sidewalls may be selective to the bitline conductor layers 16a, 16b so that the bitline conductor layers 16a, 16b are minimally affected by the etching process. After the etching process, the oxide semiconductor channel region and the ferroelectric gate dielectric layer disposed between adjacent pairs of bitline conductors 16b, 16a are removed, as indicated by the dashed circle 355. As a result, the oxide semiconductor channel 25 and the ferroelectric gate dielectric layer 26 are isolated from each pair of NOR memory strings in the active stack 24.Such isolation is beneficial not only for reducing parasitic capacitance but also for eliminating interference between adjacent pairs (i.e., in the Z direction) of NOR memory strings in the active stack 24. In embodiments of the present disclosure, the air gap cavity can be used to remove or segment only the oxide semiconductor channel 25, leaving the ferroelectric gate dielectric layer 26 as a continuous layer.

[0107] 11, an air gap liner layer may be deposited to seal surfaces exposed by the air gap 315. In particular, the air gap liner layer may be applied to seal the exposed conductive material forming the common bit lines 16a and 16b, the exposed surface of the oxide semiconductor channel region, and the exposed surface of the ferroelectric gate dielectric layer 26 within the air gap cavity 315. In some embodiments, the air gap liner layer may be a dielectric material such as silicon nitride or silicon oxide.

[0108] In some embodiments, the memory structures 300, 400 of Figures 11 and 12 can be formed using sacrificial layers instead of the insulating layers 17a, 17b, which can be replaced with cavities or air gaps in subsequent processing steps. In this case, the memory structure is formed with a cavity or air gap between each pair of source and bit lines. In this manner, parasitic capacitance between adjacent source and bit line conductors is reduced. When the sacrificial layers are replaced with cavities, the oxide semiconductor channel 25 and ferroelectric gate dielectric layer 26 are maintained to form the channel region and gate dielectric of the ferroelectric storage transistor. In some embodiments, an air gap liner layer can be applied to seal the exposed surfaces of the air gap cavities.

[0109] In the above-described embodiments, the ferroelectric storage transistors in the three-dimensional array of NOR memory strings use an oxide semiconductor material to form their channel regions. In yet other embodiments of the present invention, the NOR memory strings can be formed using a polysilicon material for the channel regions. That is, the oxide semiconductor channel region 25 in any of the above embodiments can be replaced with a polysilicon channel. In that case, an interfacial dielectric layer is added between the polysilicon channel region and the ferroelectric gate dielectric layer. In one embodiment, the interfacial dielectric layer is a silicon oxide layer (SiO2), a silicon nitride layer (SiN), or an aluminum oxide layer.

[0110] In some embodiments, the source and drain layers can each be formed using a conductive layer (e.g., metal) with or without a heavily doped polysilicon layer as the source or drain region. In one embodiment, the polysilicon channel is a heavily doped N-type layer to form a junctionless channel. The heavily doped N-type channel region, like the oxide semiconductor channel, forms a depletion-mode ferroelectric transistor. In one embodiment, the polysilicon channel is about 2-5×10 18 cm -3 The heavily doped N-type channel region allows direct contact with the metal conductors that form the source and drain layers, eliminating the need for polysilicon source / drain layers.

[0111] In another aspect of the present disclosure, air gap cavities can be applied to memory structures to isolate individual NOR memory strings within an active stack. FIG. 13 illustrates a cross-sectional view of a portion of a memory structure including a three-dimensional array of NOR memory strings, in which the ferroelectric transistors are isolated by air gap cavities, according to another embodiment of the present invention. For ease of illustration, similar elements in FIGS. 1, 3, and 13 are labeled with similar reference numerals. Referring to FIG. 13, a memory structure including a three-dimensional array of NOR memory strings of ferroelectric storage transistors formed on the upper side of a semiconductor substrate (not shown in FIG. 13) is shown. The memory structure 500 is constructed using alternating conductive layers as common bit lines and common source lines. Therefore, as in the previously described embodiments, adjacent pairs of NOR memory strings do not share a common source line. Thus, the memory structure 500 includes an active stack formed by individual NOR memory strings 11-0 through 11-7, each with its own common bit line 16 and common source line 18 separated from each other by an insulating layer 17. In this embodiment, each NOR memory string is formed adjacent to a respective oxide semiconductor channel region 25 and ferroelectric gate dielectric layer 26. A pair of active stacks of NOR memory strings 24 bordering the same narrow trench 22 share a gate conductor 28. Each active stack 24 includes a ferroelectric storage transistor formed on both sides of the stack. When the LWL structures are staggered in the Y direction, adjacent narrow trenches 22 have storage transistors formed offset from each other in the Y direction, so that an active stack 24 does not include a storage transistor formed directly across the active stack in the X direction. The local word line structures formed in each trench 22 are insulated from each other by a dielectric material 23.

[0112] In the memory structure 500, each active layer, e.g., 11-0 through 11-7, includes a common bit line (first conductive layer 16) and a common source line (second conductive layer 18) separated by an insulating layer 17 to form a NOR memory string. In embodiments of the present disclosure, each NOR memory string is separated from other NOR memory strings in the Z direction by an air gap or air gap cavity 415. In this manner, the air gap cavity 415 insulates adjacent ferroelectric storage transistors in each active stack of the memory structure from each other. The three-dimensional array of NOR memory strings may include a bottom insulating layer 405 formed at the bottom of the memory array to insulate the conductive layer 18 from the semiconductor substrate. The three-dimensional array of NOR memory strings may further include a top insulating layer 425 formed over the three-dimensional array to insulate the memory array from conductive connectors formed over the memory array.

[0113] The memory structure 500 is formed in substantially the same manner as the memory structure 300 of FIG. 11 and includes air gaps or cavities for isolating the NOR memory strings. In some embodiments, the air gaps 415 in the memory structure 500 can be formed by replacing portions of the insulating layers with air gap sacrificial layers during a multilayer sequential deposition process such as that shown in FIG. 9A . For example, in the multilayer structure of FIG. 9A , all layers of the insulating dielectric layer 140, except for the bottom insulating dielectric layer, can be replaced with air gap sacrificial layers. Then, after the formation of local word line structures in the trenches 22, e.g., after the process of FIG. 9N in which the memory structure 500 including the oxide semiconductor channel 25, the ferroelectric gate dielectric layer 26, and the gate electrode 28 is formed, the air gap sacrificial layers can be etched away, e.g., through one or more shafts formed in the narrow trenches 22 at designated locations. The air gap sacrificial layers can be etched using isotropic dry etching, wet etching, or, in the case of a carbon sacrificial layer, ashing. Local word line structures and dielectric material 23 formed in trenches 22 between the active stacks 24 support the active stacks 24. The air gap sacrificial layer along the length of the NOR memory string in the Y direction is etched away to form elongated air gap cavities 415 bounded by adjacent bit line / source line conductors. Furthermore, in this embodiment, the air gap cavities 415 serve as access means for further etching away the exposed sidewalls of the oxide semiconductor channel 25 and the ferroelectric gate dielectric layer 26. In this manner, the oxide semiconductor channel 26 and the ferroelectric gate dielectric layer 26 are isolated for each NOR memory string. Thus formed, the memory structure 500 includes periodic air gaps 415 formed in the array between each adjacent bit line 16 and source line 18 of adjacent NOR memory strings in the active stack. The periodic air gaps 415 have a low dielectric constant, which has the advantage of reducing parasitic capacitance between the bit lines and source lines of adjacent NOR memory strings (in the Z direction) in the active stack.Additionally, segmenting the oxide semiconductor channel and ferroelectric gate insulating layer into each NOR memory string using air gap cavities 415 further reduces parasitic capacitance and minimizes interference (i.e., in the Z direction) between adjacent NOR memory strings in the active stack 24. In some embodiments, an air gap liner layer can be applied to seal the exposed surfaces of the air gap cavities.

[0114] In this detailed description, process steps described in one embodiment can be used in another embodiment even if not explicitly described in another embodiment. When a method including two or more defined steps is referred to herein, the defined steps can be performed in any order or simultaneously, unless the context dictates or specific instructions are provided otherwise herein. Furthermore, unless the context dictates or specific instructions are provided otherwise, the method can also include one or more other steps performed before any defined step, between two defined steps, or after all defined steps.

[0115] In this detailed description, various embodiments or examples of the present invention can be embodied in various forms, such as processes, devices, systems, and compositions of matter. A detailed description of one or more embodiments of the present invention is provided above, along with accompanying figures that illustrate the principles of the present invention. While the present invention has been described in connection with such embodiments, the present invention is not limited to any particular embodiment. Various modifications and variations are possible within the scope of the present invention. The scope of the present invention is limited only by the appended claims, and the present invention encompasses various alternatives, modifications, and equivalents. Numerous specific details are described herein to provide a thorough understanding of the present invention. These details are provided for illustrative purposes, and the present invention may be practiced according to the claims without some or all of these specific details. For the purposes of clarity, technical matters known in the art related to the present invention have not been described in detail so as not to unnecessarily obscure the present invention. The present invention is defined by the appended claims.

Claims

1. A three-dimensional memory structure formed on a planar surface of a semiconductor substrate, comprising: a plurality of stacks of thin-film ferroelectric field effect transistors (FeFETs) configured as a plurality of stacks of NOR memory strings extending along a first direction generally parallel to the plane of the semiconductor substrate; Each stack of the NOR memory strings is stacked along a second direction substantially perpendicular to the plane; the thin-film ferroelectric field effect transistors (FeFETs) of each of the NOR memory strings share a common source layer and a common drain layer extending along the first direction; (i) each stack of NOR memory strings includes a plurality of memory string pairs stacked along the second direction, each memory string pair being insulated from other memory string pairs by a first insulating layer; (ii) each of the memory string pairs includes a first common drain layer, a first common source layer, and a second common drain layer, each layer spaced apart from one another in the second direction by a second insulating layer; (iii) each of the memory string pairs is composed of a first NOR memory string formed by the first common drain layer and the first common source layer, and a second NOR memory string formed by the second common drain layer and the first common source layer; (iv) a semiconductor layer is provided adjacent to each stack of the NOR memory string and in contact with the common source layer and the common drain layer of each stack, and a channel region for the thin-film ferroelectric field effect transistor (FeFET) of each NOR memory string is formed by the semiconductor layer provided between the common source layer and the common drain layer adjacent to each other in the second direction; (v) a ferroelectric gate dielectric layer disposed adjacent to the semiconductor layer and along the second direction; (vi) a plurality of conductors are disposed adjacent to the ferroelectric gate dielectric layer between adjacent stacks of the NOR memory strings and along the second direction, each conductor functioning as a common gate electrode for each of the thin film ferroelectric field effect transistors (FeFETs) of the NOR memory strings of the adjacent stacks.

2. 2. The memory structure of claim 1, The memory structure wherein the ferroelectric gate dielectric layer includes a ferroelectric polarization layer disposed as a continuous layer adjacent each of the conductors in the second direction.

3. 2. The memory structure of claim 1, the semiconductor layer includes a doped N-type polysilicon layer; each said thin-film ferroelectric field effect transistor (FeFET) comprising a depletion mode transistor; The memory structure further includes an interfacial dielectric layer disposed between the N-type polysilicon layer and the ferroelectric gate dielectric layer.

4. 4. The memory structure of claim 3, The memory structure, wherein the interfacial dielectric layer comprises one or more of a silicon nitride layer and an aluminum oxide layer.

5. 2. The memory structure of claim 1, The memory structure, wherein the semiconductor layer comprises an oxide semiconductor layer.

6. 6. The memory structure of claim 5, The memory structure, wherein the oxide semiconductor layer comprises one of an indium zinc oxide (IZO) layer and an indium gallium zinc oxide (IGZO) layer.

7. 6. The memory structure of claim 5, The memory structure, wherein the ferroelectric gate dielectric layer is in substantially direct contact with the oxide semiconductor layer without an interfacial dielectric layer.

8. 2. The memory structure of claim 1, The memory structure, wherein the semiconductor layer is provided as a continuous layer along the sidewall of each stack of the NOR memory string.

9. 9. The memory structure of claim 8, The memory structure, wherein the semiconductor layer includes a continuous layer formed on opposing sidewalls of adjacent stacks of the NOR memory string.

10. 10. The memory structure of claim 9, the NOR memory strings are arranged in rows of the NOR memory strings along a third direction that is substantially orthogonal to both the first direction and the second direction; the semiconductor layer associated with a first set of the conductors functioning as the common gate electrode between adjacent stacks of the NOR memory strings is spaced apart in the third direction from the semiconductor layer associated with another set of the conductors functioning as the common gate electrode between other adjacent stacks of the NOR memory strings.

11. 2. The memory structure of claim 1, the semiconductor layer and the ferroelectric gate dielectric layer are formed adjacent to each of the conductors between adjacent stacks; The memory structure, wherein the semiconductor layer is insulated in the first direction from the semiconductor layer associated with other conductors disposed between the stacks.

12. 2. The memory structure of claim 1, The memory structure wherein the first insulating layer includes an air gap cavity.

13. 13. The memory structure of claim 12, the air gap cavity extends to the ferroelectric gate dielectric layer of the thin-film ferroelectric field effect transistor (FeFET) in the stack of the NOR memory string; The semiconductor layer is disposed adjacent only to each pair of NOR memory strings in the stack and is segmented by the air gap cavity between adjacent pairs of NOR memory strings.

14. 14. The memory structure of claim 13, the air gap cavity extends to the conductor forming the common gate electrode of the thin film ferroelectric field effect transistors (FeFETs) in the stack of NOR memory strings; the semiconductor layer and the ferroelectric gate dielectric layer are provided adjacent only to each pair of memory strings in the stack and are segmented by the air gap cavity between adjacent pairs of NOR memory strings.

15. 13. The memory structure of claim 12, The memory structure wherein the second insulating layer includes an air gap cavity.

16. 13. A memory structure according to claim 1 or 12, comprising: the first insulating layer has a first dimension in the second direction; the second insulating layer has a second dimension in the second direction; The memory structure, wherein the second dimension is a channel length of the thin film ferroelectric field effect transistor (FeFET).

17. 17. The memory structure of claim 16, The memory structure, wherein the first dimension of the first insulating layer is smaller than the second dimension of the second insulating layer.

18. 17. The memory structure of claim 16, the first dimension of the first insulating layer is 30 nm; The memory structure, wherein the second dimension of the second insulating layer is between 30 and 80 nm.

19. 2. The memory structure of claim 1, The memory structure, wherein the common source layer and the common drain layer each include a metal layer.

20. 20. The memory structure of claim 19, the semiconductor layer associated with the thin-film ferroelectric field effect transistor (FeFET) of each of the NOR memory strings is connected to the metal layer that forms the common source layer and the common drain layer, providing a junctionless channel region for each of the thin-film ferroelectric field effect transistors (FeFETs).

21. 20. The memory structure of claim 19, The memory structure, wherein the metal layer comprises one or more of molybdenum, titanium, tungsten, lanthanum, tantalum, ruthenium, any suicide thereof, any nitride thereof, and any combination thereof.

22. 2. The memory structure of claim 1, The memory structure, wherein the common drain layer of each of the NOR memory strings functions as a common bit line for each of the NOR memory strings.

23. 2. The memory structure of claim 1, A memory structure wherein each of the conductors comprises a titanium nitride layer.

24. 24. The memory structure of claim 23, A memory structure wherein each of the conductors includes a titanium nitride layer formed adjacent to the ferroelectric gate dielectric layer and a tungsten layer formed adjacent to the titanium nitride layer.

25. 2. The memory structure of claim 1, The memory structure wherein the ferroelectric gate dielectric layer comprises a doped hafnium oxide layer.

26. 26. The memory structure of claim 25, 10. A memory structure comprising: a doped hafnium oxide layer comprising one or more of zirconium-doped hafnium oxide (HZO), silicon-doped hafnium oxide (HSO), aluminum-zirconium-doped hafnium oxide (HfZrAlO), aluminum-doped hafnium oxide (HfO2:Al), lanthanum-doped hafnium oxide (HfO2:La), hafnium zirconium oxynitride (HfZrON), hafnium zirconium aluminum oxide (HfZrAlO), and any hafnium oxide containing zirconium impurities.

27. 2. The memory structure of claim 1, each said thin-film ferroelectric field effect transistor (FeFET) is electrically placed in a first polarization state by applying a first voltage to both said common source layer and said common drain layer and applying a second voltage to the associated said common gate electrode; each said thin-film ferroelectric field effect transistor (FeFET) is electrically placed in a second polarization state by applying a third voltage to said common drain layer, a fourth voltage different from said third voltage to said common source layer, and a fifth voltage to an associated said common gate electrode.

28. 2. The memory structure of claim 1, each said thin-film ferroelectric field effect transistor (FeFET) being electrically placed in a first polarization state by applying a first voltage to both said common source layer and said common drain layer and applying at least a second voltage to an associated said common gate electrode; 1. A memory structure wherein each of the thin-film ferroelectric field effect transistors (FeFETs) is electrically placed in two or more polarization states by applying voltages to the common drain layer, the common source layer, and the associated common gate electrode, the voltage ranges being different for each of the two or more polarization states.

29. 29. The memory structure of claim 28, The two or more polarization states comprise a range of analog states.

30. 28. The memory structure of claim 27, the thin-film ferroelectric field effect transistors (FeFETs) formed in the second direction columns in each stack of the NOR memory strings are grouped to form a page of memory cells; The page of memory cells are together placed in the first polarization state by applying the first voltage to the common source layer and the common drain layer and the second voltage to the common gate electrode.

31. 28. The memory structure of claim 27, the common source layer of the NOR memory string is electrically floating; A memory structure wherein the common source layer is biased to a given voltage during a precharge period and is then left floating.

32. 2. The memory structure of claim 1, A memory structure, wherein each stack of the NOR memory string includes the thin-film ferroelectric field effect transistor (FeFET) formed on opposite sidewalls of the stack.

33. 2. The memory structure of claim 1, The memory structure, wherein circuitry for supporting memory operations is formed in the planar surface of the semiconductor substrate beneath the plurality of stacks of thin-film ferroelectric field effect transistors (FeFETs).

34. 34. The memory structure of claim 33, A memory structure wherein the circuitry for supporting memory operations includes both analog and digital circuitry.

35. 34. The memory structure of claim 33, A memory structure, wherein the circuitry for supporting memory operations performs erase, program, or read operations on the plurality of stacks of thin-film ferroelectric field effect transistors (FeFETs) in response to erase, program, or read commands provided to the memory structure.

36. 34. The memory structure of claim 33, further comprising a layer of interconnect conductors formed above and electrically connected to the NOR memory strings and the circuitry for supporting memory operations; The memory structure, wherein the layer of interconnect conductors is provided for routing control and data signals between the NOR memory strings and the circuitry for supporting memory operations.

37. 37. The memory structure of claim 36, 1. A memory structure, wherein the circuits for supporting memory operations include two or more of word line driver circuits, bit line driver circuits, input / output driver circuits, address decoders, sense amplifiers, voltage sources for generating operating voltages for memory operations, latches, registers, other memory elements, and a state machine for managing memory operations in the thin film ferroelectric field effect transistors (FeFETs) of the NOR memory strings.

38. 36. The memory structure of claim 35, A memory structure wherein the circuitry for supporting memory operations is coupled to a memory controller formed on a separate semiconductor substrate and receives the command and data signals from the memory controller.

39. 2. The memory structure of claim 1, A memory structure wherein each of the thin film ferroelectric field effect transistors (FeFETs) has a data retention time of greater than 1 hour and a program / erase cycle endurance of greater than 108 cycles.

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