Semiconductor device

Abstract

To provide a semiconductor device in which the damage of a diode is suppressed.SOLUTION: A semiconductor device 100 includes a semiconductor substrate 10, and an ESD protection circuit 50, an internal circuit 52, an input-output terminal Ts, and power source terminals T1 and T2 on the semiconductor substrate. The ESD protection circuit includes diodes D1 and D2 and an ESD protection element 54. The diode D1 has a cathode connected to the power source terminal T1 and an anode connected to the input-output terminal. The diode D2 has a cathode connected to the input-output terminal Ts and an anode connected to the power source terminal T2. The ESD protection element is connected in parallel to the diodes D1 and D2 between the power source terminals and includes transistors F1 and F2 that are NMOSFET. A transistor F1 has a drain connected to the power source terminal T1 and a source and a gate connected together. A transistor F2 has a drain connected to the source of the transistor F1, has a source connected to the power source terminal T2, and has the source and a gate connected together.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] It is known that a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor is provided with a protection circuit to protect the circuit from surges such as electrostatic discharge (ESD).It is also known that the protection circuit is provided within a guard ring (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-177246 Summary of the Invention [Problem to be solved by the invention]

[0004] When an ESD protection circuit uses a diode and an ESD protection element connected in parallel with the diode, the diode may be destroyed by an ESD surge.

[0005] The present disclosure provides a semiconductor device that can suppress breakdown of a diode. [Means for solving the problem]

[0006] According to an embodiment of the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first power supply terminal provided on the semiconductor substrate, a second power supply terminal provided on the semiconductor substrate, an input / output terminal provided on the semiconductor substrate, a wiring connected to the second power supply terminal, a first guard ring provided in the semiconductor substrate at a peripheral portion of the semiconductor substrate, the first conductivity type and connected to the first power supply terminal, a second guard ring provided in the semiconductor substrate, the first conductivity type and connected to the first guard ring, a well region provided in the semiconductor substrate, surrounded by the second guard ring, and of a second conductivity type different from the first conductivity type, and a gate electrode provided in the well region. a first diode having one end connected to the first power supply terminal and the other end connected to the input / output terminal; a second diode provided in the well region and having one end connected to the input / output terminal and the other end connected to the second power supply terminal; and a protection element provided on the semiconductor substrate and connected in parallel to the first diode and the second diode between the first power supply terminal and the second power supply terminal, wherein a first contact connected to the first power supply terminal is not connected to a portion of the second guard ring that surrounds the second diode, and the wiring is connected to the second diode at a location in the half of the well region surrounded by the surrounding portion on the opposite side to the first guard ring. [Effects of the Invention]

[0007] According to the present disclosure, breakdown of the diode can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a schematic plan view of the ESD protection circuit in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is an enlarged plan view of the vicinity of the diode in FIG. [Figure 5] FIG. 5 is an enlarged plan view of the vicinity of the diode in FIG. [Figure 6] FIG. 6 is an enlarged plan view of the vicinity of the diode D2 in FIGS. [Figure 7] FIG. 7 is a cross-sectional view taken along line AA in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along the line BB in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line CC in FIG. [Figure 10] FIG. 10 is a cross-sectional view of the diode D2 of the semiconductor device according to the first comparative example. [Figure 11] FIG. 11 is a plan view of a diode of a semiconductor device according to a second comparative example. [Figure 12] FIG. 12 is a cross-sectional view of a diode D2 of a semiconductor device according to a second comparative example. [Figure 13] FIG. 13 is a cross-sectional view of the diode D2 of the semiconductor device according to the first embodiment. [Figure 14] 14(a) and 14(b) are diagrams showing voltage and current versus time in the first comparative example and the first embodiment, respectively. [Figure 15] 15(a) to 15(c) are circuit diagrams illustrating the flow of current in the first comparative example. [Figure 16] 16(a) to 16(c) are cross-sectional views showing the flow of current in the first comparative example. [Figure 17] FIG. 17 is a diagram showing ESD resistance versus voltage in the first embodiment and the first comparative example. [Figure 18] FIG. 18 is a block diagram of a semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is an enlarged plan view of the vicinity of the diode in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0010] (First embodiment) Fig. 1 is a block diagram of a semiconductor device according to a first embodiment. As shown in Fig. 1, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 10, an ESD protection circuit 50, an internal circuit 52, an input / output terminal Ts, and power supply terminals T1 and T2. The ESD protection circuit 50, the internal circuit 52, the input / output terminal Ts, and the power supply terminals T1 and T2 are provided on the semiconductor substrate 10.

[0011] The ESD protection circuit 50 includes diodes D1 and D2 and an ESD protection element 54. The cathode (one end) of the diode D1 (first diode) is electrically connected to the power supply terminal T1, and the anode (the other end) of the diode D1 is electrically connected to the input / output terminal Ts. The cathode (one end) of the diode D2 (second diode) is electrically connected to the input / output terminal Ts, and the anode (the other end) of the diode D2 is electrically connected to the power supply terminal T2.

[0012] The ESD protection element 54 is connected in parallel to the diodes D1 and D2 between the power supply terminals T1 and T2. The ESD protection element 54 is a FET-type ESD protection element and includes transistors F1 and F2. The transistors F1 and F2 are NMOSFETs (Field Effect Transistors). The drain of the transistor F1 is electrically connected to the power supply terminal T1, and the source and gate of the transistor F1 are electrically connected. The drain of the transistor F2 is electrically connected to the source of the transistor F1, the source of the transistor F2 is electrically connected to the power supply terminal T2, and the source and gate of the transistor F2 are electrically connected.

[0013] Although an example in which two transistors F1 and F2 are connected in series as the ESD protection element 54 has been described, the number of transistors in the ESD protection element 54 may be one, or three or more transistors may be connected in series.

[0014] The input / output terminal Ts is a terminal through which signals or power are input or output. The power supply terminals T1 and T2 are terminals between which a power supply voltage is supplied. The power supply terminal T1 (first power supply terminal) is supplied with, for example, a voltage VDD. The power supply terminal T2 (second power supply terminal) is supplied with, for example, a voltage VSS. The voltage VSS is, for example, a ground voltage, and the voltage VDD is a voltage higher than the voltage VSS.

[0015] Voltages VDD and VSS are supplied as power supply voltages to the internal circuit 52. Using the voltages VDD and VSS as power supplies, the internal circuit 52 processes signals or power input to the input / output terminal Ts, or outputs the processed signals or power to the input / output terminal Ts. The internal circuit 52 is, for example, a control circuit that controls a battery or the like, or a power conversion circuit.

[0016] The ESD protection circuit 50 is a circuit that protects the internal circuit 52 when a surge such as ESD is applied to the input / output terminal Ts. When a positive surge is applied to the input / output terminal Ts, a current flows from the input / output terminal Ts to the power supply terminal T1 via the diode D1. This prevents the positive surge from being applied to the internal circuit 52. When a negative surge is applied to the input / output terminal Ts, a current flows from the power supply terminal T2 to the input / output terminal Ts via the diode D2. This prevents the negative surge from being applied to the internal circuit 52.

[0017] However, the reverse voltage ESD tolerance of diodes D1 and D2 is low. If diodes D1 and D2 are enlarged to improve their ESD tolerance, the area of ​​ESD protection circuit 50 would increase. When a negative surge is applied to input / output terminal Ts, current flows from power supply terminal T1 to input / output terminal Ts via ESD protection element 54 and diode D2, as indicated by arrow 51. This prevents a reverse voltage from being applied to diode D1, which could cause breakdown of diode D1.

[0018] Transistors F1 and F2 are off because their sources and gates are shorted. The drain breakdown voltage of transistors F1 and F2 is set to be equal to or greater than voltage VDD-VSS. Therefore, even if voltage VDD-VSS is applied to ESD protection element 54, no current flows through ESD protection element 54. When a negative voltage is applied to input / output terminal Ts and exceeds the breakdown voltage of transistors F1 and F2, current flows through ESD protection element 54 as indicated by arrow 51.

[0019] 2 is a block diagram of a semiconductor device according to the first embodiment. As shown in FIG. 2, multiple internal circuits 52 are provided on a semiconductor substrate 10, and each internal circuit 52 is provided with an input / output terminal Ts. Diodes D1 and D2 are provided for each input / output terminal Ts. An ESD protection element 54 can be provided in common for multiple input / output terminals Ts. This allows the area of ​​the ESD protection circuit 50 to be reduced.

[0020] 3 is a schematic plan view of the ESD protection circuit in the semiconductor device according to the first embodiment. The thickness direction of the semiconductor substrate 10 is the Z direction, the extension direction of the sides of the semiconductor substrate 10 is the X direction, and the direction perpendicular to the X and Y directions is the Y direction. The guard rings 14a and 14b are shown using cross-hatching, and the wirings 26a and 26b are shown using dashed lines.

[0021] The ESD protection circuit 50 is provided near the input / output terminal Ts. The input / output terminal Ts is provided on the periphery of the chip-shaped semiconductor substrate 10. Therefore, the ESD protection circuit 50 is also provided on the periphery of the semiconductor substrate 10.

[0022] For ESD protection, guard rings 14a and 14b are provided on the semiconductor substrate 10. Guard ring 14a (second guard ring) is a guard ring that surrounds diodes D1 and D2 and transistors F1 and F2. Guard ring 14b (first guard ring) is a chip guard ring that is provided on the periphery of the chip-shaped semiconductor substrate 10. Guard rings 14a and 14b are formed from N-type diffusion regions in the semiconductor substrate 10, and guard rings 14a and 14b are in contact with each other.

[0023] The wiring 26a supplies a voltage VDD to the cathode of the diode D1 and the drain of the transistor F1, and the wiring 26b supplies a voltage VSS to the anode of the diode D2 and the source of the transistor F2.

[0024] 4 and 5 are enlarged plan views of the diode and its vicinity in FIG. 3. FIG. 4 is a plan view mainly showing guard rings 14a and 14b, N-type diffusion regions 15, 16, and 17, and P-type diffusion regions 18 and 19. Guard rings 14a and 14b, N-type diffusion region 16, and P-type diffusion region 18 are shown using cross-hatching. N-type diffusion regions 15, 17, and P-type diffusion region 19 are shown using dashed lines. FIG. 5 is a plan view mainly showing guard rings 14a and 14b, wiring 26a to 26d and 28, pad 30, and contact wiring 27 and 29. Wiring 26a to 26d are shown using cross-hatching, guard rings 14a and 14b are shown using dashed lines, wiring 28 is shown using a thick dashed line, and pad 30 is shown using a thick solid line.

[0025] Figure 6 is an enlarged plan view of the vicinity of diode D2 in Figures 4 and 5. Figures 7 to 9 are cross-sectional views taken along lines AA, BB, and CC in Figure 6, respectively. Figure 6 mainly shows guard rings 14a and 14b, N-type diffusion regions 15 and 17, P-type diffusion region 19, contact wiring 25, and wirings 26a, 26b, and 26d. In Figure 6, wirings 26a to 26d and guard rings 14a and 14b are shown using cross-hatching, and N-type diffusion regions 15 and 17 and P-type diffusion region 19 are shown using dashed lines.

[0026] 4 and 7 to 9, guard rings 14a and 14b are provided in a semiconductor substrate 10. The semiconductor substrate 10 is N-type, and the guard rings 14a and 14b are N-type diffusion layers. The impurity concentrations in the guard rings 14a and 14b are higher than the impurity concentration in the semiconductor substrate 10. The guard ring 14b is provided on the periphery of the semiconductor substrate 10. The guard rings 14a and 14b are provided in contact with each other.

[0027] A P-type well region 12 surrounded by a guard ring 14a is provided in a semiconductor substrate 10. A P-type diffusion region 18 and an N-type diffusion region 16 are provided in the well region 12. The P-type diffusion region 18 is provided so as to surround the N-type diffusion region 16. The P-type diffusion region 18 and the N-type diffusion region 16 face each other with the well region 12 interposed therebetween. The impurity concentrations of the P-type diffusion region 18 and the N-type diffusion region 16 are higher than the impurity concentrations of the well region 12.

[0028] An N-type diffusion region 15 is provided above guard rings 14a and 14b. The impurity concentration of N-type diffusion region 15 is higher than that of guard rings 14a and 14b. An N-type diffusion region 17 is provided above N-type diffusion region 16. The impurity concentration of N-type diffusion region 17 is higher than that of N-type diffusion region 16. A P-type diffusion region 19 is provided above P-type diffusion region 18. The impurity concentration of P-type diffusion region 19 is higher than that of P-type diffusion region 18. N-type diffusion regions 15, 17 and P-type diffusion region 19 are contact regions with contact wiring and may not be provided.

[0029] An element isolation oxide film 38 is provided on the upper surface of the semiconductor substrate 10. The N-type diffusion regions 15 and 17 and the P-type diffusion region 19 are surrounded by the element isolation oxide film 38. The element isolation oxide film 38 is a LOCOS (Local Oxidation of Silicon) film or an STI (Shallow Trench Isolation) film.

[0030] 5 to 8, an interlayer insulating film 21 is provided on a semiconductor substrate 10 and an element isolation oxide film 38. Wirings 26a to 26d are provided on the interlayer insulating film 21. A contact wiring 25 (also simply referred to as a contact) is provided to penetrate the interlayer insulating film 21. The wiring 26a is electrically connected to the N-type diffusion region 15 and the N-type diffusion region 17 of the diode D1 via the contact wiring 25. As a result, the guard rings 14a and 14b and the N-type diffusion region 16 of the diode D1 are electrically connected to the power supply terminal T1 via the wiring 26a.

[0031] The wiring 26b is electrically connected to the P-type diffusion region 19 of the diode D2 via the contact wiring 25. As a result, the P-type diffusion region 19 of the diode D2 is electrically connected to the power supply terminal T2 via the wiring 26b.

[0032] The wiring 26c is electrically connected to the P-type diffusion region 19 of the diode D1 via a contact wiring 25. The wiring 26d is electrically connected to the N-type diffusion region 17 of the diode D2 via a contact wiring 25.

[0033] The wirings 26a and 26d are drawn in the +Y direction from the N-type diffusion regions 16 of the diodes D1 and D2, respectively. The wirings 26c and 26b are drawn in the −Y direction from the P-type diffusion regions 18 of the diodes D1 and D2.

[0034] An interlayer insulating film 22 is provided on the interlayer insulating film 21 and the wirings 26a to 26d. A wiring 28 is provided on the interlayer insulating film 22. A contact wiring 27 is provided to penetrate the interlayer insulating film 22. The wiring 28 electrically connects the wirings 26b and 26c via the contact wiring 27. This electrically connects the P-type diffusion region 18 of the diode D1 and the N-type diffusion region 16 of the diode D2.

[0035] An interlayer insulating film 23 is provided on the interlayer insulating film 22 and the wiring 28. A pad 30 is provided on the interlayer insulating film 23. A contact wiring 29 is provided penetrating the interlayer insulating film 23. The pad 30 is electrically connected to the wiring 28 via the contact wiring 29. As described above, the pad 30 is electrically connected to the P-type diffusion region 18 of the diode D1 and the N-type diffusion region 16 of the diode D2. The pad 30 corresponds to the input / output terminal Ts.

[0036] The semiconductor substrate 10 is, for example, a silicon (Si) substrate. The impurities in the N-type region in the semiconductor substrate 10 are donor elements such as phosphorus (P) or arsenic (As). The impurities in the P-type region in the semiconductor substrate 10 are acceptor elements such as boron (B) or aluminum (Al). The wirings 26a to 26d, 28, the pad 30, and the contact wirings 25, 27, and 29 are metal layers such as aluminum layers or copper layers. The element isolation oxide film 38 is, for example, a silicon oxide (SiO2) film.

[0037] The impurity concentration of the semiconductor substrate 10 is, for example, 1×10 14 ~1×10 15 cm -3 As an example, 5×10 14 cm -3 The impurity concentration of the well region 12 is, for example, 1×10 15 ~1×10 16 cm -3 As an example, 5×10 15 cm -3 The impurity concentration of the N-type diffusion region 16 and the P-type diffusion region 18 is, for example, 5×1016 ~5×10 17 cm -3 As an example, 1×10 17 cm -3 The impurity concentration of the N-type diffusion regions 15 and 17 and the P-type diffusion region 19 is, for example, 5×10 19 ~5×10 20 cm -3 As an example, 1×10 20 cm -3 is.

[0038] 9, a diode d2 is formed between the N-type diffusion region 16 and the P-type diffusion region 18 in the well region 12. The N-type diffusion region 16 corresponds to the cathode region, and the P-type diffusion region 18 corresponds to the anode region.

[0039] The main features of the first embodiment are, first, that the wiring 26a is not connected to the guard ring 14a but is electrically connected to the guard ring 14a via the guard ring 14b, and second, that the wiring 26b is drawn out in the −Y direction from the P-type diffusion region 18. The effects of these two features will be described below with reference to a comparative example.

[0040] (First Comparative Example) 10 is a cross-sectional view of diode D2 of a semiconductor device according to a first comparative example. As shown in FIG. 10, in the first comparative example, wiring 26a is connected to N-type diffusion region 15 of guard ring 14a via contact wiring 25. This applies voltage VDD to guard ring 14a. The direction in which wiring 26b is drawn from P-type diffusion region 18 is the -Y direction, which is the same as in the first embodiment.

[0041] When a negative surge is applied to the pad 30 (input / output terminal Ts), the potential of the N-type diffusion region 16 becomes lower than the potential of the semiconductor substrate 10. As a result, an NPN parasitic bipolar transistor Bp is formed, in which the N-type diffusion region 16 corresponds to the emitter, the well region 12 corresponds to the base, and the semiconductor substrate 10 corresponds to the collector. In FIG. 9, a diode d2 formed between the N-type diffusion region 16 and the P-type diffusion region 18 causes a current to flow to the well region 12 below the N-type diffusion region 16. This turns on the transistor Bp. A current flows from the semiconductor substrate 10 to the N-type diffusion region 16 via the transistor Bp.

[0042] As shown in FIGS. 4 and 5 , the wiring 26b is drawn from the P-type diffusion region 18 in the −Y direction. That is, of the contact wirings 25, the one closest to the −Y direction is electrically closest to the power supply terminal T2. As a result, a large current flows through the diode d2 formed in the well region 12 at a location in the −Y direction. This makes it easier for the transistor Bp formed in the −Y direction below the N-type diffusion region 16 to turn on. Although the semiconductor substrate 10 has high resistivity, when the distance between the guard ring 14a to which the voltage VDD is applied and the transistor Bp is short, the collector resistance Rc is low. As a result, the current flowing through the transistor Bp increases, which may destroy the diode D2.

[0043] (Second Comparative Example) Fig. 11 is a plan view of a diode of a semiconductor device according to a second comparative example. As shown in Fig. 11, in the second comparative example, wiring 26b is drawn out in the +Y direction from P-type diffusion region 18. Wiring 26a is not connected to guard ring 14a, but is electrically connected to guard ring 14a via guard ring 14b, as in the first embodiment.

[0044] FIG. 12 is a cross-sectional view of diode D2 of a semiconductor device according to a second comparative example. As shown in FIG. 12, in the second comparative example, wiring 26b is drawn out in the +Y direction from P-type diffusion region 18, as in FIG. 11. That is, of the contact wirings 25, the contact wiring 25 closest to the +Y direction is electrically closest to power supply terminal T2. Therefore, a large current flows through diode d2 formed in a portion of well region 12 in the +Y direction. Therefore, transistor Bp formed in a portion of N-type diffusion region 16 in the +Y direction is more likely to turn on. Because the distance between guard ring 14b, to which voltage VDD is applied, and transistor Bp is short, collector resistance Rc is low. Therefore, the current flowing through transistor Bp increases, which may destroy diode D2.

[0045] (Description of the First Embodiment)

[0046] Fig. 13 is a cross-sectional view of diode D2 of the semiconductor device according to the first embodiment. As shown in Fig. 13, in the first embodiment, wiring 26b is drawn out in the -Y direction from P-type diffusion region 18 as in Fig. 5. Therefore, as shown in Fig. 10 of the first comparative example, transistor Bp, which is easily turned on, is formed in a portion of well region 12 in the -Y direction.

[0047] The wiring 26a is not connected to the guard ring 14a, but is electrically connected to the guard ring 14a via the guard ring 14b. Therefore, the distance between the guard ring 14b, to which the voltage VDD is applied, and the transistor Bp is long. This results in a high collector resistance Rc. This reduces the current flowing through the transistor Bp, preventing breakdown of the diode D2.

[0048] (experiment) ESD protection circuits according to the first embodiment and the first comparative example were fabricated. A negative voltage pulse corresponding to an ESD surge was applied to the input / output terminal Ts and the power supply terminal T1, and the voltage of the power supply terminal T1 relative to the input / output terminal Ts and the current flowing from the power supply terminal T1 to the input / output terminal Ts were measured using the TLP measurement method (Transmission Line Pulsing Method).

[0049] 14(a) and 14(b) are diagrams showing voltage and current versus time in the first comparative example and the first embodiment, respectively. The horizontal axis represents time, with pulses applied for 100 ns from 0 ns to 100 ns. The vertical axis represents the voltage at power supply terminal T1 relative to input / output terminal Ts and the current flowing from power supply terminal T1 to input / output terminal Ts.

[0050] As shown in FIG. 14(a), four periods can be observed in the first comparative example. Period P1 is between 0 ns and 25 ns, and during period P1, the voltage and current increase. The voltage peaks at approximately 70 V. Period P2 is between 25 ns and 40 ns, and during period P2, the voltage saturates at approximately 40 V and the current saturates at approximately 1 A. Period P3 is between 40 ns and 100 ns, and during period P3, the voltage decreases and the current increases. Period P4 is after 100 ns, and during period P4, both the voltage and current decrease.

[0051] 14(b), in the first embodiment, period P3 is not observed, and period P2 is between 25 ns and 100 ns. In period P2, the voltage is saturated at about 40 V and the current is saturated at about 1 A. Thus, period P3 is observed in the first comparative example, but is not observed in the first embodiment.

[0052] 15(a) to 15(c) are circuit diagrams illustrating the flow of current in the first comparative example. 16(a) to 16(c) are cross-sectional views illustrating the flow of current in the first comparative example. The internal circuit 52 is not illustrated in FIGS. 15(a) to 15(c). 16(a) to 16(c) correspond to the CC cross-sectional view of FIG. 6. In FIGS. 16(a) to 16(c), a diode d2 is formed in the well region 12 between the P-type diffusion region 18 and the N-type diffusion region 16, and a parasitic transistor Bp is formed in the N-type diffusion region 16, the well region 12, and the semiconductor substrate 10.

[0053] During period P1, no current flows initially even as the voltage rises. The withstand voltage of transistors F1 and F2 is approximately 45 V. At time t1, when the voltage exceeds approximately 45 V, leakage current begins to flow through transistors F1 and F2. The leakage current triggers the snapback operation of transistors F1 and F2, turning them on at the end of period P1.

[0054] As a result, as shown in Figure 15(a), a current 60 flows from the power supply terminal T1 to the input / output terminal Ts via the transistors F1 and F2 and the diode D2. As shown in Figure 16(a), a current 64 flows in the forward direction of the diode d2 from the P-type diffusion region 18 to the N-type diffusion region 16.

[0055] Transistors F1 and F2 are designed to hold the voltage at approximately 40V. Therefore, the voltage saturates at 40V, and the current should also saturate. However, in the first comparative example, during period P3, the voltage drops sharply and the current increases sharply. This is a characteristic that transistors F1 and F2 alone do not exhibit.

[0056] As shown in FIG. 16(b), current 64 flows through diode d2, turning on transistor Bp. As a result, current 65 flows from guard ring 14a through semiconductor substrate 10 to transistor Bp. As shown in FIG. 15(b), current 61 flows from power supply terminal T1 through semiconductor substrate 10 to N-type diffusion region 16, which serves as the cathode of diode D2, without passing through transistors F1 and F2. As a result, during period P3, the voltage drops and the current increases.

[0057] As shown in FIG. 16(c), a large current flows through transistor Bp, causing diode D2 to break down near transistor Bp (dashed circle 66). As shown in FIG. 15(c), diode D2 breaks down at dashed circle 62. After period P4, a DC voltage was applied to ESD protection circuit 50 to check for breakdown. It was confirmed that the leakage current was large, and that ESD protection circuit 50 had broken down. When the location of the breakdown was investigated, it was found that diode D2 had broken down.

[0058] In the first embodiment, after the period P4, no leakage current was observed in the ESD protection circuit 50, and the ESD protection circuit 50 was not destroyed. In the first embodiment, since the period P3 was not observed, it is considered that the current caused by the transistor Bp being turned on, as shown in Figures 15(b) and 16(b), did not flow, and that the current 60 flowed via the transistors F1 and F2, as shown in Figures 15(a) and 15(a).

[0059] A negative surge was applied to the input / output terminal Ts for the first embodiment and the first comparative example, and the ESD tolerance of the man-machine model was measured. FIG. 17 is a diagram showing the ESD tolerance versus voltage for the first embodiment and the first comparative example. The dashed circle 68 indicates the point at which the ESD protection circuit 50 was destroyed. As shown in FIG. 17, in the first comparative example, the ESD current at which the ESD protection circuit 50 was destroyed was approximately 1.5 A. In the first embodiment, the ESD current at which the ESD protection circuit 50 was destroyed was approximately 3 A. Thus, in the first embodiment, the ESD tolerance was approximately twice as high as in the first comparative example.

[0060] According to the first embodiment, the contact wiring 25 (first contact) connected to the wiring 26a (first wiring) is not connected to the portion of the guard ring 14a surrounding the diode D2. The wiring 26b (second wiring) is connected to a location 12a (see FIG. 6) in the half of the well region 12 opposite the guard ring 14b. As a result, as shown in FIG. 13, the parasitic bipolar transistor Bp, through which current easily flows, is formed at the location 12a. This allows the distance between the parasitic bipolar transistor Bp and the guard ring 14b to be increased. This increases the collector resistance Rc, thereby suppressing the current flowing through the parasitic bipolar transistor Bp. This prevents the diode D2 from being destroyed. The wiring 26b is preferably connected to a location 12b in the half of the well region 12 opposite the guard ring 14b.

[0061] 6, L1 is the distance in the Y direction between position 13a in well region 12 that is closest to guard ring 14b and position 13b that is farthest from guard ring 14b. 13c is the line connecting positions in well region 12 where distance L2 in the Y direction from position 13a is 1 / 2 of distance L1. In this case, point 12a in the half of well region 12 on the opposite side from guard ring 14b is point 12a in well region 12 that is farther from guard ring 14b than line 13c.

[0062] A line 13d connects positions in well region 12 where distance L3 in the Y direction from position 13a is 3 / 4 of distance L1. In this case, point 12b of well region 12, which is the 1 / 4 of well region 12 opposite guard ring 14b, is a point in well region 12 farther from guard ring 14b than line 13d. Distance L1 is, for example, 60 μm to 180 μm, and is, for example, 120 μm.

[0063] The diode D2 includes N-type diffusion regions 16 and 17 (first region) and P-type diffusion regions 18 and 19 (second region). A contact wiring 25 (second contact) connects the P-type diffusion regions 18 and 19 to a wiring 26b. In this configuration, the portion of the contact wiring 25 that is electrically closest to the power supply terminal T2 is provided at the location 12a. As a result, in FIG. 13, a parasitic bipolar transistor Bp, through which current easily flows, is formed at the location 12a. This increases the distance between the parasitic bipolar transistor Bp and the guard ring 14b. This increases the collector resistance Rc, thereby suppressing the current flowing through the parasitic bipolar transistor Bp. It is more preferable that the portion of the contact wiring 25 that is electrically closest to the power supply terminal T2 is provided at the location 12b.

[0064] The portion of the contact wiring 25 that is electrically closest to the power supply terminal T2 is physically farthest from the guard ring 14b. As a result, the parasitic bipolar transistor Bp, through which current easily flows, is formed at a location far from the guard ring 14b, as shown in Figure 13. This allows the collector resistance Rc formed in the semiconductor substrate 10 to be increased, thereby suppressing the current flowing through the parasitic bipolar transistor Bp.

[0065] N-type diffusion regions 16 and 17 and P-type diffusion regions 18 and 19 extend in a direction intersecting the X-direction in which guard ring 14b extends. Contact wiring 25 is arranged in a direction intersecting the X-direction. In this configuration, parasitic bipolar transistor Bp is likely to be formed at a location far from guard ring 14b. Therefore, it is preferable to extend wiring 26b in a direction away from guard ring 14b.

[0066] At least a part of the contact wiring 25 connecting the P-type diffusion regions 18 and 19 with the wiring 26b is provided in a half or a quarter of the region far from the guard ring 14b of the P-type diffusion regions 18 and 19. As a result, the parasitic bipolar transistor Bp is formed in a location far from the guard ring 14b.

[0067] The ESD protection element 54 may be connected in parallel to the diodes D1 and D2 between the power supply terminals T1 and T2. If the ESD protection element 54 is a FET, it is preferable to connect the source to the power supply terminal T2 and the drain to the power supply terminal T2. This allows the hold voltage to be set by the drain withstand voltage. The gate may be supplied with a voltage that turns off the transistors F1 and F2 except when a negative surge is applied to the input / output terminal Ts. By electrically connecting the gate to the source, the drain withstand voltage can be set without preparing a voltage to be supplied to the gate. The ESD protection element 54 may also be a bipolar transistor. In this case, it is preferable to connect the emitter to the power supply terminal T2 and the collector to the power supply terminal T2. This allows the hold voltage to be set by the collector withstand voltage.

[0068] (Second embodiment) 18 is a block diagram of a semiconductor device according to the second embodiment. As shown in FIG. 18, in a semiconductor device 102 according to the second embodiment, diodes D1a and D1b are connected in series between a power supply terminal T1 and an input / output terminal Ts. By connecting diodes D1a and D1b in series as diode D1, the withstand voltage of diode D1 can be improved. At least one of diodes D1 and D2 may have a plurality of diodes connected in series.

[0069] Fig. 19 is an enlarged plan view of the diode and its vicinity in the second embodiment. Fig. 19 mainly shows the guard rings 14a and 14b and the wirings 26a to 26f. The wirings 26a to 26f are shown using cross-hatching, and the guard rings 14a and 14b are shown using dashed lines. In addition, the electrical connections between the diodes D1a, D1b, and D2 are shown using thick lines.

[0070] 19, diode D1b is farther from guard ring 14b than diode D1a. Wiring 26a connected to the cathode of diode D1a is extended in the −X direction, and wiring 26e connected to the anode of diode D1a is extended in the +X direction. Wiring 26e connected to the cathode of diode D1b is extended in the +X direction, and wiring 26f connected to the anode of diode D1b is extended in the −X direction. The anode of diode D1a and the cathode of diode D1b are electrically connected by wiring 26e.

[0071] The wiring 26d connected to the cathode of the diode D2 is drawn in the +Y direction, and the wiring 26b connected to the anode of the diode D2 is drawn in the -Y direction. The wiring 26f and 26d are electrically connected by the wiring 28 similar to that shown in FIG.

[0072] In the second embodiment, as in the first embodiment, the guard ring 14a is not connected to the wiring 26a, and the wiring 26b is drawn out in the −Y direction, thereby preventing the diode D2 from being damaged by a surge such as an ESD surge.

[0073] In the first and second embodiments, the voltage VDD (first power supply voltage) supplied to the power supply terminal T1 is higher than the voltage VSS (second power supply voltage) supplied to the power supply terminal T2. In this case, the first conductivity type of the semiconductor substrate 10, the guard rings 14a, 14b, and the N-type diffusion regions 15, 16, and 17 is N-type. The second conductivity type, which is different from the first conductivity type of the well region 12 and the P-type diffusion regions 18 and 19, is P-type. The forward direction of the diode D1 is from the input / output terminal Ts to the power supply terminal T1. The forward direction of the diode D3 is from the power supply terminal T2 to the input / output terminal Ts. The transistors F1 and F2 are NFETs.

[0074] Although the experimental results have been described assuming that the voltage VDD-VSS is 30 V, the voltage VDD-VSS may be lower than 40 V. For example, the voltage VDD-VSS is 5 V or higher, and 20 V or higher.

[0075] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0076] 10: Semiconductor substrate 12: Well area 12a, 12b: Locations 14a, 14b: Guard ring 15, 16, 17: N-type diffusion region 18, 19: P-type diffusion region 25, 27, 29: Contact wiring 26a, 23b, 26c, 26d, 26e, 26f, 28: Wiring 30: Pad 38: Element isolation oxide film 50:ESD protection circuit 52: Internal circuit 54: ESD protection element

Claims

1. a semiconductor substrate of a first conductivity type; a first power supply terminal provided on the semiconductor substrate; a second power supply terminal provided on the semiconductor substrate; an input / output terminal provided on the semiconductor substrate; a wiring connected to the second power supply terminal; a first guard ring provided in the semiconductor substrate at a peripheral portion of the semiconductor substrate, the first guard ring being of the first conductivity type and connected to the first power supply terminal; a second guard ring provided in the semiconductor substrate, the second guard ring being of the first conductivity type and connected to the first guard ring; a well region provided in the semiconductor substrate, surrounded by the second guard ring, and having a second conductivity type different from the first conductivity type; a first diode provided in the well region, one end of which is connected to the first power supply terminal and the other end of which is connected to the input / output terminal; a second diode provided in the well region, one end of which is connected to the input / output terminal and the other end of which is connected to the second power supply terminal; a protection element provided on the semiconductor substrate and connected in parallel to the first diode and the second diode between the first power supply terminal and the second power supply terminal; Equipped with a first contact connected to the first power supply terminal is not connected to a portion of the second guard ring that surrounds the second diode; the wiring is connected to the second diode at a location in one-half of the well region surrounded by the surrounding portion on the opposite side to the first guard ring; Semiconductor device.

2. The second diode is a first region of the first conductivity type provided in the well region; a second region of the second conductivity type provided in the well region and facing the first region with a portion of the well region interposed therebetween; Equipped with the semiconductor device includes a second contact that connects the second region and the wiring; 2. The semiconductor device according to claim 1, wherein the portion of the second contact that is electrically closest to the second power supply terminal is provided at the half position.

3. 3. The semiconductor device according to claim 2, wherein a portion of the second contact that is electrically closest to the second power supply terminal is farthest from the first guard ring.

4. the first region and the second region are provided to extend in a direction intersecting the direction in which the first guard ring extends, The second region is provided to extend in the intersecting direction, 4. The semiconductor device according to claim 2, wherein the second contacts are arranged in the intersecting direction.

5. The semiconductor device according to claim 1 , wherein the protection element comprises a transistor.

6. 4. The semiconductor device according to claim 1, wherein the protection element comprises a FET having a source connected to the second power supply terminal and a drain connected to the first power supply terminal.

7. a voltage supplied to the first power supply terminal is higher than a voltage supplied to the second power supply terminal; the first conductivity type is N-type, the second conductivity type is P-type, the one end and the other end of the first diode are a cathode and an anode, respectively; the one end and the other end of the second diode are a cathode and an anode, respectively; The semiconductor device according to claim 1 .

8. The semiconductor device according to claim 1 , wherein at least one of the first diode and the second diode is a plurality of diodes connected in series.

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