Method for manufacturing semiconductor device and semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device and the semiconductor device capable of suppressing defect generation.SOLUTION: The method for manufacturing a semiconductor device includes: a semiconductor layer forming step for forming a semiconductor layer on a support substrate; a gate insulating film forming step for forming a gate insulating film on a side of the semiconductor layer opposite to the support substrate; a gate electrode layer and insulating film forming step for forming, in this order, a gate electrode layer and an insulating film on a side of the gate insulating film opposite to the side where the support substrate is formed; a photoresist forming step for patterning a photoresist on a side of the insulating film opposite to the support substrate; a gate electrode and first interlayer insulating film forming step for simultaneously patterning the gate electrode layer and the insulating film using the photoresist as a mask to form a gate electrode and a first interlayer insulating film; and a cleaning step for removing the photoresist in this order.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The following disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Patent Documents 1 and 2 disclose techniques relating to methods for manufacturing semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-093235 [Patent Document 2] Japanese Patent Application Publication No. 7-193038 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress defect generation. [Means for solving the problem]

[0005] (1) One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising, in this order: a semiconductor layer forming step of forming a semiconductor layer on a support substrate; a gate insulating film forming step of forming a gate insulating film on the semiconductor layer opposite the support substrate; a gate electrode layer and insulating film forming step of forming, in this order, a gate electrode layer and an insulating film on the gate insulating film opposite the support substrate; a photoresist forming step of patterning a photoresist on the insulating film opposite the support substrate; a gate electrode and interlayer insulating film forming step of simultaneously patterning the gate electrode layer and the insulating film using the photoresist as a mask to form a gate electrode and an interlayer insulating film; and a cleaning step of peeling off the photoresist.

[0006] (2) Furthermore, in one embodiment of the present invention, in addition to the configuration of (1), in the gate electrode and interlayer insulating film forming step, the gate electrode layer is formed on the side of the gate insulating film opposite to the support substrate, the insulating film is formed so as to be in contact with the surface of the gate electrode layer opposite to the support substrate, and then the gate electrode layer and the insulating film are simultaneously patterned using the same mask to form the gate electrode and the first interlayer insulating film.

[0007] (3) Furthermore, one embodiment of the present invention is a method for manufacturing a semiconductor device, in addition to the configuration of (1) or (2), wherein, in a planar view, the shape of the gate electrode and the shape of the first interlayer insulating film are the same.

[0008] (4) Furthermore, in one embodiment of the present invention, in addition to the configuration of (1), (2), or (3), a difference in surface energy between the first interlayer insulating film and the gate insulating film is smaller than a difference in surface energy between the first interlayer insulating film and the gate electrode.

[0009] (5) In addition to the configuration of (1), (2), (3), or (4), an embodiment of the present invention is characterized in that the difference in surface energy between the first interlayer insulating film and the gate insulating film is 0 mJ / m 2 More than 1000mJ / m 2 The following is a method for manufacturing a semiconductor device.

[0010] (6) Furthermore, in one embodiment of the present invention, in addition to the configuration of (1), (2), (3), (4), or (5), a method for manufacturing a semiconductor device further includes, after the cleaning step, a second interlayer insulating film forming step of forming a second interlayer insulating film on the side of the first interlayer insulating film opposite the support substrate.

[0011] (7) Furthermore, one embodiment of the present invention is a method for manufacturing a semiconductor device, wherein in addition to the configuration of (1), (2), (3), (4), (5), or (6), the first interlayer insulating film includes two or more insulating films having different dielectric constants.

[0012] (8) Another embodiment of the present invention is a semiconductor device comprising: a support substrate; a semiconductor layer located on the support substrate; a gate insulating film located on the semiconductor layer opposite the support substrate; a gate electrode located on the gate insulating film opposite the support substrate; and a first interlayer insulating film in contact with a surface of the gate electrode opposite the support substrate and having the same shape as the gate electrode in a planar view.

[0013] (9) Furthermore, in addition to the configuration of (8), one embodiment of the present invention is a semiconductor device further comprising a second interlayer insulating film located on the opposite side of the first interlayer insulating film from the support substrate.

[0014] (10) Furthermore, in addition to the configuration of (8) or (9), another embodiment of the present invention is a semiconductor device, wherein the first interlayer insulating film includes two or more insulating films having different dielectric constants. [Effects of the Invention]

[0015] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress defect generation. [Brief explanation of the drawings]

[0016] [Figure 1] 3 is a cross-sectional view illustrating a semiconductor layer forming step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 2] 3 is a cross-sectional view illustrating a semiconductor layer forming step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 3] 3 is a cross-sectional view illustrating a gate insulating film forming step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 4] 3A to 3C are cross-sectional views illustrating a gate electrode layer and insulating film forming step included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3 is a cross-sectional view illustrating a photoresist forming step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. [Figure 6] 3A to 3C are cross-sectional views illustrating a gate electrode and an interlayer insulating film forming step included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3 is a cross-sectional view illustrating a cleaning step included in the method for manufacturing a semiconductor device according to the first embodiment. FIG. [Figure 8] 4 is a cross-sectional view illustrating a second interlayer insulating film forming step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] 3A to 3C are cross-sectional views illustrating a process of forming a gate electrode, a first interlayer insulating film, and a second interlayer insulating film included in the semiconductor device according to the first embodiment. [Figure 10] 1A to 1C are cross-sectional views comparing gate electrode layer formation steps in the semiconductor device manufacturing method of the present embodiment and the conventional semiconductor device manufacturing method. [Figure 11] 1A and 1B are cross-sectional views comparing the steps of forming a photoresist on a gate electrode layer in the method for manufacturing a semiconductor device according to the present embodiment and the conventional method for manufacturing a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views comparing the patterning process of a gate electrode layer in the method for manufacturing a semiconductor device according to the present embodiment and the conventional method for manufacturing a semiconductor device. [Figure 13] 10A and 10B are cross-sectional views comparing the photoresist stripping step on the gate electrode in the semiconductor device manufacturing method of the present embodiment and the conventional semiconductor device manufacturing method. [Figure 14] 10A to 10C are cross-sectional views comparing the second interlayer insulating film forming step in the semiconductor device manufacturing method of the present embodiment and the conventional semiconductor device manufacturing method. [Figure 15] 4A to 4C are cross-sectional views illustrating a step of forming contact holes in a gate insulating film and a second interlayer insulating film, which is included in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views illustrating a source electrode and a drain electrode forming step included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of a semiconductor device manufacturing method and the like according to the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the drawings, identical or equivalent elements are given the same reference numerals, and redundant explanations will be omitted. The following description will focus on the main parts and parts related to the present disclosure.

[0018] (Embodiment 1) 1 and 2 are cross-sectional views illustrating a semiconductor layer forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 3 is a cross-sectional view illustrating a gate insulating film forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 4 is a cross-sectional view illustrating a gate electrode layer and insulating film forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 5 is a cross-sectional view illustrating a photoresist forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 6 is a cross-sectional view illustrating a gate electrode and interlayer insulating film forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 7 is a cross-sectional view illustrating a cleaning step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 8 is a cross-sectional view illustrating a second interlayer insulating film forming step included in the method for manufacturing a semiconductor device according to embodiment 1. FIG. 9 is a cross-sectional view illustrating a gate electrode, a first interlayer insulating film, and a second interlayer insulating film forming step included in the semiconductor device according to embodiment 1.

[0019] The method for manufacturing the semiconductor device of this embodiment includes, in this order, a semiconductor layer formation step of forming a semiconductor layer 130A on a support substrate 110, as shown in Figures 1 and 2; a gate insulating film formation step of forming a gate insulating film 140 on the side of the semiconductor layer 130A opposite the support substrate 110, as shown in Figure 3; a gate electrode layer and insulating film formation step of forming a gate electrode layer 150 and an insulating film 160 in this order on the side of the gate insulating film 140 opposite the support substrate 110, as shown in Figure 4; a photoresist formation step of patterning a photoresist 1F on the side of the insulating film 160 opposite the support substrate 110, as shown in Figure 5; a gate electrode and interlayer insulating film formation step of simultaneously patterning the gate electrode layer 150 and the insulating film 160 using the photoresist 1F as a mask to form a gate electrode 150G and an interlayer insulating film 160A, as shown in Figure 6; and a cleaning step of peeling off the photoresist 1F, as shown in Figure 7.

[0020] Here, in the manufacturing process of a semiconductor device, defects in the interlayer insulating film frequently cause point defects, line defects, etc. The reason for this is thought to be as follows: Because the surface energies of metal and insulating film (e.g., oxide film) are different from each other, when a gate electrode layer provided on a gate insulating film is patterned in the manufacturing of a semiconductor device having a top gate structure, water droplets containing foreign matter generated during peeling and cleaning of the gate electrode layer remain on the gate electrode layer. Therefore, when an interlayer insulating film is further deposited on the patterned gate electrode layer and an annealing treatment is performed, the water droplets containing the foreign matter cause defects in the interlayer insulating film, resulting in point defects, line defects, etc. in the semiconductor device.

[0021] On the other hand, in this embodiment, the gate electrode layer 150 and the insulating film 160 are successively formed in this order in the gate electrode layer and insulating film forming step, and then the gate electrode layer 150 and the insulating film 160 are simultaneously patterned in the gate electrode and interlayer insulating film forming step. Therefore, in the cleaning step, the gate electrode layer 150 can be peeled and cleaned while the surface of the gate electrode layer 150 opposite the support substrate 110 is protected by the insulating film 160 to form the gate electrode 150G. As a result, it is possible to prevent impurity-containing water droplets from remaining near the gate electrode 150G. Therefore, even if an interlayer insulating film (a second interlayer insulating film, described later) is further formed on the side of the gate electrode 150G opposite the support substrate 110 after the cleaning step, it is possible to prevent damage to the interlayer insulating film, thereby preventing the generation of defects in the semiconductor device. Each step will be described in detail below.

[0022] 1 and 2 is a step of forming a semiconductor layer 130A on a support substrate 110. The semiconductor layer formation step may be, for example, a step of forming a base coat layer 120 on the support substrate 110, forming a semiconductor layer thin film 130 on the side of the base coat layer 120 opposite the support substrate 110, and then patterning the semiconductor layer thin film 130 to form the semiconductor layer 130A, as shown in FIG.

[0023] The support substrate 110 may be, for example, an insulating substrate such as a glass substrate or a plastic substrate. Examples of materials for the glass substrate include glass such as float glass and soda glass. Examples of materials for the plastic substrate include plastics such as polyethylene terephthalate, polybutylene terephthalate, polyethersulfone, polycarbonate, and alicyclic polyolefin.

[0024] The base coat layer 120 can be formed by, for example, a CVD method. The base coat layer 120 is, for example, an insulating film containing an inorganic substance such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x≧y), or silicon nitride oxide (SiNxOy) (x>y), or a laminate film thereof.

[0025] The semiconductor layer 130A can be formed, for example, by depositing a semiconductor layer thin film 130 on the side of the base coat layer 120 opposite the support substrate 110 as shown in FIG. 1, and then patterning the semiconductor layer thin film 130 using a photolithography process as shown in FIG. 2. The semiconductor layer thin film 130 can be formed, for example, using a sputtering method or a CVD method. The semiconductor layer thin film 130 is composed of, for example, a high-resistance semiconductor layer made of amorphous silicon, polysilicon, or the like, and a low-resistance semiconductor layer made of n+ amorphous silicon, which is amorphous silicon doped with impurities such as phosphorus. Alternatively, an oxide semiconductor layer such as zinc oxide may be used as the semiconductor layer thin film 130.

[0026] 3 is a step of forming a gate insulating film 140 on the side of the semiconductor layer 130A opposite to the support substrate 110. The gate insulating film 140 can be formed by, for example, a CVD method. The gate insulating film 140 is an insulating film containing an inorganic substance such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x≧y), or silicon nitride oxide (SiNxOy) (x>y), or a laminate film thereof.

[0027] 4, the gate electrode layer and insulating film forming step is a step of forming a gate electrode layer 150 and an insulating film 160 in this order on the side of the gate insulating film 140 opposite to the support substrate 110. In the gate electrode layer and insulating film forming step, after the gate electrode layer 150 is formed on the side of the gate insulating film 140 opposite to the support substrate 110, an insulating film 160 containing an inorganic insulator not containing carbon (silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x≧y), silicon nitride oxide (SiNxOy) (x>y), etc.) is continuously formed on the gate electrode layer 150 by using, for example, a CVD method, a sputtering method, etc.

[0028] The gate electrode layer 150 can be formed by, for example, a sputtering method. The gate electrode layer 150 is a conductive layer containing, for example, a metal such as titanium, aluminum, molybdenum, copper, or chromium, or an alloy thereof.

[0029] The insulating film 160 can be formed by, for example, a CVD method, a sputtering method, etc. The insulating film 160 is an insulating film containing an inorganic substance such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x≧y), silicon nitride oxide (SiNxOy) (x>y), or a laminated film thereof.

[0030] The gate electrode layer 150 and the insulating film 160 can be patterned using photolithography. The photoresist forming step is a step of patterning a photoresist 1F on the side of the insulating film 160 opposite to the support substrate 110, as shown in FIG.

[0031] As shown in FIG. 6, the gate electrode and interlayer insulating film forming step is a step of simultaneously patterning the gate electrode layer 150 and the insulating film 160 using a photoresist 1F as a mask to form a gate electrode 150G and an interlayer insulating film 160A.

[0032] In the gate electrode layer and insulating film formation step, it is preferable to form the gate electrode layer 150 on the side of the gate insulating film 140 opposite the support substrate 110, and form the insulating film 160 so as to be in contact with the surface of the gate electrode layer 150 opposite the support substrate 110, and then, in the gate electrode and interlayer insulating film formation step, pattern the gate electrode layer 150 and the insulating film 160 simultaneously using the same mask to form the gate electrode 150G and the interlayer insulating film 160A.

[0033] The cleaning step is a step of removing the photoresist 1F, as shown in FIG.

[0034] In this embodiment, the gate electrode layer 150 and the insulating film 160 are patterned simultaneously, so that the shape of the gate electrode 150G and the shape of the first interlayer insulating film 160A match in plan view. That is, in the manufacturing method of this embodiment, the first interlayer insulating film 160A is provided only on the gate electrode 150G. In this way, in the semiconductor device 1 manufactured by the manufacturing method of this embodiment, the first interlayer insulating film 160A is provided only on the gate electrode 150G, so that it is possible to make the wettability with other regions uniform, and it is possible to prevent water droplets from remaining on the hydrophilic electrode metal (gate electrode 150G).

[0035] The surface energy of the first interlayer insulating film 160A (insulating film 160) is preferably closer to the surface energy of the gate insulating film 140 than to the surface energy of the gate electrode 150G (gate electrode layer 150). In other words, the difference in surface energy between the first interlayer insulating film 160A and the gate insulating film 140 is preferably smaller than the difference in surface energy between the first interlayer insulating film 160A and the gate electrode 150G. This configuration effectively prevents water droplets from accumulating on the gate electrode 150G during the cleaning process, thereby enabling the manufacture of a semiconductor device with reduced defect generation. The surface energy value can be calculated by dropping a liquid such as pure water onto the film, measuring the contact angle, and then calculating the liquid's physical properties and the measured contact angle. Specifically, the surface energy can be measured using a drop shape analyzer (DSA100 product by KRUSS). For example, deionized water with a known surface tension is dropped onto the surface of the member whose surface energy is to be measured, and the process of measuring the contact angle is repeated five times, and the average of the five contact angle values ​​obtained is calculated. Similarly, diiodomethane, which has a known surface tension, is dropped onto the surface and the contact angle is measured. This process is repeated five times, and the average of the five contact angles is calculated. The surface energy can then be calculated by substituting the value for the surface tension of the solvent (Strom value) using the average contact angles for deionized water and diiodomethane measured using the Owens-Wendt-Rabel-Kaelble method.

[0036] The difference in surface energy between the first interlayer insulating film 160A (insulating film 160) and the gate insulating film 140 is, for example, 0 mJ / m 2 More than 1000mJ / m 2 Preferably, it is 10 mJ / m or less. 2 More than 500mJ / m 2 More preferably, it is 50 mJ / m or less. 2 More than 300mJ / m 2 It is more preferable that:

[0037] The difference in surface energy between the first interlayer insulating film 160A (insulating film 160) and the gate electrode 150G (gate electrode layer 150) is, for example, 1000 mJ / m 2 exceeding 3000mJ / m 2 Preferably, it is 1500 mJ / m or less. 2 More than 2500mJ / m 2 More preferably, it is 1700 mJ / m or less. 2 More than 2000mJ / m 2 It is more preferable that:

[0038] 8, the method for manufacturing a semiconductor device according to this embodiment may further include, after the cleaning step, a second interlayer insulating film forming step of forming a second interlayer insulating film 170 on the side of the first interlayer insulating film 160A opposite to the support substrate 110. The second interlayer insulating film 170 preferably covers the gate electrode 150G and the interlayer insulating film 160A.

[0039] As shown in FIG. 9 , when forming the gate electrode layer 150 and the insulating film 160, for example, an insulating film 160 having a surface energy similar to that of the gate insulating film 140 is stacked on the gate electrode layer 150. Next, when forming the gate electrode 150G and the interlayer insulating film 160A, the gate electrode layer 150 and the insulating film 160 are simultaneously etched using a photoresist as a mask. Next, the photoresist is stripped, and the gate electrode 150G and the interlayer insulating film 160A are formed. Thereafter, a second interlayer insulating film 170 is formed so as to cover the gate electrode 150G and the interlayer insulating film 160A. This second interlayer insulating film can be used as the insulating film for the gate electrode 150G.

[0040] The second interlayer insulating film 170 can be formed by, for example, a CVD method, a sputtering method, etc. The second interlayer insulating film 170 is an insulating film containing an inorganic substance such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x≧y), silicon nitride oxide (SiNxOy) (x>y), or a laminated film thereof.

[0041] Here, the steps of forming the gate electrode, the first interlayer insulating film, and the second interlayer insulating film will be described in detail. FIG. 10 is a cross-sectional view comparing the step of forming a gate electrode layer in the semiconductor device manufacturing method of this embodiment and the conventional semiconductor device manufacturing method. FIG. 11 is a cross-sectional view comparing the step of forming a photoresist on the gate electrode layer in the semiconductor device manufacturing method of this embodiment and the conventional semiconductor device manufacturing method. FIG. 12 is a cross-sectional view comparing the step of patterning the gate electrode layer in the semiconductor device manufacturing method of this embodiment and the conventional semiconductor device manufacturing method. FIG. 13 is a cross-sectional view comparing the step of removing the photoresist on the gate electrode in the semiconductor device manufacturing method of this embodiment and the conventional semiconductor device manufacturing method. FIG. 14 is a cross-sectional view comparing the step of forming a second interlayer insulating film in the semiconductor device manufacturing method of this embodiment and the conventional semiconductor device manufacturing method.

[0042] In a conventional method for manufacturing a semiconductor device, as shown in Fig. 10, in the step of forming a gate electrode layer 150R, the gate electrode layer 150R is formed on a gate insulating film 140. Next, in order to pattern the gate electrode layer 150R, a pattern of photoresist 1F is formed on the gate electrode layer 150R as shown in Fig. 11. Next, as shown in Fig. 12, the gate electrode layer 150R is patterned using the photoresist 1F as a mask to form a gate electrode 150GR. At this time, the patterning may be dry or wet.

[0043] Next, as shown in FIG. 13, the photoresist 1F is stripped. At this time, the surface of the gate electrode 150GR, which contains metal, is exposed to water containing contaminants such as resist residue. Metals have a higher surface free energy and are more wettable than oxides such as the gate insulating film 140. Therefore, during the cleaning process used to strip the photoresist 1F, water droplets 150X containing foreign matter such as organic residues tend to adhere to the surface of the gate electrode 150GR, and after drying, the organic residues remain on the gate electrode 150GR. These residues can become foreign matter or can form an interlayer insulating film with insufficient film thickness or crystallinity, which can hinder subsequent structural formation and cause defects, as shown in FIG. 14.

[0044] 10, in the method for fabricating a semiconductor device of the present invention, a gate electrode layer 150 and an insulating film 160 are successively formed on a gate insulating film 140 (gate electrode layer and insulating film forming step). The insulating film 160 preferably has a surface free energy lower than that of the gate electrode layer 150. In particular, the insulating film 160 preferably has a surface free energy equal to or lower than that of the gate insulating film 140 that underlies the gate electrode layer 150, and more preferably has the same components as the gate insulating film 140 in terms of ease of formation and control of parasitic capacitance.

[0045] Next, in order to pattern the gate electrode layer 150 and the insulating film 160, a photoresist 1F is patterned as shown in Fig. 11 (photoresist formation step). Next, as shown in Fig. 12, the gate electrode layer 150 and the insulating film 160 are patterned using the photoresist 1F as a mask (gate electrode and interlayer insulating film formation step).

[0046] Next, as shown in FIG. 13, the photoresist 1F is stripped (cleaning process). The first interlayer insulating film 160A present on the gate electrode 150G contains oxide or nitride, resulting in low surface free energy and low wettability. Therefore, water droplets are less likely to adhere to the gate electrode 150G during the cleaning process when stripping the photoresist 1F, and organic residues can be efficiently removed along with the water. Because the surface of the first interlayer insulating film 160A is thus kept clean, foreign matter and film defects are less likely to occur even when the second interlayer insulating film 170 is formed, as shown in FIG. 14, and defect generation is suppressed.

[0047] The method for manufacturing a semiconductor device according to this embodiment may further include, after the second interlayer insulating film forming step, a third interlayer insulating film forming step of forming a third interlayer insulating film on the side of second interlayer insulating film 170 opposite to support substrate 110. By adopting such an embodiment, parasitic capacitance can be suppressed.

[0048] As described above, in the manufacturing method of this embodiment, the gate electrode layer 150 and the insulating film 160, which has a lower surface free energy than the gate electrode layer 150, are successively formed on the gate insulating film 140, and then the gate electrode layer 150 is patterned. Therefore, water droplets are less likely to adhere to the gate electrode 150G during the photoresist cleaning process, and organic residues can be efficiently removed together with water. As a result, the surface of the first interlayer insulating film 160A is kept clean, and therefore, even when the second interlayer insulating film 170 is formed, foreign matter and film defects are less likely to occur, and the generation of defects is suppressed.

[0049] Fig. 15 is a cross-sectional view illustrating a contact hole formation step in the gate insulating film and the second interlayer insulating film included in the method for manufacturing a semiconductor device according to embodiment 1. Fig. 16 is a cross-sectional view illustrating a source electrode and a drain electrode formation step included in the method for manufacturing a semiconductor device according to embodiment 1.

[0050] The method for manufacturing a semiconductor substrate of this embodiment may further include, after the second interlayer insulating film forming step, a contact hole forming step of forming a contact hole 180CH in the gate insulating film 140 and the second interlayer insulating film 170, as shown in FIG. 15.

[0051] The method for manufacturing a semiconductor substrate of this embodiment may further include, after the contact hole formation step, a source electrode and drain electrode formation step of forming a source electrode 180S and a drain electrode 180D that are connected to the semiconductor layer 130A via the contact hole 180CH, as shown in FIG. 16.

[0052] In the method for manufacturing a semiconductor device according to the present embodiment, for example, as shown in FIG. 1, a base coat layer 120 is formed on a glass substrate serving as a support substrate 110, and a Si (silicon) layer is formed on the base coat layer 120 as a semiconductor layer thin film 130. Next, as shown in FIG. 2, the semiconductor layer thin film 130 is patterned to form a semiconductor layer 130A. Next, as shown in FIG. 3, a gate insulating film 140 is formed on the semiconductor layer 130A. Next, as shown in FIG. 4, a gate electrode layer 150 and an insulating film 160 are successively formed on the gate insulating film 140. Next, as shown in FIGS. 5 to 7, the gate electrode layer 150 and the insulating film 160 are simultaneously patterned. Next, as shown in FIG. 8, a second interlayer insulating film 170 is formed on the first interlayer insulating film 160A. Next, as shown in FIG. 15, a contact hole 180CH is formed in the gate insulating film 140 and the second interlayer insulating film 170. Next, as shown in FIG. 16, an electrode layer 180 is formed, and then the electrode layer 180 is patterned to form a source electrode 180S and a drain electrode 180D so as to be connected to the semiconductor layer 130A via the contact holes 180CH.

[0053] 16, the semiconductor device 1 manufactured by the semiconductor device manufacturing method of the present embodiment includes a support substrate 110, a semiconductor layer 130A located on the support substrate 110, a gate insulating film 140 located on the semiconductor layer 130A opposite the support substrate 110, a gate electrode 150G located on the gate insulating film 140 opposite the support substrate 110, and a first interlayer insulating film 160A in contact with the surface of the gate electrode 150G opposite the support substrate 110 and having the same shape as the gate electrode 150G in a planar view. By adopting such an embodiment, defects in the semiconductor device 1 can be suppressed.

[0054] The semiconductor device 1 may further include a second interlayer insulating film 170 located on the opposite side of the first interlayer insulating film 160A from the support substrate 110.

[0055] (Embodiment 2) In this embodiment, the features unique to this embodiment will be mainly described, and descriptions of the same content as in the first embodiment will be omitted. This embodiment is substantially the same as the first embodiment, except for the configuration of the first interlayer insulating film. The first interlayer insulating film 160A of this embodiment includes two or more insulating films with different dielectric constants. By adopting this configuration, it is possible to control parasitic capacitance without increasing the thickness of the insulating film itself.

[0056] 17 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. As shown in FIG. 17 , in the gate electrode layer and insulating film formation step included in the method for manufacturing a semiconductor device according to this embodiment, a gate electrode layer 150 and an insulating film 160 including a lower insulating film 161 and an upper insulating film 162 having different dielectric constants are formed in this order on the side of the gate insulating film 140 opposite the support substrate 110. Furthermore, in the gate electrode and interlayer insulating film formation step included in the method for manufacturing a semiconductor device according to this embodiment, the gate electrode layer 150 and the insulating film 160 are simultaneously patterned using a photoresist 1F as a mask to form a gate electrode 150G and a first interlayer insulating film 160A including a lower interlayer insulating film 161A and an upper interlayer insulating film 162A having different dielectric constants. This configuration allows parasitic capacitance to be controlled without thickening the insulating film itself.

[0057] In this embodiment, the first interlayer insulating film 160A in embodiment 1 has a laminated structure of two or more insulating films (for example, a lower interlayer insulating film 161A and an upper interlayer insulating film 162A) made of materials with different dielectric constants. By using a laminated structure of insulating films with different dielectric constants, it is possible to control parasitic capacitance without increasing the thickness of the insulating film itself. There is no limit to the number of insulating films to be laminated, but the fewer the number the better from the standpoint of cost, and two layers is most preferable.

[0058] In the gate electrode layer and insulating film forming step included in the method for manufacturing a semiconductor device of this embodiment, the gate electrode layer 150, the lower insulating film 161, and the upper insulating film 162 can be formed in this order.

[0059] The lower insulating film 161 and the upper insulating film 162 are insulating films containing an inorganic insulator (silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNxOy), etc.).

[0060] The difference in relative dielectric constant between the lower insulating film 161 and the upper insulating film 162 is preferably 3 or more and 500 or less, more preferably 5 or more and 300 or less, and even more preferably 10 or more and 200 or less.

[0061] The first interlayer insulating film 160A provided in the semiconductor device fabricated by the manufacturing method of this embodiment includes a lower interlayer insulating film 161A and an upper interlayer insulating film 162A having different dielectric constants.

[0062] The difference in relative dielectric constant between the lower interlayer insulating film 161A and the upper interlayer insulating film 162A is preferably 3 to 500, more preferably 5 to 300, and even more preferably 10 to 200.

[0063] The above-described aspects of the present invention may be combined as appropriate within the scope of the present invention. [Explanation of symbols]

[0064] 1: Semiconductor device 1F: Photoresist 110: Support substrate 120: Base coat layer 130: Thin film for semiconductor layer 130A: Semiconductor layer 140: Gate insulating film 150, 150R: gate electrode layer 150G, 150GR: gate electrode 150X: Water drop 160: insulating film 160A: First interlayer insulating film 161: Lower insulating film 161A: Lower interlayer insulating film 162: Upper insulating film 162A: Upper interlayer insulating film 170: Second interlayer insulating film 180: Electrode layer 180CH: Contact hole 180D: Drain electrode 180S: Source electrode

Claims

1. a semiconductor layer forming step of forming a semiconductor layer on a support substrate; a gate insulating film forming step of forming a gate insulating film on the semiconductor layer on the opposite side of the support substrate; a gate electrode layer and insulating film forming step of forming a gate electrode layer and an insulating film in this order on the opposite side of the gate insulating film from the support substrate; a photoresist forming step of patterning a photoresist on the insulating film on the side opposite to the support substrate; a gate electrode and interlayer insulating film forming step of simultaneously patterning the gate electrode layer and the insulating film using the photoresist as a mask to form a gate electrode and an interlayer insulating film; and a cleaning step of removing the photoresist.

2. In the gate electrode layer and insulating film forming step, the gate electrode layer is formed on the side of the gate insulating film opposite to the support substrate, and the insulating film is formed so as to be in contact with the surface of the gate electrode layer opposite to the support substrate, 2. The method for manufacturing a semiconductor device according to claim 1, wherein in said gate electrode and interlayer insulating film forming step, said gate electrode layer and said insulating film are simultaneously patterned using the same mask to form said gate electrode and said interlayer insulating film.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a shape of said gate electrode and a shape of said interlayer insulating film coincide with each other in a plan view.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a difference in surface energy between said interlayer insulating film and said gate insulating film is smaller than a difference in surface energy between said interlayer insulating film and said gate electrode.

5. The difference in surface energy between the interlayer insulating film and the gate insulating film is 0 mJ / m ２ Above, 1000mJ / m ２ 2. The method for manufacturing a semiconductor device according to claim 1, wherein:

6. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising, after said cleaning step, a second interlayer insulating film forming step of forming a second interlayer insulating film on a side of said interlayer insulating film opposite to said support substrate.

7. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said interlayer insulating film includes two or more insulating films having different dielectric constants.

8. A support substrate; a semiconductor layer located on the support substrate; a gate insulating film located on the opposite side of the semiconductor layer from the support substrate; a gate electrode located on the opposite side of the gate insulating film from the support substrate; a first interlayer insulating film in contact with a surface of the gate electrode opposite to the support substrate and having the same shape as the gate electrode in a plan view.

9. The semiconductor device according to claim 8 , further comprising a second interlayer insulating film located on the opposite side of said interlayer insulating film from said support substrate.

10. 9. The semiconductor device according to claim 8, wherein said interlayer insulating film includes two or more insulating films having different dielectric constants.

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